™
Le58083
Low Voltage Subscriber Line Audio-processing Circuit
VE580 Series
APPLICATIONS
RELATED LITERATURE
■ Codec function on telephone switch line cards
■ 080753 Le58QL02/021/031 QLSLAC™ Data Sheet
■ 080754 Le58QL061/063 QLSLAC™ Data Sheet
■ 080761 QSLAC™ to QLSLAC™ Design Conversion
FEATURES
■ Low-power, 3.3 V CMOS technology with 5 V tolerant
digital inputs
■ Pin programmable PCM/MPI or GCI interface
■ Software and coefficient compatible to the VE580
series QLSLAC™ devices
■ Standard PCM/microprocessor interface
(PCM/MPI mode)
—
—
—
—
—
Single or Dual PCM ports available
Time slot assigner (up to 128 channels per port)
Clock slot and transmit clock edge options
Optional supervision on the PCM highway
1.536, 1.544, 2.048, 3.072, 3.088, 4.096, 6.144, 6.176,
or 8.192 MHz master clock derived from MCLK or PCLK
— µP access to PCM data
— Real Time Data with interrupt (open drain or TTL)
— Broadcast mode
■ General Circuit Interface (GCI mode)
— Control and PCM data on a single port
— 2.048 Mbits/s data rate
— 2.048 MHz or 4.096 MHz clock option
■ Performs the functions of eight codec/filters
■ Software programmable:
— SLIC device input impedance and Transhybrid balance
— Transmit and receive gains and Equalization
— Programmable Digital I/O pins with debouncing
■ A-law, µ-law, or linear coding
■ Built-in test modes with loopback, tone generation,
and µP access to PCM data
■
■
■
■
Mixed state (analog and digital) impedance scaling
Guide
■ 080758 QSLAC™ to QLSLAC™ Guide to New Designs
DESCRIPTION
The Le58083 Octal Low Voltage Subscriber Line AudioProcessing Circuit (Octal SLAC™) devices integrate the key
functions of analog line cards into high-performance, veryprogrammable, eight-channel codec-filter devices. The
Le58083 Octal SLAC devices are based on the proven design
of Zarlink’s reliable SLAC device families. The advanced
architecture of the Le58083 Octal SLAC devices implements
eight independent channels and employs digital filters to allow
software control of transmission, thus providing a cost-effective
solution for the audio-processing function of programmable line
cards. The Le58083 Octal SLAC devices are software and
coefficient compatible to the VE580 series QLSLAC™ devices.
Advanced submicron CMOS technology makes the Le58083
Octal SLAC devices economical, with both the functionality and
the low power consumption needed in line card designs to
maximize line card density at minimum cost. When used with
multiple Zarlink SLIC devices, an Le58083 Octal SLAC device
provides a complete software-configurable solution to the
BORSCHT functions.
BLOCK DIAGRAM
GCI/PCM
Interface
ANALOG
DXA/DU
DRA/DD
VIN(1-8)
VOUT (1-8)
TSCA
Signal
Processing
Channels 1-8
PCM & GCI Interface
&
Time Slot Assigner
(TSA)
Performance guaranteed over a 12 dB gain range
DXB
DRB
TSCB
Supports multiplexed SLIC device outputs
256 kHz or 293 kHz chopper clock for Zarlink SLIC
devices with switching regulator
■ Maximum channel bandwidth for V.90 modems
ORDERING INFORMATION
Device
Le58083ABGC
Package
121-pin BGA (Green package)*
VREF_1, VREF_2
SLIC
CONTROLS
Clock
&
Reference
Circuits
CD1(1-8)
CD2(1-8)
C3(1-8)
C4(1-8)
FS/FSC
PCLK/DCL
MCLK_1, MCLK_2
SLIC
Interface
(SLI)
DCLK-S0_1, DCLK-SO_2
C5(1-8)
CS/PG_1, CS/PG_2
C6(1-8)
C7(1-8)
GCI Control Logic &
Microprocessor Interface
(MPI)
DIO-S1_1, DIO-S1_2
INT_1, INT_2
*Green package meets RoHS Directive 2002/95/EC of the European
Council to minimize the environmental impact of electrical equipment.
RST
Document ID# 080921 Date:
Rev:
E
Version:
Distribution:
Public Document
Sep 18, 2007
2
Le58083
Data Sheet
TABLE OF CONTENTS
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Related Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Clock and Reference Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Microprocessor Interface (MPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Time Slot Assigner (TSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Signal Processing Channels (CHx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
SLIC Device Interface (SLI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
121-Pin BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Environmental Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Electrical Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Transmission Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Attenuation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Gain Linearity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Total Distortion Including Quantizing Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Discrimination Against Out-of-Band Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Discrimination Against 12- and 16-kHz Metering Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Spurious Out-of-Band Signals at the Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
GCI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
GCI Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Operating the Le58083 Octal SLAC Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
PCM and GCI State Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Channel Enable (EC) Register (PCM/MPI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
SLIC Device Control and Data Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Clock Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
E1 Multiplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Debounce Filters Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Real-Time Data Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Active State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Inactive State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Chopper Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Overview of Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Two-Wire Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Frequency Response Correction and Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2
Zarlink Semiconductor Inc.
Le58083
Data Sheet
Transhybrid Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Gain Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Transmit Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Transmit PCM Interface (PCM/MPI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Data Upstream Interface (GCI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Receive Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Receive PCM Interface (PCM/MPI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Data Downstream Interface (GCI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Analog Impedance Scaling Network (AISN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Speech Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Double PCLK (DPCK) Operation (PCM/MPI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Signaling on the PCM Highway (PCM/MPI Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Robbed-Bit Signaling Compatibility (PCM/MPI Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Default Filter Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Command Description and Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Command Field Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Microprocessor Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Summary of MPI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
MPI Command Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
00h Deactivate (Standby State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
02h Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
04h Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
06h No Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
0Eh Activate Channel (Operational State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
40/41h Write/Read Transmit Time Slot and PCM Highway Selection . . . . . . . . . . . . . . . . . . . . . .47
42/43h Write/Read Receive Time Slot and PCM Highway Selection . . . . . . . . . . . . . . . . . . . . . .47
44/45h Write/Read Transmit Clock Slot, Receive Clock Slot, and Transmit Clock Edge . . . . . . .48
46/47h Write/Read Chip Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4A/4Bh Write/Read Channel Enable and Operating Mode Register . . . . . . . . . . . . . . . . . . . . . . .49
4D/4Fh Read Real-Time Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
50/51h Write/Read AISN and Analog Gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
52/53h Write/Read SLIC Device Input/Output Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
54/55h Write/Read SLIC Device Input/Output Direction, Read Status Bits . . . . . . . . . . . . . . . . . .51
60/61h Write/Read Operating Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6C/6Dh Write/Read Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
70/71h Write/Read Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
73h Read Revision Code Number (RCN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
80/81h Write/Read GX Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
82/83h Write/Read GR Filter Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
84/85h Write/Read Z Filter Coefficients (FIR and IIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
86/87h Write/Read B1 Filter Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
88/89h Write/Read X Filter Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
8A/8Bh Write/Read R Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
96/97h Write/Read B2 Filter Coefficients (IIR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
98/99h Write/Read FIR Z Filter Coefficients (FIR only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
9A/9Bh Write/Read IIR Z Filter Coefficients (IIR only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
C8/C9h Write/Read Debounce Time Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
CDh Read Transmit PCM Data (PCM/MPI Mode Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
E8/E9h Write/Read Ground Key Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
General Circuit Interface (GCI) Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
GCI General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
GCI Format and Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Signaling and Control (SC) Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Programming with the Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Channel Identification Command (CIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
General Structure of Other Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
3
Zarlink Semiconductor Inc.
Le58083
Data Sheet
Summary of Monitor Channel Commands (GCI Commands) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
TOP (Transfer Operation) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
SOP (Status Operation) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
SOP Control Byte Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
COP (Coefficient Operation) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Details of COP, CSD Data Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Programmable Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
General Description of CSD Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
User Test States and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
A-Law and µ-Law Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Line card parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
LFBGA (121 Balls) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Revision A to B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Revision B to C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Revision C1 to D1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Revision D1 to E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Revision E1 to E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
LIST OF FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Transmit Path Attenuation vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Receive Path Attenuation vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
A-law Gain Linearity with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
µ-law Gain Linearity with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Total Distortion with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Discrimination Against Out-of-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Spurious Out-of-Band Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Analog-to-Analog Overload Compression. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Input and Output Waveforms for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Microprocessor Interface (Input Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Microprocessor Interface (Output Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
PCM Highway Timing for XE = 0 (Transmit on Negative PCLK Edge) . . . . . . . . . . . . .24
PCM Highway Timing for XE = 1 (Transmit on Positive PCLK Edge) . . . . . . . . . . . . . .25
Double PCLK PCM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Master Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.096 MHz DCL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.048 MHz DCL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Clock Mode Options (PCM/MPI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
SLIC Device I/O, E1 Multiplex and Real-Time Data Register Operation. . . . . . . . . . . .34
E1 Multiplex Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
MPI Real-Time Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Le58083 Octal SLAC Transmission Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Robbed-Bit Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Time Slot Control and GCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Multiplexed GCI Time Slot Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Security Procedure for C/I Downstream Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Maximum Speed Monitor Handshake Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Monitor Transmitter Mode Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Monitor Receiver State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Le57D11 SLIC/Le58083 Octal SLAC™ Application Circuit . . . . . . . . . . . . . . . . . . . . .91
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
LIST OF TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Le58083 Octal SLAC™ Device Pin Names and Numbers . . . . . . . . . . . . . . . . . . . . . . . .8
0 dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX, and AR . . . . . . . . . . .14
PCM/GCI Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Channel Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Channel Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Global Chip Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Global Chip Status Monitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
GCI Channel Assignment Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Generic Byte Transmission Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Byte Transmission Sequence for TOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
General Transmission Sequence of SOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Generic Transmission Sequence for COP Command . . . . . . . . . . . . . . . . . . . . . . . . . .79
A-Law: Positive Input Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
µ-Law: Positive Input Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
PRODUCT DESCRIPTION
The Le58083 Octal SLAC device performs the codec/filter and two-to-four-wire conversion functions required of the subscriber
line interface circuitry in telecommunications equipment. These functions involve converting audio signals into digital PCM
samples and converting digital PCM samples back into audio signals. During conversion, digital filters are used to band limit the
voice signals. All of the digital filtering is performed in digital signal processors operating from a master clock, which can be
derived either from PCLK or MCLK in the PCM/MPI mode and DCL in the GCI mode.
The Le58083 Octal SLAC device is configured as two four-channel groups that share a common reset and PCM/GCI interface.
Each four-channel group has its own chip select for individual programming. The signal names for each four-channel SLAC
device are differentiated by _1 or _2. Generic naming of each signal is C_X, where the subscript C equals the channel number
1 through 4 and the _X equals the four-channel group number 1 or 2. For example, VIN3_2 would identify channel 3 of the second
four-channel group.
Eight independent channels allow the Le58083 Octal SLAC device to function as eight SLAC devices. In PCM/MPI mode, each
channel has its own enable bit (EC1, EC2, EC3, etc.) to allow individual channel programming. If more than one Channel Enable
bit is High or if all Channel Enable bits are High, all channels enabled will receive the programming information written; therefore,
a Broadcast mode can be implemented by simply enabling all channels in the device to receive the information and enabling both
chip selects. The Channel Enable bits are contained in the Channel Enable (EC) register, which is written and read using
Commands 4A/4Bh. The Broadcast mode is useful in initializing Le58083 Octal SLAC devices in a large system.
In GCI mode, one GCI channel controls two channels of the Le58083 Octal SLAC device. The Monitor channel and SC channel
within the GCI channel are used to read/write filter coefficient data, read/write operating conditions and to read/write data to/from
the programmable I/O ports of the two channels. Two pairs of GCI channels control the two four-channel groups in the Le58083
Octal SLAC device. The four GCI channels used, of the eight total available, are determined by S0 and S1 inputs.
The user-programmable filters set the receive and transmit gain, perform the transhybrid balancing function, permit adjustment
of the two-wire termination impedance, and provide equalization of the receive and transmit paths. All programmable digital filter
coefficients can be calculated using the WinSLAC™ software.
In PCM/MPI mode, Data transmitted or received on the PCM highway can be 8-bit companded code (with an optional 8-bit
signaling byte in the transmit direction) or 16-bit linear code. The 8-bit codes appear 1 byte per time slot, while the 16-bit code
appears in two consecutive time slots. The compressed PCM codes can be either 8-bit companded A-law or µ-law. The PCM
data is read from and written to the PCM highway in user-programmable time slots at rates of 128 kHz to 8.192 MHz. The transmit
clock edge and clock slot can be selected for compatibility with other devices that can be connected to the PCM highway.
In GCI mode, two 8-bit companded codes are received or transmitted per GCI channel. The compressed PCM codes can be
either 8-bit companded A-law or µ-law. There is no Signaling or Linear mode available when GCI mode is selected.
The programming software is backward compatible to the Zarlink Le58000 SLAC family of devices.
DEVICE DESCRIPTION
PCM/GCI Highway
Programmable I/O
per Channel
Dual/single
Chopper Clock
Package
Part Number
Yes
BGA
Le58083GC
Five I/O
Two Output
BLOCK DESCRIPTIONS
Clock and Reference Circuits
This block generates a master clock and a frame sync signal for the digital circuits. It also generates an analog reference voltage
for the analog circuits.
Microprocessor Interface (MPI)
This block communicates with the external control microprocessor over a serial interface. It passes user control information to
the other blocks, and it passes status information from the blocks to the user. In addition, this block contains the reset circuitry.
When GCI is selected, this block is combined with the TSA block.
Time Slot Assigner (TSA)
This block communicates with the PCM highway, where the PCM highway is a time division mutiplexed bus carrying the digitized
voice samples. The block implements programmable time slots and clocking arrangements in order to achieve a first layer of
switching. Internally, this block communicates with the Signal Processing Channels (CHx). When GCI is selected, this block is
combined with the TSA block.
6
Zarlink Semiconductor Inc.
Le58083
Data Sheet
Signal Processing Channels (CHx)
These blocks do the transmission processing for the voice channels. Part of the processing is analog and is interfaced to the VIN
and VOUT pins. The remainder of the processing is digital and is interfaced to the Time Slot Assigner (TSA) block.
SLIC Device Interface (SLI)
This block communicates digitally with the SLIC device circuits. It sends control bits to the SLIC devices to control modes and to
operate LEDs and optocouplers. It also accepts supervision information from the SLIC devices and performs some filtering.
CONNECTION DIAGRAM
121-Pin BGA
L
VIN 4 _1
VIN 4 _2
NC
C5 3 _1
C4 3 _2
DGND
C5 4 _1
C3 4 _2
C7 4 _2
DRA/DD
DXB
K
VOUT 4 _1
VOUT 4 _2
VCCA
C4 3 _1
C3 3 _2
VCCD
C4 4 _1
CD2 4 _2
C6 4 _2
DRB
DXA/DU
J
NC
NC
AGND
C3 3 _1
CD2 3 _2
C7 3 _2
C3 4 _1
CD1 4 _2
C5 4 _2
FS/FSC
TSCB
H
VREF_2
AGND
AGND
CD2 3 _1
CD1 3 _2
C6 3 _2
CD2 4 _1
NC
C4 4 _2
RST
TSCA
G
VREF_1
VCCA
VCCA
CD1 3 _1
C7 3 _1
C5 3 _2
CD1 4 _1
C7 4 _1
INT_2
NC
PCLK/
DCL
F
VIN 3 _1
VIN 2 _2
VIN 3 _2
NC
C6 3 _1
NC
CD1 1 _1
C6 4 _1
INT_1
VCCD
DIO_1/
S1_1
E
VOUT 3 _1
VOUT 2 _2
VOUT 3 _2
CD1 2 _1
NC
C3 2 _2
CD2 1 _1
C5 1 _1
C3 1 _2
DGND
DCLK_1/
S0_1
D
NC
NC
NC
CD2 2 _1
C6 2 _1
C4 2 _2
C3 1 _1
C6 1 _1
C4 1 _2
CS_1/
PG_1
DIO_2/
S1_2
C
NC
NC
NC
C3 2 _1
C7 2 _1
C5 2 _2
C4 1 _1
C7 1 _1
C5 1 _2
CS_2/
PG_2
DCLK_2/
S0_2
B
VOUT 1 _1
VOUT 2 _1
VOUT 1 _2
C4 2 _1
CD1 2 _2
C6 2 _2
VCCD
CD1 1 _2
C6 1 _2
MCLK_1/
E1_1
MCLK_2/
E1_2
A
VIN 1 _1
VIN 2 _1
VIN 1 _2
C5 2 _1
CD2 2 _2
C7 2 _2
DGND
CD2 1 _2
C7 1 _2
CHCLK_1
CHCLK_2
1
2
3
6
7
4
5
7
Zarlink Semiconductor Inc.
8
9
10
11
Le58083
Data Sheet
Table 1. Le58083 Octal SLAC™ Device Pin Names and Numbers
Pin Name
Pin #
Pin Name
Pin #
Pin Name
Pin #
VIN1_1
A1
CD14_2
J8
C51_1
E8
VIN2_1
A2
CD21_1
E7
C52_1
VIN3_1
F1
CD22_1
D4
VIN4_1
L1
CD23_1
VIN1_2
A3
VIN2_2
Pin Name
Pin #
Pin Name
Pin #
CHCLK_1
A10
VCCD
B7
A4
CHCLK_2
A11
VCCD
F10
C53_1
L4
MCLK_1/E1_1
B10
AGND
H2
H4
C54_1
L7
MCLK_2/E1_2
B11
AGND
H3
CD24_1
H7
C51_2
C9
CS_1/PG_1
D10
AGND
J3
F2
CD21_2
A8
C52_2
C6
CS_2/PG_2
C10
DGND
L6
VIN3_2
F3
CD22_2
A5
C53_2
G6
DCLK_1/S0_1
E11
DGND
A7
VIN4_2
L2
CD23_2
J5
C54_2
J9
DCLK_2/S0_2
C11
DGND
E10
VOUT1_1
B1
CD24_2
K8
C61_1
D8
DIO_1/S1_1
F11
NC
C1
VOUT2_1
B2
C31_1
D7
C62_1
D5
DIO_2/S1_2
D11
NC
C2
VOUT3_1
E1
C32_1
C4
C63_1
F5
INT_1
F9
NC
C3
VOUT4_1
K1
C33_1
J4
C64_1
F8
INT_2
G9
NC
D1
VOUT1_2
B3
C34_1
J7
C61_2
B9
PCLK/DCL
G11
NC
D2
VOUT2_2
E2
C31_2
E9
C62_2
B6
FS/FSC
J10
NC
D3
VOUT3_2
E3
C32_2
E6
C63_2
H6
DRA/DD
L10
NC
J1
VOUT4_2
K2
C33_2
K5
C64_2
K9
DRB
K10
NC
J2
VREF_1
G1
C34_2
L8
C71_1
C8
DXA/DU
K11
NC
L3
VREF_2
H1
C41_1
C7
C72_1
C5
DXB
L11
NC
F4
CD11_1
F7
C42_1
B4
C73_1
G5
TSCA
H11
NC
E5
CD12_1
E4
C43_1
K4
C74_1
G8
TSCB
J11
NC
F6
CD13_1
G4
C44_1
K7
C71_2
A9
RST
H10
NC
H8
CD14_1
G7
C41_2
D9
C72_2
A6
VCCA
G2
NC
G10
CD11_2
B8
C42_2
D6
C73_2
J6
VCCA
G3
CD12_2
B5
C43_2
L5
C74_2
L9
VCCA
K3
CD13_2
H5
C44_2
H9
VCCD
K6
8
Zarlink Semiconductor Inc.
Le58083
Data Sheet
PIN DESCRIPTIONS
Pin Names
AGND, DGND
CD1C_X,
CD2C_X
Type
Power
Inputs/Outputs
Description
Separate analog and digital grounds are provided to allow noise isolation; however, the two
grounds are connected inside the part, and the grounds must also be connected together on
the circuit board.
Control and Data. CD1 and CD2 are TTL compatible programmable Input or Output (I/O)
ports. They can be used to monitor or control the state of SLIC device or any other device
associated with the subscriber line interface. The direction, input or output, is programmed
using MPI Command 54/55h or GCI Command SOP 8. As outputs, CD1 and CD2 can be used
to control relays, illuminate LEDs, or perform any other function requiring a latched TTL
compatible signal for control. In PCM/MPI mode, the output state of CD1 and CD2 is written
using MPI Command 52h. In GCI mode, the output state of CD1 and CD2 is determined by
the C1 and C2 bits contained in the down stream C/I channel for the respective channel. As
inputs, CD1 and CD2 can be processed by the Le58083 Octal SLAC device (if programmed
to do so). CD1 can be debounced before it is made available to the system. The debounce
time is programmable from 0 to 15 ms in 1 ms increments using MPI Command C8/C9h and
GCI Command SOP 11. CD2 can be filtered using the up/down counter facility and
programming the sampling interval using MPI Command E8/E9h or GCI Command SOP 12.
Additionally, CD1 can be demultiplexed into two separate inputs using the E1 demultiplexing
function. The E1 demultiplexing function of the Le58083 Octal SLAC device was designed to
interface directly to Zarlink SLIC devices supporting the ground key function. With the proper
Zarlink SLIC device and the E1 function of the Le58083 Octal SLAC device enabled, the
CD1 bit can be demultiplexed into an Off-Hook/Ring Trip signal and Ground Key signal. In the
demultiplex mode, the second bit, Ground Key, takes the place of the CD2 as an input. The
demultiplexed bits can be debounced (CD1) or filtered (CD2) as explained previously. A more
complete description of CD1, CD2, debouncing, and filtering functions is contained in the
Operating the Le58083 Octal SLAC Device section on page 30.
Once the CD1 and CD2 inputs are processed (Debounced, Filtered and/or Demultiplexed) by
the Le58083 Octal SLAC device, the information can be accessed by the system in two ways
in the PCM/MPI mode: 1) on a per channel basis along with C3, C4, and C5 of the specific
channel using MPI Command 53h, or 2) by using MPI Command 4D/4Fh, which obtain the
CD1 and CD2 bits from all four channels, of a selected four-channel, simultaneously. This
feature reduces the processor overhead and the time required to retrieve time-critical signals
from the line circuits, such as off-hook and ring trip. With this feature, hookswitch status and
ring trip information, for example, can be obtained from four channels of a Le58083 Octal
SLAC device with one read command.
C3C_X,
C4C_X,
Inputs/Outputs
C5C_X
C6C_X,
C7C_X
CHCLK_X
In the GCI mode, the processed CD1 and CD2 inputs are transmitted upstream on the CD1
and CD2 bits for the respective analog channel, 1 or 2, using the C/I channel.
Control. C3, C4, and C5 are TTL-compatible programmable Input or Output (I/O) ports. They
can be used to monitor or control the state of the SLIC device or any other device associated
with subscriber line interface. The direction, input or output, is programmed using MPI
Command 54/55h or GCI Command SOP 8. As outputs, C3, C4, and C5 can be used to
control relays, illuminate LEDs, or perform any other function requiring a latched TTL
compatible signal for control. In PCM/MPI mode, the output state of C3, C4, and C5 is written
using MPI Command 52h. In GCI mode, the output state of C3, C4, and C5 is determined by
the C3, C4, and C5 bits contained in the down stream C/I channel for the respective analog
channel. As inputs, C3, C4, and C5 can be accessed by the system in PCM/MPI mode by
using MPI Command 53h. In GCI mode, C3 is transmitted upstream, along with CD1 and
CD2, for the respective analog channel using C3 of the C/I channel. Also, in GCI mode, C3,
C4, and C5 can be read along with CD1 and CD2 using GCI Command SOP 10.
Outputs
Additional Control outputs.
Output
Chopper Clock. This output provides a 256 kHz or a 292.57 kHz, 50% duty cycle, TTLcompatible clock for use by up to four SLIC devices with built-in switching regulators. The
CHCLK frequency is synchronous to the master clock, but the phase relationship to the
master clock is random.
9
Zarlink Semiconductor Inc.
Le58083
Pin Names
Type
Data Sheet
Description
Chip Select/PCM-GCI. The CS/PG input along with the DCLK/S0 input are used to determine
the operating state of the programmable PCM/GCI interface. On power up, the Le58083 Octal
SLAC device will initialize to GCI mode if CS/PG is low and there is no toggling (no high to
low or low to high transitions) of the DCLK/S0 input. The device will initialize to the PCM/MPI
mode if either CS is high or DCLK is toggling.
CS_X/PG_X
Input
Input
DCLK_X/S0_X
Input
DIO_X/S1_X
Input/Output
Input
Inputs
DRA/DD, DRB
Input
Outputs
DXA/DU, DXB
Output
Input
FS/FSC
Input
Once the device is in PCM/MPI mode, it is ready to receive commands through its serial
interface pins, DIO and DCLK. Once a valid command has been sent through the MPI serial
interface, GCI mode cannot be entered unless a hardware reset is asserted or power is
removed from the part. If a valid command has not been sent since the last hardware reset or
power up, then GCI mode can be re-entered (after a delay of one PCM frame) by holding CS/
PG low and keeping DCLK static. While the part is in GCI mode, then CS/PG going high or
DCLK toggling will immediately place the device in PCM/MPI mode.
In the PCM/MPI mode, the Chip Select input (active Low) enables the device so that control
data can be written to or read from the part. The channels selected for the write or read
operation are enabled by writing 1s to the appropriate bits in the Channel Enable Registers of
the Le58083 Octal SLAC device prior to the command. See EC1, EC2, EC3, EC4. of the
Channel Enable Register and Command 4A/4Bh for more information. If Chip Select is held
Low for 16 rising edges of DCLK, a hardware reset is executed when Chip Select returns
High.
Data Clock. In addition to providing both a data clock input and an S0 GCI address input,
DCLK/S0 acts in conjunction with CS/PG to determine the operational mode of the system
interface, PCM/MPI or GCI. See CS/PG for details.
In the PCM/MPI mode, the Data Clock input shifts data into and out of the microprocessor
interface of the Le58083 Octal SLAC device. The maximum clock rate is 8.192 MHz.
Select Bit 0. In GCI mode, S0 is one of two inputs (S0, S1) that is decoded to determine on
which GCI channel pair a four-channel group of the Le58083 Octal SLAC device transmits and
receives data.
Data Input/Output. In the PCM/MPI mode, control data is serially written into and read out of
the Le58083 Octal SLAC device via the DIO pin, most significant bit first. The Data Clock
determines the data rate. DIO is high impedance except when data is being transmitted from
the Le58083 Octal SLAC device.
Select Bit 1. In GCI mode, S1 is the second of two inputs (S0, S1) that is decoded to determine
on which GCI channel pair a four-channel group of the Le58083 Octal SLAC device transmits
and receives data.
PCM Data Receive (A/B). In the PCM/MPI mode, the PCM data is serially received on either
the DRA or DRB port during user-programmed time slots. Data is always received with the
most significant bit first. For compressed signals, 1 byte of data for each channel is received
every 125 µs at the PCLK rate. In the Linear mode, 2 consecutive bytes of data for each
channel are received every 125 µs at the PCLK rate.
GCI Data Downstream. In GCI mode, the B1, B2, Monitor and SC channel data is serially
received, from the individual channels, on the Data Downstream input for all four channels of
the Le58083 Octal SLAC device. The Le58083 Octal SLAC device requires four of the eight
GCI channels for operation. The four GCI Channels, out of the eight possible, are determined
by the S0 and S1 inputs. Data is always received with the most significant bit first. 4 bytes of
data for each GCI channel is received every 125 µs at the 2.048 Mbit/s data rate.
PCM Data Transmit. In the PCM/MPI mode, the transmit data, from the individual channels,
is sent serially out on either the DXA or DXB port or on both ports during user-programmed
time slots. Data is always transmitted with the most significant bit first. The output is available
every 125 µs and the data is shifted out in 8-bit (16-bit in Linear or PCM Signaling mode)
bursts at the PCLK rate. DXA and DXB are High impedance between time slots, while the
device is in the Inactive mode with no PCM signaling, or while the Cutoff Transmit Path bit
(CTP) is on.
GCI Data Upstream. In the GCI mode, the B1, B2, Monitor and SC channel data is serially
transmitted on the Data Upstream output of the Le58083 Octal SLAC device. Which GCI
channels the device uses is determined by the S0 and S1 inputs. Data is always transmitted
with the most significant bit first. 4 bytes of data for each GCI channel is transmitted every 125
µs at the DCL rate.
Frame Sync. In the PCM/MPI mode, the Frame Sync (FS) pulse is an 8 kHz signal that
identifies Time Slot 0 and Clock Slot 0 of a system’s PCM frame. The Le58083 Octal SLAC
device references individual time slots with respect to this input, which must be synchronized
to PCLK.
Frame Sync. In GCI mode, the Frame Sync (FSC) pulse is an 8 kHz signal that identifies the
beginning of GCI channel 0 of a system’s GCI frame. The Le58083 Octal SLAC device
references individual GCI channels with respect to this input, which must be synchronized to
DCL.
10
Zarlink Semiconductor Inc.
Le58083
Pin Names
INT_X
MCLK_X/E1_X
Type
Output
Input/Output
NC
—
Input
PCLK/DCL
Input
RST
Input
TSCA, TSCB
Outputs
VCCA, VCCD
Power
VINC_X
Inputs
VOUTC_X
Outputs
VREF_X
Output
Data Sheet
Description
Interrupt. INT is an active Low output signal, which is programmable as either TTL-compatible
or open drain. The INT output goes Low any time one of the input bits in the Real Time Data
register changes state and is not masked. It also goes Low any time new transmit data
appears if this interrupt is armed. INT remains Low until the appropriate register is read via
the microprocessor interface, or the Le58083 Octal SLAC device receives either a software
or hardware reset. The individual CDxC bits in the Real Time Data register can be masked
from causing an interrupt by using MPI Command 6C/6Dh or GCI Command SOP 14. The
transmit data interrupt must be armed with a bit in the Operating Conditions Register.
Master Clock/Enable CD1 Multiplex. In PCM/MPI mode only, the Master Clock can be a 1.536
MHz, 1.544 MHz, or 2.048 MHz (times 1, 2, or 4) clock for use by the digital signal processor.
If the internal clock is derived from the PCM Clock Input (PCLK) or if GCI mode is selected,
this pin can be used as an E1 output to control Zarlink SLIC devices having multiplexed hook
switch and ground key detector outputs.
No connect. This pin is not internally connected.
PCM Clock. In the PCM/MPI mode, the PCM clock determines the rate at which PCM data is
serially shifted into or out of the PCM ports. PCLK is an integer multiple of the frame sync
frequency. The maximum clock frequency is 8.192 MHz and the minimum clock frequency is
128 kHz for dual PCM highway versions and 256 kHz for single PCM highway versions. The
minimum clock rate must be doubled if Linear mode or PCM signaling is used. PCLK
frequencies between 1.03 MHz and 1.53 MHz are not allowed. Optionally, the digital signal
processor clock can be derived from PCLK rather than MCLK. In PCM/MPI mode, PCLK can
be operated at twice the PCM data rate in the Double PCLK mode (bit 1 of PCM/MPI
Command C8/C9h).
GCI Data Clock. In GCI mode, DCL is either 2.048 MHz or 4.096 MHz, which is an integer
multiple of the frame sync frequency. Circuitry internal to the Le58083 Octal SLAC device
monitors this input to determine which frequency is being used, 2.048 MHz or 4.096 MHz.
When 4.096 MHz clock operation is detected, internal timing is adjusted so that DU and DD
operate at the 2.048 Mbit/s rate.
Reset. A logic Low signal at this pin resets both four-channel groups of the Le58083 Octal
SLAC device to their default state.
Time Slot Control. The Time Slot Control outputs are open-drain outputs (requiring pull-up
resistors to VCCD) and are normally inactive (high impedance). In the PCM/MPI mode, TSCA
or TSCB is active (low) when PCM data is transmitted on the DXA or DXB pin, respectively.
In GCI mode, TSCA is active (low) during the two GCI time slots selected by the S1 and S0.
Analog and digital power supply inputs. VCCA and VCCD are provided to allow for noise
isolation and proper power supply decoupling techniques. For best performance, all of the
VCC power supply pins should be connected together at the connector of the printed circuit
board.
Analog Input. The analog voice band signal is applied to the VIN input of the Le58083 Octal
SLAC device. The VIN input is biased at VREF by a large internal resistor. The audio signal
is sampled, digitally processed and encoded, and then made available at the TTL-compatible
PCM output (DXA or DXB) or in the B1 and B2 of the GCI channel. If the digitizer saturates in
the positive or negative direction, VIN is pulled by a reduced resistance toward AGND or
VCCD, respectively.
Analog Output. The received digital data at DRA/DRB or DD (GCI mode) is processed and
converted to an analog signal at the VOUT pin.The VOUT voltages are referenced to VREF.
Analog Voltage Reference. The VREF output is provided in order for an external capacitor to be
connected from VREF to ground, filtering noise present on the internal voltage reference.
VREF is buffered before it is used by internal circuitry. The voltage on VREF and the output
resistance are given in Electrical Characteristics, on page 13. The leakage current in the
capacitor must be low.
11
Zarlink Semiconductor Inc.
Le58083
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to absolute maximum ratings for extended periods can affect device reliability.
Storage Temperature
–60° C < TA < +125° C
Ambient Temperature, under Bias
Ambient relative humidity (non condensing)
VCCA with respect to AGND
5 to 95%
–0.4 to + 4.0 V
VCCA with respect to VCCD
±0.4 V
VCCD with respect to DGND
–0.4 to + 4.0 V
–0.4 V to (VCCA + 0.4 V)
–40° C < TA < +85° C
VIN with respect to AGND
AGND with respect to DGND
Digital pins with respect to DGND
Total combined CD1–C7 current for each four-channel group:
Source from VCCD
Sink into DGND
Latch up immunity (any pin)
Total VCC current if rise rate of VCC > 0.4 V/µs
±50 mV
–0.4 to 5.5 V or VCCD + 2.37 V, whichever is smaller
40 mA
40 mA
± 100 mA
1.0 A
Package Assembly
The green package devices are assembled with enhanced environmental, compatible lead-free, halogen-free, and antimony-free
materials. The leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer leadfree board assembly processes. The peak soldering temperature should not exceed 245°C during printed circuit board assembly.
Refer to IPC/JEDEC J-Std-020B Table 5-2 for the recommended solder reflow temperature profile.
OPERATING RANGES
Zarlink guarantees the performance of this device over commercial (0º C to 70º C) and industrial (−40º C to 85º C) temperature
ranges by conducting electrical characterization over each range and by conducting a production test with single insertion
coupled to periodic sampling. These characterization and test procedures comply with section 4.6.2 of Bellcore GR-357-CORE
Component Reliability Assurance Requirements for Telecommunications Equipment
Environmental Ranges
Ambient Temperature
−40° C < TA < +85° C
Ambient Relative Humidity
15 to 85%
Electrical Ranges
+3.3 V ± 5%
VCCD ± 50 mV
Analog Supply VCCA
Digital Supply VCCD
+3.3 V ± 5%
DGND
AGND
CFIL Capacitance: VREF_X to AGND
Digital Pins
0V
±10 mV
0.1 µF ± 20%
DGND to +5.25 V
12
Zarlink Semiconductor Inc.
Le58083
Data Sheet
ELECTRICAL CHARACTERISTICS
Typical values are for TA = 25º C and nominal supply voltages. Minimum and maximum values are over the temperature and
supply voltage ranges shown in Operating Ranges, except where noted.
Symbol
VIL
Digital Input Low voltage
Parameter Descriptions
VIH
Digital Input High voltage
IIL
Digital Input leakage current
Pins connected to one channel group
0 < V < VCCD
Otherwise
Pins connected to both channel groups
0 < V < VCCD
Otherwise
VOL
Digital Output Low voltage
CD1–C7 (IOL = 4 mA)
CD1–C7 (IOL = 8 mA)
TSCA/ TSCB (IOL =14 mA)
Other digital outputs (IOL = 2 mA)
VOH
Digital Output High voltage
CD1–C7 (IOH = 4 mA)
CD1–C7 (IOH = 8 mA)
Other digital outputs (IOH = 400 µA)
VIR
VIOS
Max
2.0
Digital Input hysteresis
GIN
Typ
0.8
VHYS
IOL
Min
–7
–120
+7
+180
–14
–240
+14
+360
0.16
0.25
0.34
0.4
0.8
0.4
0.4
VCCD – 0.4 V
VCCD – 0.8 V
2.4
Digital Output leakage current (Hi-Z state)
Pins connected to one channel group
0 < V < VCCD
Otherwise
Pins connected to both channel groups
0 < V < VCCD
Otherwise
Input attenuator gain
DGIN = 0
DGIN = 1
Analog input voltage range (Relative to VREF)
AX = 0 dB, attenuator on (DGIN = 0)
AX = 6.02 dB, attenuator on (DGIN = 0)
AX = 0 dB, attenuator off (DGIN = 1)
AX = 6.02 dB, attenuator off (DGIN = 1)
–7
–120
+7
+180
–14
–240
+14
+360
0.6438
1
Unit
V
µA
V
1
V
1
µA
6
V/V
±1.584
±0.792
±1.02
±0.51
Vpk
Offset voltage allowed on VIN
–50
50
mV
Analog input impedance to VREF, 300 to 3400 Hz
600
1400
kΩ
IIP
Current into analog input for an input voltage of 3.3 V
50
115
IIN
Current out of analog input for an input voltage of –0.3 V
50
130
ZOUT
VOUT output impedance
1
Allowable capacitance, VOUT to AGND
10
Ω
pF
4
mApk
IOUT
VOUT output current (F< 3400 Hz)
VREF_X output open circuit voltage (leakage < 20 nA)
ZREF
VREF_X output impedance (F
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