LE75183AFQC

™ Le75183 Line Card Access Switch VE750 Series Data Sheet Features Document ID#:081126 • Small size/surface-mount packaging • Monolithic IC reliability • Low impulse noise • Make-before-break, break-before-make operation • Clean, bounce-free switching • Low, matched ON-resistance • Built-in current limiting, thermal shutdown and SLIC protection Version Device Le75183BFQC Le75183BFSC • No EMI Le75183CZFSC • Latched logic level inputs, no drive circuitry • Only one external protector required • TTL logic control compatible • Default power up state • DAML • HFC/FITL Tray 28 Pin SOIC (GULL) Tube 1. The green package meets RoHS Directive 2002/95/EC of the European Council to minimize the environmental impact of electrical equipment. 2. For delivery using a tape and reel packing system, add a "T" suffix to the OPN (Ordering Part Number) when placing an order. Description The VoiceEdge™ family VE750 series of Line Card Access Switches (LCAS), which includes the Le75181, Le75282 and Le75183 devices, is a family of monolithic solid-state switches that is designed to provide both power ringing access and test access on the analog line card. These devices, while not a pinfor-pin replacement for the traditional electromechanical relay (EMR) solution, provide the equivalent switching functionality. The VE750 series of LCAS is meant as a solid-state alternative to the EMRs. Related Literature • 32 Pin QFN LE75183AFSC Applications PBX Tube LE75183CFQC Battery monitor, all OFF state upon loss of battery • 20 Pin SOIC (GULL) Le75183AFQC • DLC Packing2 Le75183CDSC 5 V only operation, very low power consumption • Package Type Le75183ADSC • Central office April 2011 Ordering Information Le75183BDSC • 6 081123 Le75282 Dual Intelligent Line Card Access Switch Data Sheet • 081105 Le75181 Ringing Access Switch Data Sheet • 080754 Le58QL061/063 QLSLAC Data Sheet • 080676 Le5711 Dual SLIC Data Sheet • 081047 Le5712 Dual SLIC Data Sheet The Le75183A/B/C devices are pin-for-pin compatible with Zarlink’s L7583A/B/C devices. Zarlink also offers a range of compatible SLIC devices and codec/filters that can be used with the VE750 series LCAS for complete line card solutions that can be used worldwide in analog line card applications. 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2007-2010, Zarlink Semiconductor Inc. All Rights Reserved. Le75183 Data Sheet Table of Contents 1.0 Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.0 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.0 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.0 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.0 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 Environmental Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 Electrical Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.3 Handling Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.1 Summary of Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.2 Supply Currents and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.0 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.1 Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.0 Zero Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9.0 Switching Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10.0 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11.0 Loss of Battery Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 12.0 Impulse Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 13.0 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 13.1 Integrated SLIC Device Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 13.1.1 Diode Bridge/SCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 13.1.2 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 13.1.3 Temperature Shutdown Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 13.1.4 External Secondary Protector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 14.0 Typical Performance Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 15.0 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 16.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 16.1 28-Pin, Plastic SOIC (GULL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 16.2 20-Pin, Plastic SOIC (GULL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 16.3 32-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 17.0 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 17.1 Revision A1 to B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 17.2 Revision B1 to C1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 17.3 Revision C1 to C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 17.4 Revision C2 to Ver 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 17.5 Revision Ver 5 to Ver 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2 Zarlink Semiconductor Inc. Le75183 Data Sheet List of Figures Figure 1 - Le75183A/C Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2 - Le75183B Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3 - Protection Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 4 - Switches 3, 7, 9, and 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 5 - Switch 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 6 - Switches 1, 2, and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 7 - Switches 6, 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 8 - Typical LCAS Application, A/C Versions, Idle or Talk State Shown . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 Zarlink Semiconductor Inc. Le75183 1.0 Data Sheet Product Description The Le75183A/B/C Line Card Access Switch is a monolithic solid-state device providing the equivalent switching functionality of three 2 form C switches. The Le75183 is designed to provide power ringing access, line test access (test out), and SLIC test access (test in) to tip and ring in central office, digital loop carrier, private branch exchange, digitally added main line, and hybrid fiber coax/fiber-in-the-loop analog line card applications. An additional pair of solid-state contacts are also available to provide access for testing of the ringing generator. The Le75183A/B has seven states: the idle talk state (line break switches closed, all other switches open), the power ringing state (ringing access switches closed, all other switches open), loop access (test out) state (loop access (test out) switches closed, all other switches open), SLIC test state (test in switches closed, all other switches open), simultaneous loop and SLIC access state (loop and test in switches closed, all others open), ringing generator test state (ring test switches closed, all others open), and an all OFF state. The seven states in the Le75183A/B are also in the Le75183C, with an additional simultaneous test-out and ring-test state, making the Le75183C appropriate for digital loop carrier and other Telcordia TR-57 applications. The Le75183 offers break-before-make or make-before-break switching, with simple logic level input control. Because of the solid-state construction, voltage transients generated when switching into an inductive ringing lead during ring cadence or ring trip are minimized, possibly eliminating the need for external zero cross switching circuitry. State control is via logic level inputs, so no additional driver circuitry is required. The line break switch is a linear switch that has exceptionally low ON-resistance and an excellent ON-resistance matching characteristic. The ringing access switch has a breakdown voltage rating >480 V which is sufficiently high, with proper protection, to prevent breakdown in the presence of a transient fault condition (i.e., passing the transient on to the ringing generator). Incorporated into the Le75183A and Le75183C is a diode bridge/SCR clamping circuit, current-limiting circuitry, and a thermal shutdown mechanism to provide protection to the SLIC device and subsequent circuitry during fault conditions. This is shown in block diagram as version A/C. Positive and negative lightning is reduced by the current-limiting circuitry and steered to ground via diodes and the integrated SCR. Power cross is also reduced by the current-limiting and thermal shutdown circuits. The Le75183B version provides only an integrated diode bridge along with current limiting and thermal shutdown (see block diagram for version B). This will cause positive faults to be directed to ground and negative faults to battery. In either polarity, faults are reduced by the current-limit and/or thermal shutdown mechanisms. To protect the Le75183 from an overvoltage fault condition, use of a secondary protector is required. The secondary protector must limit the voltage seen at the tip/ring terminals to prevent the breakdown voltage of the switches from being exceeded. To minimize stress on the solid-state contacts, use of a foldback- or crowbar- type secondary protector is recommended. With proper choice of secondary protection, a line card using the Le75183 will meet all relevant ITU-T, LSSGR, FCC, or UL* protection requirements. The Le75183 operates off of a 5 V supply only. This gives the device extremely low idle and active power dissipation and allows use with virtually any range of battery voltage. This makes the Le75183 especially appropriate for remote power applications such as DAML or FOC/FITL or other Telcordia TA 909 applications where power dissipation is particularly critical. A battery voltage is also used by the Le75183, only as a reference for the integrated protection circuit. The Le75183 will enter an all OFF state upon loss of battery. During power ringing, to turn on and maintain the ON state, the ring access switch and ring test switch will draw a nominal 2 mA from the ring generator. The default power up state of Le75183 is in all OFF state, unless otherwise being overwritten by external controls. The Le75183 device is packaged in a 20-pin, plastic SOIC (GULL) (Le75183ADSC/BDSC/CDSC), a 32-pin QFN (Le75183AFQC/BFQC/CFQC), and a 28-pin, plastic SOIC (GULL) (Le75183AFSC/BFSC/CZFSC). The 28-pin package is available to support existing designs. For new designs, it may be advantageous to use the other two smaller size packages. 4 Zarlink Semiconductor Inc. Le75183 2.0 Data Sheet Block Diagrams Le75183A/C VBAT FGND SCR & Trip Circuit SW1 SW2 TTESTin RTESTin RBAT TBAT SW3 TLINE SW4 SW5 SW6 TRINGING RLINE RRINGING SW7 TTESTout SW8 RTESTout SW10 SW9 LATCH VDD INTESTin Control Logic TSD INRING INTESTout DGND Figure 1 - Le75183A/C Block Diagram Le75183B VBAT FGND TTESTin SW1 SW2 RBAT TBAT TLINE SW3 SW4 SW5 SW6 RLINE RRINGING TRINGING SW7 TTESTout RTESTin SW8 SW9 SW10 RTESTout LATCH VDD Control Logic TSD INTESTin INRING INTESTout DGND Figure 2 - Le75183B Block Diagram 5 Zarlink Semiconductor Inc. Le75183 NC VBAT NC RTESTin 31 30 29 28 27 26 NC NC 32 1 FGND Top View NC TTESTin Connection Diagrams 25 24 RBAT 23 NC 3 22 RLINE 4 21 NC TBAT 2 NC TLINE 32-pin QFN NC 5 TRINGING 6 10 11 12 13 14 15 INTESTout INRING INTESTin NC NC 2 27 NC 18 RBAT NC 3 26 NC 17 RLINE NC 4 25 NC 16 RRINGING TTESTin 5 24 RTESTin 15 RTESTout TBAT 6 23 RBAT 14 LATCH TLINE 7 22 RLINE TRINGING 8 21 NC NC 9 20 RRINGING TTESTout 10 19 RTESTout NC 11 18 LATCH VDD 12 17 INTESTin TSD 13 16 INRING DGND 14 15 INTESTout TTESTin 2 19 TBAT 3 TLINE 4 TRINGING 5 7 RTESTout 17 16 RTESTin VBAT NC 18 VBAT 20 6 NC 28 1 TTESTout 19 FGND 1 FGND 20-Pin SOIC RRINGING LATCH 9 DGND 8 TSD 7 EXPOSED PAD NC NC TTESTout 20 VDD 3.0 Data Sheet VDD 8 13 INTESTin TSD 9 12 INRING DGND 10 11 INTESTout 28-Pin SOIC 6 Zarlink Semiconductor Inc. Le75183 3.1 Data Sheet Pin Descriptions Pin Name Type Description DGND Ground Digital ground. FGND Ground Fault ground. INRING Input Logic level switch input control. Internally 75 kΩ typical pull up. INTESTIN Input Logic level switch input control. Internally 75 kΩ typical pull down. INTESTOUT Input Logic level switch input control. Internally 75 kΩ typical pull up. LATCH Input Data input control, active-high, transparent low. Internally 75 kΩ typical pull down. NC — No connection. RBAT Input/Output Connect to RING on SLIC side. RLINE Input/Output Connect to RING on line side. RRINGING Input/Output Connect to ringing generator. RTESTin Input/Output Test (in) access on RING. RTESTout Input/Output Test (out) access on RING. TBAT Input/Output Connect to TIP on SLIC side. TLINE Input/Output Connect to TIP on line side. TRINGING Input/Output Connect to return ground for ringing generator. TTESTin Input/Output Test (in) access on TIP. TTESTout Input/Output Test (out) access on TIP. TSD Input/Output Temperature shutdown pin. Can be used as a logic level input or an output. See Tables 12 and 13, Truth Tables, and the Switching Behavior section of this data sheet for input pin description. As an output flag, will read HIGH when the device is in its operational mode and LOW in the thermal shutdown mode. To disable the thermal shutdown mechanism, tie this pin to HIGH (not recommended) VBAT Battery Battery voltage. Used as a reference for protection circuit. VDD Power 5 V supply. EPAD — Exposed pad in QFN package. No internal electrical connection. Not recommended to make any external electrical connection (such as VBAT or ground) to the EPAD. D: Internally 75 kΩ typical pull down. U: Internally 75 kΩ typical pull up. 7 Zarlink Semiconductor Inc. Le75183 4.0 Data Sheet Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Parameter Min. Max. Unit Operating Temperature Range –40 110 °C Storage Temperature Range –40 150 °C Relative Humidity Range 5 95 % Pin Soldering Temperature (t=10s max) — 260 °C -0.3 7 V — –85 V -0.3 VDD+0.3 V Input-to-output Isolation — 330 V Pole-to-pole Isolation (All except SW6, SW8) — 330 V Pole-to-pole Isolation (Ringing Access Switch, SW8) — 480 V Pole-to-pole Isolation (Ringing Test Switch, SW6) — 260 V 5 V Power Supply Battery Supply Logic Input Voltage ESD Immunity (Human Body Model) JESD22 Class 1C compliant Note: For LCAS in the QFN package, it is desirable that the exposed pad be soldered to an equally sized exposed copper surface (with no further electrical connection such as VBAT or ground) for mechanical stability. 8 Zarlink Semiconductor Inc. Le75183 5.0 Data Sheet Operating Ranges Package Assembly Green package devices are assembled with enhanced, environmental compatible lead-free, halogen-free, and antimony-free materials. The leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer lead-free board assembly processes. The peak soldering temperature should not exceed 245°C during printed circuit board assembly. Refer to IPC/JEDEC J-Std-020B Table 5-2 for the recommended solder reflow temperature profile. 5.1 Environmental Ranges Zarlink guarantees the performance of this device over commercial (0 to 70º C) and industrial (-40 to 85ºC) temperature ranges by conducting electrical characterization over each range and by conducting a production test with single insertion coupled to periodic sampling. These characterization and test procedures comply with section 4.6.2 of Bellcore GR-357-CORE Component Reliability Assurance Requirements for Telecommunications Equipment. −40° to 85°C Ambient Temperature 5.2 Electrical Ranges Supply VDD VBAT* Min. Typ. Max. Unit 4.5 –19 5 — 5.5 –72 V V *VBAT is used only as a reference for internal protection circuitry. If VBAT rises above typically –10 V, the device will enter an all OFF state and remain in this state until the battery voltage drops below typically –15 V. *Applied voltage is 100 Vp-p square wave at 100 Hz. 5.3 Handling Precautions Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Zarlink employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for CDM. However, a standard HBM (resistance = 1500Ω, capacitance = 100 pF) is widely used and therefore can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using these circuit parameters. 9 Zarlink Semiconductor Inc. Le75183 6.0 Electrical Characteristics 6.1 Summary of Assumptions Data Sheet Unless otherwise noted, the test conditions are defined by the Le75183 device application circuit shown in Figure 8 on page 23 with: VBAT = −48 V, VDD = 5.0 V. 6.2 Supply Currents and Power Dissipation Operational State IDD mA Condition LCAS Device Power mW IBAT µA Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. All OFF VDD=5V, VBAT=-48V — 0.760 1.1 — 4 10 — 3.8 6 Power Ringing or Access VDD=5V, VBAT=-48V — 0.850 2.1 — 4 10 — 4.4 11 Idle/Talk VDD=5V, VBAT=-48V — 0.860 1.3 — 4 10 — 4.5 7 Measure Min. Typ. Max. ISWITCH — — 1 7.0 Specifications 7.1 Device Specifications Parameter Test Condition Unit Off-state Leakage Current: +25°C Vswitch (differential) = –320 V to Gnd Vswitch (differential) = –60 V to +260 V +85°C Vswitch (differential) = –330 V to Gnd Vswitch (differential) = –60 V to +270 V ISWITCH — — 1 –40°C Vswitch (differential) = –310 V to Gnd Vswitch (differential) = –60 V to +250 V ISWITCH — — 1 ISWITCH (on) = ±5 mA, ±10 mA ISWITCH (on) = ±5 mA, ±10 mA ISWITCH (on) = ±5 mA, ±10 mA ∆ VON ∆ VON ∆ VON — — — 49 — 37 — 77 — Ω Isolation: +25 °C +85 °C –40 °C Vswitch (both poles) = ±320 V, Logic inputs = Gnd Vswitch (both poles) = ±330 V, Logic inputs = Gnd Vswitch (both poles) = ±310 V, Logic inputs = Gnd Iswitch Iswitch Iswitch — — — — — — 1 1 1 µA dV/dt Sensitivity* — — 200 — V/µs ON-resistance (SW1, SW2): +25 °C +85 °C –40 °C — *Applied voltage is 100 Vp-p square wave at 100 Hz. Not tested in production. Table 1 - Test-In Switches, 1 and 2 10 Zarlink Semiconductor Inc. µA Le75183 Parameter OFF-state Leakage Current: +25°C Test Condition Vswitch (differential) = –320 V to Gnd Vswitch (differential) = –60 V to +260 V Data Sheet Measure Min. Typ. Max. ISWITCH — — 1 Unit µA +85°C Vswitch (differential) = –330 V to Gnd Vswitch (differential) = –60 V to +270 V ISWITCH — — 1 –40°C Vswitch (differential) = –310 V to Gnd Vswitch (differential) = –60 V to +250 V ISWITCH — — 1 ON-resistance (SW3, SW4): +25 °C +85 °C –40 °C TLINE = ±10 mA, ±40 mA, TBAT = –2 V TLINE = ±10 mA, ±40 mA, TBAT = –2 V TLINE = ±10 mA, ±40 mA, TBAT = –2 V ∆ VON ∆ VON ∆ VON — — — 21.5 — 16 — 31 — Ω ON-resistance Match All except Le75183CZFSC Per ON-resistance test condition of SW3, SW4 Magnitude RON_SW3 – RON_SW4 — 0.2 1.0 Ω ON-resistance Match Le75183CZFSC Per ON-resistance test condition of SW3, SW4 Magnitude RON_SW3 – RON_SW4 — 0.2 0.55 Ω ON-state Voltage* (Figure 2, Switch 3) Iswitch = ILIMIT @ 50 Hz/60 Hz VON — — 220 V ON-state Voltage* (Figure 3, Switch 4) Maximum Differential Voltage (Vmax) Foldback Voltage Breakpoint 1 (V1) Foldback Voltage Breakpoint 2 (V2) VON VON VON — 100 V1+0.5 — — — 320 — — V Vswitch (on) = ±10 V Vswitch (on) = ±10 V Iswitch Iswitch 80 — — — — 250 ILIMIT1 Iswitch Iswitch 80 2 — — 250 — mA DC Current Limit (Figure 2, Switch 3): +85 °C –40 °C DC Current Limit (Figure 3, Switch 4): ILIMIT2 mA Dynamic Current Limit (t =