™
Le9502
Ringing Subscriber Line Interface Circuit
VE950 Series
APPLICATIONS
ORDERING INFORMATION
and 5 REN loads
Voice over IP/DSL – Integrated Access Devices, Smart
Residential Gateways, Home Gateway/Router
Cable Telephony – NIU, Set-Top Box, Home Side Box,
Cable Modem, Cable PC
Fiber–Fiber In The Loop (FITL), Fiber to the Home
(FTTH)
Wireless Local Loop, Intelligent PBX, ISDN NT1/TA
FEATURES
Integrated Dual-Channel Device
— Built-in boost switching power supply tracks line voltage
minimizing power dissipation
— Only +3.3 V and +12 V (nominal) required
— Wide range of input voltages (+8 V to +40 V) supported
— Minimal external discrete components
— 44-pin eTQFP package
Ringing
—
—
—
—
—
70 Vpk into 5REN
90 Vpk capable
Sinusoidal or trapezoidal capability
DC offset support
Common differential interface for both channels
World Wide programmability:
— Two-wire AC impedance
— Dual Current Limit
— Loop closure and ring trip thresholds
Five SLIC States, including:
— Low power Standby state
— Reverse Polarity
Package1
Device
Short/Medium Loop: approximately 2000 ft. of 26 AWG,
Le9502BTC
1.
2.
44-pin eTQFP (Green Package)
DESCRIPTION
The Zarlink Le9502 Ringing Subscriber Line Interface Circuit
(RSLIC) device from the VE950 series has enhanced and
optimized features to directly address the requirements of
Voice over Broadband applications. Its goal is to reduce system
level costs, space, and power through higher levels of
integration, and to reduce the total cost of ownership by offering
better quality of service. The Le9502 RSLIC device provides a
totally configurable solution to the BORSCHT functions for two
lines. The resulting system is less complex, smaller, and
denser, yet cost effective with minimal external components.
The Le9502 RSLIC device requires only two power supplies:
+3.3 VDC and nominally +12 VDC. The latter power supply can
range from +8 VDC to +40 VDC, depending on the application.
A single TTL-level clock source drives an external transistor
which controls the ramp voltage that in turn feeds the switching
regulators. Five programmable states are available: Active,
Reverse Polarity, Ringing, Standby, and Disconnect. The DC
feed, two-wire AC input impedance, hook-switch threshold, and
ring trip threshold are programmable via external discrete
components. Binary fault detection is provided upon
application of fault conditions or thermal overload.
BLOCK DIAGRAM
Le9502
081189 Le9500 RSLIC Device Data Sheet
Switching Power
Supply
081208 Le9501 RSLIC Device Data Sheet
2-wire
Tip+Ring
Interface
080696 Le77D11 VoSLIC™ Device Data Sheet
080697 Le78D11 VoSLAC™ Device Sheet
Differential
080716 Le77D11 /Le78D11 Chip Set User’s Guide
080780 Layout Considerations for the Le77D11 and
Le9502 Devices Application Note
Tray
The green package meets RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of
electrical equipment.
For delivery using a tape and reel packing system, add a "T" suffix
to the OPN (Ordering Part Number) when placing an order.
RELATED LITERATURE
Packing2
Codec
Device
Ring
Tip
2-wire to 4-wire
conversion
Codec
Interface
2-wire to 4-wire
conversion
2-wire
Tip+Ring
Interface
Ring
Tip
Switching Power
Supply
Document ID# 081007 Date:
Rev:
G
Version:
Distribution:
Public Document
Sep 18, 2007
3
Le9502
Data Sheet
TABLE OF CONTENTS
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Related Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Two-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Switcher Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Signal Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Fault Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Reference Current Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Supply Currents and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Device Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Line Card Parts List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
44-Pin eTQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Revision A1 to B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Revision B1 to C1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Revision C1 to D1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Revision D1 to E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Revision E1 to F1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Revision F1 to G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Revision G1 to G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Revision G2 to G3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2
Zarlink Semiconductor Inc.
Le9502
Data Sheet
PRODUCT DESCRIPTION
The VE950 series Le9502 RSLIC device uses reliable, dielectrically isolated, fully complementary bipolar technology to
implement BORSCHT functions for short loop applications. Internal power dissipation is minimized by two independent line
voltage tracking, buck-boost switching regulators. Two power supplies are required: 3.3 V and a positive supply (VSW). A TTLlevel clock is required to drive the switching regulator. Five programmable states control loop signaling, transmission, and ringing.
The Le9502 RSLIC device DC current feed limit (ISC) is resistor-programmable up to 45 mA.
Figure 1. Typical Le9502 RSLIC/Codec Application in an 8-Port Integrated Access Device in Customer Premises
Din
1
Dual
RSLIC
Codec
Dout
Dual
RSLIC
PCM I/F
Codec
DCLK/CS
Dual
RSLIC
DSP +
Network
Processor
Loop/Cable
MODEM
WLL
Codec
Din
Dual
RSLIC
Codec
Dout
Data Interfaces
8
Ethernet USB HomePNA
BLOCK DESCRIPTIONS
Figure 2. Le9502 RSLIC Device Block Diagram
F1
Fault
Detection
Signal
Transmission
A1 (TIP)
Two-Wire
Interface
Signal
Conditioning
B1 (RING)
VRINGM
VRINGP
VINP 1
VINM 1
VOUT 1
VHP 1
CFILT 1
LPF 1
DET 1
RTRIP 1
RDC
VREG 1
SD 1
Switcher
Controller
ILS 1
CHS 1
VSW
VRAMP
Control
Logic
C1 1
C2 1
Ref
Current
Generator
ISET
SD 2
Switcher
Controller
ILS 2
CHS 2
Control
Logic
C1 2
C2 2
VREG 2
A2 (TIP)
Signal
Conditioning
Two-Wire
Interface
B2 (RING)
Signal
Transmission
Fault
Detection
DET 2
RTRIP 2
VINP 2
VINM 2
VOUT 2
VHP 2
CFILT 2
LPF 2
F2
BGND 1
BGND 2
AGND
VCC
3
Zarlink Semiconductor Inc.
DSLAM/
HEADEND
Le9502
Data Sheet
Two-Wire Interface
The two-wire interface block provides DC current and sends/receives voice signals to a telephone connected via the Ai(Tip) and
Bi(Ring) pins. The Ai(Tip) and Bi(Ring) pins are also used to send the ringing signal to the telephone. The Le9502 RSLIC device
can also be programmed in Disconnect state to place the Ai and Bi pins at high impedance with the Switching Regulator disabled.
DC Feed
DC feed is controlled in the Le9502 RSLIC device. Only the current limit threshold (ILTH) can be set via the RDC pin. The current
limit threshold can be set from 0 to 30 mA.
Referring to Figure 3, the DC feed curve consists of two distinct regions. The first region is a flat anti-sat region that supplies a
constant Tip-Ring voltage (VAB open). The second region is a constant current region that begins when the loop current reaches
the programmed current limit threshold (ILTH). This region looks like a constant current source with 3.2 kΩ shunt resistor. The
short circuit current is nominally 17.0 mA greater than ILTH.
A block diagram of the DC feed control circuit is shown in Figure 4. In the anti-sat region, current source CS1 creates a constant
reference current, which is limited to sub-voice frequencies by CLPFi. This filtered current is then steered by the Polarity Control,
depending on whether the SLIC mode is Standby, Normal Active, or Reverse Polarity. The steered current then takes one of two
paths to the Level Shift block, where it is used to set VA (TIP) and VB (RING). This voltage from the Level Shift block is buffered
by the output amplifiers and appears at Ai (TIP) and Bi (RING).
When ILOOP/500 becomes greater than ILTH/500, the difference is subtracted from CS1, and again filtered by CLPFi. This reduced
current causes a reduced DC feed voltage. In Standby and Normal Active, Ai (TIP) is held constant, while Bi (RING) is changed
to reduce the feed voltage. In Reverse Polarity, Ai (TIP) and Bi (RING) are swapped. When (ILOOP-ILTH)/500 = CS1, all of the
current from CS1 is subtracted, making the TIP-RING voltage = 0 V. This is the short circuit condition. At least 100 Ω loop and
fuse resistance are required to ensure stability of the Ai (TIP) and Bi (RING) output amplifiers.
The capacitor CLPFi, in conjunction with an internal 25 kΩ resistor (not shown), is used to create a low pass filter for the DC feed
loop. This capacitor should nominally be 4.7 µF, setting a 1.4 Hz pole. The purpose of this capacitor is to stabilize the DC feed
and filter any AC components.
Figure 3. DC Feed Curve
VAB
ILTH
VAB open
(48 V)
I SC = I LTH + 17.0mA
1.4 V
I LTH = -------------------------R DC K DC
17.0 mA
0
ISC
ILOOP
Note:
1.
RDC = external resistor from RDC to AGND
2.
VAB = VAi – VBi Tip-Ring differential voltage
3.
4.
1
KDC = Le9502 RSLIC device DC current gain, which is: K DC = --------500
ISC = Loop short circuit current limit.
5.
ILTH = Loop current limit threshold.
4
Zarlink Semiconductor Inc.
Le9502
Figure 4.
Data Sheet
DC Feed Block Diagram, Active and Standby Modes
VCC
CS1
ILOOP KDC
RDC*
LPFi
Current Mirrors
RS
RDC
ILTH
Ai (TIP)
CLPFi *
KDC
IA
Level Shift
Sum/
Sense
ILOOP
RL
Polarity Control
IB
RS
Bi (RING)
Fi
Note:
* denotes external components.
Ringing
The Le9502 RSLIC device only provides a method for creating internal ringing. Internal ringing is accomplished by applying a
single or differential ringing waveform using the VRINGP and VRINGM pins, and placing the Le9502 RSLIC device into the
ringing state via the device's control bits. When the Le9502 RSLIC device is in the Ringing state, the gain from the Le9502 RSLIC
device's differential ringing input pin to the output, is KR (the ringing voltage gain). The output waveform is a quasi-balanced
waveform as shown below in Figure 5). On the positive half cycle of the input waveform, the Ai (TIP) lead of the Le9502 RSLIC
device is near -4 V, and the Bi (RING) lead is brought negative. Likewise, on the negative half cycle of the input waveform, the
Bi (RING) lead of the Le9502 RSLIC device is held near -4 V, while the Ai (TIP) lead is brought more negative. The low cost
regulator solution, shown in the application circuit on page 20, incorporates the use of a higher power PNP bipolar switching
transistor in the switching circuit that enables the Le9502 to provide a 90 Vpk ringing signal into a lower REN load. The waveform
can be either sinusoidal or trapezoidal under the control of the codec device.
Figure 5.
Ringing Waveforms
+VRING_pk / 2
-VRING_pk/ 2
VRINGM
VRINGP
A. Voltage Applied to VRING Input (VRINGP, VRINGM)
–4 V
–(K R • V RING_pk + 4)
B. Voltage Output at A (TIP) (dashed line) and B (RING) (solid line) Pins
5
Zarlink Semiconductor Inc.
Le9502
Data Sheet
For the reference schematic, Zetex part FZT955 in a SOT-223 package is used. Its VCEO rating is 140 V. The switching efficiency
and overhead voltage of the regulator allows a robust 70 Vpk ringing signal into a 5 REN load with VSW = 12 V.
Switcher Controller
The switcher controller’s main function is to provide a negative power supply (VREG) that tracks Tip and Ring voltage for the 2wire interface. As the Tip and Ring voltage decreases, the switcher will likewise lower VREG. In doing so, the switcher saves power
because the device is not forced to maintain static supply voltage in all states.
The switching power supply controller uses a discontinuous mode, buck-boost voltage converter topology. The frequency of
operation is set by the ISET resistor and the VRAMP capacitor values. An external clock with approximately a 10% duty cycle
drives the gate (base) of a small-signal FET which is used to reset the VRAMP capacitor voltage, creating the ramp voltage used
internally by the switching power supply control circuitry. This clock signal controls the switching supply's operating frequency.
The switcher circuit is nominally designed for 85 kHz operation based on the Application Circuit on page 20.
The duty cycle of the switching transistors is continuously variable up to 90% depending on the magnitude of the error voltage
on the compensation (CHS) pin. The error signal on CHS is compared to the ramp signal. The ramp rate of the VRAMP signal is
set by the ISET resistor (RSET) and the VRAMP capacitor (CRAMP). A 1% RSET resistor should be chosen first (see Signal
Conditioning on page 9) before using the following equation to calculate CRAMP
C RAMP_max = I RAMP_min • [ ( 100% – t CHCLK_max ) ⁄ ( f CHCLK • R SET_max ) ]
where IRAMP_min is the current going through CRAMP, tCHCLK_max is maximum duration of Chopper Clock High Duty Cycle
provided in the specification section, fCHCLK is the frequency of the chopper clock, and RSET_max is RSET_nom * 1.01. The
calculated value for CRAMP is the maximum value that can guarantee the switcher to operate. A NPO dielectric capacitor is
recommended for CRAMP.
When the external clock signal goes from a logic Low to a logic High, it will pull VRAMP voltage low which causes internal clock
(from the square wave converter) to go Low, turning on the external power switch. When the external clock signal goes from High
to Low, CRAMP will charge up. When the VRAMP voltage exceeds internal voltage threshold, the rising edge of the internal clock
from the square wave converter will reset the current limit latch getting it ready for the next cycle and turn off the external power
switch. Also on a cycle-by-cycle basis, one of the following three events will shut off the power switch, depending on which event
occurs first:
a) The VRAMP voltage exceeds the error voltage that is integrated on the CHS node (normal voltage feedback operation.)
b) The VRAMP voltage exceeds the internal voltage threshold.
c) The power switch current limit threshold is reached (set by RLIM).
Cycle-by-cycle current limiting is provided by the current sense ILSi pin which senses the external power switch current through
the resistor RLIM. If this pin exceeds VTILS, nominally −0.28 V with respect to VSW, the switching supply will set the current limit
latch and shut off the external switch drive until the next time the VRAMP pin is pulled Low to reset the latch. Thus the peak
inductor current, and also peak switching converter power output can be controlled on a cycle-by-cycle basis and set by the
equation ILIM= (VTILS)/RLIM.
This sensing configuration has the added benefit that if the clock signal is removed for some reason, the power switch cannot be
left on indefinitely. Leaving the ILSi pin unconnected or shorting this pin to VSW will disable current limiting, but is not
recommended.
A leading edge blanking filter is added at the output of the latch to ignore the first 150 ns of a current limit event. This feature is
used to ignore a false current trip that may be caused by the power switch driving the reverse recovery charge (QRR) of the
external power rectifier.
The on chip driver is designed to drive either an external PNP or a PMOS power device. Its output drive is clamped between
7-9 V below VSW, and can source or sink approximately 100 mA. The driver has approximately 50 Ω of source resistance. The
additional resistance should be added from the SDi pin to the base of the external power device if a PNP is used to limit base
drive for optimal efficiency.
When using a PMOS power switch, the SDi pin will be able to drive approximately 100 mA of drive current to the gate of the
PMOS device, and an internal clamp will limit the drive between 7-9 V. To keep system losses to a minimum, it is recommended
that low gate charge be given higher consideration over low rDS(on) when selecting a power PMOS device for your application.
6
Zarlink Semiconductor Inc.
Le9502
Figure 6.
Data Sheet
Switching Power Supply Block Diagram
VSW
VSW
+
LEADING
EDGE
BLANKING
FILTER
VCC
I
8V
800K
48 V
I
in active
800K
in active
LATCH
0.28 V
VRING ***
ILSi
RESET
in ringing
DDi*
VREF
1.4 V
CLAMP
VSW
DRIVER
-
CBDi*
SDi
RBDi*
QSWi *
+
CHSi
CSWi *
RLIMi *
800K
in ringing
CCSWi *
+
SET
OUTPUT
100
8V
800K
+
COMPARATOR
DSWi *
CHSi*
LSWi *
CFLi *
+
Ref. Current
Generator
ISET
internal clock
BGND
square wave converter
RSET *
85 kHz
10% High Duty Cycle
VRAMP
IRAMP
800 k
external clock ****
CRAMP *
RBase *
QRAMP *
VREGi
RBG*
LVREGi *
CVREGi * + CVREGii *
CESRi *
Note:
* Denotes external components.
** Generated internally by band gap ≅ 1.4 V.
*** VRING = VRINGP - VRINGM
**** Preferably, the external clock should be Low in startup. For a system (codec) which has a high impedance at the clock output in start up, the
additional RBase and RBG resistors are recommended with values of 10 kΩ and 100 kΩ respectively.
7
Zarlink Semiconductor Inc.
Le9502
Data Sheet
Signal Transmission
In Normal Active and Reverse Polarity states, the AC line current is sensed across the RS resistors (see Figure 7), summed and
attenuated, and converted to voltage at the CFILTi pin. The voltage then goes through a high pass filter implemented using the
external CHPi capacitor, is amplified, and sent to the codec device at the VOUTi pin. This output is proportional to the AC metallic
component of the line voltage. Additionally, the signal transmission block receives the analog signal from the codec device. The
analog signal is amplified and sent to the line. Finally, a proportion of the signal at VOUT is fed back to the line.
There are three parameters which define the AC characteristics of the Le9502 RSLIC device. First is the input impedance
presented to the line or 2-wire (VAB) side (Z2WIN), second is the gain from the 4-wire (VIN) to the 2-wire (VAB) side (G42), and third
is the gain from the 2-wire (VAB) side to the 4-wire (VOUT) side (G24).
Input Impedance (Z2WIN)
Z2WIN is the impedance presented to the line at the 2-wire side and is defined by:
Z 2WIN = 2R F + K V K OUT R IMT
where 2 • RF is the total resistance of the external fuse resistors in the circuit, RIMT is the impedance setting resistor for return
loss purpose, KOUT is the gain from VOUT to VAB, and KV is the voice current gain defined in the Transmission Specifications
Table. Note that the equation reveals that Z2WIN is a function of the selectable resistors, RIMT and RF. For example, if RF = 0 Ω
and RIMT is 100 k, the terminating impedance is 600 Ω. This is the configuration used in this data sheet for defining the device
specifications. However, in a real application, RF = 50 Ω is recommended, and RIMT is set to 80.6 KΩ to provide an approximate
600 Ω input impedance.
2-Wire to 4-Wire Gain (G24)
The 2-wire to 4-wire gain is the gain from the phone line to the VOUT output of the Le9502 RSLIC device. To solve for G24, set
VIN = VINP − VINM = 0 V (see Figure 7).
V OUT
1
-------------- = G 24 = ----------------------------------------V AB
2R F
-------------------- + K OUT
K V R IMT
or
2R F
G 24 = – 20 log K OUT + ------------------
K R
V
in dB
IMT
4-Wire to 2-Wire Gain (G42)
G42 is the gain from the VIN input to the line. This gain is defined as VAB/VIN. For the analysis of G42, substitute the load resistor
RL in place of the test voltage source VT (see Figure 7).
RL
K IN ------------------------
R L + 2R F
V AB
---------- = G 42 = --------------------------------------------------V IN
OUT R IMT K V
1 + K
---------------------------------
R + 2R
L
F
or
G 42
RL
-
K IN ----------------------
R
+
L 2R F
= – 20 log --------------------------------------------------- in dB
K
R
K
OUT IMT V
1 + ----------------------------------
R L + 2R F
where KIN is the gain from VIN to VAB.
8
Zarlink Semiconductor Inc.
Le9502
Figure 7.
R F*
Ai
Data Sheet
Transmission Block Diagram
RS
VINPi
CFILTi
VHPi
VOUTi
IL
Kv
C HPi*
K in
R L*
K out
Sense
VAB
R IMTi *
VINMi
RS
R F*
Bi
Note:
* denotes external components.
Fault Detection
Each channel of the Le9502 RSLIC device has a fault detection pin, F1 or F2. These pins are driven low when a longitudinal
current fault or foreign voltage fault occurs. When not in Disconnect state, there are three conditions that will cause the Fi pin to
indicate a fault condition:
•
|IA − IB| > ILONG
•
In Normal Active and Standby state, a foreign voltage fault occurs in which VA is above ground or VB is close to VREG.
•
In Reverse Polarity state, a foreign voltage fault occurs in which VB is above ground or VA is close to VREG.
In the Disconnect state, fault detection is not supported.
Signal Conditioning
The DETi outputs are used for both off-hook and ring trip detection. The threshold for each of these functions is set by external
components.
If the Le9502 RSLIC device is in Low Power Standby or Normal Active modes, the DETi output is used to indicate an off-hook
condition. The following equation will set the off-hook threshold:
500 • V REF
R SET = -----------------------------------------I offhook_threshold
where Ioffhook_threshold is a user-chosen off-hook current threshold. RSET is 68.1 kΩ as specified in the Application Circuit on
page 20. This value produces a nominal off-hook threshold of 10.3 mA.
If the SLIC device is in the Ringing state, the DETi output will indicate the ring trip condition. The threshold for ring trip detection
is set with an external resistor, RTRIP, from the RTRIPi to VREGi pins. The ring trip threshold is set on a per-channel basis. To
select the value of RTRIP, the following equation is used:
500 • ( V RING PK + 10 V )
R TRIP = --------------------------------------------------------------I trip_threshold
where
V RING
PK
+ 10 V(overhead voltage) ≈ V REG ,
For Zarlink's application, the ring trip current threshold is 74.6 mA which results in a R TRIP value of 536 kΩ. CTRIP is used as a
transient filter to debounce the output ring trip signal at the DETi pin. The value for CTRIP is nominally 47 nF as in the Application
Circuit on page 20.
The RDCi pin is used to set the DC feed current limit, as described in DC Feed on page 4.
9
Zarlink Semiconductor Inc.
Le9502
Data Sheet
Thermal Overload
When the die temperature around the power amplifier of a Le9502 RSLIC device channel reaches approximately 160° C, the Fi
pins are pulled Low and VREG will collapse. At the same time, all the blocks controlling that channel of the device are shut off,
except for the logic interface block. The SLIC channel goes into a state similar to Disconnect, making the line current zero. When
the temperature drops below 145° C, the SLIC channel returns to its previous state. It is important to recognize that even while
a channel experiences thermal overload, the state of the device can be modified.
Reference Current Generator
To set the hook switch threshold for both channels, an external resistor (RSET) from ISET to AGND pins is used. For RSET value,
please refer to Line Card Parts List on page 21.
Moreover, internally this block generates IRAMP which is used to help set the frequency of operation desired for the switcher.
Control Logic
Each channel of the Le9502 RSLIC device has three input pins from a codec device (CHS, C2, and C1). The inputs set the
operational state of each channel. There are five operational SLIC device states (See Table 1): Low Power Standby, Disconnect,
Normal Active, Reverse Polarity, and Ringing
.
Table 1. SLIC Device Operating States
CHS
C2
C1
Float
0
0
Low Power Standby
Operating State
Voice Transmission Disabled. Loop current capability is reduced.
Description
Float
0
1
Reverse Polarity
Similar to normal active, but DC polarity is reversed so that the Ring lead is
more positive than the Tip. Supports on hook transmission.
Float
1
0
Normal Active
SLIC device fully operational. Supports on hook transmission.
Float
1
1
Ringing
Ringing state with VAB set to KR•(VRINGP – VRINGM). The switching supply
maintains minimum headroom for the sourcing and sinking amplifiers in order
to maximize power efficiency.
Pull
Low *
0
0
Disconnect**
SLIC device is shut down. Mainly used if a line fault is detected or to shut down
a line.
Note:
* See CHS Specifications on page 17.
** Standby state with switcher turned off.
10
Zarlink Semiconductor Inc.
Le9502
Data Sheet
VREG2
B2 (RING)
A2 (TIP)
RTRIP 2
C12
C22
DET2
F2
VINP2
VINM2
VOUT 2
CONNECTION DIAGRAM
44 43 42 41 40 39 38 37 36 35 34
VHP2
1
33
BGND2
CFILT 2
2
32
CHS2
LPF2
3
31
ILS2
ISET
4
30
SD2
RDC
5
29
VRAMP
VCC
6
28
VSW
44-Pin eTQFP
AGND
7
27
SD1
VRINGP
8
26
ILS1
VRINGM
9
25
CHS1
LPF1
10
24
BGND1
CFILT 1
11
23
VREG1
Exposed Pad
Note:
1.
Pin 1 is marked for orientation.
11
Zarlink Semiconductor Inc.
B1 (RING)
A1 (TIP)
C11
RTRIP 1
C21
F1
DET1
VINP1
VINM1
VHP1
VOUT 1
12 13 14 15 16 17 18 19 20 21 22
Le9502
Data Sheet
PIN DESCRIPTIONS
Pin Name
Type
Description
AGND
Ground
Analog and digital ground return for VCC circuitry (common to both
channels).
A1,2 (TIP)
Output
A (TIP lead) power amplifier output for channels 1 and 2.
BGND1,2
Ground
Battery ground return for power amplifiers on channel 1 and 2.
B1,2 (RING)
Output
B (RING lead) power amplifier output for channels 1 and 2.
C11, C21
Input
Logic control inputs to control channel 1 state.
C12, C22
Input
Logic control inputs to control channel 2 state.
CFILT1,2
Output
CHS1,2
Input
AC coupling pin for 4-wire amplifier
Compensation node for switching power supply channels 1 and 2.
DET1,2
Output
Loop detector or ring trip detector output, depending on state of
control bits. If the SLIC device is in Ringing state then ring trip
indication is given, if the SLIC device is in Low Power Standby,
Normal Active or Reverse Polarity then hook switch indication is
given.
F1,2
Output
Fault detect pin for channels 1 and 2. A low indicates a fault for the
respective channel, which can be triggered by large longitudinal
current, ground key, or thermal overload.
ILS1,2
Input
Voltage sense pin to limit peak current in external switching power
supply transistor (channels 1 and 2).
ISET
Input
Dual purpose pin: 1. sets the hook switch detection threshold (for
both channels); 2. sets the current source for triangle wave
generation for the switching power supply.
LPF1,2
A capacitor tied to from this pin to AGND stabilizes the DC feed
loop, and lowers Idle Channel Noise.
Output
RDC
Input
Resistor connection to GND. Sets DC feed current limit, ILTH
(common to both channels).
RTRIP1,2
Input
Network tied from RTRIP to VREG. Sets the ring trip threshold
detection level.
SD1,2
Output
Base (gate) drive for switching power supply transistor (channels 1
and 2).
VCC
Supply
Positive supply for internal VCC circuitry (common to both
channels).
VHP1,2
Output
High pass invert summing node of the VOUT amplifier driven by the
AC current coming from CFILT1 and CFILT2.
VOUT1,2
Output
Analog (4-wire side) VOUT amplifier transmit output
VINM1,2
Input
Differential (P-M) analog (4-wire side) voice signal input.
VRAMP
Input
Switching power supply ramp voltage that sets the frequency of the
switcher and the maximum duty cycle (common to both channels).
VREG1,2
Supply
VINP1,2
VRINGP, VRINGM
Negative power supply generated by SLIC device Switching
Regulator. (channels 1 and 2)
Input
Differential ringing input (common to both channels).
VSW
Supply
Positive supply used by the SLIC device to generate the negative
regulated supplies of VREG1, VREG2 (common to both channels).
Exposed Pad
Isolated
Exposed pad on underside of device must be connected to a heat
spreading area. The AGND plane is recommended.
12
Zarlink Semiconductor Inc.
Le9502
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to absolute maximum ratings for extended periods can affect device reliability.
Storage temperature
Ambient temperature, under bias
VCC with respect to AGND
–55 to +150°C
–40° to +85°C
–0.4 to +6.5 V
VREG with respect to BGND
+0.4 to –115 V
–100 to 100 mV
BGND with respect to AGND
A (TIP) or B (RING) to BGND:
Continuous
VREG –1 to BGND +1
10 ms (F = 0.1 Hz)
VREG –5 to BGND +5
1 µs (F = 0.1 Hz)
VREG –10 to BGND +10
250 ns (F = 0.1 Hz)
Current from A (TIP) or B (RING)
C1 and C2 with respect to AGND
CHCLK
VSW
Maximum power dissipation,
TA = 85° C (See notes)
VREG –15 to BGND +15
±150 mA
–0.4 to VCC + 0.4 V
AGND to VCC
BGND to +44 V
1.8 W
Thermal Data:
In 44-pin eTQFP package
Thermal Data:
In 44-pin eTQFP package
ESD Immunity (Human Body Model)
θJA
32° C/W
θJC
9.2° C/W
JESD22 Class 1C compliant
Note:
Thermal limiting circuitry on chip will shut down the circuit at a junction temperature of about 160ºC. Continuous operation above 145ºC junction
temperature may degrade device reliability.
The thermal performance of a thermally enhanced package is assured through optimized printed circuit board layout. Specified performance requires that the exposed thermal pad be soldered to an equally sized exposed copper surface, which, in turn, conducts heat through 16 0.3 mm
diameter vias on a 1.27 mm pitch to a large (> 500 mm2) internal copper plane. (Refer to Zarlink application note Layout Considerations for the
Le77D112 and Le9502 RSLIC devices, document ID# 081013).
Package Assembly
Green package devices are assembled with enhanced environmental, compatible lead-free, halogen-free, and antimony-free
materials. The leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer leadfree board assembly processes. The peak soldering temperature should not exceed 245°C during printed circuit board assembly.
Refer to IPC/JEDEC J-Std-020B Table 5-2 for the recommended solder reflow temperature profile.
OPERATING RANGES
Zarlink guarantees the performance of this device over commercial (0° to 70°C) and industrial (−40° to 85°C) temperature
ranges by conducting electrical characterization over each range, and by conducting a production test with single insertion
coupled to periodic sampling. These characterization and test procedures comply with section 4.6.2 of Bellcore GR-357-CORE
Component Reliability Assurance Requirements for Telecommunications Equipment.
Environmental Ranges
Ambient Temperature
–40° to +85° C
Electrical Ranges
VCC
3.3 V ± 5%
VSW
8 to 40 V
VREG
–7 to –110 (0 V in Disconnect state).
13
Zarlink Semiconductor Inc.
Data Sheet
33.0
—
—
28.0
1.0
—
28.0
1.0
—
0.25
Min
38.0
3.0
26.0
38.0
3.0
26.0
38.0
3.0
0.1
1.0
Typ
42.0
—
—
48.0
5.0
—
48.0
5.0
—
3.5
Max
2000.0
—
—
500.0
50.0
—
500.0
50.0
0.0
15.0
Min
2500.0
152.0
833.0
850.0
200.0
820.0
850.0
200.0
0.5
50.0
Typ
2900.0
—
—
1150.0
360.0
—
1150.0
360.0
3.0
130.0
Max
VREG Supply Power (mW)
5.
500.0
—
—
250.0
100.0
—
250.0
100.0
5.0
20.0
Min
800.0
180.0
360.0
525.0
215.0
360.0
475.0
215.0
15.0
75.0
Typ
1010.0
—
—
650.0
320.0
—
650.0
320.0
25.0
130.0
Max
SLIC Device Power (mW)
(Note 5)
5.7
2.1
4.6
4.1
2.5
4.6
4.1
2.5
0.1
2.0
Typ
VSW Pin
Current (mA)
1, 3
1,2
1,2
1
1,2
1,2
1
1
1
1
Note
Zarlink Semiconductor Inc.
14
SLIC device power is defined as the power delivered through the VCC and VREG pins minus the power delivered to the load. It does not include any power associated with the VSW pin and
the external switcher.
V REG • I VREG
I VSW = ---------------------------------- , where η = efficiency. For our recommended circuit, an efficiency of 0.6 can be assumed under heavy loads.
η • V SW
10.0
—
—
10.0
10.0
—
10.0
10.0
7.5
8.0
Max
VREG Supply Current (mA)
(Note 4)
4.
7.5
7.0
—
4.0
7.0
7.5
7.0
7.0
7.5
7.0
5.0
5.5
Typ
—
4.0
4.0
—
4.0
4.0
2.0
3.0
Min
3.3 V VCC Supply Current
(mA)
Values shown are for one channel only but are tested with both channels in the same state.
Not tested in production. Parameter is guaranteed by characterization or correlation to other tests.
Production test forces Vin=0.5Vdc which is equivalent to VRING=0.7Vac.
VRING = 0.7 Vac
RL = 1400 Ω
VRING = 0.7 Vac
RL = open
VIN = 0 V
RL = 900 Ω
VIN = 0 V
RL = 300 Ω
VIN = 0 V
RL = open
VIN = 0 V
RL = 900 Ω
VIN = 0 V
RL = 300 Ω
VIN = 0 V
RL = open
VIN = 0 V
RL = open
VIN =0 V
RL = open
Condition
1.
2.
3.
Notes:
Ringing
Pol Rev
Active
Disconnect
Standby
Operation States
Supply Currents and Power Dissipation
Unless otherwise noted, test conditions are: VCC = 3.3 V, VSW = 12.0 V, AGND = BGND, no fuse resistors, RL = 600 Ω, 85 kHz CHCLK, ILTH=20 mA (RDC = 34.8 kΩ). Ringing
configuration is VRING = VRINGP - VRINGM = 0.7 Vpk. 20 Hz sinusoidal. Please refer to Test Circuit on page 19 for all other component values.
ELECTRICAL CHARACTERISTICS
Le9502
Le9502
Data Sheet
SPECIFICATIONS
Device Specifications
Specification
Condition
Min
Typ
Max
Unit
Note
V
1.
Line Characteristics
VA, Active
VB, Reverse Polarity
RL = open
–4
VA
Standby, RL = open
–1
VAB
Active or Reverse Polarity,
RL = open
45
48
53
Standby, RL = open
45
48
54.5
Active or Reverse Polarity,
RL = open
–50
–63
–69
Standby, RL = open
–48
–58
–64
Active or Reverse Polarity and
Standby
17.5
20
22.5
RL = 100 Ω, Active or Reverse
Polarity; ILTH=20mA.
ILTH+10
ILTH+17
ILTH+29
RL = 100 Ω, Standby;
ILTH=20mA.
ILTH+10
ILTH+17
ILTH+25
RL = 600 Ω, Active or Reverse
Polarity; ILTH=20mA.
ILTH+7
ILTH+11
ILTH+20
RL = 600 Ω, Standby;
ILTH=20mA.
ILTH+7
ILTH+11
ILTH+20
VREG
Current limit threshold,
ILTH accuracy
ISC
Loop Current
IL accuracy
LPFi
(Ioffhook_threshold)
Ring trip current accuracy
(Itrip_threshold)
mA
25
kΩ
Bias voltage with respect to
GND
2.2
V
0.1
Input impedance
1.33
1.4
5
µA
3.
Ω
10
Input voltage tolerance
Hook Switch detection threshold
programming range
Loop detect threshold tolerance
4.
Output impedance
Leakage current for capacitor
value of 4.7 µF ± 20%
RDC
4.
1.47
V
15
Standby, Active and Reverse
Polarity
8.8
11.5
14.5
VREGi = -85V
59.7
80
89.5
4.
mA
Ringing
VA, VB
VRING = 0 V, RL = 1400 Ω
VAB offset
VRING = 0 V, RL = 1400 Ω
Ringing voltage gain (KR)
Ringing, K R
–4
–2
V AB
= ---------------,
V RING
95
+2
100
V
3.
105
V/V
1.
2.4
V
4.
kΩ
3.
4.
Vin = 0.7Vpk, RL = 1400Ω
VRINGP, VRINGM Input Range
–0.3
(VRINGP - VRINGM) Differential
Input Impedance
200
Ringing Current Limit, IRSC
Ringing, RL = 100 Ω
Ringing distortion
Vin = 0.7Vpk, RL = 1400Ω
90
135
180
mApk
0.5
3.5
%
80
85
90
kHz
7.5
10
12.5
%
Switching Power Supply
fCHCLK
Chopper Clock High Duty Cycle
(tCHCLK)
15
Zarlink Semiconductor Inc.
3.
Le9502
Specification
Condition
VTILS (current limit sense
threshold)
ILSi
Data Sheet
Min
Typ
Max
Unit
0.25
0.28
0.31
V
+1
µA
Input impedance
–1
Output impedance
SDi
3
Slew Rate positive
25
VOH where VSW ≥ 12 V,
RBD = 330 Ω
VSW - 0.4
ISET
V/µsec
VSW - 0.3
V
1
MΩ
Ringing
180
Standby and Active
75
Disconnect
1
CRAMP current
72.0
Input impedance
82.2
1.33
1.4
µA
92.9
Ω
10
Input voltage tolerance
3.
VSW
VSW - 8.0
Input impedance
IRAMP
Ω
50
Slew Rate negative
VOL where VSW ≥ 12 V,
RBD = 330 Ω
CHSi
Ω
7000
Bias current
Note
1.47
V
3.
Power Supply Rejection Ratio at the 2-wire Interface
VCC
VREG to VAB
200 to 4000 Hz, 50 mVrms
4k to 50 kHz
25
45
20
40
4.
200 to 4000 Hz, 100 mVrms
25
45
4k to 50 kHz
20
40
4.
50k to 100k
15
30
4.
RL = 600 Ω, 300 to 3400 Hz, 0
dBm, Active and Reverse
Polarity
46
63
50
dB
Longitudinal Capability
Longitudinal balance
T-L balance
1 kHz, 0 dBm
40
Longitudinal current per pin
A(TIP) or B(RING)
30
Longitudinal impedance
A(TIP) or B(RING),
0 to 100 Hz
Longitudinal current detect,
ILONG
Fi low
18
dB
mA
4.
4.
1
5
Ω/pin
26
35
mA
9.54
9.74
Transmission Performance
2WRL
300 to 3400 Hz, for 600 Ω
26
VIN to VAB (KIN)
RL = open, 0dBm, 2-wire
9.34
9.34
9.54
9.74
0dBm, 1 kHz
–9.74
–9.54
–9.34
VOUT to VAB (KOUT)
Gain Accuracy, 2-Wire to 4-Wire
4.
Gain Accuracy, 4-Wire to 2-Wire
0dBm, 1 kHz
3.32
3.52
3.72
Gain Accuracy, 4-Wire to 4-Wire
0dBm, 1 kHz
–6.42
–6.02
–5.62
KV, Voice Current gain
Line Test:, Standby,
IL < |20 mA|
Active or Rev. Pol.L,
IL < |80 mA|
Ringing, IL < |100 mA|
1
---------520
1
---------500
1
---------480
16
Zarlink Semiconductor Inc.
dB
A/A
4.
3.
Le9502
Specification
Gain Accuracy over frequency
Gain tracking at 1 kHz,
relative to 0 dBm
Gain tracking, On Hook,
relative to 0 dBm
THD (Total Harmonic Distortion)
Condition
Data Sheet
Min
Typ
–0.1
+0.1
–30 dBm to +3 dBm, 2-Wire
–0.1
+0.1
–55 dBm to –30 dBm, 2-Wire
–0.1
+0.1
0 to –30 dBm, 2-wire
–0.15
+0.15
+3 to 0 dBm, 2-wire
–0.35
+0.35
0 dBm, 2-wire, 1 kHz
–64
–50
+7 dBm, 2-wire, 1 kHz
–55
–40
THD, On hook
0 dBm, 2-wire, 1 kHz
Overload Level, 2-Wire
Active or Polarity Reversal
ICN
C-message
12
ICN
Psophmetric
–78
–150
Input impedance
4.
–75
dBmP
+150
µA
Ω
3., 6.
Ω
mV
Offset voltage with respect to
VREF
–40
+40
mV
100
pF
3.,7.
3.
Resistive load on VOUT to
AGND
20
Drive capability, RL = 20 kΩ
V REF – 1
---------------------20 k
kΩ
V REF + 1
----------------------20 k
0.4
2.4
1.4
Offset voltage voice
–20
Differential Input Impedance
200
Differential Mode Input
+20
–1
1
2.4
0
RL = 300 Ω, 16.0 kHz, Active
Frequency = 12 kHz, Active
Frequency = 16 kHz, Active
µA
3.,7.
V
mV
kΩ
–0.3
RL = 300 Ω, 12.0 kHz, Active
Metering distortion,
RL = 300 Ω, VAB = 1.5 Vpk
2.
dBrnC
+20
VINP, VINM Input Range
4.,5.
5.
–20
VOUT Common Mode
Metering gain
dB
Offset voltage with respect to
VREF
VOUT Output Range
VINP − VINM
4.
15
5
Capacitive load on VOUT to
AGND
VOUTi
Note
V
8000
Drive capability, Active State
VHPi
Unit
–36
2.5
Output impedance
CFILTi
Max
Relative to gain at 1 kHz
300 to 3400 Hz
3.
V
0.25
0.5
dB
–45
–40
dB
–75
dB
4.
4.
Crosstalk Between Channels
Crosstalk coupling loss
F = 200 Hz to 3.4 kHz
Logic Interface
Inputs (C1, C2)
VIL
0.8
VIH
2.0
IIL
VIN = 0.4 V
–100
0
100
IIH
VIN = 2.4 V
–100
30
100
CHSIL
VIN = 50 mV
90
CHSFloat_Leakage
–1
17
Zarlink Semiconductor Inc.
+1
V
µA
µA
4.
4.
Le9502
Specification
Condition
Data Sheet
Min
Typ
2.4
2.8
Max
Unit
Outputs (F1, F2)
VOH
IOUT = –25 µA
VOL
IOUT = 25 µA
0.2
0.4
V
DET Pin Characteristics
VOH
IOUT = –165µA
VOL
IOUT = 165 µA
2.4
2.8
0.2
Note:
1.
VAB = Voltage between the Ai (TIP) and Bi (RING) pins.
2.
Overload level is defined when THD = 1%.
3.
Guaranteed by design.
4.
Not tested in production. Parameter is guaranteed by characterization or correlation to other tests.
5.
When On hook, RLDC is open circuit, RLAC = 600 Ω.
6.
Layout should have less than 10 pF from pin to ground.
7.
VREF is an internal value of typically VREF = 1.4V.
18
Zarlink Semiconductor Inc.
0.4
V
Note
–
To base of QSW
on
other channel
+
1
2
i = per channel component/pin
VSW *
47 µH
ES2C
FZT955
0.1 Ω
RL
4148-SOT
2.0 µF –
300 V +
150 µH
220 µF
+
–
VSW *
RING i
TIP i
* Denotes pins that are common to both channels.
Note:
100 nF
2.0 µF
300 V
Per Channel
TEST CIRCUIT
VCC*
19
AGND*
RTRIP i
VREGi
SDi
ILSi
BGNDi
VHPi
VSW*
C1i
C2i
CHSi
*RDC
*VRAMP
*VRINGM
*VRINGP
Fi
CFILT i
VOUT i
ISET*
VINPi
DETi
VINMi
U1
Le9502
LPFi
–
Bi (RING)
Ai (TIP)
+
4.7 µF
16V
Zarlink Semiconductor Inc.
47 nF
100 nF
330
10 nF
BAV99TA
68.1 kΩ
100 nF
16 V
VCC*
Le9502
536 KΩ
4.7 nF
34.8 kΩ
470 pF
1.5 µF
VRING
SELECTION
STATE
100 kΩ
2N3904
10 kΩ
VIN
85 kHz
Data Sheet
To base of
QSW on
other channel
CVREGii
LVREGi
PTC2i***
CESRi
CSW
K2
4
U3
2
1
RLIMi
5
6
7
8
DSWi
2
3
*** Total fuse resistance = 100Ω guarantees a minimum DC load.
CBDi
1
–
20
RTRIPi
CTRIPi
Zarlink Semiconductor Inc.
RSET
RTRIPi
VRAMP*
AGND*
ISET*
C1i
DETi
Fi
VRINGM*
VRINGP*
CFILTi
VHPi
VOUTi
VINPi
VINMi
C2i
BGNDi
U1
Le9502
LPFi
+
CLPFi
VREGi
SDi
ILSi
VSW*
RDC*
CHSi
Bi (RING)
Ai (TIP)
VCC*
3.3 V
RDC
RBDi
CVREGi
DD2i
CHSi
C1
** VCM is the bias voltage, which is ≥ (maximum ADC input voltage / 2)
VSW *
LSWi
QSWi
Place close
to RLIM pin
DD1
CFLi
K2
A
A
K1
CSW1
VSW
NC
G
2
3
K1
1
* Denotes pins that are common to both channels.
Note:
RINGi
TIPi
PTC1i***
APPLICATION CIRCUIT
Le9502
VCM **
ROUTi
QRAMP
CRAMP RCLK
CHPi
RIMTi
CFOUTi
Clock Output
(CHCLK)
Logic Outputs
Logic Inputs
DAC Outputs
U2
CODEC
ADC Inputs
DAC Outputs
VCCA
MCLK
DCLK
CSL
DIN
DOUT
INT
RS
TSCA
DRA
DXA
FS
PCLK
DGND
VCCD
AGND
MPI
Interface
PCM
Interface
Data Sheet
Le9502
Data Sheet
LINE CARD PARTS LIST
The following list defines the parts and part values required to meet target specification limits for channel i of the line card (i = 1, 2).
The protection circuit is included.
Quantity
(see note 1)
Type
Value
Tol.
Rating
Comments
C1
1
Capacitor
100 nF
10%
16 V
Panasonic / ECJ-1VB1C104K, 0603
CBDi
2
Capacitor
27 nF
10%
16 V
Panasonic / ECJ-1VB1C273K, 0603
CESRi,
CVREGi
4
Capacitor
0.1uF
10%
200 V
CalChip / GMB31X7R104K200NT, 1206
CFOUTi
2
Capacitor
1 µF
10%
50 V
Panasonic / ECJ-1VC1H100D, 0603
CHSi
2
Capacitor
1 nF
10%
50 V
Panasonic / ECJ-1VC1H102J, 0603
CHPi
2
Capacitor
1.5 µF
10%
6.3 V
Panasonic / ECJ-2YB0J155K, 0805
10%
6.3 V
Panasonic / ECS-T0JY475R, 1206
Item
CLPFi
2
Capacitor
4.7 µF
Tantalum
CRAMP
1
Capacitor
470 pF
5%
50 V
Panasonic / ECJ-1VC1H471J, 0603
CTRIPi
2
Capacitor
47 nF
10%
50 V
Panasonic / ECJ-1VB1C473K, 0603
20%
25 V
Panasonic / ECE-V1EA221UP, 8mmCan
10%
50 V
Panasonic / ECJ-2YB1H104K, 0805
CSW
1
Capacitor
220 µF
Alum. Elect.
CSW1
1
Capacitor
100 nF
CFLi,
2
Capacitor
2.2 µF
20%
200 V
United Chemi / THCR70E2D225MT, 3025
CVREGii
2
Capacitor
1.0 µF
10%
300 V
Tecate / CMC-300/105KX1825T060
DSWi
2
Diode
ES2C
2A
General Semi. / ES2C, DO-214AA
DD1
1
Diode
4148CC
200 mA
Fairchild / MMBD4148CC, SOT-23
DD2i
2
Diode
BAV99
200 mA
Fairchild / BAV99, SOT-23
LSWi
2
Inductor
47 µH
2.95 A
Cooper Coiltronics / DR127-470
LVREGi
2
Inductor
150 µH
205 mA
Coilcraft 1812LS154X_B
PTC1i,
PTC2i
4
PTC
50 Ω
AsiaCom / MZ2L-50R
QRAMP
1
N-channel
MOSFET
FDV301N
Fairchild / FDV301N, SOT-23
QSWi
2
PNP
Transistor
FZT955
RBDi
2
Resistor
180 Ω
RCLK
1
Resistor
RDC
1
Resistor
RIMTi
2
Resistor
84.5 k
RLIMi
2
Resistor
0.1 Ω
ROUTi
2
Resistor
51 k
RSET
1
Resistor
68.1 k
RTRIPi
2
Resistor
536 k
-140 V
Zetex / FZT955TA, SOT-223
1%
1/8 W
Yageo / 9C08052A1800FKHFT, 0805
1k
1%
1/16 W
Panasonic / ERJ-3EKF1002V, 0603
34.8 k
1%
1/16 W
Panasonic / ERJ-3EKF3482V, 0603
1%
1/16 W
Panasonic / ERJ-3EKF84R5V, 0603
1%
1/4 W
Panasonic / ERJ-L14KF10CU, 1210
5%
1/16 W
Panasonic / ERJ-3GEYJ513V, 0603
1%
1/16 W
Panasonic / ERJ-3EKF6812V, 0603
1%
1/16 W
Panasonic / ERJ-3EKF5363V, 0603
U1
1
SLIC
Le9502
-
-
Zarlink / Le79502, 44-pin eTQFP
U2
1
CODEC
-
-
-
-
U3
1
Protection
TISP61089
-170V
30A
Bourns / TISP61089BDR, DOO8
Note:
1.
Quantities required for a complete two-channel solution.
21
Zarlink Semiconductor Inc.
Note
Le9502
Data Sheet
PHYSICAL DIMENSIONS
44-Pin eTQFP
Note:
Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the
device. Markings will vary with the mold tool used in manufacturing.
22
Zarlink Semiconductor Inc.
Le9502
Data Sheet
REVISION HISTORY
Revision A1 to B1
•
In Absolute Maximum Ratings, the following changes were made:
– Changed TA from 22.7° to 32°C/W
– Added another note describing eTQFP package
•
In Supply Currents and Power Dissipation, Ringing operation state, removed condition VIN = 0.7 VDC
•
In Device Specifications, Metering gain, changed min, typ, and max values from 4.24, 4.44, and 4.64, respectively, to −
0.2, 0, and 0.2, respectively
•
In Device Specifications, Logic Interface, IIH, changed min and max values from ±40 to ±50.
•
•
•
Updated Switching Power Supply block diagram
Updated Application Circuit and Parts List
Updated Physical Dimensions drawing
Revision B1 to C1
•
In Features, the following changes were made:
– Removed (5V Tolerant) statement.
– Changed "5REN" statement to "70 Vpk @ 5REN"
– Changed "Up to 90 Vpk, Balanced" statement to "90 Vpk capable".
•
In Related Literature, added references to Le9500 and Le9501 data sheets.
•
In Two-Wire Interface, updated the paragraph under the "Ringing" section.
•
In Electrical Characteristics, the following changes were made:
– Removed "0° C < TA < 70° C" statement.
– Updated the entire table entry.
– Changed "VIN" to "VRING" for Ringing State and in Note 3.
•
In Device Specifications, the following changes were made:
– Increased VREG typical and maximum specifications.
– Removed "RL=34.8 kΩ " from ILTH accuracy and added note 4.
– Increased ISC typical and maximum specifications, and added RL=600 Ω case.
– Updated DC feed graphic and ISC nominal value to reflect typical value of (ILTH + 17.0mA).
– Added IL accuracy @ RL=600Ω case.
– Increased Ioffhook_threshold typical and maximum specifications and merged "mA" column units.
– Changed "Vin = 0.9 Vpk" references to "Vin = 0.7 Vpk".
– Increased IRSC typical and maximum specifications and added note 4.
– Added note 4. to "VRINGP, VRINGM Input Range".
– Added note 7. to KR and Ringing distortion.
– Adjusted SDi, VOH and VOL : minimum, typical and maximum values and merged "uA" column units.
– Adjusted ILONG minimum and maximum specifications.
– Added note 4. to "Negative foregin voltage threshold at VA or VB".
– Removed "TBD" references and filled with data accordingly.
– Updated "Metering gain" minimum, typical, and maximum specifications.
– Adjusted IIL, IIH, CHSIL, and CHSFloat_Leakage minimum, typical, and maximum specifications.
– Added note 4. to CHSIL and CHSFloat_Leakage.
– Add Note. 7 definition.
Updated Test Circuit, Application Circuit and Parts List.
Added "***" definition for PTCi fuse in Application Circuit.
•
•
Revision C1 to D1
•
Added green package OPN to Ordering Information on page 1
•
•
Added Package Assembly on page 13
In Device Specifications, Metering Gain, changed min/typ/max values from -0.5, .2, .05 to 0, .25, and .5, respectively.
23
Zarlink Semiconductor Inc.
Le9502
Data Sheet
Revision D1 to E1
•
In Electrical Characteristics, the following changes were made:
– Updated the entire table entry.
•
In Device Specifications, the following changes were made:
– Increased VAB maximum specifications for Standby.
– Lowered VREG minimum specifications.
– Added "ILTH = 20mA" for ISC, and IL. This required increase in ’Condition’ table size and squeezing the ’Note’ column.
– Increased ISC maximum specifications
– Increased Itrip_threshold typical specifications and added "VREGi = -85V" in the ’Condition’ column.
– Removed note 7 definition and references to it from KR and Ringing distortion. Changed note 8 references to note 7 (as
note 8 definition now defaults to note 7).
– Increased ILONG typical specifications.
– Added note 4. to "Gain tracking, On Hook, relative to 0 dBm".
– Updated "Metering gain" minimum, typical, and maximum specifications.
– Added "Active" for the 12kHz "Metering gain" and "Metering distortion".
Updated Test Circuit, the following changes were made:
– Changed CSW, CFL, CVREG, CHS, and LVREG values.
•
Revision E1 to F1
•
In Electrical Characteristics, the following changes were made:
– Updated the ’Supply Currents and Power Dissipation’ table entries for VREG and SLIC Power.
– Updated the ’Device Specifications’ table entries for VREG.
– Added note 3. to ISET and RDC - Input voltage tolerance.
Revision F1 to G1
•
In Electrical Characteristics on page 14 the following changes were made:
– Updated SLIC Device Power typical specifications for Pol.Rev.: RL=300Ω.
•
In Device Specifications on page 15, the following changes were made:
– Increased VAB maximum specifications for Active or Reverse Polarity.
Revision G1 to G2
•
Made minor edits to Features on page 1.
•
Added note to Physical Dimensions on page 22.
Revision G2 to G3
•
Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007.
24
Zarlink Semiconductor Inc.
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
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However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
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information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
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suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
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Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in an I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
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