LIN D O C #: 1668
LX1668
P ROGRAMMABLE M U LTIPLE O UTPUT DC:DC C ONTROLLER
T
H E
I
N F I N I T E
P
O W E R
O F
I
P
N N O VA T I O N
R O D U C T I O N
DESCRIPTION
The LX1668 is a Monolithic Switching
Regulator Controller IC designed to provide a low cost, high performance adjustable
power supply for advanced microprocessors
and other applications requiring a very fast
transient response and a high degree of
accuracy. It provides a programmable
switching regulator output, together with one
internal linear low dropout regulator and one
adjustable linear regulator driver. The LX1668
offers a triple-output single-chip power supply for Pentium® II and other processors.
Programmable Synchronous Rectifier
Driver for CPU Core. The main output is
adjustable from 1.3 to 3.5V using a TTLcompatible 5-bit digital code to meet Intel
specifications. The IC can read the signal
from a DIP-switch, hardwired to Pentium II
processor’s pins or from software. The 5-bit
code adjusts the output voltage between 1.30
and 2.05V in 50mV increments, and between
2.0 and 3.5V in 100mV increments. The
device can drive dual MOSFET’s resulting in
typical efficiencies of 85 – 90%, even with
loads in excess of 10A.
D
S
A T A
H E E T
K E Y F E AT U R E S
■ 5-Bit Programmable Output For CPU Core
Supply
■ Internal Fixed 2.5V Low Dropout Regulator
■ Adjustable Linear Regulator Driver
■ Complete Single-Chip Power Solution For
Pentium II Processors
■ No Sense Resistor Required For Short-Circuit
Current Limiting
■ Soft-Start And Hiccup-Mode Current Limiting
Functions
■ Modulated Constant Off-Time Control
Mechanism For Fast Transient Response And
Simple System Design
■ Power Good Flag
■ Over-Voltage Pin & SCR
■ Digital-Compatible Inputs (Including VID Pins)
■ Output Disable Function Shuts Off PWM While
Keeping 2.5V LDO Active - Compatible With
"Green PC" And "Instant On" Requirements
■ Compatible to VRM8.2 - 8.4 Specifications
Internal Low Dropout [LDO] Regulator
provides a fixed 2.5V output for powering the
clock circuit at up to 250mA.
External Linear Regulator Driver output can be connected to a MOSFET to provide
a high-current adjustable LDO function suitable for supplying the GTL+ bus circuitry on
a Pentium II processor motherboard at 1.5V.
Short-circuit Current Limiting without
Expensive Current Sense Resistors. The
current sensing mechanism can use a PCB
trace resistance or the parasitic resistance of
the main inductor. For applications requiring
a high degree of accuracy, a conventional
sense resistor can be used.
Ultra-Fast Transient Response Reduces System Cost. The fixed frequency
modulated off-time architecture results in the
fastest transient response for a given inductor.
Small Package Size. The LX1668 is available
in an economical 20-pin wide body SOIC or
a space-saving 20-pin TSSOP package.
A P P L I C AT I O N S
■ Pentium II & Pentium III Processor Supplies
■ Voltage Regulator Modules
■ General Purpose And Microprocessor DC:DC
Supplies
NOTE: For current data & package dimensions, visit our web site: http://www.linfinity.com.
PRODUCT HIGHLIGHT
5V
L2
1µH
12V
C3
1µF
C8
1µF
VOUT2
2.5V
IRL3102
2
C9
1µF
3
4
3.3V
5
6
C4
330µF
VOUT3
1.5V
7
Q3
8
IRLZ44
C6
330µF
9
R1, 0
1500µFx3
Q1
1
C5
22µF
C2
C7
1µF
10
TDRV
PGND
VCC12
BDRV
VCC5
AGND
VOUT2
SS/EN
VCC3
LDRV
LFB
LX1668
VFB
VCORE
PWRGD
VID0
OVP
VID1
VID4
VID2
VID3
R2, 50k
L1
2.5µH
RSENSE
2.5mΩ
CPU Core
VCORE
20
19
Q2
18
IRL3303
17
16 CSS
Q4*
0.1µF
14
C1
SCR
2N6504
15
1500µF x 6
PWRGD
13
12
11
VID4
VID3
VID2
VID1
VID0
R3
10k
* Q4 optional
OVP crowbar
3.3V / 5V
PA C K A G E O R D E R I N F O R M AT I O N
TA (°C)
0 to 70
SOWB
DW Plastic
20-pin
LX1668CDW
TSSOP
PW Plastic
20-pin
LX1668CPW
Note: All surface-mount packages are available in Tape & Reel, append the letter "T" to part number. (i.e. LX1668CPWT)
Copyright © 1999
Rev. 1.0 4/99
LINFINITY MICROELECTRONICS INC.
11861 W ESTERN A VENUE, G ARDEN G ROVE, CA. 92841, 714-898-8121, F AX: 714-893-2570
1
PRODUCT DATABOOK 1996/1997
LX1668
P ROGRAMMABLE M U LTIPLE O UTPUT DC:DC C ONTROLLER
P
R O D U C T I O N
A B S O LUT E M AXIM UM R AT IN GS
D
A T A
S
H E E T
(Note 1 & 2)
12V Supply Voltage (VCC12) .................................................................................. 18V
5V Supply Voltage (VCC5) ....................................................................................... 7V
Supply Voltage (Internal LDO)/(VCC3) ................................................................... 7V
Output Drive Peak Current Source (500ns) ....................................................... 1.0A
Output Drive Peak Current Sink (500ns) ........................................................... 1.0A
Input Voltage (SS, VID[0:4]) ................................................................... -0.3V to 6V
Operating Junction Temperature .................................................................... 150°C
Storage Temperature Range ........................................................... -65°C to +150°C
Lead Temperature (Soldering, 10 Seconds) .................................................... 300°C
Note 1. Exceeding these ratings could cause damage to the device. All voltages are with
respect to Ground. Currents are positive into, negative out of the specified
terminal.
Note 2. VCC3 supply is used as input to internal low dropout regulator. Voltages above
3.3V will cause increased thermal dissipation in the package. Power dissipation
should be limited to keep junction temperature below maximum rating.
T H E R MAL DATA
DW PACKAGE:
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θ JA
85°C/W
PW PACKAGE:
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θ JA
110°C/W
Junction Temperature Calculation: TJ = TA + (PD x θJA).
The θ JA numbers are guidelines for the thermal performance of the device/pc-board
system. All of the above assume no ambient airflow.
2
PACKAGE PIN OUTS
TDRV
VCC12
1
20
2
19
VCC5
VOUT2
VCC3
LDRV
LFB
VID0
VID1
VID2
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
PGND
BDRV
AGND
SS/ENABLE
VFB
VCORE
PWRGD
OVP
VID4
VID3
DW PACKAGE — 20-Pin
(Top View)
TDRV
VCC12
VCC5
VOUT2
VCC3
LDRV
LFB
VID0
VID1
VID2
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
PGND
BDRV
AGND
SS/ENABLE
VFB
VCORE
PWRGD
OVP
VID4
VID3
PW PACKAGE — 20-Pin
(Top View)
Copyright © 1999
Rev. 1.0 4/99
PRODUCT DATABOOK 1996/1997
LX1668
P ROGRAMMABLE M U LTIPLE O UTPUT DC:DC C ONTROLLER
P
R O D U C T I O N
D
A T A
S
H E E T
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, 4.75V < VCC5 < 5.25V and 10.8V < VCC12 < 13.2V, 0°C ≤ TA ≤ 70°C. Test conditions: VCC3 = VCC5, VCC5 = 5V, VCC12 = 12V,
T = 25°C.)
Parameter
Symbol
Test Conditions
Min.
LX1668
Typ.
Max.
Units
Reference & DAC
Initial Accuracy
Cumulative Regulation Accuracy
VCORE
(Less 40mV output adaptive positioning), 1.3V ≤ VCORE ≤ 35V, T = 25°C
1.3V ≤ V CORE ≤ 3.5V
-1
-1.5
+1
1.5
%
%
Timing
Off Time
Swicthing Frequency
OT
Freq
VCORE = 2.0V
VCORE = 1.3V to 3.5V
2.4
250
IFB
1.0V < VSS = VFB < 3.5V
Overdrive ≤ 5mV
-0.3
100
RCORE
VCLP
0V < VFB = VCORE < 3.5V
µs
kHz
Error Comparator / CSInput Bias Current
EC Delay to Output
-1
µA
ns
Current Sense +
Input Resistance
Pulse By Pulse Current Limit
Current Sense Delay To Output
45
12
60
100
kΩ
mV
ns
100
11
0.1
ns
V
V
Overdrive ≤ 5mV
Output Drivers
Drive Rise Time, Fall Time
Drive High
Drive Low
T RF
VDH
V DL
CL = 3000pF
ISOURCE = 20mA
ISINK = 20mA
10
VST
VCC12 > 3.9V
3.9
UVLO and Soft-Start (SS)
VCC5 Start-Up Threshold
Hysteresis
SS Resistor
SS Output Enable
Hiccup Duty Cycle
RSS
VEN
DCHIC
CSS = 0.1µF, V DAC = 2.00V, FREQ = 100Hz
4.2
0.10
18
0.5
10
ICD
IVCC12
IVCC5
IVCC3
Out Freq = 200kHz, CL = 3000pF, Synch., VSS > 0.5V
VSS < 0.5V
VSS < 0.5V
VSS < 0.5V
24
6
13
0.4
0.4
4.6
V
V
kΩ
V
%
Supply Current
VCC12 Dynamic Supply Current
Static Supply Current
12V
5V
3.3V
9
18
2
mA
mA
mA
mA
Power Good / Over-Voltage Protection (OVP)
Threshold
Hysteresis
Power Good Voltage Low
Over-Voltage Threshold
OVP Sourcing Current
(VCORE / VSET) VCORE rising, VOUT2 ≥ 2.0V
(VCORE / VSET) VCORE falling, VOUT2 ≥ 2.0V
108
90
IPWRGD = 4mA
(VCORE / VSET), V CORE rising
VOVP = 2.0V
110
35
VOUT2 = 2.5V, C OUT = 220µF
-10mA ≤ IOUT2 ≤ -150mA
VOUT2 ≤ 2V
-2.3
-1
250
+2.0
+1
%
%
mA
VLFB = 1.5V, COUT = 330µF
ILDRV flows from VCC12
-2.3
30
+1.5
%
mA
mA
0.8
V
V
110
91
2
0.5
117
60
111
92
0.7
125
%
%
%
V
%
mA
Fixed Linear Regulator (VOUT2)
Voltage Reference Tolerance
Regulation
Current Limit
Linear Regulator Controller
Voltage Reference Tolerance
Source Current
Sink Current
ILDRV
ILDRV
0.2
VID Pins
Low Input
High Input
Copyright © 1999
Rev. 1.0 4/99
VIL
VIH
Internally pulled up to VCC5 thru 30k
2.0
3
PRODUCT DATABOOK 1996/1997
LX1668
P ROGRAMMABLE M U LTIPLE O UTPUT DC:DC C ONTROLLER
P
R O D U C T I O N
D
A T A
S
H E E T
ELECTRICAL CHARACTERISTICS
Table 1 - Adaptive Transient Voltage Output
Processor Pins
Output Voltage (VSET)
0 = Low, 1 = High
VID4
VID3
VID2
VID1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
1
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
* Nominal = DAC setpoint voltage
(Output Voltage Setpoint — Typical)
VID0
0.0A
Nominal Output* (VSET)
1
1
1.34V
1.30V
1
0
1.39V
1.35V
0
1
1.44V
1.40V
0
0
1.49V
1.45V
1
1
1.54V
1.50V
1
0
1.59V
1.55V
0
1
1.64V
1.60V
0
0
1.69V
1.65V
1
1
1.74V
1.70V
1
0
1.79V
1.75V
0
1
1.84V
1.80V
0
0
1.89V
1.85V
1
1
1.94V
1.90V
1
0
1.99V
1.95V
0
1
2.04V
2.00V
0
0
2.09V
2.05V
1
1
2.04V
2.00V
1
0
2.14V
2.10V
0
1
2.24V
2.20V
0
0
2.34V
2.30V
1
1
2.44V
2.40V
1
0
2.54V
2.50V
0
1
2.64V
2.60V
0
0
2.74V
2.70V
1
1
2.84V
2.80V
1
0
2.94V
2.90V
0
1
3.04V
3.00V
0
0
3.14V
3.10V
1
1
3.24V
3.20V
1
0
3.34V
3.30V
0
1
3.44V
3.40V
0
0
3.54V
3.50V
with no adaptive output voltage positioning.
Note:
Adaptive Transient Voltage Output
In order to improve transient response a 40mV offset is built into the voltage comparator. At high currents, the
peak output voltage will be lower than the nominal set point , as shown in Figure 4. The actual output voltage
will be a function of the sense resistor, output current and output ripple.
4
Copyright © 1999
Rev. 1.0 4/99
PRODUCT DATABOOK 1996/1997
LX1668
P ROGRAMMABLE M U LTIPLE O UTPUT DC:DC C ONTROLLER
P
D
R O D U C T I O N
S
A T A
H E E T
100
100
95
95
90
90
EFFICIENCY (%)
__
EFFICIENCY (%)
__
C H A R A C T E R I S T I C S C U RV E S
85
80
85
80
EFFICIENCY AT 3.1V
EFFICIENCY AT 2.8V
EFFICIENCY AT 1.8V
75
EFFICIE NCY A T 3.1V
EFFICIE NCY A T 2.8V
75
70
EFFICIE NCY A T 1.8V
70
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
5
6
IOUT (A)
7
8
9
10
11
12
13
14
IOUT (A)
FIGURE 2 — Efficiency Test Results:
Synchronous Operation, VIN = 5V
FIGURE 1 — Efficiency Test Results:
Non-Synchronous Operation, V IN = 5V
BLOCK DIAGRAM
15
+5V
VCC3
2.5V
VOUT2
LDRV
VOUT3
LFB
16
60mV
2.5V
5
VCORE
VFB
+12V
2
PWM
IRESET
4
R
Q
S
Q
1
VCC12
TDRV
1.5V
6
PWRGD 14
OVP 13
Set
40mV
VRESET
18
RSS
20k
VID[0:4] 10
L
RSENSE
VCORE
ESR
PGND
AGND
+5V
Hiccup
9
BDRV
CIN
COUT
20
Power Good
& OVP
VREF
8
19
Error Comp
7
VIN (5V)
CS Comp
Hiccup
Off-Time
Control
UVLO
UVLO
3
VCC5
DAC
VSET
11
12
SS/ENABLE
17
CSS
FIGURE 3 — Block Diagram
Copyright © 1999
Rev. 1.0 4/99
5
PRODUCT DATABOOK 1996/1997
LX1668
P ROGRAMMABLE M U LTIPLE O UTPUT DC:DC C ONTROLLER
P
R O D U C T I O N
D
A T A
S
H E E T
FUNCTIONAL PIN DESCRIPTION
6
Pin
Number
Pin
Designator
1
TDRV
Gate drive to the top FET.
2
VCC12
+12V supply for the gate drivers. If 12V is not available in the application, a bootstrap circuit is required
to create the biasing voltage for the FET gate drivers.
3
VCC5
+5V supply for internal biasing and power to the IC.
4
VOUT2
Fixed 2.5V internal LDO regulator output.
5
VCC3
Input for the 2.5V internal LDO regulator — Recommended to be connected to 5V.
6
LDRV
Adjustable LDO driver output. Connect to gate of MOSFET.
7
LFB
Voltage feedback pin of the adjustable LDO regulator (1.5V).
8
9
10
11
12
VID0
VID1
VID2
VID3
VID4
Input pins to the DAC. The output of the DAC sets the nominal voltage of the PWM output (see Table 1).
These inputs are TTL-compatible.
13
OVP
Over-voltage protection: this pin is pulled to above 2V when the switcher output is above 17% of its set
voltage. This pin is capable of sourcing 40mA current, and can be used to drive an SCR crowbar or as a
signal to turn off the main power supply.
14
PWRGD
Open collector output, pulled down when the core voltage is not within ±10% of the DAC output or the
fixed 2.5V LDO output is below 2.0V.
15
VCORE
Output (CPU core) voltage, connected to the output of the regulator (after the sense resistor). This pin is
also connected to the power good and the over current comparators in the IC.
16
VFB
17
SS/ENABLE
18
AGND
Analog ground.
19
BDRV
Bottom FET drive.
20
PGND
Power ground. Ground return for FET drivers.
Description
Dual function pin for feedback and current sensing. The peak voltage of this is set 40mV above the
nominal set-point (VID) voltage. When the voltage difference between this pin and VOUT (pin 15) exceeds
60mV, the over current comparator will be tripped. The over current tripping level can be set as
I = 60mV/RSENSE where R SENSE is the sensing resistance (see Application Note section).
Soft-startup and hiccup capacitor pin. During startup, the voltage of this pin controls the core voltage. An
internal 20kΩ resistor and the external capacitor set the time constant for the soft-startup. Soft-start does
not begin until the supply voltage exceeds the UVLO threshold. When over-current occurs, this capacitor is
used for timing the hiccup. See Application Information for more detail. The PWM output can be disabled
by pulling the SS/ENABLE pin below 0.5V.
Copyright © 1999
Rev. 1.0 4/99
PRODUCT DATABOOK 1996/1997
LX1668
P ROGRAMMABLE M U LTIPLE O UTPUT DC:DC C ONTROLLER
P
R O D U C T I O N
D
A T A
S
H E E T
T H E O R Y O F O P E R AT I O N
SWITCHER OUTPUT VOLTAGE REGULATION
POWER UP and INITIALIZATION
Refer to the IC Block Diagram and the Product Highlight circuit.
When the top MOSFET turns ON, the inductor current increases.
The voltage at VFB pin increases due to the ESR of the output
capacitor and the current-sensing resistor. When the VFB pin
voltage reaches the threshold voltage of the error comparator,
VSET (the DAC output set-point voltage) plus 40mV offset, the
PWM latch is reset. Consequently, the top MOSFET turns OFF
and the bottom (synchronous) MOSFET turns ON. The off-time
control block controls the off-time of the top MOSFET. During
the off-time, the inductor current and the V FB pin voltage
decrease. As the off-time finishes, the synchronous MOSFET
turns OFF and the top MOSFET turns ON again, repeating the
previous cycle. A break-before-make circuit prevents simultaneous conduction of the two MOSFET’s.
The 40mV offset to the set voltage enhances the transient
response of the output voltage, as shown in Figure 4 below.
At power up, the LX1668 monitors the supply voltage to both the
+5V and the +12V pins (there is no special requirement for the
sequence of the two supplies). Before both supplies reach their
under-voltage lock-out (UVLO) thresholds, the soft-start (SS) pin
is held low to prevent soft-start from beginning; the off-time
control is disabled and the top MOSFET is kept OFF. The two
LDO regulators are designed not to over-voltage regardless of
supply voltages. After both supplies pass the UVLO thresholds,
the circuit begins soft-start.
■ The peak voltage at the VFB pin is 40mV higher than the set
voltage and its average is the peak voltage minus the ripple
voltage at VFB pin.
■ The output voltage is the voltage at the VFB pin minus the
voltage drop across the current sensing resistor (I * RSENSE ).
■ At light loads, the voltage drop across the sensing resistor
is small; hence, the output voltage is approximately the
voltage at the VFB pin (approximately 40mV higher than the
set voltage, VSET).
■ At heavy loads, larger current flows in the sense resistor,
therefore, the voltage drop is higher and the output voltage
is lower.
SOFT-START
Once the supplies are above the UVLO threshold, the soft-start
capacitor begins to be charged up by the set voltage (DAC
output) through a 20kΩ internal resistor. The capacitor voltage
at the SS pin rises as a simple RC circuit. The SS pin plus a 40mV
offset is connected to the error comparator’s non-inverting input
that controls the output peak voltage. The output voltage will
follow the SS pin voltage if sufficient charging current is provided
to the output capacitor.
The simple RC soft-start allows the output to rise faster at the
beginning and slower at the end of the soft-start interval. Thus,
the required charging current into the output capacitor is less at
the end of the soft-start interval so decreasing the possibility of
an over-current. A comparator monitors the SS pin voltage and
indicates the end of soft-start when SS pin voltage reaches 95%
of VSET. See Application Information section for further details.
This adaptive positioning of the output voltage as the load
changes allows a greater output voltage excursion during a fast
step-load transient and requires fewer output capacitors to meet
the transient-response specification.
Adaptive voltage
positioning offset
VOFFSET (40mV)
Output voltage
VOUT (50mV/Div)
Steady state voltage at high
current is approximately
VSET + VOFFSET - IOUT x RSENSE
Nominal set-point
voltage, VSET (2.0V)
Dynamic voltage tolerance
VDYN (100mV for 2µs)
Initial voltage drop is
mainly due to the product
of the load current step and
ESR of the capacitors.
∆V = ∆I * ESR
(ESL effects are ignored)
LOUT = 2.5µH, COUT = 6x1500µF Sanyo MV-GX, RSENSE = 2.5mΩ
Output current transient
step, ∆I = 0 to 14A
(5A/Div)
FIGURE 4 — Adaptive Voltage Positioning
Copyright © 1999
Rev. 1.0 4/99
7
PRODUCT DATABOOK 1996/1997
LX1668
P ROGRAMMABLE M U LTIPLE O UTPUT DC:DC C ONTROLLER
P
R O D U C T I O N
D
A T A
S
H E E T
T H E O R Y O F O P E R AT I O N
OVER-CURRENT PROTECTION (OCP) and HICCUP
OVER-VOLTAGE PROTECTION (OVP)
The over-current protection function is tripped when the inductor current exceeds its maximum limit. The current is sensed
with a resistor in series with the inductor. When the voltage
across the sensing resistor exceeds the 60mV threshold, the OCP
comparator outputs a signal to reset the PWM latch and to start
hiccup mode. The soft-start capacitor, CSS, is discharged slowly
(10 times slower than when being charged up by RSS ). When the
voltage on the SS/ENABLE pin reaches a 0.3V threshold, hiccup
finishes and the circuit soft-starts again. During hiccup, the top
MOSFET is OFF and the bottom MOSFET remains ON.
Hiccup is disabled during the soft-start interval, allowing the
circuit to start up with the maximum current. If the rise speed
of the output voltage is too fast, the required charging current to
the output capacitor may be higher than the limit-current. In this
case, the peak inductor current is regulated to the limit-current
by the current-sense comparator. The top MOSFET is turned on
at the end of the controlled off-time and is turned off when the
inductor current reaches the limit. If the inductor current still
reaches its limit after the soft-start finishes, the hiccup is triggered
again. The hiccup ensures the average heat generation on both
MOSFET’s and the average current to be much less than that in
normal operation, if the output has a short circuit.
output voltage exceeds the 117% VSET threshold, the OVP
comparator will pull up the OVP pin to 2 volts. The OVP pin has
a 40mA source current capability, so it can be used to trigger an
SCR crowbar or shut off the main power supply.
OVER-VOLTAGE PROTECTION (OVP)
The output voltage is inherently protected from an over-voltage
situation because of the peak-voltage control mechanism.
Whenever the VFB pin voltage is higher than the set voltage by
40mV, the top MOSFET is turned off and the bottom MOSFET is
turned on. In the case that a fault condition occurs where the
(continued)
OFF-TIME CONTROL and SWITCHING FREQUENCY
An internal timer controls the off-time of the top MOSFET so that
the switching frequency is constant at 200 kHz under steadystate operation. The timer begins timing once the PWM latch is
reset and set the PWM flip-flop again when the off-time finishes.
The off-time is controlled to be:
TOFF = 5µs(1-VOUT /VCC5 )
For a buck converter, the switching frequency is
fSW = (1- VOUT /VCC5 )/T OFF
Therefore, the switching frequency is nearly constant in steady
state operation. During transient loading, the top drive can
remain switched on or off until the output voltage is within
specification (see Figure 5) in order to reduce transient response
time.
POWER GOOD OUTPUT
An open-collector output, PWRGD, is provided to indicate the
status of the output voltages. PWRGD presents high impedance
when the switcher output voltage is within ±10% of its set voltage
and the fixed 2.5V internal LDO regulator output is above 2.0V.
Otherwise, PWRGD presents a low impedance path to ground.
Top FET Drive
Output Voltage
(2.8V Set Point)
13A Load Transient
(in 390ns)
VIN = 5V, VOUT = 2.8V, LOUT = 5µH, COUT = 3 x 1500µF, f = 200kHz
FIGURE 5 — Top FET Drive During Transient Load Conditions
8
Copyright © 1999
Rev. 1.0 4/99
PRODUCT DATABOOK 1996/1997
LX1668
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B I L L O F M AT E R I A L S
LX1668 Bill of Materials (Refer to Product Highlight)
Part Number / Manufacturer
Ref
Description
U1
C1
C2
C4, C6
C5
C7, C8, C9
C3
CSS
Q1
Q2
Q3
RSENSE
R1
R2
L1
L2
Controller IC
Capacitor, 1500µF, 6.3V, 44mΩ ESR
Capacitor, 1500µF, 6.3V, 44mΩ ESR
Capacitor, 330µF, Electrolytic
Capacitor, 22µF, Electrolytic
Capacitor, 1µF, SMD
Capacitor, 1µF, SMD, 16V
Capacitor, 0.1µF, SMD
MOSFET (low RDS(ON))
MOSFET (low RDS(ON))
MOSFET
Sense Resistor, 2.5mΩ
Resistor, 0Ω (see Table 6)
Resistor, 2.5mΩ (see Table 6)
Inductor, 2 - 3µH
Inductor, 1µH
Qty.
LX1668 - LinFinity
MV-GX Sanyo
MV-GX Sanyo
MV-GX Sanyo
MV-GX Sanyo
1
6
3
2
2
2
1
1
1
1
1
1
1
1
1
1
IRL3102/3103, International Rectifier
IRL3303/3103, International Rectifier
IRLZ44N, International Rectifier
PCB trace
SMD
SMD
HM00-97713 or HM00-98637, BI Technologies
Total Number of Components
26
Optional Components for Over-Voltage Protection and Power Good Signal
Q4
R3
SCR
Resistor, 10kΩ
2N6504
SMD
1
1
A P P L I C AT I O N C I R C U I T
5V
3.3V
12V
220µF
12V
220µF
LM358
VCC1
VCC3
LX1668
VID
Synch.
Switcher
1k
External
LDO
220µF
1.5k
VCC
220µF
CPU
GTL+
Clock
Camino/Whitney
Chipset
RIMM
Memory
1.5 - 2V @ 16A
[VRM 8.2/8.4]
1.5V @ 3A
2.5V @ 0.2A
1.8V @ 3A
2.5V @ 2A
FIGURE 6 — Pentium III Processor Power Supply (Whitney / Camino Chipsets)
Copyright © 1999
Rev. 1.0 4/99
9
PRODUCT DATABOOK 1996/1997
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Output Voltage
(2.8V Set Point)
Input Ripple Voltage
Input Current
LOUT = 5µH, LIN = 0
LOUT = 2.2µH, LIN = 0
FIGURE 7 — Effect Of Different Inductor Values
OUTPUT INDUCTOR
The output inductor should be selected to meet the requirements
of the output voltage ripple in steady-state operation and the
inductor current slew-rate during transient.
The peak-to-peak output voltage ripple is:
current applications, such as Pentium and other Socket 7
processors, a 5µH inductor is sufficient. The effect of different
inductor values is shown in Figure 7 above.
Notice how, with a smaller inductor, transient response time
is improved, but at the expense of much greater ripple.
VRIPPLE = ESR * IRIPPLE
INPUT INDUCTOR
where
IRIPPLE =
(VIN - VOUT )
fSW * L
*
VOUT
VIN
IRIPPLE is the inductor ripple current, L is the output inductor
value and ESR is the Effective Series Resistance of the output
capacitor.
IRIPPLE should typically be in the range of 20% to 40% of the
maximum output current. Higher inductance results in lower
output voltage ripple, allowing slightly higher ESR to satisfy the
transient specification. Higher inductance also slows the inductor current slew rate in response to the load-current step change,
∆I, resulting in more output-capacitor voltage droop. The
inductor-current rise and fall times are:
TRISE = L * ∆I/(V IN – VOUT )
and
TFALL = L * ∆I/VOUT
When using electrolytic capacitors, the capacitor voltage
droop is usually negligible, due to the large capacitance.
For higher current applications, such as Pentium II processors, a 2.5µH inductor is recommended for the best combination
of fast response and manageable ripple voltage. For lower
10
In order to supply faster transient load changes, a smaller output
inductor is needed. However, reducing the size of the output
inductor will result in a higher ripple voltage on the input supply,
as shown in Figure 8 above. This noise on the 5V rail can affect
other system components, such as graphics cards. It is recommended that a 1 – 1.5µH inductor, L2, is used on input to the
regulator, to filter the ripple on the 5V supply. Ensure that this
inductor has the same current rating as the output inductor.
OUTPUT CAPACITOR
The output capacitor is sized to meet ripple and transient
performance specifications. Effective Series Resistance (ESR) is
a critical parameter. When a step load current occurs, the output
voltage will have a step that equals the product of the ESR and
the current step, ∆I. In an advanced microprocessor power
supply, the output capacitor is usually selected for ESR instead
of capacitance or RMS current capability. A capacitor that
satisfies the ESR requirement usually has a larger capacitance and
current capability than strictly needed. The allowed ESR can be
found by:
ESR * (IRIPPLE + ∆I ) < VEX
where IRIPPLE is the inductor ripple current, ∆I is the maximum
load current step change, and VEX is the allowed output voltage
Copyright © 1999
Rev. 1.0 4/99
PRODUCT DATABOOK 1996/1997
LX1668
P ROGRAMMABLE M U LTIPLE O UTPUT DC:DC C ONTROLLER
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A P P L I C AT I O N I N F O R M AT I O N
OUTPUT CAPACITOR
(continued)
excursion in the transient. Adaptive voltage positioning increases the value of VEX, allowing a higher ESR value and
reducing the cost of the output capacitor. Typically, the
positioning voltage is 40mV (peak), using the LX1668, and the
transient tolerance is 100mV, resulting in a VEX of 140mV (see
Figure 4).
Electrolytic capacitors can be used for the output capacitor,
but are less stable with age than tantalum capacitors. As they age,
their ESR degrades, reducing the system performance and
increasing the risk of failure. It is recommended that multiple
parallel capacitors be used, so that, as ESR increases with age,
overall performance will still meet the processor’s requirements.
There is frequently strong pressure to use the least expensive
components possible, however, this could lead to degraded
long-term reliability, especially in the case of filter capacitors.
Linfinity’s demonstration boards use Sanyo MV-GX filter capacitors, which are aluminum electrolytic, and have demonstrated
reliability. The Oscon series from Sanyo generally provides the
very best performance in terms of long term ESR stability and
general reliability, but at a substantial cost penalty. The MV-GX
series provides excellent ESR performance at a reasonable cost.
Beware of off-brand, very low-cost filter capacitors, which have
been shown to degrade in both ESR and general electrolytic
characteristics over time.
INPUT CAPACITOR
The input capacitor and the input inductor are to filter the
pulsating current generated by the buck converter to reduce
interference to other circuits connected to the same 5V rail. In
addition, the input capacitor provides local de-coupling the buck
converter. The capacitor should be rated to handle the RMS
current requirement. The RMS current is:
IRMS = I L √ d(1-d)
where IL is the inductor current and the d is the duty cycle. The
maximum value, when d = 50%, IRMS = 0.5I L. For 5V input and
output in the range of 2 to 3V, the required RMS current is very
close to 0.5IL.
A high-frequency (ceramic) capacitor should be placed
across the drain of the top MOSFET and the source of the bottom
one to avoid ringing due to the parasitic inductor being switched
ON and OFF. See capacitor C7 in the Product Highlight.
SOFT-START CAPACITOR
The value of the soft-start capacitor determines how fast the
output voltage rises and how large the inductor current is
required to charge the output capacitor. The output voltage will
follow the voltage at SS pin if the required inductor current does
not exceed the maximum current in the inductor.
Copyright © 1999
Rev. 1.0 4/99
SOFT-START CAPACITOR
(continued)
The SS pin voltage can be expressed as:
VSS = VSET (1-e-t/RssCss)
where VSET is the output of the DAC. RSS and CSS are soft start
resistor and capacitor, as shown in Figure 4. The required
inductor current for the output capacitor to follow the SS-pin
voltage equals the required capacitor current plus the load
current. The soft-start capacitor should be selected so that the
overall inductor current does not exceed it maximum.
The capacitor current to follow the SS-pin voltage is:
ICout = COUT
dV
dt
=
C OUT
C SS
* e-(t/RssCss )
where COUT is the output capacitance. The typical value of CSS
should be in the range of 0.1 to 0.2µF.
During the soft-start interval, before the PWRGD signal
becomes valid, the load current from a microprocessor is
negligible; therefore, the capacitor current is approximately the
required inductor current.
CURRENT LIMIT
Current limiting occurs when a sensed voltage, proportional to
load current, exceeds the current-sense comparator threshold
value. The current can be sensed either by using a fixed sense
resistor in series with the inductor to cause a voltage drop
proportional to current, or by using a resistor and capacitor in
parallel with the inductor to sense the voltage drop across the
parasitic resistance of the inductor. The LX1668 has a threshold
of 60mV.
Sense Resistor
The current sense resistor, RSENSE, is selected according to the
formula:
RSENSE = VTRIP / ITRIP
Where VTRIP is the current sense comparator threshold (60mV)
and ITRIP is the desired current limit. Typical choices are shown
below.
TABLE 2 - Current Sense Resistor Selection Guide
Load
Pentium-Class Processor (10A)
Sense Resistor
Value
5mΩ
2.5mΩ
A smaller sense resistor will result in lower heat dissipation
(I²R) and also a smaller output voltage droop at higher currents.
11
PRODUCT DATABOOK 1996/1997
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CURRENT LIMIT (continued)
There are several alternative types of sense resistor. The
surface-mount metal “staple” form of resistor has the advantage of
exposure to free air to dissipate heat and its value can be
controlled very tightly. Its main drawback, however, is cost. An
alternative is to construct the sense resistor using a copper PCB
trace. Although the resistance cannot be controlled as tightly, the
PCB trace is very low cost.
L
RS
Current
Sense
Comparator
PCB Sense Resistor
A PCB sense resistor should be constructed as shown in Figure 8.
By attaching directly to the large pads for the capacitor and
inductor, heat is dissipated efficiently by the larger copper masses.
Connect the current sense lines as shown to avoid any errors.
2.5mΩ Sense Resistor
Inductor
100mil Wide, 850mil Long
2.5mm x 22mm (2 oz/ft2 copper)
RL
Load
CS
VCS
RS2
FIGURE 9 — Current Sense Circuit
The voltage across the capacitor will be equal to the current
flowing through the resistor, i.e.
VCS = ILRL
Since VCS reflects the inductor current, by selecting the
appropriate RS and CS, VCS can used to sense current.
Output
Capacitor Pad
Design Example
(Pentium II circuit, with a maximum static current of 14.2A)
The gain of the sensor can be characterized as:
The dc/static tripping current Itrip,S satisfies:
|T(j ω)|
Sense Lines
FIGURE 8 — Sense Resistor Construction Diagram
Recommended sense resistor sizes are given in the following
table:
TABLE 3 - PCB Sense Resistor Selection Guide
Copper
Weight
2 oz/ft2
Copper Desired Resistor
Thickness
Value
68µm
2.5mΩ
5mΩ
12
L/RSCS
Dimensions (w x l)
mm
inches
2.5 x 22
2.5 x 43
0.1 x 0.85
1/RSCS
0.1 x 1.7
Loss-Less Current Sensing Using Resistance of Inductor
Any inductor has a parasitic resistance (RL) which causes a DC
voltage drop when current flows through the inductor. Figure 9
shows a sensor circuit comprising of a surface mount resistor, RS,
and capacitor, CS, in parallel with the inductor, eliminating the
current sense resistor.
The current flowing through the inductor is a triangle wave. If
the sensor components are selected such that:
L/RL = RS * CS
RL
RL/L
ω
FIGURE 10 — Sensor Gain
Itrip,S =
V trip
RL
Select L/RSCS ≤ RL to have higher dynamic tripping current than
the static one. The dynamic tripping current Itrip,d satisfies:
Vtrip
Itrip,d = L/(R C )
S S
Copyright © 1999
Rev. 1.0 4/99
PRODUCT DATABOOK 1996/1997
LX1668
P ROGRAMMABLE M U LTIPLE O UTPUT DC:DC C ONTROLLER
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CURRENT LIMIT (continued)
General Guidelines for Selecting RS , CS , and RL
Vtrip
RL =
Select: RS ≤ 10 kΩ
Itrip,S
Ln
CS n = R R
and CS according to:
L
S
The above equation has taken into account the currentdependency of the inductance.
Typical values are: RL = 3mΩ, RS = 9kΩ, CS = 0.1µF, and L is
2.5µH at 0A current.
In cases where RL is so large that the trip point current would
be lower than the desired short-circuit current limit, a resistor (RS2)
can be put in parallel with CS, as shown in Figure 10. The selection
of components is as follows:
RL (Required)
RS2
=
RL (Actual)
RS2 + R S
CS =
L
L
RS + RS2
=
RL (Actual) * (RS2 // RS )
RL (Actual) * RS2 * RS
Again, select (RS2//RS) < 10kΩ. See Application Note AN-7 for
more information.
FET SELECTION (continued)
TABLE 4 - FET Selection Guide
This table gives selection of suitable FETs from International Rectifier.
Device
RDS(ON) @
Ω)
10V (mΩ
ID @
TC = 100°C
Max. Breakdown Voltage
IRL3803
IRL22203N
IRL3103
IRL3102
IRL3303
IRL2703
6
7
14
13
26
40
83
71
40
56
24
17
30
30
30
20
30
30
All devices in TO-220 package. For surface mount devices (TO-263 /
D2-Pak), add 'S' to part number, e.g. IRL3103S.
The recommended solution is to use IRL3102 for the high side
and IRL3303 for the low side FET, for the best combination of cost
and performance. Alternative FET’s from any manufacturer could
be used, provided they meet the same criteria for RDS(ON).
Heat Dissipated In Upper MOSFET
The heat dissipated in the top MOSFET will be:
PD = (I2 * RDS(ON) * Duty Cycle) + (0.5 * I * VIN * t SW * f S )
OUTPUT ENABLE
The LX1668 FET driver outputs are driven to ground by pulling
the soft-start pin below 0.5V.
PROGRAMMING THE OUTPUT VOLTAGE
The output voltage is set by the DAC with a 5-bit digital voltageidentification (VID) code input (see Table 1). The DAC input is
designed to be compatible with digital circuits. The VID code
may be hard-wired into the package of the processor [as in the
case of a Pentium II or Pentium Pro processor]. If the processor
does not have a VID code, the output voltage can be set by
means of a DIP-switch, jumpers or TTL-compatible digital
circuits. When using a DIP-switch or jumpers, connect the VID
pin to ground (DIP-switch ON) for a low or “0” signal and leave
the VID pin open (DIP-switch OFF) for a high or “1” signal.
FET SELECTION
To insure reliable operation, the operating junction temperature
of the FET switches must be kept below certain limits. The Intel
specification states that 115°C maximum junction temperature
should be maintained with an ambient of 50°C. This is achieved
by properly derating the part, and by adequate heat sinking. One
of the most critical parameters for FET selection is the RDS(ON)
resistance. This parameter directly contributes to the power
dissipation of the FET devices, and thus impacts heat sink design,
mechanical layout, and reliability. In general, the larger the
current handling capability of the FET, the lower the RDS(ON) will
be, since more die area is available.
Copyright © 1999
Rev. 1.0 4/99
Where tSW is switching transition line for body diode (~100ns)
and fS is the switching frequency.
For the IRL3102 (13mΩ RDS(ON)), converting 5V to 2.0V at 15A
will result in typical heat dissipation of 1.92W.
Synchronous Rectification – Lower MOSFET
The lower pass element can be either a MOSFET or a Schottky
diode. The use of a MOSFET (synchronous rectification) will result
in higher efficiency, but at higher cost than using a Schottky diode
(non-synchronous).
Power dissipated in the bottom MOSFET will be:
PD = I2 * RDS(ON) * [1 - Duty Cycle] = 3.51W
[IRL3303 or 1.76W for the IRL3102]
Non-Synchronous Operation - Schottky Diode
A typical Schottky diode, with a forward drop of 0.6V will dissipate
0.6 * 15 * [1 – 2/5] = 5.4W (compared to the 1.8 to 3.5W dissipated
by a MOSFET under the same conditions). This power loss
becomes much more significant at lower duty cycles. The use of
a dual Schottky diode in a single TO-220 package (e.g. the
MBR2535) helps improve thermal dissipation.
13
PRODUCT DATABOOK 1996/1997
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LINEAR REGULATOR
Capcitor Selection
The internal LDO regulator and the external linear regulator
driver are both designed to be insensitive to selection of
capacitors. Most Aluminum or Tantalum electrolytic capacitor
will make for suitable operation. Capacitors should be chosen
so that the voltage drop during a load transient does not exceed
the relevant specifications.
Internal LDO
A 22µF aluminum electrolytic is recommended for optimal
performance for power clock circuits at 2.5V.
External LDO
A 330µF aluminum electrolytic is recommended for powering VTT
at 1.5V. This will provide sufficient voltage hold-up for any
expected transients on the GTL+ Bus.
Internal Fixed-Voltage LDO Regulator
The internal LDO regulator has a fixed 2.5V output voltage and
is intended for powering the clock circuit. Its current is limited
to 250mA. The limitation for using this LDO regulator is heat
dissipation. Power dissipation should not exceed the limit of
400mW on average for SOIC package and 300mW for TSSOP
package.
The power dissipated in the internal LDO is as follows:
TABLE 6 Resistors Settings for Linear Regulator Output Voltage
Nominal
Set Point (V)
Ω)
R1 (kΩ
Ω)
R2 (kΩ
VOUT (V)
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
12
11.3
11.3
11
10.3
10
10
10
9.76
8.87
8.87
8.87
8.87
8.87
8.87
7.15
7.15
7.15
0
10
10
10.7
11
11
11.5
12.4
13.7
14.7
14.7
16.5
18.7
22.1
26.7
21
35.7
53.6
100
50
3.30
3.20
3.08
3.00
2.90
2.80
2.71
2.59
2.50
2.41
2.31
2.21
2.10
2.00
2.13
1.80
1.70
1.61
1.50
The maximum output current from the linear regulator section is
around 5 - 7A, and is limited only by the MOSFET’s thermal
dissipation performance (Power dissipation is equal to the
voltage drop across the MOSFET multiplied by the current; PD =
[VIN - VOUT3] * IOUT3 ). For this reason, it is preferable to use a 3.3V
supply when powering a 1.5V GTL+ Bus using the external LDO.
For example, the heat dissipated in converting 3.3V to 1.5V
at 3A would be:
PD = (VCC3 – VOUT2 ) * IOUT2
where IOUT2 is the output current from the linear regulator.
VCC3 can be connected to 5V or 3.3V, but 5V is recommended for
optimal performance.
Adjustable External LDO Regulator
The LX1668 has a linear regulator driver function. A low dropout
linear regulator can be constructed by connecting an external
MOSFET to the LDRV and LFB pins. The MOSFET can provide an
output with a minimum voltage of 1.5V. The dropout voltage
across the regulator is the product of RDS(ON) and current – this
limits the upper voltage.
The linear regulator output, VOUT3, can be used to power GTL+
Bus circuits in a Pentium II processor application at 1.5V. In this
case, the output can be connected directly to the LFB pin without
the use of resistors to set the output voltage. If an alternative
output voltage is required, a resistor divider sets the output as
follows:
VOUT3 = 1.5V * (1+R1 /R2 )
14
PD = (3.3 – 1.5) * 3 = 5.4W
Note that the MOSFET requires the same heatsink as would
be necessary for a monolithic LDO such as the LX8384.
The dropout voltage of the linear regulator will be determined by the RDS(ON) of the MOSFET (V DO = RDS(ON) * II/O). Using
a 2SK1388 at 5A, the worst case dropout voltage will be 37mΩ
* 5A = 185mV. Note that the RDS(ON) does not affect the power
dissipation, only dropout voltage. For reasons of economy,
choose a FET with higher RDS(ON) than that used for the PWM
output stages.
Disabling Linear Output
Linear regulator output can be disabled by pulling feedback pin
(LFB) up to 3.3V or 5V as shown in Figure 11. This pin should not
be pulled higher than 5V.
TABLE 7 - Linear Enable (LIN EN) Function Table
LIN EN
LIN OUTPUT
H
Disabled
L
Enabled
Copyright © 1999
Rev. 1.0 4/99
PRODUCT DATABOOK 1996/1997
LX1668
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A P P L I C AT I O N I N F O R M AT I O N
LINEAR REGULATOR (continued)
LAYOUT GUIDELINES - THERMAL DESIGN (continued)
Power Traces
To reduce power losses due to ohmic resistance, careful consideration should be given to the layout of traces that carry high
currents. The main paths to consider are:
3.3V/5V
LX1668
LDRV
LFB
C5
330µF
6
7
Q4
IRLZ44
R1
10k
10k
Supply Voltage
For I/O Chipset
C7
330µF
R2
LIN EN
■ Input power from 5V supply to drain of top MOSFET.
■ Trace between top MOSFET and lower MOSFET or Schottky
diode.
■ Trace between lower MOSFET or Schottky diode and ground.
■ Trace between source of top MOSFET and inductor, sense
resistor and load.
■ Current traces on both LDO sections
3.3V
Input
2N2222
FIGURE 11 — Enabling Linear Regulator
3.3V / 5V
Input
VOUT2
5V Input
VCC3
LX166x
LAYOUT GUIDELINES - THERMAL DESIGN
A great deal of time and effort were spent optimizing the thermal
design of the demonstration boards. Any user who intends to
implement an embedded motherboard would be well advised to
carefully read and follow these guidelines. If the FET switches
have been carefully selected, external heatsinking is generally not
required. However, this means that copper trace on the PC board
must now be used. This is a potential trouble spot; as much
copper area as possible must be dedicated to heatsinking the FET
switches, and the diode as well if a non-synchronous solution is
used.
In our demonstration board, heatsink area was taken from
internal ground and VCC planes which were actually split and
connected with VIAS to the power device tabs. The TO-220 and
TO-263 cases are well suited for this application, and are the
preferred packages. Remember to remove any conformal coating
from all exposed PC traces which are involved in heatsinking.
General Notes
As always, be sure to provide local capacitive decoupling close to
the chip. Be sure use ground plane construction for all highfrequency work. Use low ESR capacitors where justified, but be
alert for damping and ringing problems. High-frequency designs
demand careful routing and layout, and may require several
iterations to achieve desired performance levels.
Output
VOUT3
PGND
FIGURE 12 — Power Traces
All of these traces should be made as wide and thick as
possible, in order to minimize resistance and hence power losses.
It is also recommended that, whenever possible, the ground, input
and output power signals should be on separate planes (PCB
layers). See Figure 12 – bold traces are power traces.
Input Decoupling Capacitors
Ensure that capacitors C8 and C3 are placed as close to the IC as
possible to minimize the effects of noise on the device.
Layout Assistance
Please contact Linfinity’s Applications Engineers for assistance
with any layout or component selection issues. A Gerber file with
layout for the most popular devices is available upon request.
Evaluation boards are also available upon request. Please
check Linfinity's web site for further application notes.
Pentium is a registered trademark of Intel Corporation.
PRODUCTION DATA - Information contained in this document is proprietary to Lin Finity, and is current as of publication date. This document
may not be modified in any way without the express written consent of LinFinity. Product processing does not necessarily include testing of
all parameters. Linfinity reserves the right to change the configuration and performance of the product and to discontinue product at any time.
Copyright © 1999
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