LX1688

RangeMAX™ TM ® LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET DESCRIPTION The LX1688 is a fixed frequency, dual current/voltage mode, switching regulator that provides the control function for Cold Cathode Fluorescent Lighting (CCFL). This controller can be used to drive a single lamp, but is specifically designed for multiple lamp LCD panels. The IC can be configured as a master or slave and synchronize up to 12 controllers. The LX1688 includes highly integrated universal ‘PWM or DC’ dim input that allows either a PWM or DC input to adjust brightness without requiring external conditioning, since a single external capacitor CPWM can be used to integrate a PWM input. Burst mode dimming is possible if the user supplies a low frequency PWM signal on the BRITE input and no CPWM capacitor is used. The controller utilizes Microsemi’s patented direct drive fixed frequency topology and patented resonant lamp strike generation technique. Safety and reliability features include a dual feedback control loop that permits regulation of maximum lamp strike voltage as well as lamp current. Regulating maximum lamp voltage permits the designer to provide for ample worst-case lamp strike voltage while conservatively limiting maximum open circuit voltage. In addition the controller features include auto shutdown for an open or broken lamp, and a lamp fault detection with a status reporting output. To improve design flexibility the IC includes the ability to select the polarity of both the chip enable and dim (BRITE) inputs. Also included is a switched VDD output of up to 10mA that will allow the user to power other circuitry that can be switched on and off with the inverters enable input. This preserves the micro power sleep mode with no additional components. KEY FEATURES Provision to Synchronize Lamp Current & Frequency With Other Controllers Dimming With Analog or Digital (PWM) Methods (>20:1) Programmable Fixed Frequency Adjustable Power-up Reset ENABLE/BRITE Polarity Selection Voltage Limiting on Step-up Transformer Secondary Winding Open Lamp Timeout Circuitry Switched VDD Output (10mA) Micro-Amp Sleep Mode Operates With 3.3V to 5V Supply 100mA Output Drive Capability APPLICATIONS / BENEFITS W WW . Microsemi . C OM IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com Protected by U.S. Patents 5,615,093; 5,923,129; 5,930,121; 6,198,234; Patents Pending Desktop LCD Monitors Multiple Lamp Panels Low Ambient Light Displays High Efficiency Lower Cost than Conventional Buck/Royer Inverter Topologies Improved Lamp Strike Capability Improved Over-Voltage Control PRODUCT HIGHLIGHT DIMMING (BRITE) ENABLE LAMPS FETS PHASE SYNC RAMP RESET INPUT CONNECTOR 12 13 LX1688 MASTER 24 STRIKE STATUS FAULT 1 FAULT 1 FAULT 2 ENABLE BRITE 125 Hz 5% Duty cycle Burst 65KHz run frequency FETS 12 13 LX1688 SLAVE 24 VDD FAULT 2 STRIKE STATUS Ch3 10.0mV Ω Ch2 10.0mV Ω M100µs Simplified Quad Lamp Inverter Showing Synchronized Output Waveforms PACKAGE ORDER INFO TJ (°C) MIN VDD MAX VDD LX1688 LX1688 PW Plastic TSSOP 24-Pin RoHS compliant / Pb-free Transition DC: 0442 0 to 70 -40 to 85 3.0V 3.0V 5.5V 5.5V LX1688CPW LX1688IPW Note: Available in Tape & Reel. Append the letters “TR” to the part number. (i.e. LX1688CPW-TR) Copyright © 2001 Rev. 1.2, 2006-03-09 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 1 RangeMAX™ TM ® LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET ABSOLUTE MAXIMUM RATINGS Supply Voltage (VDD_P, VDD)................................................................................ 6.5V Digital Inputs ................................................................................... -0.3V to VDD +0.5V Analog Inputs.................................................................................. –0.1V to VDD +0.5V Digital Outputs................................................................................. -0.3V to VDD +0.5V Analog Outputs ................................................................................ -0.1V to VDD +0.5V Maximum Operating Junction Temperature ............................................................150°C Storage Temperature................................................................................. -65°C to 150°C Peak Package Solder Reflow Temp. (40 seconds max. exposure) ................260°C(+0.-5) Note 1: Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal. THERMAL DATA PACKAGE PIN OUT W WW . Microsemi . C OM AOUT VSS_P VSS BEPOL BRITE CPOR ENABLE I_R CPWM1 CPWM2 RMP_RST PHA_SYNC 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 BOUT VDD_P VDD VDDSW TRI_C OLSNS ISNS ICOMP VCOMP VSNS SLAVE FAULT PW PACKAGE (Top View) RoHS / Pb-free 100% matte Tin Lead Finish PW Plastic TSSOP 24-Pin THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA 100°C/W Junction Temperature Calculation: TJ = TA + (PD x θJA). The θJA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow. Pin Name AOUT VSS_P VSS BEPOL BRITE CPOR ENABLE I_R CPWM1 FUNCTIONAL PIN DESCRIPTION Description Pin Name Output Driver A Connects to dedicated GND for Aout and Bout Drivers Connects to analog GND Tri-mode input pin to control the polarity of the ENABLE and BRITE signal Analog/PWM input for brightness control Connects an external capacitor CPOR to VDD and is used for setting power-up reset pulse width. Used to enable or disable the chip Connects to external resistor RI; for bias current setting for internal oscillator Connects to external capacitor CPWM, used for integrating an external digital PWM signal for analog dimming Connects to external capacitor CPWM, used for integrating an external digital PWM signal for analog dimming. If SLAVE = “0”, RMP_RST is a CMOS output; if SLAVE = “1”, it is a CMOS input that locks the ramp oscillation frequency to the master clock If SLAVE= “0”, PHA_SYNC is a CMOS output; if SLAVE = “1”, it is a CMOS input that make the AOUT/BOUT phase synchronous with the master BOUT VDD_P VDD VDDSW TRI_C OLSNS ISNS ICOMP VCOMP Description Output Driver B Connects to dedicated VDD for Aout and Bout Drivers Connects to analog VDD Switchable VDD output controlled by ENABLE Connects to external capacitor CTRI Analog input to detect open-lamp condition Analog input from lamp current, has built-in 300mv offset Current error Amp’s output; connects to external capacitor CICOMP Voltage error Amp’s output; connects to external capacitor CVCOMP, can be used for soft-start P D PACKAGE DATA CPWM2 VSNS Analog input from transformer output voltage Input control pin for setting the IC either in Master or Slave mode; “1” for slave mode and “0” for master mode. Digital output to indicate maximum number of lamp striking attempts has occurred without lamp ignition. RMP_RST SLAVE PHA_SYNC FAULT Copyright © 2001 Rev. 1.2, 2006-03-09 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 2 RangeMAX™ TM ® LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET RECOMMENDED OPERATING CONDITIONS W WW . Microsemi . C OM Parameter Supply Voltage (VDD ,VDDP) BRITE Linear DC Voltage Range BRITE PWM Logic Signal Voltage Range Digital Inputs (SLAVE, PHA_SYNC, RMP_RST, BEPOL, ENABLE ) Min 3 1 0 0 LX1688 Typ Max 5.5 2.5 VDD VDD Units V V V V ELECTRICAL CHARACTERISTICS Unless otherwise specified, specifications apply over the range: TA=-40 to 85 C, VDD (For LX1688IWP) & TA= 0 to 70 C, VDD (For LX1688CWP), VDD_P = 3.0 to 5.5V. RI = 80Kohms, CTRI = 0.083µF O O Parameter DIMMER Conventional¹ Dimming BRITE Input Voltage Reverse Dimming BRITE Input Voltage Max Brightness VBRT Voltage Full-darkness VBRT voltage ISNS input threshold voltage ISNS input threshold voltage BRITE-to-ICOMP propagation delay STRIKE AND RAMP GENERATOR Max. number of strike before fault Triangular Wave Generator Analog Output Peak Voltage Triangular Wave Generator Analog Output Valley Voltage Triangular Wave Generator Oscillation Frequency Max. Lamp Strike Frequency Lamp Run Frequency Lamp Run Frequency Lamp Run Frequency regulation over VDD OLSNS threshold voltage OLSNS hysteresis OLSNS-to-ICOMP propagation delay Fault, PHA_SYNC, RMP_RST, logic high threshold Fault, PHA_SYNC, RMP_RST, logic low threshold Minimum Fault-pin output current Symbol VBRITE_MAX VBRITE_MIN VBRITE_MAX VBRITE_MIN VBRT_FULL VBRT_DARK VTH_IAMP VTH_IAMP TD_BRITE NFAULT VP_TRI VV_TRI F_TRI FMAX_STK FLAMP FLAMP FLAMP_REG VTH_OLSNS VH_OLSNS TD_OLSNS VH VL I_FAULT Test Conditions VBEPOL = VDD VBEPOL = VDD VBEPOL = VSS or float VBEPOL = VSS or float VBEPOL = VSS, VBRITE = 0.4V VBEPOL = VSS, VBRITE = 2.6V TA= 0 to 70 C TA= -40 to 85 C O O Min 2.6 0.4 0.4 2.6 1.90 150 150 LX1688 Typ. 2.5 0.5 0.5 2.5 2.0 0 300 300 2 Max Units V V 2.05 0.05 450 550 V V mV mV µS 63 2.3 0.15 7 FMAX_STK = FLAMP X ~2.5 VOLSNS > 0.65V; VDD=5V O TA= 0 to 70 C VOLSNS > 0.65V; VDD=5V O TA=-40 to 85 C VOLSNS > 0.65V 150 60 57 2.5 0.3 10 195 65 65 4 740 540 GBNT ² VDD – 0.5 0.7 10 15 1 790 590 70 70 6 840 640 1 2.6 0.40 13 V V Hz KHz KHz KHz % /V ‘mV ‘mV us V V ‘mA E ELECTRICALS ¹Conventional polarity means that the lamp brightness increases with increasing voltage on the BRITE pin. Reverse polarity means that brightness decreases with increasing voltage ² Guaranteed but not production tested Copyright © 2001 Rev. 1.2, 2006-03-09 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 3 RangeMAX™ TM ® LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET ELECTRICAL CHARACTERISTICS (CONTINUED) W WW . Microsemi . C OM Parameter Minimum PHA_SYNC-pin output current Minimum RMP_RST-pin output current Minimum A_SYNC output pulse duty-cycle Minimum A_SYNC input pulse duty-cycle Minimum RMP_RST output pulse duty-cycle Minimum RMP_RST input pulse duty-cycle OUTPUT BUFFER Output Sink Current Output Source Current Output Sink Current Output Source Current Output Sink Current PWM VSNS threshold voltage VCOMP Discharge Current IAMP transconductance VAMP, IAMP output source current VAMP, IAMP output sink current ICOMP discharge current VAMP transconductance ICOMP-to-output propagation delay BIAS Voltage at Pin I_R Pin I_R max. source current Power-on Reset Pulse Width Minimum VDDSW sourcing Current VDDSW Off Current GENERAL Operating Current Output buffer operating current ENABLE logic threshold ENABLE threshold hysteresis Sleep-mode current (see table-1 for Pin ENABLE polarity) Symbol I_PHA_SYNC I_RMP_RST DO_ASYNC DI_ASYNC DO_RST DI_RST ISK_OUTBUF IS_OUTBUF ISK_OUTBUF IS_OUTBUF ISK_OUTBUF VTH_VSNS ID_VCOMP GM_IAMP IS_IAMP ISK_IAMP ID_ICOMP GM_ICMP TD_ICOMP V_IR IMAX_IR TPOR IMIN_VDDSW IOFF_VDDSW IDD IDD_P VTH_EN VTH_EN IDD_SLEEP IDD_SLEEP IDD_SLEEP IDD_SLEEP Test Conditions VSLAVE = 0V VSLAVE = 0V VSLAVE = 0V VSLAVE = VDD VSLAVE = 0V VSLAVE = VDD VAOUT, BOUT = 1V VDD = 5.5V VAOUT, BOUT = 4.5V VDD = 5.5V VAOUT, BOUT = 1V, VDD = 3V VAOUT, BOUT = 2V, VDD = 3V VAOUT, BOUT = 1V, VDD = 5.5V Min 10 10 49 48 10 5 LX1688 Typ. Max Units ‘mA mA STRIKE AND RAMP GENERATOR (CONTINUED) 50 50 17 % % % % 100 100 50 50 100 1.2 1.25 4 200 75 75 10 200 500 1100 0.95 50 1.05 31 10 25 1 5.5 2 0.8 1.7 0.2 20 20 20 20 2.6 2.8 190 15 8 4 2.4 50 50 800 1.3 500 ‘mA ‘mA ‘mA ‘mA ‘mA V ‘mA µmho µA µA ‘mA µmho nS V µA mS ‘mA µA mA mA V ΔISNS = 0.2V VCOMP, ICOMP = 0 VCOMP, ICOMP =VDD ΔVSNS = 0.1V 100 CPOR =.1uF (VDD – VDDSW ) < 0.2V VENABLE = 0.8V, VBEPOL = VDD VDDSW = 0V VDD = VDD_P = 5V VOLSNS = VDD = VDD_P = 5V, CA = CB = 1000pF E ELECTRICALS V VDD_P Leakage in Sleep Mode UVLO threshold UVLO hysteresis VTH_UVLO VH_UVLO VENABLE = 0.8V (VBEPOL = VDD or float) VENABLE = 2.5V (VBEPOL = VDD or float) VENABLE = 0.8V (VBEPOL = VSS) VENABLE = 2.5V (VBEPOL = VSS) Rising turn-on threshold Falling turn-off hysteresis µA 300 300 2.9 V mV Copyright © 2001 Rev. 1.2, 2006-03-09 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 4 RangeMAX™ TM ® LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET RESPONSE VS WAVELENGTH Typical Operating Current (VDD) 6 5.5 VDD Input Current (mA) ISNS Input Threshold (V) ISNK STEP RESPONSE ISNS Input Threshold Voltage Vs Temperature 380 360 W WW . Microsemi . C OM VDD=5.5V 5 4.5 VDD=3V 4 3.5 3 -40 340 320 300 280 260 240 220 200 180 VDD=5.5V VDD=3V -15 10 35 Temperature (°C) 60 85 -40 -15 10 35 60 85 Temperature (°C) Output Frequency Vs Temperature 70 68 Output Frequency (KHz) UVLO Thresholds (V) 66 64 62 2.9 2.85 Under Voltage Lockout Vs Temperature Turn On VDD=5V 2.8 2.75 2.7 2.65 2.6 2.55 2.5 VDD=3V 60 58 56 -40 -15 10 35 60 85 Turn Off -40 -15 10 35 60 85 T emperature (°C) Temperature (°C) I_R Voltage Vs Temperature VDD=V 1.010 1.008 1.006 I_R Voltage (V) 1.004 1.002 1.000 Power-on-Reset Pulse Width Vs Temperature VDD=5V 40 35 TPOR(mS) 30 25 20 0.998 0.996 -40 15 -40 -15 10 35 Temperature (°C) 60 85 -15 10 35 Temperature (°C) 60 85 C CHARTS Copyright © 2001 Rev. 1.2, 2006-03-09 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 5 RangeMAX™ TM ® LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET TABLE 1 W WW . Microsemi . C OM Pin BEPOL VDD FLOAT VSS ENABLE POLARITY + (HI = CHIP_ON, LOW = CHIP_OFF + (HI = CHIP_ON, LOW = CHIP_OFF) - (LOW = CHIP_ON, HI = CHIP_OFF) DIMMING POLARITY* CONVENTIONAL REVERSE REVERSE * Conventional polarity means that the lamp brightness increases with increasing voltage on the BRITE pin. Reverse polarity means that brightness decreases with increasing voltage OPERATIONAL MODES Controller Mode Master Controller Operation Run Striking Fault Run Slave Striking Fault Input Pin: OLSNS > 0.6V < 0.2V X > 0.6V < 0.2V X Input Pin: SLAVE VSS VSS VSS VDD VDD VDD Output Pin: FAULT L L H L L H Pin: RMP_RST Output: FINT Output: FINT Output: FINT Input: FEXT Input: FEXT Input: FEXT Pin: A_SYNC Output: FINT / 2 Output: FINT / 2 Output: FINT / 2 Input: FEXT / 2 Input: FEXT / 2 Input: FEXT / 2 Lamp Frequency FINT / 2 Ramping up / down Off FEXT / 2 Ramping up / down Off SIMPLIFIED BLOCK DIAGRAM ISNS VSNS FEXT/2 ERROR AMP TFF R PWR_ GD PWR_ BD 1.25V VAMP PWR_ GD FAULT VOLTAGE COMPARATOR VCOMP ICOMP VDD_P Q PHA_SYNC Q A OUT T SLAVE RMP_RST FINT RAMP RUN GENERATOR STRIKE GENERATOR PWR_BD FAULT OUTPUT STEERING LOGIC Q B OUT VSS_P FEXT 300mV IAMP CURRENT COMPARATOR 1V 200K + 100K 100K 1V + BRT 100K 0-2V 800mV 600mV BRITE + - 2.5 V 100K IGNITE OLSNS CPW 1 CPW 2 BEPOL 1M 0.5 V 1M PWR_ BD VDD 6 BIT COUNTER TRI WAVE GEN TRI_C BLOCK DIAGRAM BLOCK DIAGRAM POLARITY DECODE BIAS GEN UVLO PWR_GD FAULT ENABLE VDDSW TTL BUF INTERNAL VDD PWR_BD TTL BUF FAULT VSS LX1688 VSS VDD I_R CPOR Figure – Simplified Block Diagram Copyright © 2001 Rev. 1.2, 2006-03-09 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 6 RangeMAX™ TM ® LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET DETAILED DESCRIPTION The LX1688 is a backlight controller specifically designed with a special feature set needed in multiple lamp desktop monitors, and other multiple lamp displays. While utilizing the same architecture as Microsemi’s LX1686 controller it eliminates the synchronized digital dimming and adds, lamp ‘strike’ count out timer, lamp fault status output, and external clock input/output that permits multiple controllers to synchronize their output current both in frequency and phase. OPERATION FROM 3.3V AND/OR 5.0V INPUT SUPPLY The LX1688 is designed to operate and meet all specifications at 3.3V ±10% to 5.0V ±10%. The under voltage lockout is set at nominally 2.8V with a 190mV hysteresis. MASTER/SLAVE CLOCK SYNCHRONIZATION One or more controllers (up to 11) may be designated as slave controllers and receive ramp reset and phase synchronization from the designated master controller. This will allow up to 12 lamps (24 with two lamps in series/controller design) to all operate in phase and frequency synchronization. This is important to prevent random interference between lamps through unpredictably changing electric and magnetic fields that will inevitably link them. The LX1688 has two independent oscillators, one for lamp strike and one for the lamp run frequency. The strike oscillator ramps the operating frequency slowly up and down when the open lamp sense input (OLSNS) indicates the lamp is not ignited. During this lamp strike condition the operating frequency of each IC will vary up and down as needed to strike its lamp. The controller is so designed that the master controller clock remains at the pre-selected frequency for fully ignited lamps even while striking. Likewise the designated slave controller will not alter the frequency or phase of the master clock during its strike phase. Thus each controller will vary its frequency as needed to strike its lamp then it will synchronize to the master clock frequency and phase. The TRI_C wave generator (see Block Diagram) sets the rate of operating frequency variation during lamp strike. The TRI_C generator is connected to a 6-bit counter that times out after 63 cycles and then latches the FAULT output high if the OLSNS input indicates no lamp current is flowing. Even in the case of timeout fault the master controller clock will continue to provide synchronization to the slave controllers. When synchronizing more than one controller the Ramp Reset (RMP_RST), Phase Sync (PHA_SYNC), and Slave Input/Output are used. RMP_RST and PHA_SYNC should be connected between all the controllers. The master controller should have its SLAVE pin connected to VSS (GND) and the slave controllers SLAVE input to VDD (High). BEPOL INPUT The BEPOL pin is a tri-mode input that controls the polarity of the ENABLE and BRITE input signals. Depending on the state of this pin (VDD, floating, or VSS) the controller can be set to allow active high enable with active high full brightness or active high or low enable with active low full brightness (see Table 1). BRITE INPUT (DIMMING INPUT) The BRITE input is capable of accepting either a DC voltage (> .5V to < 2.5V) or a PWM digital signal that is clamped on chip (< .5V or > 2.5V). A digital signal can either be passed unfiltered to effect pulse ‘digital’ dimming or filtered with a capacitor to effect analog dimming with a digital PWM signal. Analog Dimming Methods: • Mechanical or digital potentiometer set to provide 1V to 2.5V on the wiper output. A filter cap from BRITE to signal ground is recommended. • D/A converter output directly connected to BRITE input. A R/C filter using a capacitor from the CPW1 input to ground for applications where the ADC output may contain noise sufficient to modulate the BRITE input. • A high frequency PWM digital logic pulse connected directly to the BRITE input. The Brightness (BRT, internal node) output will be sensitive only to the PWM duty cycle, and not to the PWM signal amplitude, so long as the amplitude exceeds 2.6V for a logic high (1) and is less than .4V for a logic (0). This pulse frequency will typically be between 1KHz and 100KHz and will not be synchronized with the LCD video frame rate. A capacitor (CPWM) between CPW1 and CPW2 will integrate the PWM signal for use by the controller. Digital Dimming Methods: • Low frequency PWM digital logic pulses connected directly to the BRITE input. As above the Brightness (BRT internal) will be sensitive only to the PWM duty cycle, and not to the PWM signal amplitude, so long as the amplitude exceeds 2.6V for a logic high (1) and is less than .4V for a logic (0). This pulse frequency will typically be in the range of 90-320Hz. W WW . Microsemi . C OM A APPLICATIONS Copyright © 2001 Rev. 1.2, 2006-03-09 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 7 RangeMAX™ TM ® LX1688 Multiple Lamp CCFL Controller P RODUCTION D ATA S HEET DETAILED DESCRIPTION and may or may not be externally synchronized to the LCD video frame rate. It will directly gate the signal BRT. CPWM should not be used in this case. FAULT PIN The fault pin is a digital output that indicates that the maximum numbers of strike attempts has occurred without lamp ignition. In this condition the FAULT pin will go active high with typically 20mA drive capability. Holding the OLSNS pin low (