LX1689_06

LX1689 TM ® Third Generation CCFL Controller P RODUCTION D ATA S HEET DESCRIPTION KEY FEATURES W WW . Microsemi . C OM The LX1689 is the latest generation Direct Drive CCFL (Cold Cathode Fluorescent Lamp) Controller. It uses new circuit design techniques (patents pending) and combines digital and linear circuits with an advanced BiCMOS process to create a more complete controller in a small package. When compared to the original LX1686 design, identical module applications use from 12 to 30 less components. New functions and enhancements have been added to make the LX1689 even easier to use. The on-chip PLL circuit used to synchronize the digital dimming burst frequency to the video frame rate, as used in the LX1686, is replaced with a programmable counter. This counter can divide the video controller horizontal sync pulse, other external clock source or the internal chip clock source to generate the burst frequency. The brightness control input allows the use of either a DC voltage or a PWM input to simplify design. Programmable polarity brightness control is retained, except in the case of externally clocked digital dimming. Two onboard LDO regulators extend the input voltage range of the IC up to 28 Volts without using external circuitry as was required with our previous controllers. The LX1689 includes a new lamp strike detection scheme that saves a package pin and three external components. Internal circuits monitor lamp current pulses at the I_SNS input to determine if the lamp strikes and if it stays ignited once operational. Integrating full wave rectifiers for each of three lamp inputs has significantly reduced the lamp feedback component count. In addition the controller features include auto shutdown for open or broken lamps, and a lamp fault detection with a status reporting output. 3 to 28 Volt Single Fixed (±20%) Supply Operating Range Selectable Analog/Digital Dimming Modes Digital Dimming Can Synch to External Or Internal Clocks User Programmable Digital Dimming Burst Frequency 252 mS Power On Delay Flexible Lamp Current Compensation Input Open Lamp Shutdown and Fault Output Indicator “On Chip” Full Wave Lamp Current & Voltage Rectifiers 20 Pin TSSOP Package BENEFITS Low Component Count / Module Cost / Size High “Nits/Watt” Efficiency Operates Directly From 1 to 6 Li_Ion Cells Lamp Current Compensation Input Makes Indoor/Outdoor And Wide Temperature Range Applications Easy to Design IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com Protected By U.S. Patents: 5,615,093; 5,923,129; 5,930,121; 6,198,234; Patents Pending PRODUCT HIGHLIGHT LX1689 CCFL Inverter Layouts Examples* 2.64in. (67mm) .397 in. (10mm) Actual Inverter Size OR 1.38in. (35mm) .870 in. (22mm) Actual Inverter Size *As Shown in Figure 1 (Typical Application) Bill of Materials 1 LX1689CPW 1 Transformer 1 Dual FET 2 Connectors 7 Resistors 9 Capacitors 21 Total Count LX1689 LX1689 PACKAGE ORDER INFO TJ (°C) 0 to 70 -40 to 85 MIN VDD 3V 3V MAX VDD 28V 28V PW Plastic TSSOP 20-PIN LX1689CPW LX1689IPW RoHS Compliant / Pb-free Transition DC: 0442 Note: Available in Tape & Reel. Append the letters “TR” to the part number. (i.e. LX1689CPW-TR) Copyright © 2000 Rev. 1.1, 2006-02-27 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 1 LX1689 TM ® Third Generation CCFL Controller P RODUCTION D ATA S HEET ABSOLUTE MAXIMUM RATINGS Supply Voltage (V_BATT)................................................................................................. 30V Digital Input (ENABLE).....................................................................................-0.3V to 7V Analog Inputs Transient Peak (I_SNS, OC_SNS, OV_SNS)..............................-25V to +25V Analog Inputs (BRITE_IN, EA_IN).................................................................. -0.3V to 5.5V Digital Inputs (DIM_CLK,DIM_MODE, DIV_248) ......................................... -0.3V to 5.5V Digital Output (AOUT, BOUT) .................................................................-0.3V to VDD_P +0.5V Analog Outputs (BRITE_C, I_R, BRITE_OUT, BRITE_R, EA_OUT) ...-0.3V to VDD_A_ +0.5V Storage Temperature Range ........................................................................ -65°C to 150°C Maximum Operating Junction Temperature...............................................................150°C RoHS / Pb-free Peak Package Solder Reflow Temperature (40 second maximum exposure).....................................................................260°C (+0,-5) Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of specified terminal. PACKAGE PIN OUT W WW . Microsemi . C OM GND AOUT BOUT DIM_CLK DIM_MODE DIV_248 BRITE_C BRITE_R BRITE_IN ENABLE 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD_P VDD_A V_BATT OC_SNS OV_SNS I_SNS BRITE_OUT EA_OUT EA_IN I_R PW PACKAGE (Top View) RoHS / Pb-free 100% Matte Tin Lead Finish THERMAL DATA PW Plastic TSSOP 20-Pin 144°C/W THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA Junction Temperature Calculation: TJ = TA + (PD x θJA). The θJA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow. FUNCTIONAL PIN DESCRIPTION PIN NAME GND Ground Power VDD_P Supply Output. This output pin is used to connect an external capacitor to stabilize and filter the on chip VDD_P LDO regulator. The input of the LDO is the switched V_BATT supply. LDO output is normally 5.3V and is used only to drive the output buffers at AOUT and BOUT. The external capacitor will be a 100 to 1000nF ceramic dielectric. Up to 5mA DC additional load may be imposed by external circuitry. External load must be reduced if the combination of output current and input voltage exceeds power dissipation capability of the die. A buffer N-FET driver output. The pin includes a internal 10K pull down resistor. Analog VDD_A Supply Output. This output pin is used to connect an external capacitor to stabilize and filter the on chip VDD_A LDO regulator. The input of the LDO is the switched V_BATT supply. LDO output is normally 2.95V and is used to drive all circuitry except the output buffers at AOUT and BOUT. Average internal load is 6mA. Up to 5mA DC additional load may be imposed by external circuitry. External load must be reduced if the combination of output current and input voltage exceeds power dissipation capability of the die. The external capacitor will be a 100 to 1000nF ceramic dielectric type. B buffer N-FET driver output. The pin includes a internal 10K pull down resistor. Voltage Input, 3 to 28V input range. V_BATT is switched (see ENABLE) to remove power from chip. Two LDO regulators follow the switch, one generates VDD_P (see VDD_P) and the other VDD_A (see VDD_A). Care must be taken in power distribution design to minimize transients and noise coupling from the VDD_P output to the VDD_A output. The external capacitor will be a 100 to 1000nF ceramic dielectric type. DESCRIPTION VDD_P AOUT VDD_A PACKAGE DATA PACKAGE DATA BOUT V_BATT Copyright © 2000 Rev. 1.1, 2006-02-27 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 2 LX1689 TM ® Third Generation CCFL Controller P RODUCTION D ATA S HEET FUNCTIONAL PIN DESCRIPTION (CONTINUED) PIN NAME DESCRIPTION Digital Dimming Clock / Dimming Polarity. An input pin that may be selected to control burst frequency for external Digital Dimming. This input can be any clock signal up to 200KHz. This pin is also used to control the dimming polarity when operating in the analog or internal digital mode. If DIM_MODE is in the open condition (Analog Dimming Mode) the DIM_CLK input should be connected to VDD_A for conventional dimming polarity or set to Ground for reverse polarity. Conventional polarity means that lamp brightness increases with increasing voltage on the BRITE_IN pin. Reverse polarity means that brightness decreases with increasing voltage. Over Current Sense Input. A full wave AC voltage input centered on ground that is proportional to total high voltage transformer secondary winding current. The OC_SNS input is full wave rectified, then applied to a digital comparator with a 2V reference to cause peak voltages greater than 2V to digitally reset the PWM logic on a pulse by pulse basis. Frequency range of the input signal is 10kHz to 500KHz. Normal operating voltage levels should be under max ±1.8VPK, and abnormal voltage can operate continuously as high as ± 10V peak under load fault conditions. Transients under fault conditions can reach ± 25VPK. Dimming Mode Input. This three state input pin places the IC in Analog Dimming Mode, internal Digital Dimming Mode, or external Digital Dimming Mode. If the input is left open or forced to VDD_A / 2 Analog mode is selected. If connected to VDD_A, Digital Dimming with a external clock source applied to the DIM_CLK input is selected to the burst timing generator. If connected to Ground, Digital Dimming with a internal clock is selected. The internal clock is equivalent to the frequency at AOUT divided by two, both the internal or external clock frequency can be divided down by setting the DIV_248 pin. (see DIV_248) Over Voltage Sense Input. A full wave AC voltage input centered around ground that is proportional to lamp voltage. The OV_SNS input will be full wave rectified, then applied to a digital comparator with a 2V reference to cause peak voltage greaten than 2V to digitally reset the PWM logic on a pulse by pulse basis. Frequency range of the input signal is 10Khz to 500KHz. Normal operating voltage levels should be under ±1.8VPK, and abnormal voltage can operate continuously as high as ±10V peak under load fault conditions. Transients under fault conditions can reach ± 25VPK. The input has a 10K pull down resistor that serves as a DC restorer to the external capacitor that divides down lamp voltage. Divide Digital Dimming clock by 2, 4, or 8. This three state input pin causes the internal or external digital dimming clock source to be divided by one of the three values, 2, 4, or 8. Its purpose is to allow a selection of three possible burst rates for any given external or internal clock source. A high (VDD_A) selects divide by 2, open selects divide by 4, and ground selects divided by 8. We advise keeping burst above 95Hz and below about 400HZ. This will minimize visible flicker and possible audible noise from the power supply components. Current Sense Input. A full wave AC voltage input centered around ground that is proportional to lamp current. The I_SNS input is full wave rectified and amplified, then presented to the inverting input of the current error amplifier through a 100K resistor. Frequency range of the input signal is 10KHz to 500KHz. Normal operating voltage levels will be in the range of ± 0.5 to 2.5VPK, and abnormal voltage can operate continuously as high as ± 10V peak under load fault conditions. Transient under fault conditions can reach ± 25VPK. We strongly recommend a 10K resistor be placed in series with the pin to limit current from voltage spikes that can occur by intermittent lamp connectors, or arcing from a faulty high voltage transformer. This resistor will eliminate the possibility of IC damage under these fault conditions. The open lamp fault logic monitors the I_SNS pin voltage and number of lamp current cycles. If the number of lamp current cycles with amplitude below fault threshold are less than 8 in a given fault checking period then the strike latch will not be reset and a fault is declared, which shuts down the A/B outputs. In the strike mode, if no lamp current is detected after 15 attempts a fault is likewise declared. ( See further LX1689 operation section) W WW . Microsemi . C OM DIM_CLK OC_SNS DIM_MODE OV_SNS DIV_248 PACKAGE DATA PACKAGE DATA I_SNS Copyright © 2000 Rev. 1.1, 2006-02-27 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 3 LX1689 TM ® Third Generation CCFL Controller P RODUCTION D ATA S HEET FUNCTIONAL PIN DESCRIPTION (CONTINUED) PIN NAME DESCRIPTION BRITE Filter Capacitor and FAULT Output. Used to convert higher frequency digital PWM inputs to proportional DC currents at the BRITE_OUT pin. The capacitor forms a low pass filter with an internal 200K resistor. This pin will be driven to VDD_A if a lamp fault is detected by the LX1689. If no fault is present the voltage at this pin will vary from 50mV to 1.05V as BRITE_IN varies from 0 to 2V. A CMOS gate may be connected to this pin to sense the fault condition. TTL gates or other low impedance (less than 20 megohm) must not be connected to this node as their DC resistance will load the internal 200K resistor and create error in the BRITE_OUT current level. Error Amp Inverting Input. Frequency Compensation input for the Error Amplifier. See EA_OUT below. A 100K, negative TC on chip resistor connected between the inverting input of the error amplifier and the output of the I_SNS full wave rectifier is the resistor in an R/C loop compensation network. Dedicated Bias resistor for BRITE_OUT current source. Error Amp Output. Error amplifier is a GM type and does not require a external capacitor for stability. An external capacitor is connected from this pin to EA_IN to adjust the loop response of the inverter module. This capacitor value can vary from 100pF to 5000pF in various applications. This capacitor may also be connected from the EA_OUT to ground. Brightness Control Input. The input signal can be a DC voltage, a low frequency pulse width modulated digital signal, or a high frequency pulse width modulated digital signal. Active DC voltage range is 0.5 to 2.0V. Signals above 2V are clipped and signals below 0.5V make output current from the BRITE_OUT pin near zero. Low frequency digital PWM signals up to 500Hz can be applied to affect Digital Dimming. Higher frequency PWM signals, up to 100KHz are filtered to an equivalent DC current at the BRITE_OUT pin by adding a capacitor at the BRITE_C pin. On chip signal conditioning amplifiers clip inputs above 2V so that lamp current amplitude is not sensitive to the voltage level variations of a digital PWM input signal. Brightness Reference Current Output. This variable current source is the mirror of BRITE_R current multiplied by the voltage at BRITE_C (0 to 1.0V) when analog dimming is selected, or by 1.0V when digital dimming is selected. It becomes the reference voltage to the lamp current error amplifier when applied to an external precision resistor connected from the BRITE_OUT pin to ground. BRITE_OUT current: W WW . Microsemi . C OM BRITE_C EA_IN BRITE_R EA_OUT BRITE_IN IBRITE_OUT = IBRITE_R × 1.0 (Digital Dimming Mode) BRITE_OUT IBRITE_OUT = IBRITE_R × VBRITE_C (Analog Dimming Mode) VBRITE_OUT = IBRITE_R × R BRITE_OUT IBRITE_R = 1.00V R BRITE_R ENABLE Chip Enable Input. If logic high, all functions are enabled. If logic low, internal power is disconnected from the V_BATT pin, disabling all functions. Logic threshold is about 1.2V. Maximum current into V_BATT when ENABLE < 0.3V, V_BATT 2.05V; TA = 25°C BRITE_IN > 2.05V BRITE_IN < 0.45V; TA = 25°C µA mV V V V V mV % % % % 52 1.04 1.04 1.06 1.06 62 10 92 100 1.12 1.14 1.14 1.16 120 15 100 Reverse Dimming BRITE_OUT DIGITAL DIMMER BLOCK Conventional Dimming Duty Cycle BRITE_ IN < 0.45V BRITE_IN > 2.05V Minimum Duty Cycle; BRITE_IN ≤ 0.55V Maximum Duty Cycle; BRITE_IN =1.90V Maximum Duty Cycle; BRITE_IN ≥ 1.95V Maximum Duty Cycle; BRITE_IN ≤ 0.55V Maximum Duty Cycle; BRITE_IN = 0.6V Minimum Duty Cycle; BRITE_IN ≥ 1.95V Reverse Dimming Duty Cycle TIMING GENERATOR BLOCK Number of Lamp Return Current Cycles before Run Mode I_SNS Run Mode Checking Interval 92 10 100 15 % % NIGNITE To switch to Run Mode Lamp return current cycles, 8192 x 1 /fO I_ SNS Open Lamp Fault Detect, TA =25°C FLAMP Sweep Cycles, I_SNS = 0V_SNS = 0V 16384 X Lamp Run Period 250 8 126 305 15 252 1024 16 350 Cycles mS mVPK Fault Comparator Threshold Voltage Number of Strike sweep Attempts NSTRK_FAULT Before Fault Shutdown Power On Delay Before Strike TD_PWRON Number of Sweeping Strike Frequency Steps per Attempt Number of Output Pulses per Striking Step LAMP FEEDBACK CONDITIONING BLOCK I_SNS Input Current OV_SNS Input High Threshold OV_SNS Input Low Threshold OV_SNS Input Current OC_SNS Input High Threshold OC_SNS Input Low Threshold OC_SNS Input Current I_SNSIIN VTH_OV_SNS VTL_OV_SNS OV_SNSIIN VTH_OC_SNS VTL_OC_SNS OC_SNSIIN ms Steps Cycles I_SNS =10V I_SNS = -10V Active Over Voltage Protection Inactive Over Voltage Protection OV_SNS = 10V OV_SNS = -10V Active Over Current Protection Inactive Over Voltage Protection OC_SNS = 10V OC_SNS = -10V I_SNS = 0.3VDC, TA = 25°C 0.27 1.95 0.24 1.75 I_SNS = 2.0VDC, TA = 25°C I_SNS = -0.3VDC, TA = 25°C I_SNS = -2.0VDC, TA = 25°C ± 1.8 ± 1.8 80 -200 ±2 ±2 260 -320 ±2 ±2 45 -110 0.31 2 0.3 1.9 150 -350 ± 2.2 400 -450 ± 2.2 80 -180 0.35 2.05 0.36 2.05 µA µA VPK VPK µA E ELECTRICALS µA VPK VPK µA µA V V V V Full Wave Rectifiers RMS Transfer I_SNSRMS Copyright © 2000 Rev. 1.1, 2006-02-27 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 7 LX1689 TM ® Third Generation CCFL Controller P RODUCTION D ATA S HEET BLOCK DIAGRAM W WW . Microsemi . C OM V _BATT ENABLE & BIAS GENERATOR BLOCK PW M CONTROL BLOCK RAMP_D OUTPUT DRIVERS BLOCK AO UT O UTPUT STEERING LOGIC ENABLE SLEEP SHUTDOW N VDD_A DUAL LDO 10K FAULT 5.3V BOUT + RAMP_C VDD_P UVLO BIAS 2.0V REF BRITE_OUT 10K 2.95V EA_OUT + - PW R_GD DIM CLOCK IGNITE ERROR AMP I_R DIGITAL DIM 0.5V 50K EA_IN BRITE_IN - F EXT 2.0V + 50K 100K 75K 100K + - DDIM LAMP FEEDBACK CONDITIONING BLOCK 0.5V VDD_A + 2.0V + I_SNS LSNS RECTIFIER OC_SNS OC_SNS RECTIFIER OV_SNS OV_SNS RECTIFIER BRITE_C FAULT 0.5V + ANADIM 100K 200K BRITE_O UT VDD_A + BRITE_R I1 - 1V + RESET + 300m V GND 200K I1 DIM _CLK + 6BIT VDAC 6 BIT COUNTER RUN MODE FAULT DET STRIKE MO DE FAULT DET DIM _ M ODE 3 STATE DECODER DIV_248 3 STATE DECODER EXT ANLG INT MUX & DIV N R STRIKE DETECTION BLOCK FAULT IGNITE BLOCK DIAGRAM BLOCK DIAGRAM Q Q D QS R RS RMP_D OUT 20 BIT COUNTER & POW ER ON RESET LOGIC 10 BIT REGISTER 10 BIT IDAC DIGITAL DIM ANALOG DIM RAMP GENERATO R RAMP_C TIMMING GENERATOR BLOCK DIMMING CONTROL BLOCK FIGURE 1 – Simplified Block Diagram Copyright © 2000 Rev. 1.1, 2006-02-27 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 8 LX1689 TM ® Third Generation CCFL Controller P RODUCTION D ATA S HEET TYPICAL APPLICATION 3.0V < VBATT < 5V VBATT GND BRITE ENABLE W WW . Microsemi . C OM C1 100nF 16V Nominal 3.2V to 4.2V U2 FDC6305N 6 FAIRCHILD T1 SGE2697-1 MICROSEMI 1 2 6 Lamp C8 100nF 50V Lamp 1 4,5 3 275VRMS ± IOUT = 3.5m 100kHz 1:53 BRITE Input Control Range (Linear DC) Min. Brite 'LO' = 2.00V (2.5V to 3.3V Logic PWM) Min. Brite Pos Duty = 92% PWM freq 7.5Khz to 100Khz Burst Rate Freq: 195Hz ± 4% LMT1410 C9* 2pF C4 100nF 16V C3 100nF 16V VDD_A 3 4 + C6 100µF 10V 20% TANT R5 10 2,5 GND AOUT VDD_A VDD_P VDD_A VBATT OC_SNS OV_SNS I_SNS BRITE_OUT EA_OUT EA_IN I_R BOUT DIM_CLK DIM_MODE DIV_248 C2 BRITE_C 100nF 16V BRITE_R R1 6.65K 1% C11 1.0uF 10V 10% Alternate Maximum Lamp Current Table Lamp current | R1 value | 4.0mArms 3.5mArms 3.0mArms 2.5mArms 2.0mArms 1.5mArms | 6.65K 1% | 6.65K 1% | 6.65K 1% | 11.8K 1% | 11.8K 1% | 11.8K 1% R7 Value | 221 1% | 255 1% | 294 1% | 200 1% | 249 1% | 332 1% N.C. R4 10K C5 470pF 16V C7 1nF 16V R3 4.99K 1% R6 120 C10 1.5nF 25V 5% COG R7 255Ω 1% BRITE_IN ENABLE Enable input Logic Level: 2.5V to 3.3V ON: Logic 'HI' = >1.5V OFF: Logic 'LOW' =< 0.8V LX1689CPW R2 51.1K 1% *C9 PCB CAPACITOR COPPER AREAS TO EQUAL APPROXIMATELY 342MM FOR 0.80MM THICK PCB PCB CAP AREA FORMULA (K TYPICIALLY = 5.35) AREA(MM²) = D(mm) x C x 113097 E+9 / K FIGURE 2 – LX1689 Typical 1W Application DIMMING TABLE DIM_MODE DIM_CLK VDD_A External Clock Source DIMMING MODE External Burst Dimming from divided DIM_CLK input DIMMING POLARITY* Conventional Floating or VDD_A/2 VDD_A Analog Dimming Conventional APPLICATIONS APPLICATIONS Floating or VDD_A/2 GND Analog Dimming Internal Burst Dimming from divided Run Frequency Internal Burst Dimming from Divided Run Frequency Reverse GND GND VDD_A GND Conventional Reverse * Conventional polarity means that the lamp brightness increases with increasing voltage on the BRITE_IN pin. Reverse polarity means that brightness decreases with increasing voltage. Copyright © 2000 Rev. 1.1, 2006-02-27 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 9 TM VDD_A V_BATT U2 Si9945AEY VISHAY x I_SNS x C7 100nF 16V DIV_248 BRITE_C BRITE_OUT R5 10K R4 12.7K 1% I_SNS I_SNS R26 2.2K R7 680Ω C9 1.0nF 25V W WW . Microsemi . C OM A APPLICATION Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 CN2 R13 150Ω 7 R2 10K 1% BRITE_R BRITE_IN ENABLE LX1689CPW EA_OUT EA_IN I_R R3 64.9K 1% C8 4.7nF 16V R8 1.0K x Third Generation CCFL Controller P RODUCTION D ATA S HEET R6 4.99K 1% VDD_P U4A LMV393MM - I_LMP - Copyright © 2000 Rev. 1.1, 2006-02-27 1 8 VIN power input functional:12V ±15% Nominal: 12V ±10% T1 SGE2682-1 MICROSEMI 1 2 C2 22µF 20% 25V TANT SLEEP input (2.5V t 3.3V Logic Level) ON: Logic "HI" > 1.5V OFF: Logic "LO" < 0.8V AOUT R9 39Ω Alternate Maximum Lamp Current Table: 3 2 7 Lamp LO Lamp HI 3 6 5 4 5 6 BRITE Control Range (Linear DC) Min. Bright: "LO" < 0.50V Max. Bright: "HI" > 2.0V (2.5V to 3.3V PWM Logic) Min. Bright Positive Duty Cycle: 0% Max. Bright Positive Duty Cycle: 100% PWM Freq: 7.5kHz to 100kHz BOUT R10 39Ω LMT2110 1:32 D1 BAV70WT1 C12 2.7nF 5% 25V COG C10 100nF 20% 50V R15 47K 4 C11 2.0pF (PCB Cap) Burst Rate Freq: 156Hz ±4% F1 2A 24V U2 Si9945AEY VISHAY OC_SNS V_BATT VDD_P OV_SNS BOUT R12 39Ω D2 BAW56WT1 VDD_P R1 10 Ω C1 100nF 20% 25V VIN VIN GND GND BRITE SLEEP OV_SNS Q2 MBT3904DW1T1 ® C11 & C14 PCB Cap. copper areas to equal approximately 442mm for 1.0mm thick PCB D3 BAW56WT1 AOUT R11 39Ω C4 1.0µF 20% 16V R14 150Ω VDD_P VDD_A C3 22µF 20% 25V TANT 1 8 1 2 7 2 7 R19 274Ω 1% VDD_P I_LMP D5 BAV70WT1 C5 470nF 20% 10V R18 270K T2 SGE2682-1 MICROSEMI R17 47K VDD_P C6 470nF 20% 10V APPLICATION FIGURE 3 – Typical Dual 4 Watt Application R20 274Ω 1% Microsemi C15 2.7nF 5% 25V COG D4 BAW56WT1 GND 3 6 3 VDD_P VDD_A 4 5 5 4 6 Lamp LO Lamp HI C14 2.0pF (PCB cap) CN3 AOUT BOUT V_BATT OC_SNS OV_SNS LMT2110 1:32 C13 100nF 20% 50V CN2 & CN3 Operational RMS lamp condition @ 6.5mA, 80kHz: 535V ± 15% U4B LMV393MM R24 4.7K DIM_CLK DIM_MODE OV_SNS + OC_SNS VDD_A R25 10K C17 100nF 16V R23 1.0M x R21 1.0M C16 100nF 16V + R22 4.7K LX1689 Page 10 LX1689 TM ® Third Generation CCFL Controller P RODUCTION D ATA S HEET DESCRIPTION FEATURE REVIEW Lamp Current Compensation On-Chip LDO Regulators Two LDO regulators extend the input voltage range of the IC up The BRITE_OUT pin outputs a precision current that is to 28 Volts without using external circuitry as was required with proportional to the BRITE_IN signal. This current can be applied to our previous controllers. a precision resistor to develop the brightness control voltage at the error amplifiers non-inverting input. Since the output is constant Under Voltage Lockout If the battery input voltage is too low for the controller to current, designers can easily compensate lamp current with respect function properly, it will turn itself off, preventing spurious to temperature, input voltage, ambient or lamp light output, and operation. If the battery voltage falls to less than 1V where UVLO combinations of these conditions by using various temperature or is no longer guaranteed, 10K pull down resistors on the AOUT and light sensitive components in combination with resistors. This capability is very useful in automotive and outdoor applications BOUT pins insure the external power FETs cannot be biased on. where operating temperatures and ambient light vary over wide Power On Delay ranges. See functional pin description for details. A power up reset delays AOUT and BOUT turn on for Strike Voltage Generation approximately 16384 x 1/fO milliseconds after power is applied. Improved strike voltage generation circuits ramp strike voltage to This gives extra time for the BRITE_IN source voltage to stabilize so the lamp is not inadvertently powered up at high brightness and 5X fO and repeats it’s cycle unless excessive high voltage is sensed at OV_SNS. If OV_SNS is detected during strike, strike voltage then suddenly lowered, creating an undesirable light flash. will not ramp and will hold the current voltage until total strikes Enhanced BRITE Conditioning Circuitry lamp cycles numbers reach 245,760. Strike potential is removed The BRITE_IN input is now enhanced to accept either DC immediately when the lamp strikes or if the time limit is reached. voltage or logic PWM signals. When PWM signals are input, their Strike Detection levels are clipped at 2V and 0.5V so lamp current will not be The LX1689 includes a new lamp strike detection scheme that affected by variations in logic signal level. In addition, the saves a package pin and three external components. Internal circuits BRITE_C pin permits filtering DC inputs and converting high frequency PWM inputs to DC voltages with the addition of only a monitor lamp current pulses at the I_SNS input to determine if the single external capacitor. A low frequency (less than 500Hz) lamp strikes and if it stays ignited once operational. PWM signal can be used to directly modulate the duty cycle of the Fault Time Out lamp current. In this case the capacitor at BRITE_C is not If the lamp fails to ignite with in approximately 1.6 seconds installed. (depending on Run Frequency) at maximum strike potential, or if it extinguishes while enabled, or the external clock frequency at the Digital or Analog Dimming Modes A DIM_MODE input pin selects either Analog or Digital mode. DIM_CLK pin terminates, the output drive is shut down and the In Analog mode DC voltage at BRITE_IN controls lamp current BRITE_C pin is driven high. This pin can be monitored with a amplitude. In Digital mode it controls digital dimming duty cycle CMOS gate to obtain a logical indication that a lamp fault has with amplitude fixed at a value set by the external current scaling occurred. It is especially useful in multiple lamp applications or for resistor (BRITE_R). When in Digital mode, the dimming burst system diagnostic input. frequency can be synchronous to lamp current by selecting internal The voltage on pin BRITE_C will vary directly with BRITE clocking, or to an external clock that may be a multiple of the input voltage, but does not exceed 1.2V unless a fault condition video vertical frame rate. With an external clock source, three burst occurs. rate selections are available by programming the DIV_248 input to On Chip Rectifier divide the source clock by 2,4, or 8. This clock source is further Integrating full wave rectifiers for each of three lamp inputs has divided by 64 generating the internal burst ramp waveform. Using significantly reduced lamp feedback component count. Current the internal clock as source the DIV_248 input changes to divide Sense (I_SNS), Over Current Sense (OC_SNS) and Over Voltage by 4, 8, or 16. This feature allows the designer to set a burst Sense (OV_SNS) signals are now detected using only one external frequency in the range of 100 to 500Hz. The external clock source scaling resistor or capacitor each. Rectification accuracy is must not be interrupted unless the BRITE_IN is set > 2V or the improved with high performance on chip rectifiers to provide better lamp will extinguish. lamp current and voltage regulation. Brightness Polarity Control Complete Fault Protection In Analog dimming mode or internal Digital Dimming, the IC In addition to the faulty lamp time out, lamp open, lamp shorted, can be programmed to either increase or decrease lamp current and either lamp terminal shorted to ground are detected. Open amplitude as a function of increasing signal at the BRITE_IN pin circuit voltage can never go higher than the preset maximum strike by simply connecting the DIM_CLK input to ground or VDD_A potential and total current from the circuit is safely limited with a or open(see Dimming Table). If External Digital dimming mode is scaling resistor. UL safety specifications can now be easily met in used, lamp current amplitude is constant and its duty cycle is any application. always directly proportional to DC input voltage and / or PWM duty cycle at the BRITE_IN pin. Copyright © 2000 Rev. 1.1, 2006-02-27 W WW . Microsemi . C OM DESCRIPTION DESCRIPTION Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 11 LX1689 TM ® Third Generation CCFL Controller P RODUCTION D ATA S HEET DESCRIPTION (CONTINUED) LX1689 OPERATION Four operating modes: Power On Delay, Strike, Run, and Fault modes are employed by the LX1689. Upon power up or ENABLE going true, Power On Delay is automatically invoked. Immediately after termination of Power On Delay, or ENABLE going true, strike mode is entered. After a successful strike, e.g. lamp is ignited, run mode is entered. If ignition is unsuccessful, or if the lamp extinguishes while running, Fault mode is entered. Lamp ignition is determined by monitoring the lamp current feedback voltage at pin I_SNS. Lamp current cycles are counted from the beginning of Strike mode. If 8 or more complete cycles occur the lamp is declared ignited. If less than 8, the lamp is considered not ignited and Strike mode continues until ignition is detected or strike time out is reached. After run mode is entered lamp current cycles are sampled every 8192 x 1/fO to determine that the lamp has not inadvertently extinguished. If at least 8 lamp current pulses are counted in each sample, Run mode is maintained. Otherwise, Fault mode is entered. Strike mode can be entered only once for each on/off cycle of either V_BATT or ENABLE. This insures that even intermittent lamp failures cannot cause the module to continuously output maximum strike voltage. Power ON Delay Mode All functions are activated except that AOUT and BOUT are inhibited. Delay is 16384 x 1/fO determined by counting Ramp clocks. The first of 16 sweeps is decoded as the power on delay period. The subsequent 15 sweeps are used for controlling the Ramp generator during Strike Mode. Power on delay is activated at every V_BATT power up sequence and ENABLE sequence. Strike Mode Entered from Power On Delay, or upon an ENABLE sequence. Control of the Ramp Generator frequency is switched to a DAC output. Frequency is increased in a saw tooth fashion from normal run value to as high as five times that value, for up to 15 sweeps. If while strike frequency is ramping up, the over voltage set point at OV_SNS is detected, strike frequency will freeze at that value until either the lamp strikes or the timeout is reached. Strike Mode is terminated by reaching 15 sweep counts or by detecting lamp ignition. If strike is successful, Run Mode is entered. If unsuccessful, Fault mode is entered, a fault is declared and the A & B outputs are shut off. The purpose of sweeping lamp frequency up during strike is to operate at the unloaded resonant frequency of the transformer and lamp load. This generates the high lamp striking voltage required, since at resonance, output voltage from the transformer will increase to any value needed to cause ignition. A capacitive voltage divider provides output voltage feedback to the OV_SNS pin, which freezes Strike Frequency to limit maximum output voltage to a safe value. Since strike frequency is held constant once the LX1689 senses maximum safe output voltage, maximum strike potential is continuously impressed across the lamp for the entire strike period. Because strike frequency is ramped up rather than simply stepped, the entire range of possible self-resonant frequencies is covered. Transformer manufacturing is simplified and parasitic panel capacitance values are no longer critical. The 5:1 strike frequency range easily covers the self-resonant frequency of all practical lamp assembly and transformer combinations. The only way to re-initiate the strike process is to either cycle V_BATT or ENABLE off and on. If ignition is successful, ramp frequency immediately returns to its normal run value. Run Mode Entered only by detection of a successful Strike. Ramp generator frequency control is immediately switched from DAC output to a fixed reference that sets the normal run frequency. During Run mode, the Fault Detect Counter is reset approximately every 8192 x 1/fO. The lamp current cycle counter is monitored to insure at least 8 current cycles received during each period. If less than 8, the lamp is considered extinguished and the Fault Mode is entered. Fault Mode Fault Mode may be entered from either Strike or Run Mode as described above. In Fault Mode, the A & B output drivers are forced low and the BRITE_C pin is driven to VDD_A to indicate the fault condition. Fault mode may be cleared by cycling ENABLE off then on, or by removing and applying V_BATT. External load on the BRITE_C pin is limited to a filter capacitor and single CMOS gate input. DESIGN PROCEDURE Selecting the I_R resistor value This resistor determines the frequency of the on chip oscillator. The output of the oscillator, RAMP_C, controls all timing functions. It must be chosen first, and will be in the range of 10K to 150K ohms. The output frequency approximated by the following formula : RI_R = 5.24E9 / FLAMPOUT(Hz) RAMP_C frequency is twice lamp output current frequency. Driving the BRITE_IN Input BRITE_IN can be a DC voltage, a low frequency PWM signal that produces direct digital dimming, or a higher frequency PWM signal that is converted to a proportional DC level by adding a filter capacitor at the BRITE_C pin. 100% duty cycle corresponds to 1.1 volt, and 0% duty cycle corresponds to zero volts at the BRITE_C pin. Maximum BRITE_IN input frequency for PWM inputs is 100 KHz, but when converting frequencies above 25 KHz to DC, some accuracy is lost. The BRITE_IN input circuitry includes on-chip active voltage clamps that ignore input voltage greater than 2.0V and less than 0.5V. This allows the use of digital PWM input signals where brightness is dependent only on duty cycle, with no contribution W WW . Microsemi . C OM D DESCRIPTION Copyright © 2000 Rev. 1.1, 2006-02-27 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 12 LX1689 TM ® Third Generation CCFL Controller P RODUCTION D ATA S HEET DESCRIPTION (CONTINUED) W WW . Microsemi . C OM due to varying input signal amplitude. Input impedance is very high so BRITE_IN can also be driven from a 100K potentiometer with no offset error. BRITE_R and BRITE_OUT Resistor values. The BRITE_OUT pin is the output from the BRITE_IN signal processor. It is a linear current source that varies from 0 to the current value established at pin BRITE_R multiplied by the DC voltage at pin BRITE_C. The optimum value for BRITE_R is usually 10K ohms. The BRITE_OUT voltage range can be scaled from 300mV to 2.0V. However, it is recommended that the scaling of BRITE_OUT (including Analog mode BRITE_IN range) be within 400mV to 1.2V. Maximum voltage correlates to full brightness settings. It is the ratio of the two resistors multiplied by the voltage at BRITE_C: V BRITE_OUT = V BRITE_C (RBRITE_OUT / RBRITE_R_) In some applications, a precision 10K resistor is connected from BRITE_OUT and BRITE_R to ground to develop 1.0V to represent maximum lamp brightness. In Analog mode the BRITE_OUT voltage potential is proportional to BRITE_IN. The minimum brightness setting at BRITE_IN corresponds to the minimum voltage at BRITE_OUT. In digital mode, BRITE_IN has no effect on BRITE_OUT. Because the BRITE_OUT output is a linear current source, you can place other components, such as a thermistor or photo resistor, at this pin to generate complex functions for controlling brightness. For example; use a PWM input at the BRITE_IN pin to control dimming, and boost analog lamp current amplitude at cold lamp temperature with a thermistor at the BRITE_OUT pin. This will help warm the lamp faster at start up so final brightness is reached sooner. SETTING THE OUTPUT CURRENT. Referring to the application examples figures 2 and 3. The current setting resistor(s) are R7, and R19 and R20 respectively. The value these resistor(s) are in the range of 200 to 400ohms. The following formula can be used to determine the current setting resistor value. Use 1180 for Digital mode and 1260 for analog dim. RSNS = 1180 or 1260 x RBRITE_OUT / IOUT(mARMS) x RBRITE_R In the 1W burst dimming application example shown in figure 2 the output current is set for nominally 3.5mA. RSNS is calculated using the formula above as follows: RSNS = 1180 x 4990 / 3.5 x 6550 = 256.8 ohms A standard value of 255 ohms was chosen. It is recommended to keep the value of the sense resistor in the range of 200 to 400 ohms as stated above. If calculated value exceeds 400 ohms its best to increase the value of the RBRITE_R resistor. MECHANICAL DRAWING PW 20-Pin Thin Small Shrink Outline (TSSOP) Dim 321 E1 E e D A2 A SEATING PLANE 1 L c b A1 A A1 A2 b c D E E1 e L Θ1 *LC MILLIMETERS MIN MAX 1.10 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 6.40 6.60 6.25 6.55 4.30 4.50 0.65 BSC 0.45 0.75 0° 8° 0.10 INCHES MIN MAX 0.043 0.002 0.006 0.031 0.041 0.007 0.012 0.004 0.008 0.252 0.260 0.246 0.258 0.169 0.177 0.026 BSC 0.018 0.030 0° 8° 0.004 MECHANICALS MECHANICALS * Lead Coplanarity Note: 1. Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm(.006”) on any side. Lead dimension shall not include solder coverage. Copyright © 2000 Rev. 1.1, 2006-02-27 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 13 LX1689 TM ® Third Generation CCFL Controller P RODUCTION D ATA S HEET NOTES W WW . Microsemi . C OM NOTES PRODUCTION DATA – Information contained in this document is proprietary to Microsemi and is current as of publication date. This document may not be modified in any way without the express written consent of Microsemi. Product processing does not necessarily include testing of all parameters. Microsemi reserves the right to change the configuration and performance of the product and to discontinue product at any time. Copyright © 2000 Rev. 1.1, 2006-02-27 Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 14