LX7309ILQ

LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet Description The LX7309 is a versatile current-mode DC-DC controller for isolated/non-isolated topologies. It features a low-resistance current-sensing scheme for max 200mV drop, using a differential current-sense amplifier for Kelvin connectivity and low noise pickup. The LX7309 provides an out-of-phase drive signal for driving a synchronous rectifier or an active clamp. Duty cycle is limited to 50%, which is helpful in implementing a high-power Forward converter topology. It also helps avoid subharmonic instability without requiring slope compensation. The IC has differential voltage sensing for implementing topologies with power-ground separated from IC ground. The switching frequency can be set from 100500 kHz, externally synchronizable up to 1MHz. It has a programmable UVLO threshold, Power Fail Warning (PFW), and a programmable Low Power (pulse-skip) Mode for better light-load efficiency. Copyright © 2013 Rev. 3.2, November 2013 Features ♦ Current-mode control for fast line and load correction responses ♦ 50% duty cycle limit for simple Forward converters and for avoiding subharmonic instability in Flyback, Boost and Buck-Boost ♦ 200mV peak current sense signal with differential Kelvin sensing for noise immunity and higher efficiency ♦ Two out-of-phase driver stages for synchronous rectification or active clamp ♦ ROHS-compliant, 24-pin, 4x4 mm QFN Applications ♦ Isolated and Non-isolated topologies ♦ Buck, Boost, Buck-boost, Forward, Flyback ♦ PoE PD applications Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 1 Figure 1: 12V/4A Output Isolated fly-back with Secondary Synchronous Rectification 1 R16 8.66K 294K R12 VIN+ EXTERNAL SY NC ENABLE R19 100K VDD VIN- + EP 6 5 4 3 2 1 348K R15 C12 100n C1 47uF 100V 1 EP HY ST NC VINS EN VCC VH 2 + 1 C14 22uF 100V CSP 42V TO 57V INPUT 10uH U1 LX7309 R17 100K VDD 1 R13 49.9K 1 100n 16V CSN C32 1nF CSP 1 VDD 1 1 15 13 C4 2.2uF 100V X7R C13 100n 1.0uF 10V C16 VDD C3 2.2uF 100V X7R 16 17 18 14 C18 VSP COMP DAO FB GND VDD SG C2 2.2uF 100V X7R VR1 100 R40 R7 13K 0.25W 100 R41 CSPFLT C11 22uF 25V + C5 100n 100V 1 2 L1 24 7 4 1 1 D3 SS16 D2 R37 5.6K 1W CSNFLT CSNFLT SG Q2 FDMS86200 6.8 R9 R38 5.6K 1W CSPFLT 1SMA5929BT3 1 HYST NC SYNC 23 8 RFRQ 9 PG 22 CSP CSN 10 VINS_SEL 21 CSN SS 19 SG 20 PGND RCLP 11 VSN 12 2 ES1C 2 C6 18nF 100V 1 24 R39 R4 0.05 1/2W 2 3 8 7 6 5 VIN+ C15 1 R23 1.2K 8 5 4 5 T3 6 7 10 9 REF* Q1 2 1 R3 750 FDS86322 D1 S1 D2 S2 D3 S3 D4 GATE 4 1 CNY 17F3SM U2 8 7 6 5 R43 GDRIVE REF* 0.68uF 16V X7R C20 1 2 3 4 C34 SECONDARY FA2659-AL 1n 2000V PRIMARY 1u 16V X7R C19 C35 REF* VDD R42 REF* 2 3 1 5 T2 T2: Primary Inductance = 35uH Turns Ns/Np = 0.444 Turns Naux /Ns = 1.0 1 2 Copyright © 2013 Rev. 3.2, November 2013 R14 1K D5 TL431A 1 4 C17 R6 1.6K C8 270uF + 100n C9 1u 25V X7R 2 LL4148 D8 R10 4.99K R8 19.1K 1 1 1uH L2 *determined at design v erification on final PCB lay out D7 LL4148 2 C7 270uF + 3 5 VIN+ C10 10uF Q3 MMBT2907A GDRIVE 2 4 3 2 1 12V @ 4.0 AMPS MAX CI5104P1V00 4 3 2 1 J1 L2 AND C10 ARE OPTIONAL LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Microsemi Page 1 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet VPP C11 + 100u 100V 12V (+) D4 B370-13-F C13 22uF 16V C12 22uF 16V 2 C10 100n 100V 1 37V to 57V C14 100n 25V 12V (-) R21 130K L1 Q2 NOTE: 12V (-) IS FLOATING WITH RESPECT TO SYSTEM GROUND. DO NOT CONNECT TO SYSTEM GROUND! 47uH 47uH MMBTA06LT1 D6 VCC 1 C18 4.7uF 25V D7 EDZTE6111B 2 B170-13-F SMA TP2 1 5 6 7 8 CSP CSN R2 Q1 FDS3512 PD-SO8 19 4.7 SG CSN PGND COMP NC VL 17 16 FB 15 DAO 14 COMP 13 VSP C19 1uF CSP GND_C C20 1nF R7 0.09 1/4W R8 100 VSN COMP GND_C R15 750K R14 634K R5 100 CSN VSN RCLP R3 10K 18 12 7 EP VSP SS HY ST 11 EP VPP DAO 10 6 FB VINS RFRQ 5 GND U1 LX7309 EN 9 4 VINS + VCC VINS_SEL 3 SYNC 2 VCC C25 0.1uF 25V VDD VH 8 1 CSP NC C15 100nF PG 1 2 3 21 20 23 22 24 4 R9 100K 30K 22nF R16 C23 TP1 1 FB R11 75.0K R12 75.0K R17 1.07K R18 1.07K VINS VSP 20K R19 R10 51.1K ENABLE R20 20.0K R13 33.2K VSN DAO C24 68pF C21 220nF CONNECT PGND TO GND_C WITH SINGLE POINT CONNECTION AT C19 GND_C GND_C GND_C GND_C Figure 2: 12V/22W Non-Isolated Buck Copyright © 2013 Rev. 3.2, November 2013 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 2 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet Pin Configuration 19 VDD GND 3 EPAD FB VINS 4 (connect on PCB to GND DAO NC 5 COMP HYST 6 VSP 9 10 11 12 RCLP VSN 8 SS 7 RFREQ 2 ENABLE VINS_SEL VCC SYNC VH 1 18 SG 20 17 PGND 21 16 CSN 22 15 CSP 23 14 PG 24 13 NC LX7309 TOP VIEW (4x4 QFN – 24) Figure 3: Pinout Ordering Information Ambient Temperature Type -40°C to 85°C RoHS compliant, Pb-free Copyright © 2013 Rev. 3.2, November 2013 Package Part Number Package Type QFN-24 (4mm × 4 mm, 0.5mm pitch) LX7309ILQ Bulk LX7309ILQ-TR Tape and Reel Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 3 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet Pin Description (LX7309) Pin Number Designator Description 1 VH 2 VCC 3 ENABLE Internal rail of -5V with respect to VCC, brought out for decoupling purposes. Connect a 0.1µF ceramic cap very close from this pin to VCC pin. Supply pin of the IC. Provide up to 10mA startup bias current to start PWM switching after UVLO (9.5V max) is reached. Standby current may be lowered using one of the methods outlined on page 25. Logic-level input to enable/disable the converter. Connect to Pin 17 GND to disable switching in the LX7309. May be pulled high with a 100k resistor connected to VDD. Input for Power Fail Warning (PFW) or VPP UVLO, depending on state of VINS_SEL pin. The following table describes VINS pin function: VINS Pin Function VINS VINS_SEL 4 VINS 5 NC 6 HYST 7 SYNC Copyright © 2013 Rev. 3.2, November 2013 VIN_SEL = VDD VINS < 1.2V VIN_SEL = VDD VINS ≥ 1.2V VIN_SEL = Pin 17 Ground VINS < 1.2V VIN_SEL = Pin 17 Ground VINS ≥ 1.2V Function VPP UVLO Mode. LX7309 switching is disabled; standby current will be drawn by VCC Pin. VPP UVLO Mode. LX7309 switching is enabled; full operation current will be drawn by VCC pin. Power Fail Warning (PFW) Mode. HYST pin is low, indicating VPP power failure. LX7309 switching is enabled. Power Fail Warning (PFW) Mode. HYST pin is high, indicating VPP power OK. LX7309 switching is enabled. No connection internally. Output of the UVLO comparator as shown in Fig. 6 (Block Diagram). In VPP UVLO Mode, a resistor between this pin and VINS programs the rising and falling thresholds of the UVLO. The state of this pin is monitored for Power Fail Warning. Used to synchronize the LX7309 to a frequency higher than its default value as set on RFREQ pin. The synchronizing clock must be 2x the desired sync frequency, with a maximum synchronizing clock frequency of 1MHz (for 500kHz PWM frequency). The PG pin’s rising edge will occur at the same instant as the rising edge of the clock being applied on the SYNC pin. Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 4 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet 8 VINS_SEL 9 RFREQ Logic-level pin to select VPP UVLO Mode or Power Fail Warning Mode. See the function description for Pin 4 VINS for further details. Connect a programming resistor from this pin to Pin 17 GND to set the switching frequency. A typical value of the programming resistor is 50k (49.9k), and this value will provide a frequency between 200 to 250 kHz. Halving it will roughly double the frequency, whereas doubling it will halve the frequency. Note that the LX7309 is designed to operate from 100kHz to 500 kHz. The switching frequency is approximated by: 7 Freq(kHz) ≈ 10 /RFREQ 10 SS Soft Start Pin. A capacitor between this pin and Pin 17 GND controls the rate of soft start during power-up, and provides the recovery period during over-current hiccup mode. Do not leave this pin float even if the soft start function is provided by alternate circuitry. It is advised to place a 0.1uF cap to ground on this pin; however the actual capacitor used will be determined by the application. The soft start period can be approximated by: Tss ≈ Css X RFREQ 11 RCLP 12 VSN 13 VSP 14 COMP 15 DAO 16 FB 17 GND 18 VDD 19 SG Copyright © 2013 Rev. 3.2, November 2013 Hiccup Mode recovery period time will be 10 X the soft start period. Low power clamp resistor. Connect a resistor from this pin to Pin 17 GND to set the level at which pulse-skipping mode is entered at light loads. Connecting this pin directly to Pin 17 GND, will limit the pulse skip to comp pin voltages of 200mV or less; this effectively disables the pulse skip for most applications. The method to select the threshold (and RCLP resistor value) is described in the Applications Information section of this datasheet. Negative input of the internal differential-sense voltage amplifier. Used for differential sensing of the output voltage in non-isolated applications where output ground is separated from IC ground. Positive input of the internal differential-sense voltage amplifier. Used for differential sensing of the output voltage in non-isolated applications where output ground is separated from IC ground. Output of the internal error amplifier, and the input of the PWM comparator. May be bypassed by an external source, such as an optoisolator output with a pullup resistor to VDD. Output of the internal differential voltage amplifier with a fixed gain of 7. For typical use connect DAO to the feedback pin (FB) as shown in Fig. 2. Error Amplifier feedback input. Voltages at this pin are compared to a 1.2V reference internally. If the internal error amplifier is not used and the COMP pin is being driven directly, the FB pin can be either tied high (to VDD), or connected to COMP. LX7309 signal ground. Connect GND and PGND together on a copper island on the component side, and then connect that through several vias very close to the chip on to a large ground plane which extends up to the ground side of the current sense resistor. Internal 5V supply output. At least a 1µF ceramic cap placed close to this pin, connected to IC ground is recommended for proper decoupling. This pin can also provide up to 5mA for external circuitry if required. Secondary Gate driver. Used to drive a synchronous FET or an active clamp FET. Maximum output voltage is VCC. On resistance is 10Ω for both high and low state. SG is the compliment of PG with a typical 110ns blanking time on both edges, to prevent crossconduction. SG is held low in pulse-skip mode, and is also low during soft-start. SG pin does Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 5 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet 20 PGND 21 CSN 22 CSP 23 PG 24 25 NC EPAD not support diode-emulation mode (discontinuous conduction mode). Leave floating if unused. Power ground (for internal SG and PG drivers). This is best for VCC decoupling, and the Primary-side current sense resistor’s lower terminal. The negative input of the internal current-sense voltage amplifier. May be tied directly to PGND; however, to avoid noise from ground bounce, it is best to route this on the PCB in Kelvin manner to the ground side of the sense resistor to avoid noise related to layout. The positive input of the internal current-sense voltage amplifier. The internal gain of the current sense amplifier is fixed at 5. 240mV between CSP and CSN will cause the PWM output to truncate pulses for current limiting. 360mV between CSP and CSN will trigger hiccup mode. Primary FET Gate driver. Maximum output voltage is VCC. On resistance isΩ 10 for high state and 5Ω for low state. Not connected. Connect on PCB to GND (Pin 17) Typical Performance Curves (Supply Pin Current versus Pin Voltage, Frequency and Loading) Figure 4: Supply Pin current as a function of its voltage (no load on drivers) Copyright © 2013 Rev. 3.2, November 2013 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 6 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet Figure 5: Supply Pin current as a function of its frequency (with different loads on its drivers) Copyright © 2013 Rev. 3.2, November 2013 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 7 Copyright © 2013 Rev. 3.2, November 2013 Csoftstart Enable Rfreq 9 RFREQ SYNC 7 15 offset -+ DAO FB 16 COMP 14 10 SS ENABLE 3 + - Differential amp output Soft-start / Logic VREF 4 offset Clock VINS + + - - LX7309 Vin Power fail warning (PFW) RCLP 11 Pulse skip Mode Blanking and Limiting PWM logic DAO UVLO/PFW select VIN GND + - PGND 20 + - ×7 ×5 VCC VCC Differential Voltage sense amplifier 17 2 5V drop Differential Current sense amplifier VREF (1.2V) 5V LDO VCC Chip Supply VDD UVLO/PFW select Dead time VINS_SEL 8 “High” Internal Rail “Low” Internal Rail (VDD) Rskip SYNC CLK + - VIN HYST 6 VDD 12 VSN 13 21 VCP CSN 22 CSP SG 19 23 PG VDD 18 VH 1 Rsense Decoupling for VH rail Rlower Rupper Vout_high Decoupling for VL (VDD) rail Vout_low Rlower Rupper LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet Functional Block Diagram Figure 6: Block Diagram (LX7309) Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Microsemi Page 8 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet Absolute Maximum Ratings Performance is not necessarily guaranteed over this entire range. These are maximum stress ratings only. Exceeding these ratings, even momentarily, can cause immediate damage, or negatively impact long-term operating reliability. The voltages are with respect to IC ground (GND and PGND combined), unless otherwise indicated. Min -0.3 -0.3 -0.3 0.3 -0.3 -40 VCC PG, SG VDD VH (with respect to VCC) All other pins Junction Temperature Lead Soldering Temperature (40s, reflow) Storage Temperature ESD rating HBM MM CDM -65 Max 40 20 6 -6 VDD+0.3 150 260 150 ±2 ±200 ±500 Units V V V V V °C °C °C kV V V Operating Ratings Performance is generally guaranteed over this range as further detailed below under Electrical Characteristics. The voltages are with respect to IC ground. VCC Fsw (adjustable frequency range) Max Duty Cycle fsw_synch (synchronization frequency range) Ambient Temperature* Min 9.6 100 * Corresponding Max Operating Junction Temperature is 125°C. Thermal Properties Thermal Resistance θJA Min 200 -40 Typ 36 Max 20 500 44.5 1000 85 Units V kHz % kHz °C Max Units °C/W Note: The θ JA number assumes no forced airflow. Junction Temperature is calculated using T J = T A + (P D x θ JA ). In particular, θ JA is a function of the PCB construction. The stated number above is for a four-layer board in accordance with JESD-51 (JEDEC). Copyright © 2013 Rev. 3.2, November 2013 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 9 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet Electrical Characteristics Unless otherwise specified under conditions, the Min and Max ratings stated below apply over the entire specified operating ratings of the device ( i.e. -40°C ≤ T A ≤ +85°C , 7V ≤ VCC ≤ 20V ). Typ values stated, are either by design or by production testing at 25°C ambient. The voltages are with respect to IC ground. Symbol Parameter Conditions Input Voltage Current UVLO threshold VCC_UVLO_UP VCC rise time > 0.5 ms; with input rising UVLO threshold VCC_UVLO_DN VCC rise time > 0.5 ms with input falling VENABLE or VINS = Low. See Note 2 VENABLE and VINS = High; VVCC < IC input current V CC_UVLO_UP ; -40°C ≤ Temp ≤ PG and SG = 1nF +55°C. See Note 2 IVCC_SD load to ground, VENABLE and VINS = High; No Load on VDD. VVCC < VCC_UVLO_UP ; RFREQ = 49.9k +55°C < Temp ≤ +85°C See Note 1,2 IC input current VENABLE = High, and (switching, no IVCC_Q load on SG, PG, VVCC > VCC_UVLO_UP, fsw = 500kHz VDD) Input UVLO/PFW Threshold on VINS_TH Rising or falling VINS pin Hysteresis pin VHYST_HIGH IHYST_SOURCING = 1mA high voltage Hysteresis pin VHYST_LOW IHYST_SINKING = 3mA low voltage LDOs VDD VDD rail IVDD_EXT < 5mA (current out of pin) VH rail (with VH respect to VCC) Hysteresis of VL No current in/out of pin VCLS_ON threshold Copyright © 2013 Rev. 3.2, November 2013 Min Typ Max Units 8.85 9.15 9.5 V 7 7.3 7.6 V 220 2000 µA 2000 uA 4.5 mA 3.5 mA 1.229 V 1.171 1.200 2.8 4.75 V 5 20.9 -5 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 0.4 V 5.25 V 23.9 V V Page 10 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet Symbol Soft Start Parameter Conditions Current out of SS ISS_CH pin during RFREQ=33.3k, VSS=0.5V charging phase Current into SS pin during ISS_DISCH RFREQ=33.3k, VSS=0.5V discharging phase Soft start charge VSS_CH By design only completed threshold Soft start discharge VSS_DISCH completed threshold Soft-start pin RSS_DISCH discharge FET resistance Soft-start tDISCH discharge FET on- time Switching Frequency and Synchronization Switching RFREQ=33.2k fsw_range frequency See Note 3 accuracy Max fsync_max synchronization frequency SYNC pin high VSYNC_HI threshold SYNC pin low VSYNC_LO threshold Minimum pulse tsync width of SYNC pulse Copyright © 2013 Rev. 3.2, November 2013 Min Typ Max Units 32 36 40 µA % of ISS_CH 10 90 285 95 % of VREF 50 mV 50 Ω 32 Switch cycles 315 345 KHz 1 MHz 2.4 V 0.8 100 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 V ns Page 11 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet Symbol Parameter Max SYNC pulse Dsync_max duty cycle Error Amplifier Reference VREF voltage DC Open-loop GainDC_OPL gain Unity Gain AVUGBW Bandwidth Output sourcing ICOMP_OUT current Output sinking ICOMP_IN current Max of input VEA_CMR_MAX common-mode range COMP pin high VCLAMP clamp PWM Comparator Inserted offset in VOFFSET inverted input Voltage set on RCLP pin by VRCLP external resistor to GND Current Sense Amplifier GainCSA DC Gain Max continuous IAUX current from VAUX Max input VCSA_CMR_MAX common-mode range tBLANK Blanking time Copyright © 2013 Rev. 3.2, November 2013 Conditions Min Typ Max Units 90 % 1.229 V 1.171 1.200 Rload=100k 70 100 dB Cload=10pF (By design only) 2 5 MHz 0.2V< VCOMP < 1.3V 110 0.2V< VCOMP < 1.3V 145 620 495 2 1.8 µA µA V 2.1 2.6 V 200 300 mV 0 1 V 5.25 V 4.75 5 4 mA 2 V 50 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 100 ns Page 12 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet Symbol Parameter Current limit threshold on VILIM output of current sense amplifier Current Limit threshold on output of VILIMHICCUP current sense amplifier capability Differential Voltage Amplifier DC gain of GainDA differential voltage amp Unity Gain Bandwidth of AVUGBW_DA differential voltage amp Max of input VDA_CMR_MAX common-mode range Drivers Drive resistance RPG_HI when PG is high Drive resistance RPG_LO when PG is low Minimum ontPG_MIN time of PG PG max duty DMAX cycle Drive resistance RSG_HI when SG is high Drive resistance RSG_LO when SG is low Copyright © 2013 Rev. 3.2, November 2013 Conditions Min Typ Max Units Where PWM pulses start to get truncated 1.1 1.2 1.3 V Where PWM pulses start to get omitted in hiccup mode 1.7 1.8 1.9 V 6.68 7.0 7.14 5 MHz 3.5 V 10 Ω 5 Ω 44.5 120 ns 50 % 10 Ω 10 Ω Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 13 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet Symbol Parameter tDEAD Conditions PG low to SG high or PG high to SG low Deadtime Logic Levels on VINS and ENABLE Input high VHI threshold Input low VLO threshold Thermal Protection Thermal TSD shutdown (rising) Thermal THYST shutdown hysteresis Min Typ Max Units 60 110 190 ns 2 V 0.8 157 15 V °C 30 °C NOTES: 1) Current may be reduced using a simple circuit covered on page 25. 2) Min and Maximum current are guaranteed by design. 3) Switching Frequency Equation: 𝐹𝑟𝑒𝑞 = 1 where Freq is [Hz] �90𝑝𝐹 ×𝑅𝐹𝑅𝐸𝑄 �+ 150𝑛𝑠 Applications Information Setting Switching Frequency A resistor, RFREQ, is connected from RFREQ pin to IC ground. Based on that, we get the following frequency fsw = 1 �90pf x RFREQ �+150nSec where Freq is [Hz] For example, by setting RFREQ=33.2k, we get fsw = 1 (90pf × 33.2 × 103 )+150nSec Copyright © 2013 Rev. 3.2, November 2013 = 1 (2.988𝜇𝑆+150𝑛𝑆) = 318.7 kHz Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 14 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet We can set any frequency between 100 to 500 kHz. Note that when synchronizing, the default frequency (as set by RFREQ) must be lower than the synchronization clock. In case the synchronization breaks, the converter will lapse back to the default value. When synchronizing, the switching frequency is ½ the synchronizing frequency. Setting Soft-Start A capacitor is connected between SS pin and IC ground. The current the cap is charged by is ISS _CHG = 1.2V (in seconds) RFREQ For example, if RFREQ=49.9k, we get ISS _CHG 1.2V 3 49.9 × 10 (in Amperes) = 2.4 × 10−5 ⇒ 24µA So, to charge a 0.1µF ceramic cap on the soft-start pin from 0 to 1.2V will take t SS C × ∆V ISS _CHG (in seconds) = 0.1µ × 1.2 0.12 (in seconds) = (in seconds) = 5 × 10−3 (in seconds) ⇒ 5ms 24µ 24 This is the soft-start time in this case. Setting Pulse-skip Mode threshold If a programming resistor RCLP is placed between RCLP pin and IC ground, the clamping voltage level is given by VCLP = 0.3 × RCLP (in Volts) RFREQ For example, if RCLP = RFREQ, say both are 49.9k, then the converter will enter pulse skipping when the output of the current sense amplifier drops to 0.3V. Note that the gain of this current amplifier is 5, so in terms of the voltage on the sense resistor (input of the current amp), we get 0.3V/5 = 0.06V. Since we usually design the converter so that its peak is around 0.2V (the peak of Rsense voltage before it starts to current limit), we are getting a ratio of 0.06V/0.2V = 0.3. In other words, the converter will enter pulse-skipping when the output current is 30% of the max designed output current. Setting VPP UVLO/Hysteresis thresholds Suppose we have a divider connected to input at the VINS pin. Suppose we call the resistors RUPPER and RLOWER. We also have a hysteresis resistor, RHYST, from the output of the UVLO comparator, which provides positive Copyright © 2013 Rev. 3.2, November 2013 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 15 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet feedback on to the VINS pin, as explained in the Pin Description section. So, when the input voltage is rising, in effect the hysteresis resistor is in parallel to the lower resistor RLOWER. When the voltage on the VINS pin rises above 1.2V, the UVLO comparator flips and the hysteresis resistor appears connected to 5V (output of the UVLO comparator). Example for Setting the UVLO Thresholds: VDD = 5.0V VCCRISING = 39.8V VCCFALLING = 34.8V Establish the Hysteresis: Vh = VRISING − VFALLING = 39.8 − 34.8 = 5 Set RHYST for 10µA current when HYST pin is high: VDD−1.2 5−1.2 R HYST = 10×10−6 = 10×10−6 = 380k ; use 374k Establish RUPPER and RLOWER: Vh 5 R UPPER = R HYST × VDD = 374 × 103 × 5 = 374k ; use 374k R LOWER = use 12.1k 1.2 × R UPPER × R HYST 1.2 × 374k × 374k = = 12k R HYST × VRISING − 1.2(R UPPER + R HYST ) 374k × 39.8 − 1.2(374k + 374k) So with the selected resistors, we get a rising threshold of 39.8V, and a falling threshold of 34.8V. Note that unless we tie VINS_SEL high (to VDD), the converter will not stop switching below 34.8V, but will stop only when VCC falls below its lower operating range of 7.6V. Copyright © 2013 Rev. 3.2, November 2013 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 16 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet Figure 7: Equivalent Diagrams for UVLO and Hysteresis Setting the Voltage Divider for Output Rails Generically, we can state the equation for setting the output voltage to be VOUT = VX × R UP + R LOW R LOW Copyright © 2013 Rev. 3.2, November 2013 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 17 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet Where RUP is the name we have given to the upper resistor (connected to output rail) and RLOW is the name we have given here to the resistor connected to the lower rail (usually IC ground). Vx is the reference the feedback voltage is compared too. This is application dependent, but can be summarized for three cases: a) Non-isolated topologies with simple divider connected to FB pin directly. For this use VX = 1.2V. b) Isolated topologies with divider to another reference (such as TL431 with an internal reference of 2.5V), as in Fig. 1. For this use VX = 2.5V. c) Non-isolated topologies with a differential divider connected to differential voltage amplifier of the LX7309 . Here we use the same divider equation provided above, but using VX = 0.171V (that is 1.2V divided down by the gain of the diff-amp, i.e. by 7). We need two identical dividers as shown in Fig.2. Selecting the Sense Resistor In a Buck topology, the center of the switch current ramp equals the output current. To that we need to add about 30% for the peak current “IPEAK+” because of the rising ramp caused by the inductor. That is a factor of 1.3. We also need to include some headroom for proper transient response at max load. Since the peak voltage on the sense resistor is 0.2V, to leave headroom, we should plan that the switch current peak stays at around 0.18V max at max load. This means that IPEAK = 1.3 × IO , So R SENSE = R SENSE = 0.18 0.138 = 1.3 × IO IO 0.138 (Buck) IO Assuming we have designed the converter to operate up to 44% max duty cycle, we can quickly estimate the peak current as follows. For example, if we have a Buck application for 5A output, irrespective of the input and output voltage conditions (as long as they are not violating the min and max duty cycle limits of the converter), and assuming we have selected inductance appropriately, we should pick a sense resistor of R SENSE = 0.138 =0.028 Ω 5A Copyright © 2013 Rev. 3.2, November 2013 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 18 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet For a Forward converter (Buck with a transformer), instead of the load current IOR in the above equation, use the reflected load current of IO/n, where n is the turns ratio (number of Primary-side turns divided by number of Secondary-side turns). You will also need to lower the sense resistance further to account for the magnetization current component on the switch side. So roughly R SENSE ≈ 0.138 NP (Forward) × IO NS For a Boost or Buck-Boost, we have to account for the fact that the peak current is not just 1.3 times max load current, but is actually IPEAK = 1.3 × IO (where D can be as high as 44%) 1−D So we should use the following equation for sense resistor R SENSE = R SENSE = 0.18 × (1 − D ) 1.3 × IO = 0.101 1 = 1.3 × IO 13 × IO 0.077 (Boost, Buck-Boost) IO For example, if the max load current is 5A, the sense resistor value to use is R SENSE = 0.077 =0.015 Ω 5A As we can see, this is roughly half of what we got for the Buck (same load current). For a Flyback topology (Buck-Boost with a transformer), we have to use the reflected output current. So we get R SENSE ≈ 0.077 NP (Flyback) × IO NS Input Feedfoward One of the ‘tricks’ to more effective current limiting in Flyback converters is to place a resistor from VIN to the ISENSE pin. The purpose of this is to reduce the current limit and thus also effectively limit the maximum available duty cycle at high line. At high line the steady operating duty cycle is naturally lower, and so is the peak current. Copyright © 2013 Rev. 3.2, November 2013 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 19 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet But under overloads, the converter will try to hit any available brickwall, whichever comes up first. So it will try to reach maximum duty cycle or hit current limit, all this happening till the slower Secondary-side current limit can start to work and limit the output power. But even during this interval, damage can occur. This situation cannot be understood in terms of any steady state scenario. For example if the output voltage is zero (perfect short), then the down-slope of the Primary-side inductor current VOR/LP (or equivalently the downslope of the Secondary-side current VO/LS) is almost zero (actually it is VD/L). Therefore the current can never reach the state it started the cycle off with, and steady-state by definition does not exist. So we will ultimately get a ‘flux-walking’/‘current staircasing’ condition. Till we hit the current limit. But now, though the peak Primary-side peak current is supposedly fast and limited precisely by the sense resistor, and should therefore protect the switch and the transformer from saturation, this does not happen in practice. It can be shown that the blanking time requirement of all current mode control ICs such as the LX7309 translates to a minimum pulse width. And it can be shown that that can effectively over-ride any set current limit, in this condition. The current limit, whenever reached, can only respond by commanding the controller to limit the duty cycle further. Which it may not be able to do anymore. Even during this minimum pulse width of 100 ns to 150 ns or so, the slope of the up-ramp which is VIN/L, is very high. And there is also virtually no down-ramp. So the current will actually continue to staircase beyond the set current limit. Many modern current mode DC-DC controllers/switchers respond by initiating a ‘frequency foldback’ whenever the voltage on the feedback pin falls below a certain threshold. In doing so they effectively reduce the duty cycle under current limit, and this extends the off-time by a typical factor of 4 to 6, giving enough time for the current to ramp down to a value less than what it started the cycle with, thereby quashing staircasing. But note that the effectiveness of this technique depends largely on the diode drop! So ‘good’ diodes (with lower forward drops) actually make the fault currents even more severe, as they do not provide enough down-slope. In the case of the LX7309 we can protect ourselves from this situation by reducing the current limit at high line, so we have some enforced headroom available before the transformer can saturate. We now give the equations to implement this. Basically, by introducing a ‘feedforward’ resistor RFF, the current sense signal is DC shifted a little higher by an amount RFF×IFF, so it will hit the current limit a little earlier. Note that we do not want to affect the current limit at lower input voltages. If RBL is the resistor normally connected between the sense resistor and the current sense pin of the IC (CSP), (typically 100 Ω to 1 kΩ or so), the current limit at high line VIN_MAX as a ratio of the current limit at VIN_LO is CLIMVIN _ MAX CLIMVIN _ LO V  VCLIM −  IN _ MAX × R BL   R FF  = V  VCLIM −  IN _ LO × R BL   R FF  Copyright © 2013 Rev. 3.2, November 2013 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 20 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet where VCLIM is the voltage on the current sense pin corresponding to current limit (0.2V in the case of the LX7309). So if for example, in a universal input AC-DC application, VIN_MAX = 389VDC, VIN_LO = 85VDC, RBL=1k, VCLIM = 1V, we get the required value of the feedforward resistor for reducing the current limit threshold from 0.2V to 0.15 V (factor of 0.75V) 1-  389 ×1000  R FF  0.75=  1-  85 ×1000  R FF   Solving we get R FF = 1.3M At 60VAC (85VDC) this will also lower the current limit threshold slightly below 0.2V. The current IFF is 85VDC/1.3M=65µA. Passing through the blanking resistor 1kΩ, it causes a drop of 0.065V. So the current limit threshold is now 0.2-0.065 = 0.135V. Note that the current limit threshold actually has a typical tolerance of ±10%. Knowing this we can correctly set RSENSE (in series with FET). Start-up Circuits Many applications use input voltages higher than the rated maximum voltage for VCC. For these applications, VCC must be provided by means of an external regulator or voltage source. Most Flyback and Forward applications use an additional winding on the power transformer or inductor to generate VCC. This method is shown in both Figures 1 and 2. Generating VCC by means of an additional winding, (sometimes called a “bootstrapped” supply), requires that the converter must be running and at the correct output voltage for the generated VCC to be stable and at the correct voltage. For these applications a method to start-up the controller and keep it running long enough for the bootstrapped supply to provide stable VCC must be implemented. The most simple of these methods is shown in Figure 8. This simple resistor-capacitor circuit, connected between the input voltage and ground, provides enough current at VCC UVLO to start the controller and keep it running until the bootstrap supply is stable. The resistor is sized to provide enough current to charge the VCC capacitor and satisfy the maximum standby current requirement; the capacitor is sized to hold up the voltage long enough for the bootstrap supply to take over. Copyright © 2013 Rev. 3.2, November 2013 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 21 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet To VIN 13.7k From Transformer Auxiliary Winding To VCC 22uF Figure 8: Simple Start-Up Circuit The start-up resistor’s value is calculated using the difference of the minimum input voltage, the maximum UVLO rising threshold divided by the maximum standby current: R START = VMIN -VUVLOMAX ISTANDBYMAX For minimum input voltage of 37V, and using the values found in the Electrical Characteristics Table for VUVLO and maximum standby current: 37V-9.5V R START = = 13.7k 2mA The absolute worst case power dissipation of the start-up resistor will be at maximum input voltage, with the VCC capacitor fully discharged. To account for this condition the power is simply Vmax2/RSTART. However, this equation accounts for the worse case condition with VCC = 0, and doesn’t take into account the steady state power dissipation, which is less. In actual applications the period of time taken to charge the VCC cap to the UVLO level is short, in which case the steady state power dissipated by the resistor can be found by: (𝑉𝑀𝐴𝑋 − 𝑉𝑈𝑉𝐿𝑂𝑀𝐼𝑁𝐹𝐴𝐿𝐿 )2 𝑃R START = R START For example: If VMAX = 57V, and using the minimum threshold for falling UVLO from the Electrical Characteristics Table: 𝑃R START = Copyright © 2013 Rev. 3.2, November 2013 (57V − 7V)2 = 183𝑚𝑊 13.7k Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 22 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet The user needs to take into account the surge rating of start-up resistor used and the period of time taken to charge VCC to the UVLO point to insure that the maximum surge rating of the resistor is not exceeded. When in doubt, it is best to use the worse case power dissipation at VCC = 0. Sizing the VCC capacitor requires knowledge of operating current during the start-up phase. Operating current is application dependent, in that it is affected by number of FETs used and their respective gate charges, as well as external loads on VDD and VCC . Using the value of operating current (either estimated or measured), the capacitor needs to be sized to keep VCC from dropping below the maximum UVLO falling limit during the soft start period, which starts at the minimum UVLO rising threshold. For example, assuming that all of the operating current is provided by the capacitor, and using an estimated operating current of 5mA, soft start time of 5ms and the value for minimum rising UVLO and maximum falling UVLO found in the Electrical Characteristics Table: CVCC = 𝑇SS ×𝐼OP 5ms×5mA = = 20µF VUVLOMINRISE -VUVLOMAXFALL 8.85V-7.6V For this example we would use a 22uF capacitor. The above method requires minimum parts; however, the start-up resistor dissipates unneeded power after the converter has started, and it’s large value and large VCC capacitor creates a long delay time from the initial application of voltage to the UVLO threshold. Adding a zener diode and pass transistor creates a more efficient start-up method. This method is outlined in Figure 9. To VIN 130k MMBTA06 11V EDZTE6111B From Transformer Auxiliary Winding To VCC 4.7uF Figure 9: Efficient Start-Up Circuit For the above circuit, the zener is sized such that after start-up (during normal operation) the pass transistor’s Base-Emitter junction is reversed biased. Under this condition VCC current flows from the bootstrap supply only. With this method the only power loss is through the zener and resistor, which can be reduced to a minimum. Also smaller VCC capacitor can be used, due to the fact that the current required to hold up VCC during start-up is sourced by the pass transistor. Copyright © 2013 Rev. 3.2, November 2013 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 23 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet The pass transistor is sized to provide the operating current during start-up, with a maximum collector-emitter voltage rating greater than the maximum input voltage. The current limiting resistor is sized at minimum input voltage to provide the minimum required zener current for regulation, as well as the minimum base current to meet the DC gain required by the transistor. Using our example: With VMAX = 57V, we choose an 80V transistor. The transistor chosen has a maximum current capability of 100mA, which more than meets our needs. Our bootstrap supply is designed with an average steady state output of 12V. The zener voltage needs to be a minimum of 0.7V below this. An 11V zener will meet this requirement. During the soft start period, the transistor will provide VCC current. VCC voltage during this period needs to be above the maximum UVLO and will be approximately: VCC=𝑉ZENER -VBE ≅ 11𝑉 − 0.7𝑉 = 10.3𝑉 10.3V is above the maximum UVLO of 9.6V. The current limiting resistor is calculated based on the DC gain of the transistor and the zener current requirements. Using the datasheet for the chosen zener, the zener voltage is acceptable at 100uA. The DC gain of the transistor at 10mA is specified at 100, which will require a minimum base current of 100uA. This transistor has plenty of margin, so we can use a base current of 100uA. The minimum required current provided by the resistor at the minimum input voltage is 200uA. For a minimum input voltage of 37V: R LIM = VMIN − VZENER 37V − 11V = = 130𝑘 𝐼MIN 200µA The power dissipated by the limiting resistor and zener are determined at the maximum input voltage. For maximum input voltage of 57V: PRLIM = PZENER = (57V − 11V)2 = 16mW 130k (57V − 11V) × 11V = 4mW 130k Note: Care must be taken that the voltage generated by the bootstrap supply does not exceed the maximum specified reverse breakdown voltage for the transistor’s base-emitter junction. If the voltage exceeds the specified reverse VBE, then a small signal diode, such as a MMBD4148 may be placed in series with the emitter and VCC. If this extra diode is needed, the zener voltage may need to be increased to account for the extra voltage drop. Copyright © 2013 Rev. 3.2, November 2013 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 24 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet Controlling Standby Current The LX7309 standby current at temperatures greater than +55°C may be improved by replacing the typical 100k pull-up resistor connected between VDD and Enable with a simple RC connected between VDD and Pin 17 GND. For this method, size the resistor and capacitor such that the voltage at the enable is delayed with respect to the rising VCC voltage. Set the delay such that the voltage at VCC reaches 5.0V before the voltage at enable is above 1.1V. The following component values may be used for a start-up resistor of 13k and a 22uF VCC filter: To VDD 330k To Enable 0.47uF Figure 10: Enable Delay Circuit for Reducing High-Temperature Standby Current Using the above method will reduce the maximum VCC standby current to 2mA at temperatures greater than +55°C. Note: this method is only needed if the simple start-up circuit shown in Figure 8 is used; this method is not necessary if using the start-up circuit shown in Figure 9. The value of the above capacitor needed for proper delay may be estimated using the following method: Example Parameters: VCC cap = 22uF RSTART = 13k VMIN = 37V Enable Pullup Resistor = 330k ICC = 2mA First determine the starting and finishing current when charging VCC capacitor to 5V: ICAPSTART = Copyright © 2013 Rev. 3.2, November 2013 VMIN 37V − ICC = − 2mA = 846µA 𝑅START 13k Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 25 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet ICAPFINISH = VMIN − VFINISH 37V − 5V − ICC = − 2mA = 462µA 𝑅START 13k Next, determine the time required for the VCC voltage to reach 5V: T5V = ln � ICAPFINISH 462µA � × 13k × 22uF = 173ms � × 𝑅START × CAPVCC = ln � ICAPSTART 846µA There is an approximate 2 diode drop (1.4V) between VCC and VDD at voltages below 7V. This voltage offset will delay the start of VDD rising by: ICAP1.4V = TDLY = ln � ICAP1.4V VMIN − 1.4V 35.6V − ICC = − 2mA = 738µA 13k 𝑅START 738µA � × 13k × 22uF = 39ms � × 𝑅START × CAPVCC = ln � ICAPSTART 846µA The average VDD voltage during the time period required for VCC to reach 5V is determined: VDDAVG = 5V − 1.4V = 1.8V 2 Finally the estimated capacitor required on Enable pin for the proper delay: CDLY = For margin, use a 0.47uF. Copyright © 2013 Rev. 3.2, November 2013 T5V − TDLY 173ms − 39ms = = 0.39µF 1.1V V �ln �1 − VDDT �� × 𝑅PULLUP �ln �1 − 1.8V�� × 330k AVG Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 26 LX7309 Advanced Multi-topology Current-Mode Controller Production Datasheet Package Dimensions D b L D2 E E2 e A1 A A3 Copyright © 2013 Rev. 3.2, November 2013 Dim A A1 A3 b D E e D2 E2 L MILLIMETERS MIN MAX 0.80 1.00 0 0.05 0.20 REF 0.18 0.30 4.00 BSC 4.00 BSC 0.50 BSC 2.30 2.55 2.30 2.55 0.30 0.50 INCHES MIN MAX 0.031 0.039 0 0.002 0.008 REF 0.007 0.011 0.157 BSC 0.157 BSC 0.019 BSC 0.090 0.100 0.090 0.100 0.012 0.020 Note: 1. Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm(.006”) on any side. Lead dimension shall not include solder coverage. Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 27