Data Sheet
May 2012
MAX24288 EV KIT
Evaluates: MAX24288
General Description
The MAX24288 EV Kit is an easy-to-use evaluation kit
for the MAX24288 IEEE 1588 Packet Timestamper and
Clock. On the network side of the MAX24288 an SFP
module cage supports either a 1000BASE-X optical
module or a module containing a 10/100/1000Mbps
Ethernet PHY with an SGMII system interface. On the
system side of the MAX24288 an unmanaged switch IC
with integrated PHYs plus magnetics and RJ-45 jacks
provides an easy Cat 5 Ethernet connection to 1588 test
equipment or a processor board running 1588 software.
An on-board high-stability TC-OCXO oscillator is
provided to allow evaluation of 1588 performance with a
variety of network PDV and impairment scenarios. Also,
the board can accept an external oscillator input for
testing alternate oscillators. The board provides SMB
connectors for three device GPIO signals. Through
these connectors clock and 1PPS signals can be input
or output to lock the MAX24288 time clock to a master
time clock or to lock other 1588 components to the
MAX24288.
Typically the board is controlled by EV kit software
running on a Windows PC through the USB interface.
The board also has SPI and JTAG headers through
which the MAX24288 can be controlled by a processor
on another board as needed.
Features
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
Network-Side SFP Cage Accepts Optical or
Electrical Ethernet SFP modules
System-Side Unmanaged Ethernet Switch for Easy
Connection to Processor Running 1588 Software.
GPIO SMB Connectors to Input or Output Clock
Signals and 1PPS Signals
Onboard TC-OCXO Provides Stable Reference for
High-Quality Timing over IEEE1588
Connectors and Component Sites for Alternate
Oscillators as Needed
Included Universal 5V Power Supply
Jumpers to Configure Reset State of MAX24288,
GPIO Termination, Ethernet Switch Mode and More
LEDs for Power Supplies Valid and Port Status
Soldered MAX24288 for Best Signal Integrity
Easy-to-Read Silkscreen Labels Identify the
Signals Associated with All Connectors,
Jumpers, and LEDs
Windows®-Based Evaluation Software Provides
Easy Configuration and Monitoring of the
MAX242888 Device
Evaluation Software Calls MAX24288 HAL
Software and Structure is Similar to HAL Software
Minimum System Requirements
Demo Kit Contents
♦
MAX24288 Board
♦
PC Running Windows XP or later
♦
Power Supply
♦
Available USB Port
♦
USB Cable
Ordering Information appears at end of data sheet.
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Contents
1.
Board Floorplan .................................................................................................................................................... 4
2.
Connections to the Board ..................................................................................................................................... 5
2.1
Power-Supply Connection ........................................................................................................................... 5
2.2
USB Connection .......................................................................................................................................... 5
2.3
Ethernet Connections and IP Addresses ..................................................................................................... 5
2.4
Example Setup ............................................................................................................................................. 5
3.
Installing the Software .......................................................................................................................................... 5
3.1
Troubleshooting Software Installation.......................................................................................................... 6
4.
Running the Software ........................................................................................................................................... 6
5.
Software User Interface ........................................................................................................................................ 7
5.1
Status Display .............................................................................................................................................. 7
5.2
Configuration Menu and Command Prompt ................................................................................................ 8
5.2.1
Navigating Menus and Changing Settings............................................................................................... 8
5.2.2
Configuring the Device............................................................................................................................. 8
5.2.3
Other Commands ..................................................................................................................................... 9
5.3
Configuration Menu Detailed Descriptions .................................................................................................. 9
6.
Jumpers, Connectors and LEDs......................................................................................................................... 21
7.
Component List .................................................................................................................................................. 26
8.
Schematics ......................................................................................................................................................... 28
9.
Ordering Information ........................................................................................................................................... 28
10.
Revision History ............................................................................................................................................. 28
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________________________________________________________________________________ MAX24288 EV KIT
List of Figures
Figure 1. MAX24288 EV Kit Board Floorplan .............................................................................................................. 4
Figure 2. Example Setup ............................................................................................................................................. 5
Figure 3. User Interface Main Screen .......................................................................................................................... 7
List of Tables
Table 1. Status Display Fields ..................................................................................................................................... 7
Table 2. MAIN Menu .................................................................................................................................................... 9
Table 3. CONFIG SCRIPTING Menu .......................................................................................................................... 9
Table 4. GPIO PINS Menu .......................................................................................................................................... 9
Table 5. DATA PATH Menu ....................................................................................................................................... 10
Table 6. 1588 TIME ENGINE Menu .......................................................................................................................... 10
Table 7. 1588 EVENT GENERATORS Menu ........................................................................................................... 12
Table 8. PEG1/PEG2 COMMANDS Submenu .......................................................................................................... 12
Table 9. 1588 TIMESTAMPERS Menu ..................................................................................................................... 12
Table 10. PACKET TS FIFO ENABLES Submenu ................................................................................................... 13
Table 11. 1588 PACKET CLASSIFIERS Menu ......................................................................................................... 13
Table 12. UID CHECK Menu ..................................................................................................................................... 14
Table 13. CPC CLASSIFIER Menu ........................................................................................................................... 14
Table 14. 1588 ON-THE-FLY INSERTION Menu ..................................................................................................... 16
Table 15. ON-THE-FLY CORRECTION Menu .......................................................................................................... 18
Table 16. TIMESTAMP INSERTION Menu ............................................................................................................... 18
Table 17. LOCK TO PPS Menu ................................................................................................................................. 19
Table 18. TEST Menu ................................................................................................................................................ 20
Table 19. Power and Reset Components .................................................................................................................. 21
Table 20. MAX24288 REFCLK Jumpers and Connectors ........................................................................................ 21
Table 21. MAX24288 Pin Configuration Jumpers ..................................................................................................... 21
Table 22. MAX24288 Parallel Interface Configuration .............................................................................................. 23
Table 23. MAX24288 GPIO1 Jumpers and Connectors ........................................................................................... 23
Table 24. MAX24288 GPIO2 Jumpers and Connectors ........................................................................................... 23
Table 25. MAX24288 GPIO3 Jumpers and Connectors ........................................................................................... 23
Table 26. Processor and Debug Jumpers and Connectors ...................................................................................... 24
Table 27. Ethernet Switch Jumpers, Connectors and LEDs ..................................................................................... 24
Table 28. SFP Module Jumpers and LEDs ............................................................................................................... 25
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________________________________________________________________________________ MAX24288 EV KIT
1. Board Floorplan
When the board is oriented as shown in Figure 1, The 5V power supply and USB cable included with the kit are
connected to jacks J1 and J2 at the top of the board. An SFP module is inserted into the SFP cage lower-left, and
an appropriate cable is connected to the SFP module. The SFP module can be 1000BASE-X optical for a
1000Mbps optical connection, or it can contain a 10/100/1000Mbps copper PHY with an SGMII interface to the
MAX24288 and an RJ-45 jack on the other side. The SFP module is the network side of the MAX24288, and
timestamping of IEEE1588 messages occurs as packets enter and leave the MAX24288 from/to the SFP module.
The board ships with a TCXO mounted in the Y3 oscillator position and a 25MHz XO in the Y1 position. See
section 6 for detailed descriptions of the board’s jumpers, connectors and LEDs.
Pwr
Jack
USB Jack
Y3
OSC
Processor
Y2 OSC
Y1
OSC
Ethernet
RJ-45 Jack
Ethernet
Switch IC
Ethernet SFP Module Cage
(serial side of MAX24288)
MAX
24288
(parallel side
of MAX24288)
Ethernet
RJ-45 Jack
MAX24288 Config Jumpers
Figure 1. MAX24288 EV Kit Board Floorplan
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________________________________________________________________________________ MAX24288 EV KIT
2. Connections to the Board
2.1
Power-Supply Connection
The board is powered through connector J1 using the provided AC wall-plug 5V power supply. LED DS1
illuminates to indicate that the board is powered.
2.2
USB Connection
The MAX24288 EV kit software application communicates with the EV kit board through USB connector J2.
2.3
Ethernet Connections and IP Addresses
The Ethernet switch on the board, Realtek RTL8363, operates by default as a simple, unmanaged switch. To avoid
set-up problems, each system connected to the MAX24288 EV Kit board must have a unique IP address.
2.4
Example Setup
1588 Master or
Grandmaster
Enet
MAX24288EVKit
Network
(switches, routers)
Master
Clock or 1PPS Signal
Enet
SFP
Slave
Clock or 1PPS Signal
‘288
Switch
Enet
CPU
Running 1588 Code
USB
Time Interval
Analyzer
Figure 2. Example Setup
3. Installing the Software
Important Note: Do not connect the board to the PC until after installing the software. The device driver for the
USB microcontroller will not be installed correctly.
Follow these steps to install the MAX24288 EV Kit software:
1. To install the software, run max24288evk.exe. The latest version of the EV Kit software can be
downloaded from the Microsemi website or requested from Microsemi timing products technical support.
2. In the window that indicates the publisher could not be verified, click Run.
3. Follow the prompts in the MAX24288 Eval Kit setup wizard, For a default installation, click Next three
times.
4. Connect the power cord to the J1 connector on the EV Kit board.
5. Connect a USB cable from a USB jack on the PC to the J2 connector on the EV Kit board.
6. In the notification area, Windows will indicate “Installing device driver” and then indicate “Freescale CDC
Device (COM6) Device driver software installed successfully.”
The text “COM6” indicates the virtual COM port number assigned to the board. This
number varies from system to system. Write down the assigned number to use when
running the EV Kit software.
If Windows does not show the messages above then verify that the board is powered and
is connected to the PC. If the board was already connected to the PC before installing the
software then see follow the troubleshooting steps in section 3.1.
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________________________________________________________________________________ MAX24288 EV KIT
3.1
Troubleshooting Software Installation
If the board was connected to the PC before installing the software or if the EV kit software does not list the board’s
COM port number as an option, then follow these steps:
1. In Windows, go to the Device Manager. In recent versions of Windows this is done by going to Control
Panel and double-clicking System. Then in the upper-left corner click Device Manager.
2. In the Device Manager window, under Other devices, right-click on Unknown device and select
Uninstall. In the Confirm Device Uninstall pop-up click OK.
3. In Control Panel double-click Programs and Features.
4. Right-click on MAX24288 Eval Kit and select Uninstall.
5. Disconnect power and USB cables from the EV Kit board.
6. Follow the steps in section 3.
4. Running the Software
To run the software, double-click on the MAX24288 Eval Kit shortcut on the desktop, or in the Windows Start
menu, select All Programs Microsemi MAX24288 Eval Kit.
At the prompt enter the COM port number assigned to the board in step 6 in section 3.
The software then displays its main menu, as shown in Figure 3.
To start communication with the MAX24288 on the EV kit board, type 1 then Enter to create the MAX24288 HAL. If
the software and the USB device driver have been installed correctly then regular screen updates begin, the TE
SEC field increments once per second, and TE NS fields displays ever-changing values.
If the software exits unexpectedly then run the software again and specify a different COM port number. If none of
the listed COM port numbers is correct then follow the troubleshooting steps in section 3.1.
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5. Software User Interface
Configuration Menu
MAIN MENU
1> CREATE MAX24288 HAL
2> MAX24288 PHY ADDRESS
3> MAX24288 SPI MODE
4> CONFIG SCRIPTING
5> GPIO PINS
6> DATA PATH
7> 1588 TIME ENGINE
8> 1588 EVENT GENERATORS
9> 1588 TIMESTAMPERS
10> 1588 PACKET CLASSIFIERS
11> 1588 ON-THE-FLY INSERTION
12> 1588 LOCK TO PPS
13> TEST
FUNC>
UNIT32> 4
LIST> DISABLED
MENU>
MENU>
MENU>
MENU>
MENU>
MENU>
MENU>
MENU>
MENU>
MENU>
Command Prompt
>_
--------------------------------------------------------------------------MSG: c=clr counts, p=previous, q=quit, s=start/stop status polling
COM6: 115200
TE SEC 827
TE NS 237481562
ID 0X0EE0
LNK UP 1
AN PAGE 0
AN RX 0X0000
AN COMP 0
R FAULT 0
TS1 SEC 0
TS1 NS 0
TS1EDGE NONE – OFF TS1 CNT 0
TS2 SEC 0
TS2 NS 0
TS2EDGE NONE – OFF TS2 CNT 0
EGR MSG 0
UID 0
SEQ 0
GPIO 0X06
TS3 SEC 0
TS3 NS 0
TS3EDGE NONE – OFF TS3 CNT 0
ING MSG 0
UID 0
SEQ 0
DPL LOS ON
STATE OFF
ERR NS 0
DPLL BW 0
DF 0
INTEG 0
FREQ 0
Status Display
Figure 3. User Interface Main Screen
5.1
Status Display
The status display area (see the bottom of Figure 3) shows the latest data polled from the device. To start software
polling and updating of these fields, select CREATE MAX24288 HAL in the main menu. To start or stop polling,
use the s command at the command prompt. Table 1 lists and describes the status display fields.
Table 1. Status Display Fields
Row
1
1
1
1
2
2
2
Field
TE SEC
TE NS
ID
LNK UP
AN PAGE
AN RX
AN COMP
Description
Time engine seconds field
Time engine nanosecond field
Value read from the MAX24288 ID register
Link Up, MAX24288 BMSR register bit 2, 1=link up
Auto-negotiation page available, 1=yes
Auto-negotiation receiver register value
Auto-negotiation complete, MAX24288 BMSR register bit 5, 1=complete
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Row
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
8
8
8
9
9
9
9
5.2
Field
R FAULT
TS1 SEC
TS1 NS
TS1EDGE
TS1 CNT
TS2 SEC
TS2 NS
TS2EDGE
TS2 CNT
EGR MSG
EGR UID
EGR SEQ
GPIO
TS3 SEC
TS3 NS
TS3EDGE
TS3 CNT
ING MSG
ING UID
ING SEQ
DPL LOS
STATE
ERR NS
DPLL BW
DF
INTEG
FREQ
Description
Remote fault, MAX24288 BMSR register bit 4
Timestamper 1, timestamp seconds field
Timestamper 1, timestamp nanoseconds field
Timestamper 1, timestamp edge type, 0=falling, 1=rising
Count of timestamps done by timestamper 1 since HAL started or last c command.
Timestamper 2, timestamp seconds field
Timestamper 2, timestamp nanoseconds field
Timestamper 2, timestamp edge type, 0=falling, 1=rising
Timestamper 2, count of timestamps done since HAL started or last c command
Timestamper 2, 4-bit egress PTP messageType field
Timestamper 2, 12-bit egress PTP identity code. See MAX24288 data sheet section 6.13.5
Timestamper 2, 16-bit egress PTP sequenceID field
MAX24288 GPIO status register (GPIOSR) bits 6:0
Timestamper 3, timestamp seconds field
Timestamper 3, timestamp nanoseconds field
Timestamper 3, timestamp edge type, 0=falling, 1=rising
Timestamper 3, count of timestamps done since HAL started or last c command.
Timestamper 3, 4-bit ingress PTP messageType field
Timestamper 3, 12-bit ingress PTP identity code. See MAX24288 data sheet section 6.13.5
Timestamper 3, 16-bit ingress PTP sequenceID field.
Hardware/Software DPLL loss of signal
Hardware/Software DPLL state
Hardware/Software DPLL time error in nanoseconds
Hardware/Software DPLL bandwidth
Hardware/Software DPLL damping factor
Hardware/Software DPLL integral path control
Hardware/Software DPLL frequency control
Configuration Menu and Command Prompt
5.2.1 Navigating Menus and Changing Settings
Figure 3 shows the main screen of the MAX24288 software. In the upper half of the screen the command menu
has two columns. The left-hand column shows numbered command/menu options. The right-hand column
indicates what happens when an option is chosen. FUNC> indicates that a function is executed, LIST> indicates a
list of choices will be presented, and MENU> indicates that the user will be taken to a submenu. Data types such
as UINT32> or STR> indicate that a value with the specified data type can be entered. UINT32>, for example,
means a 32-bit unsigned integer. STR> means text string.
To change the device configuration, the user types a number at the command prompt followed by the Enter key. If
the option selected has a data type in the right-hand column, such as UINT32> then the cursor moves to the right
of the data type. The user then enters the desired value followed by the Enter key. The cursor then moves back to
the command prompt area.
If the option selected has LIST> in the right-hand column, then the cursor moves to the right of the LIST> text and
a list of options is shown in an additional column on the right. The user then enters the option number from the list
followed by the Enter key. The value next to LIST> then changes to the option selected, and the cursor moves
back to the command prompt area.
5.2.2 Configuring the Device
All menus of the software are designed to have a two-step configuration process:
1. Configure the relevant values using data-type or LIST> menu options.
2. Configure the HAL or the device using a FUNC> menu option.
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________________________________________________________________________________ MAX24288 EV KIT
For example, in the main menu the PHY address and SPI mode are configured first, and then CREATE MAX24288
HAL is selected. As another example, in the DATA PATH menu, AUTO-NEGOTIATE MODE and AUTONEGOTIATE ADVERT are configure first, and then CONFIG AUTO-NEGOTIATE is selected.
5.2.3 Other Commands
In addition to menu item numbers, the following commands are also valid at the command prompt:
c – clear counts in status area
p – return to previous menu (when in a submenu)
q – quit the program
s – stop/start status polling
5.3
Configuration Menu Detailed Descriptions
Table 2. MAIN Menu
Name
CREATE MAX24288 HAL
MAX24288 PHY ADDRESS
MAX24288 SPI MODE
CONFIG SCRIPTING
GPIO PINS
DATA PATH
1588 TIME ENGINE
1588 EVENT GENERATORS
1588 TIMESTAMPERS
1588 PACKET CLASSIFIERS
1588 ON-THE-FLY INSERTION
1588 LOCK TO PPS
TEST
Description
This function creates the MAX24288 HAL and starts polling device status. The three
MAX24288* fields below must be set before this function is executed.
Specifies the address of the MAX24288 on the MDIO bus to the HAL. The MAX24288
gets its PHY address from pins RXD[7:4] and RX_ER when the MAX24288 RST_N
pin is asserted.
Disable/Enable.
Affects MAX24288 register bit PAGESEL.SPI_DIS.
Opens the CONFIG SCRIPTING menu. See Table 3.
Opens the GPIO PINS menu. See Table 4.
Opens the DATA PATH menu. See Table 5.
Opens the 1588 TIME ENGINE menu. See Table 6.
Opens the 1588 EVENT GENERATORS menu. See Table 7.
Opens the 1588 TIMESTAMPERS menu. See Table 9.
Opens the 1588 PACKET CLASSIFIERS menu. See Table 11.
Opens the 1588 ON-THE-FLY INSERTION menu. See Table 14.
Opens the 1588 LOCK TO PPS menu. See Table 17.
Opens the TEST menu. See Table 18.
Table 3. CONFIG SCRIPTING Menu
Name
READ CONFIGURATION
WRITE CONFIGURATION
READ CONFIG FILE NAME
WRITE CONFIG FILE NAME
Description
Function reads configuration information from the file specified by the READ CONFIG
FILE NAME parameter below.
Function writes configuration information to the file specified by the WRITE CONFIG
FILE NAME parameter below.
The file name for the READ CONFIGURATION function above. The file extension is
.cfg.
The file name for the WRITE CONFIGURATION function above. The file extension is
.cfg.
Table 4. GPIO PINS Menu
Name
CONFIG GPIO
GPIO CONFIG SELECT
GPOx MODE, GPIOx MODE
(9 fields total)
Description
Function writes GPIO configuration from the fields below to MAX24288 register
GPIOCR1 or GPIOCR2 for the pin(s) specified by GPIO CONFIG SELECT below.
Specifies one or all of {GPO1, GPO2, GPIO1-7} to be configured by the CONFIG
GPIO function above.
Specify high-impedance, low, high, and several other options. Other options are pindependent and include:
INT = interrupt output
EXT CLK = Output the PTP_CLKO signal from the time engine
REFCLK PLL 125 MHZ = Output 125MHz from the reference clock PLL
RX 125/25 MHZ = Output clock from receive clock recovery PLL; the frequency is
specified by GPIO RX PLL CLK MODE in the DATA PATH menu.
RX 125/25 MHZ SQUELCH = same as RX 125/25 MHZ above and the output clock
9
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Name
Description
signal is squelched when certain receiver conditions occur such as LOS or ALOS
LOS or ALOS = Output real-time link status, 1= link up
CRS = Output carrier sense status
PEG1 = Output signal generated by Programmable Event Generator 1
PEG2 = Output signal generated by Programmable Event Generator 2
See Table 6-4 through Table 6-6 in the MAX24288 data sheet.
Note that GPIO4 through GPIO7 are the TXD4 through TXD7 pins, which are not
available when the parallel MII interface is configured as GMII.
Table 5. DATA PATH Menu
Name
CONFIG DATA PATH
DEVICE DATA PATH MODE
LOOPBACK MODE
SERIAL TCLK PIN MODE
GPIO RX PLL CLK MODE
TXCLK PIN 125MHZ
CONFIG DIAG PATTERN
DIAGNOSTIC PATTERN MODE
CUSTOM 10-BIT PATTERN
CONFIG AUTO-NEGOTIATE
AUTO-NEGOTIATE MODE
AUTO-NEGOTIATE ADVERT
Description
Function writes configuration from fields LOOPBACK MODE through TXCLK PIN
125MHZ below to MAX24288 registers.
Specifies the combination of serial interface type, parallel interface type and interface
speeds. Examples include (1) GMII ⇔SGMII (1000Mbps) and (2) RGMII10 ⇔SGMII
(10Mbps).
Affects MAX24288 register fields PCSCR.BASEX, GMIICR.SPD, GMIICR.DTE_DCE,
and GMIICR.DDR.
Controls loopback modes. See the block diagram in the MAX24288 data sheet for
loopback locations.
Affects register fields BMCR.DLB, PCSCR.TLB, GMIICR.RLB, CR.DLBDO,
CR.RLBDO, CR.TLBDO.
Enables/disables the TCLKP/N differential pair.
Affects register field CR.TCLK_EN.
Specifies the frequency, 25MHz or 125MHz, of the receive recovered clock that can
be output on GPIO pins. Also specifies whether this clock is squelched when any of
several conditions occur, such as Rx loss of signal.
Affects register fields CR.RCFREQ and CR.RCSQL.
In GMII and RGMII modes, the TXCLK pin is not used for parallel interface operation.
The TXCLK_EN bit enables TXCLK to output a 125MHz clock from the TX PLL in
those modes. TXCLK_EN is ignored in MII mode.
Affects register field GMIICR.TXCLK_EN.
Function writes configuration from fields DIAGNOSTIC PATTERN MODE and
CUSTOM 10-BIT PATTERN to MAX24288 registers.
Specifies a diagnostic pattern transmit, typically for jitter testing.
Affects register fields JIT_DIAG.JIT_EN, JIT_DIAG.JIT_PAT.
Specifies a custom 10-bit diagnostic pattern.
Affects register field JIT_DIAG.CUST_PAT.
Function writes configuration from AUTO-NEGOTIATE MODE and AUTONEGOTIATE ADVERT to MAX24288 registers.
Enables/disables MAX24288 auto-negotiation.
Affects register fields BMCR.AN_EN and AN_START.
Specifies the auto-negotiation tx_Config_Reg[15:0] value for the MAX24288.
Affects register field AN_ADV.
Table 6. 1588 TIME ENGINE Menu
Name
SET TIME
TIME SEC
TIME NS
SET FREQ OFFSET
FREQ OFFSET +/- PPT
DO TIME BUILD OUT
Description
Function writes time from TIME SEC and TIME NS below to the MAX24288 time
engine.
Specifies the seconds portion of the time for the SET TIME function above.
Affects the MAX24288 TIME register field.
Specifies the nanoseconds portion of the time for the SET TIME function above.
Affects the MAX24288 TIME register field.
Function adjusts the MAX24288 PERIOD register from its nominal value of 8.0ns by
the amount specified in the FREQ OFFSET field below.
Specifies a time engine frequency offset in parts per trillion (PPT).
Affects the MAX24288 PERIOD register field.
Function adjusts MAX24288 time engine time smoothly. Time is advanced by the
amount specified by TBO ADJUSTMENT (below) over a duration specified by TBO
DURATION (below). For example, if TBO ADJUSTMENT is 100ns and TBO
DURATION is 1s then DO TIME BUILD OUT advances time in the MAX24288 time
engine by an extra 100ns, but it does this extra advance at a rate of
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________________________________________________________________________________ MAX24288 EV KIT
Name
TBO DURATION +/- NS
TBO ADJUSTMENT +/- NS
CONFIG EXT CLK & PTP_CLKO
EXT CLK SOURCE
EXT CLK ENABLE
EXT CLK DIVIDE
EXT CLK LIMIT
EXT CLK PER NS (16-255)
PTP_CLKO DIVIDE (0=NO DIV)
PTP_CLKO INVERT
Description
100ns/1s=0.1ppm.
DO TIME BUILD OUT makes one-time or repeated used of the precise time
adjustment feature described in section 6.13.1.3 of the MAX24288 data sheet.
Affects register fields PER_ADJ and ADJ_CNT.
Specifies the total time duration during which the time is adjusted by the DO TIME
BUILD OUT function above.
Specifies the total time adjustment desired for the DO TIME BUILD OUT function
above.
Function configures the MAX24288 external clock and PTP_CLKO output clock
features using the settings of the EXT CLK SOURCE through PTP_CLKO INVERT
fields below. See MAX24288 data sheet section 6.13.1.4 for more information about
the external clock syntonization feature. See MAX24288 data sheet section 6.13.2 for
more information about the PTP_CLKO output clock.
Specifies the input signal pin for the MAX24288 external clock syntonization feature.
Affects register field PTPCR3.EXT_SRC.
Enable/disable control for the MAX24288 external clock syntonization feature.
Affects register field PTPCR3.EXT_CLK_ENA.
Specifies the external clock divider value.
Affects register field PTPCR3.EXT_DIV.
Specifies the maximum number of nanoseconds to adjust the time engine accumulator
period from the nominal value set by the MAX24288 PERIOD register.
Affects register field PTPCR3.EXT_LIM.
Specifies the period of the external clock after being divided by the EXT CLK DIVIDE
value.
Affects register field PTPCR3.EXT_PER.
Specifies the divide value for the PTP_CLKO signal. PTP_CLKO frequency is 125MHz
divided by this value.
Affects register field PTPCR2.CLKO_DIV.
Invert/non-invert control.
Affects register field PTPCR2.CLKO_INV.
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Table 7. 1588 EVENT GENERATORS Menu
Name
CONFIG PEG
PEG CONFIG SELECT
PEG1 MODE
PEG1 OFFSET NS
PEG2 MODE
PEG2 OFFSET NS
PEG1 COMMANDS
PEG2 COMMANDS
Description
Function configures the MAX24288 programmable event generator(s) (PEGs) using
settings from the fields below and the PEG1 COMMMANDS and PEG2 COMMANDS
submenus.
Specifies one or both of the PEGs to be configured by the CONFIG PEG function
above.
Allows the user to specify that PEG1 generate one of several common clock
frequencies from 0.5Hz through 31.25MHz. If the CUSTOM option is selected then the
user can specify a custom PEG command script in the PEG1 COMMANDS submenu.
When PEG1 MODE≠CUSTOM then this field specifies an offset from the one-second
boundary for the first edge generated by the PEG. If PEG1 OFFSET=0 then PEG1 is
configured to generate the first output signal edge when the time engine’s nanosecond
field equals 0. If, for example, PEG1 OFFSET=-10 then PEG1 is configured to
generate the first output signal edge when the time engine’s nanoseconds field equals
999,999,990 (i.e. 10ns before the nanoseconds field rolls over to 0).
Same as PEG1 MODE above but for PEG2.
Same as PEG1 OFFSET above but for PEG2.
Opens the PEG1 COMMANDS Menu where a custom PEG1 command script can be
entered. See Table 8.
Same as PEG1 COMMANDS above but for PEG2.
Table 8. PEG1/PEG2 COMMANDS Submenu
Name
CMD RESOLUTION
CMD WORD LENGTH
CMD WORD 0 –
CMD WORD 15
Description
Specifies 1ns or 1/256ns resolution for the 16-bit and 32-bit relative time commands
written to the PEG command FIFO.
Affects register field PEGCR.P1RES for PEG1 and PEGCR.P2RES for PEG2.
Specifies the number of words of CMD WOR 0 through CMD WORD 15 below that the
software should write to the PEG command FIFO. CMD WORD LENGTH=1 indicates
that only CMD WORD 0 should be written. CMD WORD LENGTH=4 indicates that
CMD WORD 0 through CMD WORD 3 should be written.
Specifies up to 16 entries to be written to the PEG command FIFO. The CMD WORD
LENGTH field above specifies the number of entries that are written to the PEG
command FIFO.
Table 9. 1588 TIMESTAMPERS Menu
Name
CONFIG TS
TS CONFIG SELECT
TS1 SOURCE
TS1 EDGE
TS1 OFFSET NS
TS1 DIVIDER 1
TS1 DIVIDER 2
TS2 SOURCE
TS2 EDGE
Description
Function configures the MAX24288 timestampers using settings from the fields below
and the PACKET TS FIFO ENABLES submenu.
Specifies one or all of the timestampers to be configured by the CONFIG TS function
above. The “with PTP HDR” options tell the software that PTP packets (rather than
input signal edges) are being timestamped by TS2 or TS3. Therefore, when software
reads each timestamp it should also read the HDR_DAT1 and HDR_DAT2 registers to
get packet ID information.
Specifies the source of the signal to be timestamped by timestamper 1.
Affects register field TSCR.TS1SRC_SEL.
Specifies whether positive edges, negative edges or both should be timestamped by
timestamper 1.
Affects register field TSCR.TS1EDGE.
Specifies an offset in nanoseconds that software adds to each timestamp generated
by the MAX24288. This field allows software to correct for cable delays, signal skews,
etc.
Specifies the timestamper 1 divider 1 setting. One or both of the TS1 dividers can be
used to divide down the frequency of the input signal that goes to timestamper 1 in
order to reduce the number of edges that must be timestamped. The input signal
frequency is divided by value entered + 1.
Affects register field TS1_DIV1.
Specifies the timestamper 1 divider 2 setting.
Affects register field TSCR.TS2SRC_SEL.
Specifies the source of the signal to be timestamped by timestamper 2.
Affects register field TSCR.TS2SRC_SEL.
Specifies whether positive edges, negative edges or both should be timestamped by
12
________________________________________________________________________________ MAX24288 EV KIT
Name
TS2 OFFSET NS
TS3 SOURCE
TS3 EDGE
TS3 OFFSET NS
TS3 GATED BY TS1
PACKET TS FIFO ENABLES
Description
timestamper 2.
Affects register field TSCR.TS2EDGE.
Same as TS1 OFFSET NS above but for timestamper 2.
Specifies the source of the signal to be timestamped by timestamper 3.
Affects register field TSCR.TS3SRC_SEL.
Specifies whether positive edges, negative edges or both should be timestamped by
timestamper 3.
Affects register field TSCR.TS3EDGE.
Same as TS1 OFFSET NS above but for timestamper 3.
See section 6.13.8 of the MAX24288 data sheet.
Affects register field PTPCR1.TS3_FIFO.
Opens the PACKET TS FIFO ENABLES Menu. This menu has enable/disable fields
that specify, for each PTP message type, whether timestamps are written to the
timestamp FIFO. See Table 10.
Table 10. PACKET TS FIFO ENABLES Submenu
Name
TS2 EGRESS MSG0 (SYNC)
TS2 EGRESS MSG1 (DLY REQ)
TS2 EGRESS MSG2 (PDLY REQ)
TS2 EGRESS MSG3 (PDLY RSP)
TS2 EGRESS MSG4 ENABLE –
TS2 EGRESS MSG7 ENABLE
TS3 INGRESS MSG0 (SYNC)
TS3 INGRESS MSG1 (DLY REQ)
TS3 INGRESS MSG2 (PDLY REQ)
TS3 INGRESS MSG3 (PDLY RSP)
TS3 INGRESS MSG4 ENABLE –
TS2 INGRESS MSG7 ENABLE
Description
Controls whether timestamps for egress PTP Sync messages are written to the TS2
timestamp FIFO.
Affects register field TS_FIFO_EN.EM0_EN.
Same as above but for egress PTP Delay_Req messages.
Affects register field TS_FIFO_EN.EM1_EN.
Same as above but for egress PTP Pdelay_Req messages.
Affects register field TS_FIFO_EN.EM2_EN.
Same as above but for egress PTP Pdelay_Resp messages.
Affects register field TS_FIFO_EN.EM3_EN.
Same as above but for egress PTP message types 4 through 7, which are currently
not defined for PTPv2.
Affects register field TS_FIFO_EN.EM4_EN through EM7_EN.
Controls whether timestamps for ingress PTP SYNC messages are written to the TS2
timestamp FIFO.
Affects register field TS_FIFO_EN.IM0_EN.
Same as above but for ingress PTP Delay_Req messages.
Affects register field TS_FIFO_EN.IM1_EN.
Same as above but for ingress PTP Pdelay_Req messages.
Affects register field TS_FIFO_EN.IM2_EN.
Same as above but for ingress PTP Pdelay_Resp messages.
Affects register field TS_FIFO_EN.IM3_EN.
Same as above but for ingress PTP message types 4 through 7, which are currently
not defined for PTPv2.
Affects register field TS_FIFO_EN.IM4_EN through IM7_EN.
Table 11. 1588 PACKET CLASSIFIERS Menu
Name
CONFIG PACKET CLASSIFIER
ENET PTP HW CLASS ENABLE
ENET CFG HW CLASS ENABLE
ENET CFG ETYPE
IPV4 UDP HW CLASS ENABLE
IPV6 UDP HW CLASS ENABLE
Description
Function configures the MAX24288 packet classifiers using settings from the fields
below and the UID CHECK and CPC CLASSIFIER submenus.
Controls whether the hardwired packet classifier looks for PTP messages in Ethernet
frames with Ethertype=0x88F7.
Affects register field PKT_CLASS.ENET.
Controls whether the hardwired packet classifier looks for PTP messages in Ethernet
frames with Ethertype=ENET CFG ETYPE below.
Affects register field PKT_CLASS.ENET_CFG.
Specifies the alternate Ethertype used by the hardwired packet classifier when ENET
CFG HW CLASS ENABLE is set to ON.
Affects register field ETYPE_ALT.
Controls whether the hardwired packet classifier looks for PTP messages in IPv4/UDP
packets.
Affects register field PKT_CLASS.UDP_IPv4.
Controls whether the hardwired packet classifier looks for PTP messages in IPv6/UDP
packets.
Affects register field PKT_CLASS.UDP_IPv6.
13
________________________________________________________________________________ MAX24288 EV KIT
Name
UDP SRC PORT
UDP DST PORT
MPLS UCAST HW CLASS
ENABLE
MPLS MCAST HW CLASS
ENABLE
MPLS HW LABEL (20 BIT)
MEF CFG HW CLASS ENABLE
MEF CFG HW ECID (20 BIT)
VLAN2 ID
PTP VERSION (0-7)
PTP VERSION CHECK MODE
UID CHECK
CPC CLASSIFIER
Description
IP/UDP packets must have a UDP source port number that matches this field to be
qualified. A value of 0xFFFF disables UDP source port matching.
Affects register field UDP_SRC.
IP/UDP packets must have a UDP destination port number that matches this field to
be qualified. A value of 0xFFFF disables UDP destination port matching.
Affects register field UDP_DST.
Controls whether the hardwired packet classifier looks for PTP messages in MPLS
unicast packets.
Affects register field PKT_CLASS.MPLS_UCAST.
Controls whether the hardwired packet classifier looks for PTP messages in MPLS
multicast packets.
Affects register field PKT_CLASS.MPLS_MCAST.
MPLS packets must have an inner label that matches this field to be qualified.
Affects register fields MPLS_LABEL_HI and MPLS_LABEL_LO.
Controls whether the hardwired packet classifier looks for PTP messages in MEF
pseudowire packets.
Affects register field PKT_CLASS.MEF_CFG.
MEF pseudowires must have an ECID that matches this field to be qualified.
Affects register fields MEF_ECID_HI and MEF_ECID_LO.
Specifies an alternate (optional) Ethertype for VLAN headers. Should be set to 0x8100
to not specify an alternate Ethertype.
Affects register fields VLAN2_ID.
Packets must have versionPTP field “match” this field to be qualified. The definition of
“match” is specified by PTP VERSION CHECK MODE below.
Affects register fields PKT_CLASS.PTP_VERSION.
Specifies how a packet’s versionPTP field is compared to the PTP VERSION field
above. Two options are available: (1) version must be less than or equal to PTP
VERSION, or (2) version must exactly match.
Affects register fields PKT_CLASS.VER_EXACT.
Opens the UID CHECK Menu. See Table 12.
Opens the CPC CLASSIFIER Menu. See Table 13.
Table 12. UID CHECK Menu
Name
CONFIG PACKET CLASSIFIER
UID CHECK ENABLE
UID IDENTITY CODE (12 BITS)
COMPUTE UID
CLOCK ID (16 HEX DIGITS)
CLOCK ID (8 CHARS)
PORT NUMBER
Description
Same function as in Table 11 above.
Enables/disables UID checking for ingress PTP messages. Each PTP package has a
10 byte field in the header called the sourcePortIdentity field. This field consists of an
eight byte clockIdentity and a two byte portNumber. When UID checking is enabled
the MAX24288 calculates a 12-bit code from the sourcePortIdentity field of each
ingress packet and compares it to a stored 12-bit code (the UID IDENTITY CODE
below). The 12-bit code must match for the message timestamp to be stored in the
TS3 FIFO. See section 6.13.6.4 of the MAX24288 data sheet for details.
Affects register field UID_CHK.CHK_EN.
Specifies the stored 12-bit code mentioned above. This field is automatically updated
when the COMPUTE UID function is selected below.
Affects register field UID_CHK.UID.
Function calculates the 12-bit UID IDENTITY CODE above from the CLOCK ID and
PORT NUMBER fields below.
One of two ways to specify the sourcePortIdentity.clockIdentity field from which the
UID IDENTITY CODE above is computed. When 16 hexadecimal digits are entered,
the equivalent ASCII string is calculated and displayed in the CLOCK ID (8 CHARS)
field below.
The second of two ways to specify the sourcePortIdentity.clockIdentity field. When a
string is entered, the hex equivalent is calculated and displayed in the CLOCK ID (16
HEX DIGITS) field above.
Specifies the sourcePortIdentity.portNumber field from which the UID IDENTITY
CODE above is computed.
Table 13. CPC CLASSIFIER Menu
Name
CONFIG PACKET CLASSIFIER
Description
Same function as in Table 11 above.
14
________________________________________________________________________________ MAX24288 EV KIT
Name
CPC MODE
CPC START POSITION
CPC PTP HEADER OFFSET
CPC #0 OFFSET
CPC #0 MASK
CPC #0 MATCH
CPC #1 OFFSET
CPC #1 MASK
CPC #1 MATCH
CPC #2 OFFSET
CPC #2 MASK
CPC #2 MATCH
CPC #3 OFFSET
CPC #3 MASK
CPC #3 MATCH
CPC 4-7
Description
Specifies AND mode or OR mode. In AND mode the hardwired packet classifier (HPC)
and the configurable packet classifier (CPC) must both match to qualify the packet. In
OR mode either the HPC or the CPC must match.
Affects register fields PKT_CLASS.CFG_OR and PTPCR1.TOP_MODE.
Specifies the position in the packet from which CPC offsets (below) are calculated.
Affects register field PKT_CLASS.CFG_START.
When CPC MODE is set to OR this field must be set to specify the offset from the
CPC START POSITION (above) to the start of the PTP message header.
Affects register CFG_OFFSET through which the indirect register PTP_OFFSET is
written.
See section 6.13.6.2 in the MAX24288 data sheet for details. The CPC has eight bitmaskable 16-bit matching criteria, any or all of which can be used to set up packet
qualification criteria. This field specifies the offset from the CPC START POSITION
(above) to the comparison point for comparison #0.
Affects register CFG_OFFSET.
Specifies which bits should be compared for comparison #0.
Affects register CFG_MASK.
Specifies the required values of the bits to be compared for comparison #0.
Affects register CFG_MATCH.
Same as CPC #0 OFFSET above but for CPC #1.
Same as CPC #0 MASK above but for CPC #1.
Same as CPC #0 MATCH above but for CPC #1.
Same as CPC #0 OFFSET above but for CPC #2.
Same as CPC #0 MASK above but for CPC #2.
Same as CPC #0 MATCH above but for CPC #2.
Same as CPC #0 OFFSET above but for CPC #3.
Same as CPC #0 MASK above but for CPC #3.
Same as CPC #0 MATCH above but for CPC #3.
Opens the CPC CLASSIFIER 4-7 menu, which is exactly the same as the CPC
CLASSIFIER 0-3 menu but corresponds to CPC classifiers 4-7.
15
________________________________________________________________________________ MAX24288 EV KIT
Table 14. 1588 ON-THE-FLY INSERTION Menu
Name
CONFIG ON-THE-FLY
TRANSPARENT CLOCK MODE
ORDINARY CLOCK MODE
PDELAY_REQ/RESP MODE
TDMOP MODE
Description
Function configures the MAX24288 on-the-fly packet modifier logic using settings from
the fields below and the ON-THE-FLY CORRECTION and TIMSTAMP INSERTION
submenus.
MANUAL: User configures all transparent clock on-the-fly behavior using other
settings in the 1588 ON-THE-FLY menu and submenus.
END TO END: Sets up typical E2E TC configuration:
Sets TS_INSERT_EN.TC_CF_EN to enable one-step TC residence time
correction for Sync and Delay_Req messages.
Writes software TC ASYMM CORRECTION value to CF_COR1 register.
Sets CF_INGRESS.IM0_CF to add CF_COR1 to correctionField of ingress
Sync messages.
Sets CF_EGRESS.EM1_CF to subtract CF_COR1 from correctionField of
egress Delay_Req messages.
END TO END + PDELAY CORR: Same configuration as END TO END above plus:
Sets TS_INSERT_EN.TC_CF_PD to enable one-step TC residence time
correction for Pdelay_Req and Pdelay_Resp messages.
Sets CF_EGRESS.EM2_CF to subtract CF_COR1 from correctionField of
egress Pdelay_Req messages.
Sets CF_INGRESS.IM3_CF to add CF_COR1 to correctionField of ingress
Pdelay_Resp messages.
PEER TO PEER: Sets up typical P2P TC configuration:
Sets TS_INSERT_EN.TC_CF_EN to enable one-step TC residence time
correction for Sync messages.
Sets CF_INGRESS.IM0_CF to add CF_COR1 to correctionField of ingress
Sync messages.
MANUAL: User configures all ordinary clock on-the-fly behavior using other settings in
the 1588 ON-THE-FLY menu and submenus.
1 STEP MASTER: Sets up typical configuration for OC master port with one-step
operation (i.e. no PTP Follow_Up messages).
Sets TS_INSERT_EN.EM0_EN to enable TS insertion into egress Sync
messages.
Sets TS_INSERT_EN.IM1_EN to enable TS insertion into ingress Delay_Req
messages.
1 STEP SLAVE: Sets up typical configuration for OC slave port with one-step
operation (i.e. no PTP Follow_Up messages).
Sets TS_INSERT_EN.IM0_EN to enable TS insertion into ingress Sync
messages.
1 STEP SLAVE + MICROSEMI TS INS: Same as 1 STEP SLAVE but also enables
Microsemi’s method for timestamp insertion into egress Delay_Req messages as
described in MAX24288 data sheet section 6.13.7.3.
Sets TS_INSERT_EN.IM0_EN to enable TS insertion into ingress Sync
messages.
Sets TS_INSERT_EN.EM1_EN to enable TS insertion into egress Delay_Req
messages.
MANUAL: User configures all Peer-to-Peer (P2P) behavior using other settings in the
1588 ON-THE-FLY menu and submenus.
1 STEP: Sets up typical P2P configuration for one-step operation (i.e. no PTP
Pdelay_Resp_Follow_Up messages).
Sets TS_INSERT_EN.IM3_EN to enable TS insertion into ingress Pdelay_Resp
messages.
Sets TS_INSERT_EN.EM3_EN to enable TS insertion into egress
Pdelay_Resp messages.
1 STEP + MICROSEMI TS INS: Same as 1 STEP but also enables Microsemi’s
method for timestamp insertion into egress Pdelay_Req messages as described
in MAX24288 data sheet section 6.13.7.3.
Sets TS_INSERT_EN.IM3_EN to enable TS insertion into ingress Pdelay_Resp
messages.
Sets TS_INSERT_EN.EM3_EN to enable TS insertion into egress
Pdelay_Resp messages.
Sets TS_INSERT_EN.EM2_EN to enable TS insertion into egress Pdelay_Req
messages.
Enables a special mode in the MAX24288 to support timestamping circuit emulation
16
________________________________________________________________________________ MAX24288 EV KIT
Name
CLR TS ON EGRESS
SEC TS INSERT
SEC TS OFFSET (BYTES)
NS TS INSERT
NS TS OFFSET (BYTES)
TC ASYMM CORRECTION (NS)
TC MEAN PATH DELAY (NS)
ON-THE-FLY CORRECTION
TIMESTAMP INSERTION
Description
packets rather than PTP packets. See the MAX24288 data sheet, section 6.13.8.
Affects register PTPCR1.TOP_MODE.
ON = the MAX24288 should clear the bytes specified by the SEC TS OFFSET and NS
TS OFFSET fields below in egress messages.
Affects register TS_INSERT_EN.CLR_TS_INS.
When this field is set to a value other than DISABLED the MAX24288 writes 1, 4 or 6
bytes of seconds information from the ingress timestamp into ingress PTP messages
at the offset specified by the SEC TS OFFSET field. Only the PTP message types
specified in the fields in Table 18 are affected by the timestamp insertion circuitry.
Affects register TS_INSERT.SEC_ENA.
Specifies the byte offset from the start of the PTP message header to the first byte that
should be written with timestamp seconds information. Ignored when SEC TS INSERT
= DISABLED.
Affects register TS_INSERT.SEC_OFF.
When this field is ENABLED the MAX24288 writes all four bytes of nanoseconds
information from the ingress timestamp into ingress PTP messages at the offset
specified by the NSEC TS OFFSET field. Only the PTP message types specified in the
fields in Table 18 are affected by the timestamp insertion circuitry.
Affects register TS_INSERT.NSEC_ENA.
Specifies the byte offset from the start of the PTP message header to the first byte that
should be written with timestamp nanoseconds information. Ignored when NSEC TS
INSERT = DISABLED.
Affects register TS_INSERT.NSEC_OFF.
Specifies an asymmetry correction value to be written to the MAX24288.
Affects register CF_COR1.
Specifies a P2P TC mean path delay value to be written to the MAX24288. In a peerto-peer transparent clock, the system transmits Pdelay_Req messages to its
neighbors, receives Pdelay_Resp messages, and then calculates meanPathDelay as
specified in section 11.4.3 of IEEE1588-2008. This meanPathDelay is then added to
the correctionField of Sync messages passing through the system. The MAX24288
can add this meanPathDelay value to ingress Sync messages on-the-fly.
Affects register MEAN_PATH_DELAY.
Opens the ON-THE-FLY CORRECTION menu. See Table 17.
Opens the TIMESTAMP INSERTION menu. See Table 18.
17
________________________________________________________________________________ MAX24288 EV KIT
Table 15. ON-THE-FLY CORRECTION Menu
Name
CONFIG ON-THE-FLY
CORRECTION REG 1 (NS)
CORRECTION REG 2 (NS)
CORRECTION REG 3 (NS)
INGRESS SYNC CORRECTION
INGRESS DELAY_REQ CORR
INGRESS PDELAY_REQ CORR
INGRESS PDELAY_RESP CORR
INGRESS MSG 4 CORRECTION
INGRESS MSG 5 CORRECTION
INGRESS MSG 6 CORRECTION
INGRESS MSG 7 CORRECTION
EGRESS SYNC CORRECTION
EGRESS DELAY_REQ CORR
EGRESS PDELAY_REQ CORR
EGRESS PDELAY_RESP CORR
EGRESS MSG 4 CORRECTION
EGRESS MSG 5 CORRECTION
EGRESS MSG 6 CORRECTION
EGRESS MSG 7 CORRECTION
Description
Same function as in Table 14 above.
One of three correction registers that can be added to the correctionField of ingress
messages and subtracted from the correctionField of egress messages as specified
by the fields below.
Affects register CF_COR1.
The second of three correction registers. See CORRECTION REG 1 above.
Affects register CF_COR2.
The third of three correction registers. See CORRECTION REG 1 above.
Affects register CF_COR3.
These fields enable on-the-fly correctionField adjustment for ingress type 0 (Sync)
through type 7 PTP messages and specify which CORRECTION REG above to add to
the correctionField.
Affects register fields CF_INGRESS.IM0_CF through IM7_CF.
These fields enable on-the-fly correctionField adjustment for egress type 0 (Sync)
through type 7 PTP messages and specify which CORRECTION REG above to
subtract from the correctionField.
Affects register fields CF_EGRESS.EM0_CF through EM7_CF.
Table 16. TIMESTAMP INSERTION Menu
Name
CONFIG ON-THE-FLY
INGRESS SYNC ENABLE
INGRESS DELAY_REQ EN
INGRESS PDELAY_REQ EN
INGRESS PDELAY_RESP EN
INGRESS MSG 4 ENABLE
INGRESS MSG 5 ENABLE
INGRESS MSG 6 ENABLE
INGRESS MSG 7 ENABLE
Description
Same function as in Table 14 above.
These fields enable on-the-fly timestamp insertion for ingress type 0 (Sync) through
type 7 PTP messages. The seconds and nanoseconds portions of the ingress
timestamp are written as specified by the SEC TS INSERT, SEC TS OFFSET, NSEC
TS INSERT and NSEC TS OFFSET fields in Table 14.
Affects register fields TS_INSERT-EN.IM0_EN through IM7_EN.
18
________________________________________________________________________________ MAX24288 EV KIT
Table 17. LOCK TO PPS Menu
Name
CONFIG LOCK TO PPS
PLL MODE
Description
Function configures the evaluation software using settings from the fields below to
work with the MAX24288 hardware to form a hardware/software PLL that locks to an
input 1PPS signal. In this PLL, timestamper 1 (TS1) in the MAX24288 timestamps
edges of a 1PPS input signal. The edges of this signal are assumed to occur at the
exact one-second boundary. Therefore ideally the timestamp nanoseconds field
should be 0. The difference between the nanosecond field and zero is the error
information used to control the PLL.
Note 1: TS1 must be configured to timestamp an input 1PPS signal in the 1588
TIMESTAMPERS Menu (Table 9) before executing the CONFIG LOCK TO PPS
function.
Note 2: The evaluation software controls the time and/or frequency of the MAX24288
time engine when PLL MODE below is not OFF. Therefore previous settings of time
engine values may be overwritten by the evaluation software when the LOCK TO PPS
PLL is enabled.
Specifies operating mode of the hardware/software PLL.
Mode
OFF
FREERUN
FREQ MEASURE
FREQ ADJUST
TIME ADJUST
TIME MEASURE
TIME BUILD OUT
LOCK
HOLDOVER
AUTO FREQ LOCK
AUTO TIME LOCK
EVENTS PER SECOND
FREERUN FREQ PPM
FREQ RATE OF CHANGE
PPM/SEC
PLL BANDWIDTH, HZ
PLL DAMPING FACTOR
Description
Disable the PLL
Ignore error information from TS1 and clock the time
engine at the frequency specified by the FREE RUN FREQ
PPM field below.
For debug only. These values force the hardware/software
PLL into a particular operating state.
Ignore error information from TS1 and clock the time
engine at a holdover frequency averaged by the evaluation
software while the PLL was locked to an input signal.
Fully automatic PLL operation with frequency-only locking.
When the PLL is locked its output frequency tracks the
frequency of the input signal, but time is not adjusted.
Therefore the MAX24288 time engine will have a fixed time
offset vs. the source of the input signal.
Fully automatic PLL operation with time-and-frequency
locking. When the PLL is locked the time and frequency of
the MAX24288 time engine track the input signal.
Specifies the number of edges per second in the input signal timestamped by TS1. For
a 1PPS signal this field should be set to 1.
Specifies a frequency offset vs. the frequency accuracy of the REFCLK oscillator for
when PLL MODE above is set to FREERUN.
Specifies the maximum frequency rate of change that the evaluation software can use
when locking to an input signal.
Specifies the bandwidth of the hardware/software PLL in Hz.
Specifies the damping factor of the hardware/software PLL. A typical value is 5. Larger
numbers provide more damping, i.e. less peaking at the PLL corner frequency.
19
________________________________________________________________________________ MAX24288 EV KIT
Table 18. TEST Menu
Name
READ REGISTER
WRITE REGISTER
REGISTER ACCESS MODE
REGISTER ADDRESS HEX
REGISTER ADDRESS DEC
REGISTER DATA HEX
REGISTER DATA DECIMAL
READ SFP MODULE INFO
Description
Function reads the register specified by the REGISTER ADDRESS fields below and
displays the value in the REGISTER DATA fields below.
Functions writes the data value specified in the register data fields below into the
register address specified by the REGISTER ADDRESS fields below.
Specifies the register access mode.
MAX24288 USER MODE: The registers in Table 7-1 of the MAX24288 data sheet are
at addresses 0-31 decimal, and the registers in Table 7-2 of the MAX24288 data
sheet are at 32 (decimal) + SPI address.
MAX24288 MDIO: The MAX24288 registers are addressed using the MDIO addresses
in Tables 7-1 and 7-2 of the MAX24288 data sheet. The page number must be
manually set by writing the PAGESEL register at address 31 decimal. To use this
mode polling must be stopped by entering s on the command line. This prevents
the polling routine from changing the MDIO page in the PAGESEL register.
SW PHY0 (MDIO#8): Accesses the registers of PHY0 on the evaluation board’s switch
chip.
SW PHY1 (MDIO#9): Accesses the registers of PHY1 on the evaluation board’s switch
chip.
SW MAC (MDIO#A): Accesses the MAC registers of the evaluation board’s switch
chip for the port connected to the MAX24288.
SFP CFG (I2C#A0): Accesses the SFP module’s internal EEPROM memory.
SFP PHY (I2C#AC): Accesses the SFP module’s PHY registers.
Specifies the register address in hexadecimal for the READ REGISTER and WRITE
REGISTER functions above. When REGISTER ADDRESS DEC below is changed,
this field is changed to match. The REGISTER ACCESS MODE field above specifies
the register mapping.
Specifies the register address in decimal for the READ REGISTER and WRITE
REGISTER functions above. When REGISTER ADDRESS HEX above is changed,
this field is changed to match.
Indicates the data value in hexadecimal from the last time the READ REGISTER
function was executed or the last time one of the REGISTER DATA fields was change
by the user.
Indicates the data value in decimal from the last time the READ REGISTER function
was executed or the last time one of the REGISTER DATA fields was change by the
user.
Functions reads and displays the data from the evaluation board’s SFP module. To
end the data display and return to the menu, press the ENTER key.
20
________________________________________________________________________________ MAX24288 EV KIT
6. Jumpers, Connectors and LEDs
Table 19. Power and Reset Components
COMPONENT
LABEL AND TYPE
BASIC SETTING
SCHEMATIC
PAGE
J1
5V jack
Connected
4
Power jack for 5V wall adapter
(supplied)
DS1
DS2
DS3
SW1
5.0V_OK LED
3.3V_OK LED
1.2V_OK LED
DUT_RST button
On
4
Lit when power is within range for 5V,
3.3V, and 1.2V, respectively
Unused
5
Manual reset for entire system
DESCRIPTION
Table 20. MAX24288 REFCLK Jumpers and Connectors
Note: MAX24288 is intolerant of REFCLK signal changes during operation. To make REFCLK signal changes, power down the board, change
the jumpers as needed then apply power to the board again.
COMPONENT
LABEL AND TYPE
JP1
Y2OSC / Y3OSC
selection 3-pin header
J3
OSC_OUT
SMB connector
SER_TRM
2-pin header
J4
J10
J25
EXT_REFCLK
SMB connector
50PAR
2-pin header
BASIC SETTING
Jumper
connecting
pins 2 and 3
Not monitored
Not monitored
SCHEMATIC
PAGE
7
7
7
Not monitored
7
Not monitored
7
J14
REFCLK
2x3pin header
Jumper
connecting
pins 5 and 6
7
J19
OSC 3.3V POWER
2x3pin header
All jumpered
7
DESCRIPTION
Drives SMB connector J3 and jumper
J14 pin 1.
Connect the Y3OSC pin to the center
pin to connect the Y3 oscillator output
to J3 and J14.
Connect the Y2OSC pin to the center
pin to connect the Y2 oscillator output
to J2 and J14.
J3 is driven by a buffer sourced by
the center pin of JP1.
Install a jumper on J4 to apply 50
ohm parallel termination to J3
External REFCLK oscillator input.
Signal goes to J14 pin 1.
Jumper J25 to apply 50 ohm
parallel termination to J10.
Connects 25MHz XO clock or Y2/Y3
clock or external clock to MAX24288
REFCLK pin. Frequency must match
the settings of the REF[1:0] jumpers
(see Table 21).
Connect pins 1 and 2 to select the
external clock signal from SMB J10.
Connect pins 3 and 4 to select the Y2
or Y3 clock signal from JP1.
Connect pins 5 and 6 to select the Y1
clock signal.
Connect/disconnect 3.3V power for
oscillator components Y1, Y2 and Y3.
Connect pins 1 and 2 to power Y3
Connect pins 3 and 4 to power Y2
Connect pins 5 and 6 to power Y1
Note: the silkscreen mistakenly has
Y2OSC and Y3OSC labels swapped.
Table 21. MAX24288 Pin Configuration Jumpers
COMPONENT
LABEL AND TYPE
BASIC SETTING
SCHEMATIC
PAGE
JP13
HW_MODE
3-pin header
Jumper in the
15PIN position.
3
DESCRIPTION
MAX24288 COL pin. At reset this pin
specifies 3-pin or 15-pin configuration
mode.
21
________________________________________________________________________________ MAX24288 EV KIT
COMPONENT
JP15
LABEL AND TYPE
TXCLK
3-pin header
BASIC SETTING
Jumper in the
GND position.
SCHEMATIC
PAGE
DESCRIPTION
3
MAX24288 TXCLK pin. At reset the
value on this pin is latched into the
GMIICR.TXCLK_EN bit to configure
TXCLK behavior. 0=high impedance.
1=125MHz from TX PLL. Ignored in MII
mode.
MAX24288 RX_DV pin. At reset the
value on this pin is latched into the
BMCR.AN_EN bit ton configure autonegotiation. 0=auto-negotiation
disabled. 1=enabled.
JP16
AN_EN
3-pin header
Jumper in the
GND position.
3
JP17
DDR
3-pin header
Jumper in the
GND position.
3
JP29
JP30
SPEED[1:0]
3-pin header
JP29: VCC
JP30: GND
3
JP18
GPIO1_TX125
3-pin header
Jumper in the
GND position.
3
JP19
BASEX_DCE
3-pin header
Jumper in the
GND position.
3
JP14
JP23
JP24
JP25
JP26
JP27
JP28
JP12
TP1
TP2
DDR: MAX24288 CRS pin.
SPEED[1:0]: MAX24288 RXD[1:0] pins.
At reset the values on these pins are
latched into the GMIICR.DDR and
SPD[1:0] register bits. These jumpers
together set the parallel interface mode
for the MAX24288. See Table 22 for
encodings. The equivalent interface
configuration must be made on the
Ethernet switch IC MODE and SPEED
jumpers (see Table 27).
MAX24288 GPO1 pin. At reset the
value on this pin is latched into
GPIOCR1.GPIO1_SEL[2] to configure
GPIO1 behavior. 0=high impedance.
1=125MHz from TX PLL.
MAX24288 GPO2 pin. At reset the
value on this pin is latched into
GMIICR.DTE_DCE when SPEED[1:0]
and DDR specify 10/100 MII mode or
into PCSCR.BASEX when SPEED[1:0]
and DDR specify some other mode.
For 10/100 MII, 0=DCE, 1=DTE and the
serial interface is configured for SGMII
mode (PCSCR.BASEX=0).
ADDRESS[4:0]
3-pin headers
JP14: GND
JP23: GND
JP24: VCC
JP25: GND
JP26: GND
3
REF[1:0]
3-pin headers
JP27: VCC
JP28: GND
3
TX_ER
3-pin header
TP1, TP2
Test points
Jumper in the
GND position.
3
Not used
1
For other parallel interface modes,
0=SGMII, 1=BASEX.
MAX24288 RX_ER and RXD[7:4] pins.
At reset the values on these pins are
latched into the internal MDIO PHY
address register. Address 11111
enables factory test mode and should
not be used.
JP14 is RX_ER and ADDRESS[4].
JP23-JP26 are RXD[7:4] and
ADDRESS[3:0].
MAX24288 RXD[3:2] pins. At reset the
values on these pins are latched into
the internal REFCLK frequency
register. 00=10MHz, 01=12.8MHz,
10=25MHz, 11=125MHz.
MAX24288 TX_ERR pin.
Test points for TCLKN (TP1) and
TCLKP (TP2)
22
________________________________________________________________________________ MAX24288 EV KIT
COMPONENT
TXTX+
RX+
RXTP10
LABEL AND TYPE
TX-, TX+, RX+, RX-,
TP10
Test points
BASIC SETTING
SCHEMATIC
PAGE
Not used
NA
DESCRIPTION
Unconnected copper shapes have
been placed next to each trace, and a
section of the trace metal is exposed.
A solder bridge may be used to bridge
the trace to the shape, creating a test
point.
Table 22. MAX24288 Parallel Interface Configuration
SPEED[1] SPEED[0]
Speed
DDR=0
DDR=1
0
0
10Mbps
MII
RGMII-10
0
1
100Mbps
MII
RGMII-100
1
0
1000Mbps
GMII
RGMII-1000
1
1
reserved
Table 23. MAX24288 GPIO1 Jumpers and Connectors
COMPONENT
LABEL AND TYPE
BASIC SETTING
J18
SMB Connector
GPIO1
3-pin header
Not jumpered
SCHEMATIC
PAGE
3
Not jumpered
3
JP5
JP6 and JP9
3-pin headers
Not jumpered
3
J22
2-pin header
Not jumpered
3
J26
2-pin header
Not jumpered
3
DS4
LED
Off
3
DESCRIPTION
I/O connector for GPIO1.
Can be used to bias GPIO1 high or low.
To drive a signal from SMB J18 to
GPIO1, jumper JP6 2-3 and JP9 2-3.
To drive a signal from GPIO1 to SMB
J18, jumper JP6 1-2 and JP9 1-2.
Install J22 to short the 30 ohm series
termination at JP6.2.
Install J26 to apply 50 ohm parallel
termination to JP9.2
Lit when GPIO1 is high.
Table 24. MAX24288 GPIO2 Jumpers and Connectors
COMPONENT
LABEL AND TYPE
BASIC SETTING
J16
SMB Connector
GPIO1
3-pin header
Not jumpered
SCHEMATIC
PAGE
3
Not jumpered
3
JP4
JP7 and JP10
3-pin headers
Not jumpered
3
J23
2-pin header
Not jumpered
3
J27
2-pin header
Not jumpered
3
DESCRIPTION
I/O connector for GPIO2.
Can be used to bias GPIO2 high or low.
To drive a signal from SMB J16 to
GPIO2, jumper JP7 2-3 and JP10 2-3.
To drive a signal from GPIO1 to SMB
J16, jumper JP7 1-2 and JP10 1-2.
Install J23 to short the 30 ohm series
termination at JP7.2.
Install J27 to apply 50 ohm parallel
termination to JP10.2
Table 25. MAX24288 GPIO3 Jumpers and Connectors
COMPONENT
LABEL AND TYPE
BASIC SETTING
J17
SMB Connector
GPIO1
3-pin header
Not jumpered
SCHEMATIC
PAGE
3
Not jumpered
3
JP3
JP8 and JP11
3-pin headers
Not jumpered
3
J24
2-pin header
Not jumpered
3
J28
2-pin header
Not jumpered
3
DESCRIPTION
I/O connector for GPIO3.
Can be used to bias GPIO3 high or low.
To drive a signal from SMB J17 to
GPIO3, jumper JP8 2-3 and JP11 2-3.
To drive a signal from GPIO1 to SMB
J17, jumper JP8 1-2 and JP11 1-2.
Install J24 to short the 30 ohm series
termination at JP8.2.
Install J28 to apply 50 ohm parallel
termination to JP11.2
23
________________________________________________________________________________ MAX24288 EV KIT
Table 26. Processor and Debug Jumpers and Connectors
COMPONENT
LABEL AND TYPE
BASIC SETTING
SCHEMATIC
PAGE
J2 (USB)
USB jack
Connected
8
USB connector, attach to PC with
supplied cable
J5
PROCESSOR DEBUG
2x3pin header
Not Connected
8
BDM connector for use with debug pod
J9
COM_BCLK
2x3pin header
J12
J13
J15
Not jumpered
5
2x5pin header
Jumpered 3-4,
5-6, 7-8, 9-10
5
2x5pin header
Jumpered 1-2,
3-4, 5-6, 7-8
5
Not used
5
2x7 header
J21
2x5 header
Not used
5
J11
2-pin header
Not used
5
J34
2x5pin header
Jumpered 9-10
5
JB1
2x5 header
(just below the
company logo)
Not jumpered
8
DESCRIPTION
Used to make a common
communication clock. Jumper options
allow to short MDC, I2C_CLK and SPI
clock.
Connection points for processor pins to
SFP I2C and MAX24288 MDIO.
Disconnect if connecting an external
processor.
Connection points for processor pins to
MAX24288 SPI. Disconnect if
connecting an external processor.
Connection for external processor
board
SPI bus connection to external board
such as Microsemi’s DS31400DK.
Place a jumper to connect 5V to J15
pin 2.
MAX24288 JTAG header. When not in
JTAG mode the JTRST pin should be
driven low by connecting pins 9 and 10.
Connects to several GPIO on the
processor to provide for future board
application options.
Table 27. Ethernet Switch Jumpers, Connectors and LEDs
COMPONENT
JP2
J7
J8
JP20
JP21
LABEL AND TYPE
SWITCH OSC
3-pin header
BASIC SETTING
Jumper in the
25MHZ position.
SCHEMATIC
PAGE
7
EXT_SOSC
SMB connector
Not Driven
7
50PAR
2-pin header
Not jumpered
7
SPEED[1:0]
3-pin headers
JP20: GND
JP21: VCC
11
DESCRIPTION
Selects clock signal applied to the
RTL8363 switch XTAL1 pin.
Connect center pin to 25MHZ pin to
select the clock signal from Y1.
Connect center pin to EXT_SOSC to
select the clock signal from SMB J7.
External clock for Ethernet switch
IC. JP2 must have jumper in the
EXT_SOSC position to use this
signal.
Install jumper to apply 50 ohm
parallel termination to the signal on
J7.
Switch IC P2SPD[1:0] pins. Selects
speed of MII interface to MAX24288.
The equivalent interface configuration
must be made on the MAX24288
SPEED jumpers (see Table 21).
00: 10M
01: 100M
10: 1000M
24
________________________________________________________________________________ MAX24288 EV KIT
COMPONENT
LABEL AND TYPE
BASIC SETTING
SCHEMATIC
PAGE
DESCRIPTION
Switch IC P2IF[2:0] pins. Selects mode
of MII interface to MAX24288. The
equivalent interface configuration must
be made on the MAX24288 DDR and
BASEX_DCE jumpers (see Table 21).
000: GMII/PHY MODE MII
001: GMII/MAC MODE MII
010: RGMII
011: RMII (do not use, not compatible
with MAX24288)
Switch IC RXDLY pin, adds delay to RX
CLK between MAX24288 and switch
IC.
Jumper to VCC to add 1.5nsec delay
Jumper to GND to add 0 delay
Switch IC TXDLY pin, adds delay to TX
CLK between MAX24288 and switch
IC.
Jumper to VCC to add 1.5nsec delay
Jumper to GND to add 0 delay
JP22
JP33
JP32
MODE[2:0]
3-pin headers
JP22: GND
JP33: GND
JP32: GND
11
JP31
RXDLY
3-pin header
Jumper in the
VCC position.
11
Jumper in the
VCC position.
11
Not Connected
10
Interface to Port 1 of Ethernet Switch IC
Connected
10
Interface to Port 0 of Ethernet Switch IC
JP34
J29
J31
DS14
DS13
DS12
DS11
DS8
DS7
DS6
DS5
TXDLY
3-pin header
PORT1
RJ-45 jack
PORT0
RJ-45 jack
DUP / COL
LED
10_LINK/ACT
LED
100_LINK/ACT
LED
GIG_LIN/ACT
LED
DUP / COL
LED
10_LINK/ACT
LED
100_LINK/ACT
LED
GIG_LIN/ACT
LED
---------
10
10
10
Port 1 status LEDs, indicate link status
and speed.
10
10
10
10
Port 0 status LEDs, indicate link status
and speed.
10
Table 28. SFP Module Jumpers and LEDs
COMPONENT
LABEL AND TYPE
BASIC SETTING
SCHEMATIC
PAGE
J30
2x5pin header
Jumpered 8-6
Jumpered 4-3
6
DS9
TX_FAULT LED
--
6
DS10
LOS LED
--
6
DESCRIPTION
SFP test points and bias points
Default option 8-6 enables TX.
Default option 4-3 connects SFP_LOS
signal to MAX24288 ALOS pin.
Indicates SFP module transmit fault
signal is active.
Indicates SFP module LOS signal is
active.
25
________________________________________________________________________________ MAX24288 EV KIT
7. Component List
DESIGNATION
Reference designators shown on next
row (C1, …, CB143)
QTY
81
DESCRIPTION
0402 CERAM 1uF 10V
SUPPLIER
TDK
PART
C1005X5R1A105M
C1, C2, C12, C13, C14, C22, C27, CB8, CB10, CB13, CB14, CB21, CB23, CB25, CB28, CB30, CB31, CB34, CB35, CB36, CB37, CB38,
CB39, CB40, CB41, CB42, CB45, CB49, CB50, CB51, CB52, CB53, CB54, CB55, CB57, CB58, CB62, CB64, CB66, CB67, CB69, CB70,
CB71, CB73, CB74, CB76, CB77, CB79, CB81, CB84, CB86, CB87, CB89, CB91, CB92, CB94, CB95, CB98, CB99, CB100, CB102,
CB104, CB106, CB107, CB113, CB115, CB116, CB119, CB121, CB122, CB123, CB124, CB127, CB128, CB129, CB133, CB134, CB135,
CB141, CB142, CB143
Reference designators shown on next
row (C3, …, CB145)
41
0402 CERAM 0.01uF 16V 10%
Panasonic
ECJ-0EB1C103K
C3, C8, C10, C17, C24, CB3, CB7, CB12, CB26, CB27, CB47, CB59, CB60, CB61, CB63, CB65, CB68, CB72, CB75, CB78, CB80, CB82,
CB83, CB85, CB88, CB90, CB93, CB96, CB97, CB101, CB103, CB105, CB108, CB109, CB110, CB111, CB114, CB117, CB118, CB120,
CB145
C4, C9, C11, C15, C16, C18, C19, C20,
C21, C23, C25, C26, CB1, CB2, CB4,
CB5, CB9, CB11, CB15, CB19, CB20,
CB24, CB29, CB32, CB33, CB44, CB46,
CB56, CB112, CB125, CB130, CB131,
CB132, CB139, CB140, CB146
C5, CB18
36
2
0603 CERAM 10uF 6.3V 20%
MULTILAYER
0603 CERAM .1uF 16V 20% X7R
Panasonic
AVX
ECJ-1VB0J106M
0603YC104MAT
C6, C7
2
0603 CERAM 22pF 25V 5% NPO
AVX
06033A220JAT
CB17, CB22
CB43, CB48, CB126, CB136, CB137,
CB138
2
0603 CERAM 4.7uF 6.3V MULTILAYER
UNK
ECJ-1VB0J475M
6
CAP CER 3.3UF 4.0V X5R 0402
AMK
AMK105BJ335MV-F
CB6, CB16, CB144
3
D CASE TANT 470uF 6.3V 20%
KEM
T491D477M006AS
SCHOTTKY DIODE, 1 AMP 40 VOLT
International
Rectifier
10BQ040
11
LED, GREEN, SMD
Panasonic
LN1351C
DS4, DS15, DS16
3
LED, GREEN, SMD
Panasonic
LN1351C
DS9, DS10
GND_TP1, GND_TP2, GND_TP3,
GND_TP4
2
LED, RED, SMD
Panasonic
LN1251C
4
KEYSTONE
4954
J1
1
STANDARD GROUND CLIP
2.0MM SURFACE MOUNT POWER
JACK
CUI INC
PJ-002AH-SMT
J11
1
2 PIN HEADER, .100 CENTERS,
VERTICAL
Samtec
TSW-102-07-T-S
J12, J13, J30, J34
4
TERMINAL STRIP, 10 PIN, DUAL ROW,
VERT
DIG
J15
1
HEADER, 14 PIN, DUAL ROW, VERT
NOT POPULATED
S2012-05-ND
HDR-TSW-107-14-T-D
Samtec
J2
1
TYPE B SINGLE RT ANGLE, BLACK
MOL
NA
J29, J31
2
CONNECTOR, SINGLE LEVEL, GIGABIT
RJ-45, 10 PIN WITH LED
Halo
Electronics
HFJ11_1G41E_L12RL
J3, J7, J10, J16, J17, J18
6
CONNECTOR, SMB, 50 OHM VERTICAL,
5PIN
AMP
413990-1
100 MIL 2 POS JUMPER
NA
NA
Samtec
TSW-103-07-T-D
DNP
DNP
DB1
DS1, DS2, DS3, DS5, DS6, DS7, DS8,
DS11, DS12, DS13, DS14
J4, J8, J22, J23, J24, J25, J26, J27, J28,
J32, J33
1
11
J5, J6, J9, J14, J19
5
JB1 J15, J21
3
TERMINAL STRIP, 6 PIN, DUAL ROW,
VERT
TERMINAL STRIP, 10 PIN, DUAL ROW,
VERT DO NOT POPULATE
26
________________________________________________________________________________ MAX24288 EV KIT
DESIGNATION
QTY
JP1, JP2, JP3, JP4, JP5, JP6, JP7, JP8,
JP9, JP10, JP11, JP12, JP13, JP14,
JP15, JP16, JP17, JP18, JP19, JP20,
JP21, JP22, JP23, JP24, JP25, JP26,
JP27, JP28, JP29, JP30, JP31, JP32,
JP33, JP34
LB1, LB3, LB4, LB9, LB10, LB11, LB12,
LB13, LB14
SUPPLIER
PART
NA
NA
9
100 MIL 3 POS JUMPER
FERRITE 3A 100 OHM AT 100 MHZ 1206
SMD
Steward
HI1206N101R-00
LB5, LB6, LB7, LB8
4
1uH ±10% 0805 Multilayer Ceramic 400
mA (ok to sub with 445-3156-1-ND)
Murata
LQM21FN1R0N00D
R1, R4, R5, R6, R7, R9, R10, RB5
9
RES 0603 30 Ohm 1/16W
Panasonic
ERJ-3GEYJ300V
R11, R18, R19, R21, R57, RB8, RB3
4
RES 0402 0 OHM 1/10W 5%
Panasonic
ERJ-2GE0R00X
R12, R17, R20, R22, R23, R29, R31,
R32, R33, R34, R35, R36, R37, R38,
R39, R40, R41, R42, R43, R44, R45,
R46, R47, R48, R49, R50, R51, R52,
R53, R54, R55, R56
32
RES 0201 30.0 OHM 1/16W 1%
Panasonic
ERJ-1GEJ300C
RES 0402 10.0 KOHM 1/16W 1%
Panasonic
ERJ-2RKF1002X
R13, R14, R25, R26, RB23, RB24,
RB25, RB38, RB44, RB45, RB49, RB50,
RB51, RB52, RB53, RB54, RB56, RB57,
RB63, RB64, RB69, RB71, RB72, RB73,
RB77, RB78, RB79, RB80, RB81, RB86,
RB87,
34
DESCRIPTION
31
R16, RB27, RB28, RB29
4
RES 0402 30.0 OHM 1/16W 1%
Panasonic
ERJ-2RKF30R0X
R30, R15
2
RES 0402 100 OHM 1/16W 1%
Panasonic
ERJ-2RKF1000X
R2, R3
2
RES 0603 33.2 Ohm 1/16W 1%
Panasonic
ERJ-3EKF33R2V
R24, R28, R62, R63, RB13, RB15,
RB16, RB17, RB18, RB19, RB20, RB21,
RB22, RB26, RB39, RB40, RB41, RB42,
RB43, RB82
18
RES 0402 1.00 KOHM 1/16W 1%
Panasonic
ERJ-2RKF1001X
R27
1
RES 0402 1.40 KOHM 1/16W 1%
Panasonic
ERJ-2RKF1401X
R8
1
RES 0603 1.00M Ohm 1/16W 1%
Panasonic
ERJ-3EKF1004V
11
RES 0603 1.0K Ohm 1/16W 5%
Panasonic
ERJ-3GEYJ102V
RB14, RB84, RB85, R60
5
RES 0603 330 Ohm 1/16W 5%
Panasonic
ERJ-3GEYJ331V
RB2, RB11, RB35, RB36, RB37
5
RES 0402 49.9 OHM 1/16W 1%
Panasonic
ERJ-2RKF49R9X
RB1, RB4, RB9, RB30, RB31, RB32,
RB33, RB34, RB60, RN1
RB6, RB10, RB83
3
RES 0603 10K Ohm 1/16W 5%
Panasonic
ERJ-3GEYJ103V
RB65
1
RES 0603 2.49K Ohm 1/16W 1%
Panasonic
ERJ-3EKF2491V
RB7
1
RES 0603 10.0K Ohm 1/16W 1%
Panasonic
ERJ-3EKF1002V
RPB5, RPB6, RPB7, RPB9, RPB13
6
RESISTOR, 4 PACK, 330 OHM 5PCT
QUAD 0603
Panasonic
EXB-V8V331JX
2
RESISTOR, 4 PACK, 10K OHM 5PCT
QUAD 0603
Panasonic
EXB-V8V103JX
3
RESISTOR, 4 PACK, 33 OHM 5PCT
QUAD 0603
Panasonic
EXB-V8V330JV
RPB8, RPB12
2
RESISTOR, 4 PACK, 4.7K OHM 5PCT
QUAD 0603
Panasonic
EXB-V8V472JX
SW1
TP1,TP2,TP3,TP4,TP5,TP6,TP7,TP8,TP
9,TP10,TP11,TP12,TP13,TP15,TP16,TP
17,TPB1,TPB2,TPB3,TPB4,TPB5,TPB6,
TPB7,TPB8,TPB9,TPB10
1
SWITCH MOM 4PIN SINGLE POLE
Panasonic
EVQPAE04M
26
TESTPOINT, 1 PLATED HOLE, DO NOT
STUFF
NA
NA
U1
1
MICROPROCESSOR VOLTAGE
MONITOR, 3.08V RESET, 4PIN SOT143
Maxim
MAX811TEUS-T
U2
1
VOLTAGE MONITOR 5, 3.3, 2.5, ADJ
Maxim
MAX6709AUB+
RPB10, RPB11
RPB2, RPB3, RPB4
27
________________________________________________________________________________ MAX24288 EV KIT
DESIGNATION
QTY
UB3,UB4,UB5,UB6,UB9,UB10,UB11,UB
12,UB13,UB14,UB15,UB16,UB19,UB20
14
DESCRIPTION
SUPPLIER
PART
HIGH SPEED BUFFER
FAIRCHILD
NC7SZ86
U4
1
IC, HCS08 8-BIT MICROCONTROLLER,
32K FLASH, 2K RAM, 2 UART, 2 SPI,
I2C, USB, -40 TO 85C, 64 PIN LQFP
FREESCALE
MC9S08JM32CLH-ND
U5
1
RTL8363 PHY
REALTEK
RTL8363C
U6
1
MAX24288 QFN 8X8
MICROSEMI
MAX24288ETK+
U7
1
SFP host / receptacle
PARTS_KIT
SFP_HOST-TYCO
U8
1
IC, LINEAR REG ADJ, 2A, 14TSSOP-EP
MAXIM
MAX8526EUD+
Maxim
MAX1793EUE-33
FOX
FOXSDLF-120-20
ConnorWinfield
MX010-025.0M
VEC
MC853X4-035W
RAKON
P5299LF
TSW-103-07-T-D
UB2, UB7, UB17, UB18, UB21
5
XB1
1
IC, LINEAR REGULATOR, 1.5W, 3.3V
OR ADJ, 1A, 16 PIN TSSOP-EP
XTAL, HC49SD, 12.0000MHz +/-50PPM,
CL=20PF
Y1
1
OSCILLATOR LVCMOS, 3.3V, 25 MHZ, 4
PIN SMD
Y2
1
Y3
1
OSCILLATOR, VECTRON OCXO, 3.3V,
12.8 MHZ, 5 PIN THROUGH-HOLE
OSCILLATOR, RAKON TC-OCXO, 3.3V,
10MHZ RFPO-30-RX-C-LF
J9
1
TERMINAL STRIP, 6 PIN, DUAL ROW,
VERT NOT POPULATED
Samtec
NOT POPULATED
TP14
1
TESTPOINT, 1 PLATED HOLE RED
KEYSTONE
5000R
U3,UB1,UB8
3
TINYLOGIC HIGH SPEED 2-INPUT AND
GATE, 5 PIN SOT23
Fairchild
NC7SZ08M5
8. Schematics
The MAX24288 EV Kit board design is a bill of materials modification of the MAX24287 EV Kit. See the following
pages for the MAX24287 EV Kit schematics.
9. Ordering Information
PART
MAX24288EVKIT
10.
TYPE
Evaluation Kit
Revision History
REVISION
DATE
10/11
2012-05
DESCRIPTION
Initial Release
Reformatted for Microsemi. No content change.
28
8
7
6
5
4
3
2
1
MAX24287 EVKIT Rev_B
D
D
TXD7
TXD6
TXD5
TXD4
30.0
30.0
30.0
30.0
V1_2
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
R12
R20
R23
R44
REFCLK
RST_DUT
GTXCLK
SCLK
SDI
SDO
GPIO1
GPIO2
GPIO3
TX_ER
TX_EN
V3_3
TP4 TP7
TP3
U6
TQFN
TP10
C
REFCLK
RST_N
GTXCLK
DVDD3.3
SCLK
SDI
SDO
GPIO1
GPIO2
GPIO3
TX_ER
TX_EN
DVDD1.2
TXD7
TXD6
TXD5
TXD4
C
2
100
R15
1
2
TCLKN
TCLKP
TVDD33
TDN
TDP
TVDD12
RVDD33
RDP
RDN
RVDD12
MAX24287, MAX24288 OR MAX24188
TXD3
TXD2
TXD1
TXD0
DVSS
TXCLK/RCLK1
CS_N
JTDO
JTRST
MDIO
MDC
RXCLK
DVDD3.3
RXD0
RXD1
RXD2
RXD3
GVDD12
ALOS
DVDDD3.3
JTCK
JTMS
JTDI
GPO1
GPO2
CRS/COMMA
COL
RX_ER
RX_DV
DVDD1.2
RXD7
RXD6
RXD5
RXD4
100
TP1
TP2
GVSS
CVDD3.3
CVDD1.2
CVSS
TCLKN
TCLKP
TVDD3.3
TDN
TDP
TVSS
TVDD1.2
RVDD3.3
RDP
RDN
RVSS
RVDD1.2
NC
CS_N
JTDO
JTRST
30.0 R16
MDC
R52
30.0
TXCLK
MDIO
R51
R53
R54
R55
R56
30.0
V3_3
RXCLK
30.0
30.0
30.0
30.0
RXD0
RXD1
RXD2
RXD3
B
30.0
30.0
30.0
30.0
30.0
30.0
30.0
30.0
30.0
30.0
R48
R49
R50
R42
GPO1
GPO2
CRS
COL
RX_ER
RX_DV
RXD7
RXD6
RXD5
RXD4
V3_3
TXD3
TXD2
TXD1
TXD0
V1_2
R17
R22
R43
R45
R46
R47
V1_2
ALOS
JTCK
JTMS
JTDI
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
B
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
EP
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TP8 17
EP2
TVDD33
TVDD12
R30
A
A
Top level Hierarchy block
TITLE:
DATE:
MAX24287 EVKIT Rev_B
ENGINEER:
8
7
6
5
4
3
07-11-2011
1/11(TOTAL)
1/8 (BLOCK)
PAGE:
Steve Scully
2
1
8
7
6
5
4
3
2
1
D
D
Switch Hierarchy block.
Contents on page 9
C
C
REALTEK_SWITCH_DN
RXD0
TP5 RXD0
TXD0
TXD0
RXD1
RXD1
TXD1
TXD1
RXD2
RXD2
TXD2
TXD2
RXD3
RXD3
TXD3
TXD3
RXD4
RXD4
TXD4
TXD4
RXD5
RXD5
TXD5
TXD5
RXD6
RXD6
TXD6
TXD6
RXD7
RXD7
TXD7
RX_DV
RX_ER
RXCLK
TP6
GTXCLK
TX_EN
RX_ER
TXCLK
RXCLK
TX_ER
TXD7
TP11
TX_EN
TXCLK
B
GTXCLK
LED4
LED6
LED6
LINKA0
LINKA0
LINKA1
LINKA1
RESET
LED2
SWITCH_OSC
LED5
LED2
CRS
LED5
1 J32
LED4
LED1
MDIO
COL
LED0
LED1
MDC
LED0
1 J33
B
TP9 RX_DV
A
MDC
MDIO
COL 2
2
CRS
SWITCH_OSC
RESET
A
Top level Hierarchy block
TITLE:
DATE:
MAX24287 EVKIT Rev_B
ENGINEER:
8
7
6
5
4
3
07-11-2011
2/11(TOTAL)
2/8 (BLOCK)
PAGE:
Steve Scully
2
1
8
7
6
5
4
3
2
1
V3_3
3
NC7SZ86_U
BUFFER
JP18
2
D
2
2RB82
GPO1
RB87
UB20 1
1
1
1.00K
1
DS15
2
4
330
1
NC7SZ86_U
BUFFER
DS4
UB6
GPIO1_LED
V3_3
1
1
GREEN
2
RB14
4
330
RB84
3
NC7SZ86_U
330
BUFFER
JP19
2
2
2 R24
GPO2
RB86
UB19 1
1
1
1.00K
1
D
RB85
GREEN
10.0K
DS16
2
4
1
GREEN
V3_3
3
10.0K
V3_3
RB49
10.0K
GPIO1
J18
4
RX_DV
V3_3
1
1
2
2
2
JP16
2
2
JP23
2
1
RXD7
V3_3
V3_3
1
3
10.0K
3
RB57
1
2
2
TXCLK
1
JP24
2
2
GPIO2
1
RXD5
49.9
1
2
2
1
JP26
2
2
10.0K
10.0K
RB64
2
JP30
2
1
RXD0
V3_3
V3_3
3
3
1
10.0K
R13
RB69
RXD1
J24
4
2
2
1
2
2
JP12
10.0K
1
GPIO3
JP8
GPIO3_SMB
30.0
TX_ER
JP29
1
3
RB63
J17
2
JP28
2
1
RXD2
V3_3
10.0K
1
A
3
3
1
1
RB28
2
3
1
BUFFER
2
10.0K
2
RB77
49.9
10.0K
2
4
NC7SZ86_U
UB9
1
J28
11
RXD3
1
2
2
JP27
10.0K
1
JP3
2
1
A
2
1
2
JP11
1 GPIO3
RB37
3
GPIO3_SMB
UB10
1
V3_3
1
BUFFER
RB25
JP13
1
RXD4
NC7SZ86_U
V3_3
B
R26
COL
RB78
2
4
V3_3
V3_3
10.0K
J27
11
1
2
V3_3
RB35
10.0K
2
JP25
J16
3
JP7
GPIO2_SMB
3
3
2
30.0
UB11
1
2
1
JP10
GPIO2
1
RB27
1
BUFFER
1
1
1
2
2
4
NC7SZ86_U
3
RB23
2
JP4
1
RB79
1
3
B
3
UB12
2
3
J23
BUFFER
1
10.0K
NC7SZ86_U
JP15
10.0K
1
RXD6
V3_3
GPIO2_SMB
Top level Hierarchy block
TITLE:
DATE:
MAX24287 EVKIT Rev_B
ENGINEER:
7
6
5
4
3
07-11-2011
3/11(TOTAL)
3/8 (BLOCK)
PAGE:
Steve Scully
8
C
10.0K
RB80
V3_3
JP17
10.0K
2
R25
J26
11
GPIO1_LED
RB81
CRS
RB71
1
JP6
GPIO1_SMB
30.0
V3_3
3
2
RX_ER
1
3
2
1
3
1
1
1
RB29
1
GPIO1
1.00K
10.0K
BUFFER
RB36
1
1
UB13
1
2 2
RB26
2
4
NC7SZ86_U
2
1
JP9
RB24
JP5
1
2
49.9
3
GPIO1_SMB
3
UB14
V3_3
C
2
JP14
J22
BUFFER
3
NC7SZ86_U
2
1
8
5
IN4
7
SHDN*
7
2
IN1
OUT1
12
3
IN2
OUT2
13
4
IN3
OUT3
14
OUT4
15
RST*
6
11
GND
10
1.0UF CB10
6
CB39
5
CB40
CB66
1.0UF
15
RST*
6
7
SHDN*
V5_0
LB8
3.3V
7
2
IN1
OUT1
12
3
IN2
OUT2
13
4
IN3
OUT3
14
OUT4
15
RST*
6
IN4
V3_3
4
SET
11
GND
10
SHDN*
SET
11
GND
10
U2
V1_2
V3_3
1
3.3V
R60
330
4
MAX1793
3
MAX6709AUB
IN1 5.0V PWRGD1
VCC
2
IN2
3.3V
PWRGD2
8
3
IN3
2.5V
PWRGD3
7
IN4
ADJ
TP12
PWRGD4
GND
12
OUT
13
4
IN
FB
9
5
IN
GND
EP
8
TP14
GND_TP2 GND_TP4
GND_TP3 GND_TP1
V5_0
6
TITLE:
MAX24287 EVKIT Rev_B
ENGINEER:
Steve Scully
2
DB1
15
MAX1793
V5_0
3
4
1
CENTER POST
2
BARREL
9
10
PAGE:
1
10UF C26
U8
0.01UF CB145
0.0
R18
2
1.0UF C22
1.40K
R27
OUT
IN
11
MAX8526EUD
R28
IN
3
OUT
1.00K
2
10
0.0
EN
OUT
R57
0.01UF C24
1
ADJ
1
14
OUT4
CB26
OUT3
IN4
0.01UF
IN3
5
2
4
TP13
1.0K
13
1.0K
OUT2
10UF CB4
3.3V
V3_3
RB9
5
3
1.0UF CB128
IN2
1.0K
3
1
470UF
12
1.0UF C27
UB21
2 CB6
OUT1
10UF CB146
IN1
10UF C23
2
1.0UF CB142
V5_0
10UF C21
4
1.0UF CB135
10UF C19
1.0UF CB143
5
RB4
RB1
1.0UF CB127
10UF C25
V1_2
CB41
0.01UF C17
1.0UF CB124
LB7
1.0UF
0.01UF CB110
1.0UF CB77
0.01UF C10
RVDD33
V3_3
1.0UF
CB37
1.0UF
CB55
1.0UF
CB38
RVDD12
1.0UF C14
1.0UF C13
10UF C16
0.01UF CB101
1.0UF CB104
10UF C15
0.01UF CB80
1.0UF CB79
TVDD33
6
1.0UF
1.0UF CB113
10UF CB19
1UH
1.0UF
CB36
1.0UF
0.01UF CB85
TVDD12
LB6
1.0UF
CB134
1.0UF CB84
0.01UF CB96
1.0UF CB95
10UF CB20
0.01UF
1UH
1.0UF
UB2
CB114
0.01UF
CB88
1UH
CB42
V5_0
1.0UF CB123
10UF CB140
10UF C11
1.0UF CB87
LB5
CB133
SET
0.01UF CB78
1.0UF CB115
10UF CB112
1.0UF CB99
0.01UF CB105
1UH
10UF CB5
1.0UF C12
C
0.01UF CB111
CB3
0.01UF
2 CB16 1
470UF
7
1.0UF
A
1.0UF CB14
10UF CB139
1.0UF CB141
D
10UF CB9
2 CB144 1
470UF
8
1
V1_2
TP15
D
UB18
J1
B
ADJ INPUT RANGE IS
0.609V TO 0.635V
V3_3
Top level Hierarchy block
DATE:
07-11-2011
4/11(TOTAL)
4/8 (BLOCK)
C
NC
MAX1793
V5_0
B
MAX6709
GREEN
DS1
DS2
DS3
5
A
8
7
6
5
4
3
2
1
J21
J15
1
TPB2
3
TPB3
5
8
RPB4 1
TPB1
7
7
2
TPB6
9
MDIO
6
SFP_I2C_SDA
5
33
3
11
4
13
1
4
5
6
7
8
9
10
11
12
13
14
J11
SCLK
2
2
3
CS_N
2
D
1
V5_0
4
1 RPB2 8 1
2
SDI
3
SDO
4
73
33
65
57
9
6
8
TPB5
8
RPB3 1
10
TPB4
7
2
12
6
14
5
33
1
2
3
4
5
6
7
8
9
10
2
TPB7
4
TPB8
6
TPB9
8
TPB10
J9
1
10
COM_BCLK
3
5
CS_N
1
2
3
4
5
6
2
MDC
4
SFP_I2C_CLK
6
SCLK
CONN_10P
COM_BCLK
3
D
CONN_6P_U
SDI
4
SDO
CONN_14P
EXTERNAL SBC CONNECTOR
DS31400DK CONNECTOR
C
J12
Processor Hierarchy block.
Contents on page 8
1
MC9S08JM_BLOCK
PROC_GPIO2
LED1
PROC_GPIO3
LED2
PROC_GPIO4
LINKA0
PROC_GPIO5
LED4
PROC_GPIO8
LINKA1
5
PROC_GPIO0
7
PROC_GPIO1
9
PROC_INTREQ
2
4
5
6
7
8
9
10
2
4
SFP_I2C_CLK
6
SFP_I2C_SDA
8
MDC
10
MDIO
B
PULLUPS ARE IN PROCESSOR BLOCK
PROCESSOR TRISTATES PIN AT END OF CYCLE
J13
SPI1_MISO
1
SPI1_MOSI
3
SPI1_SCK
5
SPI1_CS
7
9
RESET
PROC_GPIO7
LED6
I2C_SDA_P
1
3
CONN_10P
PROC_GPIO6
LED5
3
PROC_GPIO9
1
2
3
4
5
6
7
8
9
10
2
SDO
4
SDI
6
8
SCLK
J34
V3_3
CS_N
1
10
3
5
CONN_10P
7
9
A
3.08V
U1
MAX811_U
V3_3
3
MR*
VCC
4
3
1
GND
RESET*
2
TDI
5
TMS
VCC
TCK
GND
RST
0.0
RB8
TITLE:
JTDI
6
JTMS
8
JTCK
10
JTRST
V3_3
A
WHEN NOT IN JTAG
MODE INSTALL JUMPERS
ON BOTTOM 4 ROWS
DATE:
MAX24287 EVKIT Rev_B
6
5
4
3
07-11-2011
5/11(TOTAL)
5/8 (BLOCK)
PAGE:
Steve Scully
7
JTDO
4
Top level Hierarchy block
RST_DUT
0.0
ENGINEER:
8
2
RB3
10UF CB1
4
2
10UF CB2
1
TDO
CONN_10P
RESET
SW1
1
3
10K
LED0
I2C_SCL_P
RB83
B
C
2
1
8
7
6
5
4
3
2
1
3.3V
LB10
UB17
OUT3
14
IN4
OUT4
15
RST*
6
7
SHDN*
SET
11
GND
10
10UF C18
SFP_VCCR
100O100MZH
0.01UF CB93
IN3
10UF CB56
4
D
LB11
1.0UF CB92
12
13
SFP_3.3V_REG
1.0UF CB102
OUT2
0.01UF CB103
OUT1
IN2
100O100MZH
10UF C9
IN1
3
1.0UF CB129
10UF C20
1.0UF CB62
2
5
SFP_VCCT
TP16
V5_0
D
SFP_3.3V_REG
MAX1793
1 RPB11 8
2
C
J30
10K
3
4
SFP_DEV_DETECT
1
3
SFP_LOS
SFP_I2C_SDA
5
SFP_I2C_CLK
7
SFP_TX_FAULT
9
1
2
3
4
5
6
7
8
9
10
2
4
10
SFP_TX_DISABLE
6
SFP_I2C_SDA
5
SFP_I2C_CLK
SFP_3.3V_REG
ALOS
6
8
SFP_TX_FAULT
7
1 RPB10 8
SFP_RATE
2
SFP_LOS
7
10K
3
SFP_TX_DISABLE
4
SFP_RATE
6
C
PULLUPS FOR OPEN
DRAIN PINS
5
CONN_10P
B
B
U7
20
VEET
TDN
19
TD-
TDP
18
TD+
17
VEET
SFP_VCCT
16
VCCT
SFP_VCCR
15
VCCR
14
VEER
BUFFER
SFP_TX_DISABLE
MOD-DEF2
4
SFP_I2C_SDA
MOD-DEF1
5
SFP_I2C_CLK
MOD-DEF0
6
SFP_DEV_DETECT
RATE
7
RDP
13
RD+
LOS
8
RDN
12
RD-
VEER
9
11
VEER
VEER
10
CGND
CGND
CGND
CGND
CGND
CGND
CGND
CGND
CGND
CGND
CGND
NC7SZ86_U
1
SFP_TX_FAULT
3
TX_DISABLE
SFP_HOST
1
2
UB154
2
1
DS9
RED
1 RPB9
8
2
7
3
4
330
SFP_3.3V_REG
6
5
NC7SZ86_U
SFP_RATE
BUFFER
1
SFP_LOS
UB164
1
DS10
2
A
RED
21
22
23
24
25
26
27
28
29
31
30
A
VEET
TX_FAULT
Top level Hierarchy block
TITLE:
DATE:
MAX24287 EVKIT Rev_B
ENGINEER:
8
7
6
5
4
3
07-11-2011
6/11(TOTAL)
6/8 (BLOCK)
PAGE:
Steve Scully
2
1
8
7
6
5
4
3
2
1
_POW=V3.3_OSCBUF
J10
UB1
1
1
3.3V
RB2
V5_0
6
7
SHDN*
SET
11
GND
10
V3.3_OSC
J4
BUFFER
Y3
osc_racon
MAX1793
NC
3
5
J19
2
4
6
2
1
4
3
6
5
1
VDD_MOCXO
3
VDD_OCXO
5
VDD_POSC
2
NC
NC
OSC_MINIOCXO
R5
4
GND OUT
CONN_6P_U
C
30
6
VCC
10MHZ
TCXO
_POW=V3.3_OSCBUF
JMP_3
1
6
7
5
V3.3_OSCBUF
GND
C
R4
3
30
B
5
NC7SZ08
1
2
3
4
5
6
4
REFCLK
6
RST_DUT
R6
1
RF_OUT
4
C
2
30
OSC_OCXO
B
0.01UF CB27
10UF C4
10UF CB24
1.0UF CB21
OSC_MC853X4
1.0UF CB8
0.01UF CB12
1.0UF C2
0.01UF CB7
1.0UF CB13
1.0UF CB28
1.0UF CB23
1.0UF CB34
1.0UF CB25
10UF CB11
2
J14
CONN_6P_U
1
A
2
SUPPLY_V
LB1
U3
JP1
Y2
100O100MZH
1
30
UB4 4
1
J3
1
RB5
NC7SZ86_U
1
B
UB3 4
GND=GND
RN1
RST*
BUFFER
1
1.0K
15
10K
14
OUT4
NC7SZ86_U
RB10
OUT3
IN4
D
GND=GND
RST_DUT
3
IN3
5
1
1
4
NC7SZ08
0.01UF C3
OUT2
30
B
J25
TP17
1.0UF C1
IN2
13
10UF CB15
12
IN1
10UF CB29
OUT1
3
1.0UF CB31
10UF CB32
2
1.0UF CB30
D
R1
4
C
2
49.9
UB7
A
Y1
OSC_TCXO
1
VC
VS
_POW=V3.3_OSCBUF
4
UB8
1
2
GND
RF_OUT
3
2
R10
OSC_LOWCOST
R9
30
RST_DUT
A
GND=GND
3
0.01UF C8
1.0UF CB35
10UF
CB33
NC7SZ86_U
BUFFER
J7
UB5
JP2
R7
SWITCH_OSC
30
49.9
1
1
RB11
REV_A NOTE: UB1, UB8 AND U3 HAVE
REWORK TO CONNECT PIN 2 TO DUT_RST
THE REWORK IS IN THE FORM OF LIFTED PINS + 20 AWG WIRE
COMPONENT RN1 HAS BEEN ADDED TO PIN2 OF J7
THE SCHEMATIC HAS BEEN UPDATED TO MATCH THE PCB
4
C
B
NC7SZ08
30
A
A
Top level Hierarchy block
TITLE:
J8
DATE:
MAX24287 EVKIT Rev_B
1
ENGINEER:
8
7
6
5
4
3
07-11-2011
7/11(TOTAL)
8/8 (BLOCK)
PAGE:
Steve Scully
2
1
5
4
1
3
5
1
2
3
4
5
2
PTA1
C
PTA4
33
PTA5
34
PTB0/MISO2/ADP0
PTD6
52
35
PTB1/MOSI2/ADP1
PTD7
53
USB
MC9S08JM
U4
IO
PROC_GPIO6
36
PTB2/SPSCK2/ADP2
PTE0/TXD1
13
IO
PROC_GPIO7
37
PTB3/SS2/ADP3
PTE1/RXD1
14
IO
PROC_GPIO8
38
PTB4/KBIP4/ADP4
PTE2/TMP1CH0
15
IO
PROC_GPIO9
39
PTB5/KBIP5/ADP5
PTE3/TPM1CH1
16
40
PTB6/ADP6
PTE4/MISO1
17
41
PTB7/ADP7
PTE5/MOSI1
18
I2C_SCL_P
I2C_SDA_P
VBUSDET
10.0K
60
PTC0/SCL
PTE6/SPSCK1
19
61
PTC1/SDA
PTE7/SS1
20
62
PTC2
PTF0/TPM1CH2
4
63
PTC3/TXD2
PTF1/TPM1CH3
5
PTC4
PTF2/TPM1CH4
6
PTC5/RXD2
PTF3/TPM1CH5
7
9
PTC6
PTF4/TPM2CH0
RESET
8
3
RESET*
PROC_INTREQ 2
56
BKGDMS
USBDP
USBDN
2
RB19
PTF5/TPM2CH1
11
IRQ/TPMCLK
PTF6
12
BKGD/MS
PTF7
10
R2
24
USBDP
PTG0/KBIP0
26
33.2
23
USBDN
PTG1/KBIP1
27
PTG2/KBIP6
54
PTG3/KBIP7
55
PTG4/XTAL
57
PTG5/EXTAL
58
R3
SPI1_CS
IO
SPI1_MISO
IO
SPI1_MOSI
IO
SPI1_SCK
IO
2
4
5
5
6
6
7
7
8
8
9
10
SPI1_MISO
SPI1_MOSI
SPI1_SCK
SPI1_CS
B
12.0000MHZ
XB1
1
2
A
R8
PROC_GPIO0
IO
PROC_GPIO1
IO
Processor Hierarchy block.
MOUNTING HARDWARE
H1 H2 H3 H4 H5 H6 H7
4 4 4 4 4 4 4
1
7
6
5
1
1
4
1
1
1
TITLE:
Instantiated on page 5
07-11-2011
8/11(TOTAL)
1/1 (BLOCK)
ENGINEER:
PAGE:
Steve Scully
3
1.00M
DATE:
MAX24287 EVKIT
1
22PF
IO
10
C
C7
PROC_INTREQ
4
CONN_10P
59
IO
46
I2C_SDA_P
47
IO
22
I2C_SCL_P
VSS
VSSAD
VREFL
VSSOSC
5
2
1
2
RB20
RB18
1
2
RB15
1
2
RB16
1
2
RB17
9
51
32
PROC_GPIO5
2
1
3
1
RB13
1
RB21
50
PTD5
PROC_GPIO4
IO
IO
1K PULLUPS
8
PTD4/ADP11
IO
1
1
RB22
2
2
2
1
A
49
PTA3
B
1
2
3
4
48
PTD3/KBIP3/ADP10
PTA2
64
VDD
DATDAT+
GND
PTD2/KBIP2/ACMPO
30
31
1
V3_3
3
PROC_GPIO3
RB7
VBUS
1
43
PROC_GPIO2
VBUS
J2
42
PTD1/ADP9/ACMP-
IO
10K
6
PTD0/ADP8/ACMP+
IO
RB6
4
6
PTA0
29
V3_3
22PF
BKGDMS
28
PROC_GPIO1
VDD
VDDAD
VREFH
VUSB33
21
V5_0
PROC_GPIO0
D
JB1
C6
6
J6
4.7UF
6
CB17
5
2
4
D
J5
1
25
4
45
5
2
44
VBUS
1
3
.1UF
3
4.7UF
1
CONN_6P_U
2
CONN_6P_U
V5_0
CB18
JUMPER 1+3, 4+6 TO POWER FROM USB ONLY
3
.1UF
6
CB22
7
C5
8
2
1
1
1.0K 2
3
4
2.49K 5
6
AVDD33
7
AVDD12
8
P0MDIAP
9
P0MDIAN
10
11
P0MDIBP
12
P0MDIBN
13
AVDD12
14
AVDD33
15
P0MDICP
16
P0MDICN
17
18
19
P0MDIDP
20
P0MDIDN
21
AVDD12
22
AVDD12
23
AVDD33
24
P1MDIAP
25
P1MDIAN
26
27
28
P1MDIBP
29
P1MDIBN
30
AVDD12
31
AVDD33
32
P1MDICP
33
P1MDICN
34
35
P1MDIDP
36
P1MDIDN
37
AVDD12
38
AVDD33
RB60
RB65
B
8
VDD12
DVDD
VDD12
VDDIO
RESET
AVDDPLL
AVDD33
AVDD33
103
104
105
RXD0
106
RXD1
107
RXD2
108
RXD3
109
110
RXD4
111
RXD5
112
RXD6
113
RXD7
114
115
MDIO
116
MDC
LED3 117
LED7 118
119
0.0 R21 120
121
FLOAT122 122
123
SWITCH_OSC 124
125
126
127
128
RX_DV
129
7
A
8363S
P2MRXDV/P2PTXEN/P2MRXCTL/P2MSRSDV
VDD12
P2MRXD0/P2PTXD0
P2MRXD1/P2PTXD1
P2MRXD2/P2PTXD2
P2MRXD3/P2PTXD3
DVDD
P2MRXD4
P2MRXD5
P2MRXD6
P2MRXD7
VDD12
SDA/MDIO
SCL/MDC
LEDDA/LED3/LEDMODE[0]
LEDCK/LED7/LEDMODE[1]
VDDIO
RESET#
AVDDPLL
RSVD
AVSSPLL
XTAL1
XTAL2
AVDD33
AGND
AVDD33
6
RTL8363S
5
4
BGPIO1
VDD12
BGPIO2
DVDD
LEDSPSEL
ENJF
VDD12
INT
BGPIO3
WAKEUP
RSVD
RSVD
AVDD12
RSVD
RSVD
AGND
AVDD12
AGND
RSVD
RSVD
AVDD12
RSVD
AGND
RSVD
RSVD
RSVD
4
FLOAT39
64
63
VDD12
62
61
DVDD
60
LESSPSEL
59
EN_JUMBO
58
VDD12
57
56
55
54
RB41
53 RB39
1.00K
52 AVDD12
1.00K
51 FLOAT51
50 FLOAT50
49
48
AVDD12
47
46 FLOAT46
45 FLOAT45
44
AVDD12
43
42
RB40
1.00K
41
RB43
40
1.00K
39
RB42 1.00K
3
1.00K
5
R63
GTXCLK
TX_EN
VDD12
TXD0
TXD1
TXD2
TXD3
DVDD
TXD4
TXD5
TXD6
TXD7
VDD12
RXCLK
TXCLK
CRS
6
1.00K
102
101 R31
30.0
100 R40
30.0
99
DVDD
98
COL
97
96 R29
30.0
95 R41
30.0
94
93 R32
30.0
92 R33
30.0
91 R34
30.0
90 R35
30.0
89
88 R39
30.0
87 R36
30.0
86 R37
30.0
85 R38
30.0
84 RX_ER
83
82
TXDLY
81
RXDLY
80
DVDD
79 P2IF0
78 P2IF1
77 P2IF2
76 P2LINKSTA
75
VDD12
74 P2SPD0
73 P2SPD1
72 LED0
71 LED1
70
DVDD
69 LED2
68 LED4
67 LED5
66 LED6
65
7
R62
P2MRXC/P2TXC/P2MRCLK
P2MTXC/P2PRXC
P2MCRS/P2PCRS
DVDD
P2MCOL/P2PCOL
P2MGTXC
P2MTXEN/P2PRXDV/P2MTXCTL
VDD12
P2MTXD0/P2PRXD0
P2MTXD1/P2PRXD1/DISPBLK
P2MTXD2/P2PRXD2/RSVD
P2MTXD3/P2PRXD3
DVDD
P2MTXD4/FWMODE[0]
P2MTXD5/FWMODE[1]
P2MTXD6/PHYADR[3]
P2MTXD7/PHYADR[4]
VDD12
P2MRXER/P2PTXER
ENEEPROM
TXDLY
RXDLY
DVDD
P2IF[0]
P2IF[1]
P2IF[2]
P2LNKSTA
VDD12
P2SPD[0]
P2SPD[1]
LED0/AGPIO0
LED1/AGPIO1
DVDD
LED2/AGPIO2
LED4/AGPIO3
LED5/AGPIO4
LED6
BGPIO0
C
NC
NC
ATEST
MDI_REF
AGND
AVDD33
AVDD12
P0MDIAP
P0MDIAN
AGND
P0MDIBP
P0MDIBN
AVDD12
AVDD33
P0MDICP
P0MDICN
AGND
AGND
P0MDIDP
P0MDIDN
AVDD12
AVDD12
AVDD33
P1MDIAP
P1MDIAN
AGND
AGND
P1MDIBP
P1MDIBN
AVDD12
AVDD33
P1MDICP
P1MDICN
AGND
P1MDIDP
P1MDIDN
AVDD12
AVDD33
8
3
2
D
U5
TITLE:
MAX24287 EVKIT
ENGINEER:
Steve Scully
2
1
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
(MII) TX_ER
TX_EN
TXCLK
CRS
COL
IO FUNCTION FOR GMII MODE
RX_ER
RX_DV
RXD7
RXD6
RXD5
RXD4
RXD3
RXD2
RXD1
RXD0
RXCLK
RESET
GTXCLK
SWITCH_OSC
MDIO
MDC
Switch Hierarchy block.
OUT
OUT
OUT
OUT
OUT
OUT
D
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
C
IN
IN
IN
V3_3
IN
IN
IN
IO
IN
B
EPAD
A
Instantiated on page 2
DATE:
PAGE:
07-11-2011
9/11(TOTAL)
1/3 (BLOCK)
1
8
7
6
5
4
3
2
J31
1
J29
D
D
P0MDIAP
2
CMR CHOKES
TD0+
0.01 UF X4
P0MDIAN
3
750 X4
2
P1MDIAP
CMR CHOKES
TD0+
J1
MX0+
0.01 UF X4
TD0-
P1MDIAN
3
P1MDIBP
4
P1MDIBN
5
750 X4
J1
MX0+
TD0-
J2
MX0-
P0MDIBP
4
P0MDIBN
5
J2
MX0-
TD1+
TD1+
J3
MX1+
J3
MX1+
TD1-
TD1-
J6
MX1-
P0MDICP
6
J6
MX1-
TD2+
6
P1MDICP
TD2+
J4
MX2+
C
P0MDICN
7
J4
MX2+
TD2-
7
P1MDICN
J5
MX2-
P0MDIDP
8
J5
MX2-
TD3+
P1MDIDP
8
P1MDIDN
9
TD3+
J7
MX3+
P0MDIDN
9
J7
MX3+
TD3J8
MX31000PF, 2KV
1
13
GREEN
P11
P12
GND
8
RPB5 1
7
2
14
6
330
B
TD3J8
MX3-
LINKA0
IN
1
P11
P12
GND
3
8
RPB6 1
7
2
14
6
330
LINKA1
IN
3
10
15
CHGND
SH1
YELLOW
P13
P14
SH2
5
4
LED3
11
12
16
conn_hfj11_1g41e_l12rl
15
CHGND
SH1
P13
P14
LED0=GIG_LINK/ACT
LED1-100_LINK/ACT
LED2=10_LINK/ACT
LED3=DUP/COL
8
RPB8 1
LED0
8 RPB7 1
SH2
7
2
LED1
7
6
3
LED2
6
5
4
LED3
DS5
2
330
5
3
DS6
LED7
B
DS7
SWITCH1
LED4=GIG_LINK/ACT
LED5-100_LINK/ACT
LED6=10_LINK/ACT
LED7=DUP/COL
LED4
8 RPB13 1
7
2
LED5
7
6
3
LED6
6
5
4
LED7
DS11
2
330
5
3
OUT
LED2
OUT
LED4
OUT
LED5
OUT
LED6
OUT
DS13
DS14
Switch Hierarchy block.
TITLE:
DATE:
MAX24287 EVKIT
07-11-2011
ENGINEER:
PAGE: 10/11(TOTAL)
Steve Scully
6
5
4
A
DS12
4
4.7K
OUT
LED1
V3_3
DS8
8 RPB12 1
LED0
GREEN
4
4.7K
7
4
16
conn_hfj11_1g41e_l12rl
SWITCH0
A
5
YELLOW
INDICATIONS FOR PARALLEL MODE0
8
13
GREEN
1000PF, 2KV
10
11
12
C
TD2-
3
2/3 (BLOCK)
2
1
8
7
6
5
4
3
2
1
V3_3
P2SPD[1:0] STRAP OPTIONS
00: 10M
01: 100M
10: 1000M
EN_JUMBO=0: NO JUMBO FRAME
EN_JUMBO=1: JUMBO FRAME
EN_JUMBO IS DRIVEN BY P2SPD[1]
3
2
JP32
RB31
CB75
3
P2SPD1
JP22
EN_JUMBO
2
NO DELAY
2
10.0K
2
10.0K
2
10.0K
2
10.0K
3
CB117
0.01UF
1.0UF CB107
1
ADD 1.5NS DELAY TO P2MGRXC
2
RXDLY
1
LB4
RB56
1
CB47
CB61
V3_3
2
2
RB53
0.01UF
1
0.01UF
1
CB82
2
CB72
0.01UF
1
CB60
0.01UF
0.01UF
2
1.0UF CB52
1
2
2
1
1.0UF CB45
1.0UF CB58
1
2
1
1.0UF CB94
1
2
1.0UF CB53
2
1
1.0UF CB86
1
2
2
1.0UF CB73
1
2
1.0UF CB67
1.0UF CB57
1
2
1.0UF CB89
2
1
1
2
10UF CB46
2
2
CB48
3.3UF
1
1
AVDD12
1
RB45
2 P2LINKSTA PORT2 LINK
10.0K
2 LED3
LEDMODE[0]
10.0K
2 LED7
LEDMODE[1]
10.0K
1
RB73
LB14
1
RB72
0.01UF
CB108
1
UP
2
CB90
0.01UF
2
2
CB59
0.01UF
1
1
0.01UF
CB109
1
2
CB68
0.01UF
1
2
1.0UF CB50
1.0UF CB51
2
1
1.0UF CB122
2
1
1.0UF CB69
2
1
1.0UF CB74
2
1
1.0UF CB91
2
1
1.0UF CB121
2
1
10UF CB132
1
2
2
2
CB138
3.3UF
1
1
VDD12
100O100MZH
Switch Hierarchy block.
TITLE:
DATE:
MAX24287 EVKIT
07-11-2011
ENGINEER:
PAGE: 11/11(TOTAL)
Steve Scully
8
7
B
2
LESSPSEL
LED MODE PARALLEL
10.0K
2
TXD2
10.0K
2
TXD0
10.0K
2
TXD1
LED BLINK ON
10.0K
RB54
A
TXD7
V3_3
RB38
100O100MZH
C
TXD6
JP31
NO DELAY
2
2
1
10UF CB130
2
1
V3_3
3.3UF
1
CB136
2
B
RB44
ADR[0]
ADR[1]
RB50
TXD5 FWMODE[1]
TXD4
RB52
FWMODE[0]
SWITCH ADDRESS: 0=16, 1=17, 2=18
FWDMODE=STORE-FORWARD
RB51
1
LB12
AVDDPLL
JP20
1
V3_3
R14
100O100MZH
1.0K
JP34
2
2
TXDLY
2
2
10.0K
ADD 1.5NS DELAY TO P2MGTXC
3
0.01UF
CB118
1
1.0UF CB106
1
2
1
3.3UF
10UF CB131
1
2
V3_3
RB33
1
2
1
LB13
V1_2
JP21
V3_3
3
RB30
1.0K
VDDIO
2
1.0K
1
0.01UF
2
2
P2IF2
100O100MZH
RB34
V3_3
C
CB137
P2SPD0
JP33
1
CB83
0.01UF
1
1
CB63
0.01UF
1.0UF CB76
1
2
2
1.0UF CB71
1
2
1.0UF CB100
1.0UF CB119
1
2
1
2
2
2
3.3UF
1
100O100MZH
1.0UF CB49
2
1
10UF CB44
1
DVDD
CB43
2
1.0K
1
P2IF1
LB3
D
V3_3
V3_3
3
2
2
1
CB65
0.01UF
0.01UF
CB120
P2IF[2:0] STRAP OPTIONS
000: GMII/PHY MODE MII
001: GMII/MAC MODE MII
010: RGMII
011: RMII
3
1
1
1
1.0UF CB54
1
2
CB97
1.0UF CB116
1
2
0.01UF
1.0UF CB64
1
2
2
1.0UF CB81
1
2
RB32
1.0K
1.0UF CB98
1.0UF CB70
1
2
2
1
3.3UF
CB126
2
10UF CB125
2
1
P2IF0
AVDD33
100O100MZH
1
D
LB9
V3_3
6
5
4
3
3/3 (BLOCK)
2
1
A
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
solutions for: aerospace, defense and security; enterprise and communications; and industrial
and alternative energy markets. Products include high-performance, high-reliability analog and
RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and
complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at
www.microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo CA 92656 USA
Within the USA: +1 (949) 380-6100
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