MAX3612EVKIT+

19-5295; Rev 0; 6/10 EVALUATION KIT AVAILABLE MAX3612 Evaluation Kit The MAX3612 evaluation kit (EV kit) is a fully assembled and tested demonstration board that simplifies evaluation of the MAX3612 low-jitter clock generator. The EV kit includes an on-board 25MHz crystal and switches for selecting different modes of operation. The reference inputs and clock outputs use SMA connectors and are AC-coupled to simplify connection to test equipment. EV Kit Contents S MAX3612 EV Kit Board Features S Fully Assembled and Tested S On-Board 25MHz Crystal S Switches for Selecting Modes of Operation S SMA Connectors and AC-Coupled Clock I/Os Ordering Information PART TYPE MAX3612EVKIT+ EV Kit +Denotes lead(Pb)-free and RoHS compliant. Component List DESIGNATION QTY DESCRIPTION C1–C10, C14, C15, C16, C18– C24, C27–C32, C35, C36, C37 29 0.1µF ±10% ceramic capacitors (0402) C11 1 2.2µF ±10% ceramic capacitor (0603) C12 1 0.1µF ±10% ceramic capacitor (0603) C13 1 33µF ±10% tantalum capacitor (B case) AVX TAJB336K010R DESIGNATION QTY L2, L3, L6, L7, L10, L12, L14, L15, L18, L19, L22, L23, L26, L27, L30, L31, L33, L34 DESCRIPTION 18 4.7µH ±10% inductors (0805) Murata LQM21NN4R7K10 R1–R10, R12, R15–R18, R20, R21, R22 18 150ω ±1% resistors (0402) R11 1 49.9ω ±1% resistor (0402) R13 1 10.5ω ±1% resistor (0402) S1, S2, S9, S11, S13–S17 9 Switches, SP3T, slide Alps SSS211900 S3, S6, S18–S21 6 Switches, SPDT, slide E-Switch EG1218 C17 1 27pF ±5% ceramic capacitor (0402) C25 1 33pF ±5% ceramic capacitor (0402) C26 1 10µF ±20% ceramic capacitor (0603) TP1, TP2 2 Test points Keystone 5000 J1–J9, J11, J13–J20, J22, J23, J24 U1 1 21 SMA connectors, edge-mount, tab-contact Johnson 142-0701-851 Clock generator (48 TQFN-EP*) Microsemi Maxim MAX3612ETM+ U2 1 25MHz crystal NDK EXS00A-AT00429 J10, J12 2 –– 1 PCB: MAX3612 EVALUATION BOARD+ REV B L1, L4, L5, L8, L9, L11, L13, L16, L17, L20, L21, L24, L25, L28, L29, L32, L35, L36 Test points Keystone 5000 *EP = Exposed pad. 18 Ferrite beads (0402) Murata BLM15HD102SN1    1 Evaluates: MAX3612 General Description Evaluates: MAX3612 MAX3612 Evaluation Kit Quick Start 1) Set the switches to the following settings to generate a 156.25MHz LVDS output from the 25MHz crystal reference: IN_SEL = XO PLL_BP = LOW DM = LOW DF = LOW DA = LOW DB = LOW DC = LOW QA_CTRL1 = LVDS QA_CTRL2 = DISABLED QB_CTRL = DISABLED QC_CTRL = DISABLED QA_TERM1 = LVDS QA_TERM2 = LVDS QB_TERM = LVDS QC_TERM = LVDS Differential Clock Input The differential clock input (DIN) is AC-coupled at the SMA connectors and has an internal 100ω differential termination. For optimal performance, it is important to use a low-jitter, differential, square-wave clock source. Clock signals should be applied to DIN only when the switch IN_SEL is set to DIN. LVDS/LVPECL Clock Outputs The LVDS/LVPECL clock outputs (QA[4:0], QB[2:0], QC) are configured using switches S14–S21. Each output has an on-board bias-T, which provides DC-bias when configured as LVPECL and AC-coupling for direct connection to 50ω-terminated test equipment. Unused outputs should be disabled (using switches S14–S17) or have 50ω terminations placed on the SMA connectors. For optimal jitter measurements, a balun is recommended for differential to single-ended conversion when connected to single-ended test equipment such as a phase noise analyzer. See Figure 1 for the measurement setup. PHASE NOISE ANALYZER 2) Connect a +3.3V supply to VCC (J10) and GND (J12). 3) Set the supply current limit to 500mA. Using SMA cables, connect QA0 and QA0 to a phase noise analyzer or scope. Terminate all unused enabled outputs (QA1, QA1, QA2, QA2). MAX3612 EVALUATION BOARD Q_ BALUN Q_ Detailed Description The MAX3612 evaluation kit (EV kit) simplifies evaluation by providing the hardware needed to evaluate all the MAX3612 functions. Table 1 contains functional descriptions for the switches. Table 2 provides the divider settings for various frequency configurations. LVCMOS Clock Input The LVCMOS clock input (CIN) is AC-coupled at the SMA connector and has an on-board 50ω termination. For optimal performance, it is important to use a lowjitter square-wave clock source. Clock signals should be applied to CIN only when the switch IN_SEL is set to CIN. 2   _ SCOPE MAX3612 EVALUATION BOARD Q_ Q_ Figure 1. Measurement Setup MAX3612 Evaluation Kit Evaluates: MAX3612 Table 1. Switch Descriptions COMPONENT NAME FUNCTION IN_SEL Selects input reference clock source. DIN = Differential input DIN, DIN CIN = LVCMOS input CIN XO = Crystal reference (25MHz on-board) S2 PLL_BP Selects PLL bypass mode. HIGH = All outputs PLL bypass OPEN = C output bank PLL bypass LOW = All outputs PLL enabled S3 DM Selects input divider M. See Table 2. S6 DF Selects feedback divider F. See Table 2. S9 DA Selects output divider A. See Table 2. S11 DB Selects output divider B. See Table 2. S13 DC Selects output divider C. See Table 2. S14 QA_CTRL1 Selects QA[2:0] output interface (LVPECL, LVDS, or DISABLED). S15 QA_CTRL2 Selects QA[4:3] output interface (LVPECL, LVDS, or DISABLED). S16 QB_CTRL Selects QB[2:0] output interface (LVPECL, LVDS, or DISABLED). S17 QC_CTRL Selects QC output interface (LVPECL, LVDS, or DISABLED). S18 QA_TERM1 Selects QA[2:0] output termination. Provides DC path to GND for QA[2:0] bias-Ts when switched to LVPECL. DC path to GND is open when switched to LVDS. S19 QA_TERM2 Selects QA[4:3] output termination. Provides DC path to GND for QA[4:3] bias-Ts when switched to LVPECL. DC path to GND is open when switched to LVDS. S20 QB_TERM Selects QB[2:0] output termination. Provides DC path to GND for QB[2:0] bias-Ts when switched to LVPECL. DC path to GND is open when switched to LVDS. S21 QC_TERM Selects QC output termination. Provides DC path to GND for QC bias-Ts when switched to LVPECL. DC path to GND is open when switched to LVDS. S1 Table 2. Divider Settings for Various Frequency Configurations INPUT FREQUENCY (MHz) INPUT DIVIDER FEEDBACK DIVIDER DM DF 25 LOW LOW 31.25 LOW HIGH 125 HIGH LOW 156.25 HIGH HIGH VCO FREQUENCY (MHz) 625 OUTPUT DIVIDER DA, DB, DC OUTPUT FREQUENCY (MHz) OPEN 312.5 LOW 156.25 HIGH 125    3 C26 10uF DF QC_CTRL C23 0.1uF 9 10 11 12 VCC VCC DF S6 VCC DA S9 VCC DB 38 37 VCCQB 40 39 QB0 QB0 QB_CTRL QA_CTRL1 QB2 QB1 QB1 36 VCC S11 DC 35 34 33 32 31 30 29 28 27 26 25 L10 L9 R5 4.7uH 150Ω 1% FERRITE BEAD QB_TERM QA_TERM1 VCC QA_CTRL1 VCC QA_CTRL2 S15 VCC QB_CTRL S16 L18 L17 R9 4.7uH 150Ω 1% FERRITE BEAD QA_TERM1 C27 0.1uF QB_TERM S18 S20 QA_TERM2 QC_TERM S19 S21 Figure 2. MAX3612 EV Kit Schematic 4   _ L19 R10 L20 4.7uH 150Ω 1% FERRITE BEAD L22 L21 R12 4.7uH 150Ω 1% FERRITE BEAD C5 0.1uF C6 0.1uF C7 0.1uF C8 0.1uF C9 0.1uF QB2 J4 QB2 J5 QB1 J6 QB1 J7 QB0 J8 QB0 J9 QA0 C10 J11 0.1uF C14 0.1uF QA0 J13 L23 R15 L24 4.7uH 150Ω 1% FERRITE BEAD QA1 C15 J14 0.1uF C16 0.1uF QA1 J15 QA2 C22 J16 0.1uF C29 0.1uF QA2 J17 VCC QC_CTRL L26 L25 R16 4.7uH 150Ω 1% FERRITE BEAD S17 QA_TERM2 QA_TERM1 L15 R8 L16 4.7uH 150Ω 1% FERRITE BEAD C4 0.1uF EP QA_TERM1 S14 L12 R6 L11 4.7uH 150Ω 1% FERRITE BEAD L14 L13 R7 4.7uH 150Ω 1% FERRITE BEAD C28 0.1uF S13 L7 R4 L8 4.7uH 150Ω 1% FERRITE BEAD C21 0.1uF VCC QA_CTRL2 S3 13 14 15 DM VCC MAX3612ETM+ VCCQC R13 10.5Ω 1% QB_TERM VCC VCCQA QA0 QA0 QA1 QA1 QA2 QA2 QA3 QA3 QA4 QA4 VCCQA U1 DC PLL_BP S2 IN_SEL PLL_BP DM XIN XOUT VCC IN_SEL PLL_BP RES0 DF QC_CTRL VCCA RES1 RES2 L3 R2 L4 4.7uH 150Ω 1% FERRITE BEAD L6 L5 R3 4.7uH 150Ω 1% FERRITE BEAD C20 0.1uF 23 24 C24 0.1uF VCC 2 3 4 5 6 7 8 DA IN_SEL S1 VCC 1 QC QC VCC DM QA_CTRL2 VCC RES6 C25 33pF 21 22 CIN U2 25MHz CRYSTAL 43 42 41 48 47 46 C17 27pF VCC 18 19 20 C18 0.1uF R11 C19 49.9Ω 0.1uF 1% 45 44 VCC QA_CTRL1 QB2 J12 CIN J1 C1 0.1uF RES5 DC DIN J2 C12 0.1uF TP2 QB_TERM 16 17 C11 2.2uF L2 L1 R1 4.7uH 150Ω 1% FERRITE BEAD C2 0.1uF DIN DIN QB_CTRL GND C3 0.1uF DIN J3 DB RES4 DA C13 33uF J10 VCC TP1 +3.3V RES3 VCC DB Evaluates: MAX3612 MAX3612 Evaluation Kit QC J22 QC J23 C35 0.1uF C36 0.1uF L32 L33 R20 FERRITE BEAD 150Ω 1% 4.7uH L35 R21 L34 FERRITE BEAD 150Ω 1% 4.7uH L27 R17 L28 4.7uH 150Ω 1% FERRITE BEAD L30 L29 R18 4.7uH 150Ω 1% FERRITE BEAD QC_TERM QA_TERM2 L31 R22 L36 4.7uH 150Ω 1% FERRITE BEAD QA3 C30 J18 0.1uF C31 0.1uF QA3 J19 QA4 C32 J20 0.1uF C37 0.1uF QA4 J24 MAX3612 Evaluation Kit Evaluates: MAX3612 Figure 3. MAX3612 EV Kit Component Placement Guide—Component Side    5 Evaluates: MAX3612 MAX3612 Evaluation Kit Figure 4. MAX3612 EV Kit PCB Layout—Component Side 6   _ MAX3612 Evaluation Kit Evaluates: MAX3612 Figure 5. MAX3612 EV Kit PCB Layout—Ground Plane    7 Evaluates: MAX3612 MAX3612 Evaluation Kit Figure 6. MAX3612 EV Kit PCB Layout—Power Plane 8   _ MAX3612 Evaluation Kit Evaluates: MAX3612 Figure 7. MAX3612 EV Kit PCB Layout—Solder Side    9 Evaluates: MAX3612 MAX3612 Evaluation Kit Revision History REVISION NUMBER REVISION DATE 0 6/10 10 DESCRIPTION Initial release PAGES CHANGED — Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. 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