MAX3624AEVKIT+

19-5171; Rev 0; 2/10 EVALUATION KIT AVAILABLE MAX3624A Evaluation Kit The MAX3624A evaluation kit (EV kit) is an assembled demonstration board that provides convenient evaluation of the MAX3624A low-jitter, precision clock generator. The EV kit includes an on-board 25MHz crystal to allow immediate testing. The EV kit includes switches to allow easy selection of different modes of operation. The reference input and clock outputs use SMA connectors and are AC-coupled to simplify connection to test equipment. Features S AC-Coupled I/Os for Ease of Testing S Fully Assembled and Tested S +3.3V Power-Supply Operation S On-Board 25MHz Crystal Ordering Information PART TYPE MAX3624AEVKIT+ EV Kit +Denotes lead(Pb)-free and RoHS compliant. Component List DESIGNATION C1, C3, C4, C5, C7–C10, C19, C25–C30, C54 QTY DESCRIPTION DESIGNATION QTY R6, R8, R9 0 Not installed DESCRIPTION R42 1 499I Q1% resistor (0402) R57 1 49.9I Q1% resistor (0402) R59 1 10.5I Q1% resistor (0402) R61 1 36I Q5% resistor (0402) 16 0.1FF Q10% ceramic capacitors (0402) C2 1 10FF Q10% ceramic capacitor (0603) C6, C57–C60 5 0.01FF Q10% ceramic capacitors (0402) SW1, SW2, SW3, SW11 4 SP3T switches C22 1 27pF Q10% ceramic capacitor (0402) 8 SPDT switches C23 1 33pF Q10% ceramic capacitor (0402) SW4, SW6– SW9, SW12, SW13, SW15 TP6, TP7 2 Test points C65 1 4.7pF Q10% ceramic capacitor (0402) U1 1 J1, J3, J5 0 Not installed Low-jitter, precision clock generator (32 TQFN-EP*) Microsemi Maxim MAX3624AETJ+ J2, J48 2 Test points J4 1 2-pin header, 0.1in centers Y1 1 25MHz crystal NDK EXS00A-AT00429 J13–J16, J18, J19, J36, J43 8 SMA connectors — 1 Shunt L1 1 2.7FH inductor 1 PCB: MAX3624A EVALUATION BOARD+, REV A R1–R5, R7 6 150I Q5% resistors (0402) — *EP = Exposed pad. +Denotes a lead(Pb)-free/RoHS-compliant package. Component Supplier SUPPLIER NDK America PHONE 815-544-7900 WEBSITE www.ndk.com/en Note: Indicate that you are using the MAX3624A when contacting this component supplier.    1 Evaluates: MAX3624A General Description Evaluates: MAX3624A MAX3624A Evaluation Kit Quick Start For evaluation of the MAX3624A, configure the EV kit as follows: 1) D  etermine which output is going to be evaluated and connect to the test equipment through SMA cables. Be sure not to leave any outputs unterminated (i.e., place 50ω terminators on all unused outputs). 2) C  onnect a +3.3V power supply to J48 (VCC) and J2 (GND). Set the current limit to 200mA. 3) If the on-board crystal is used (IN_SEL set HIGH), the PLL divider should be set to divide by 25 (FB_SEL1 and FB_SEL0 set LOW) to achieve the standard output rates shown in Table 3. 4) U  se Table 3 to set the output divider switches to achieve the output frequency desired. 5) E  nable the output under test by setting the related output-enable switch (Qx_OE) HIGH. Table 1. Adjustment and Control Descriptions (see Quick Start first) COMPONENT NAME J4 INDUCTOR SHUNT FUNCTION SW1 SELB1 SW1 and SW2 set the output divider for the QB outputs. See Table 3 for more information. SW2 SELB0 SW1 and SW2 set the output divider for the QB outputs. See Table 3 for more information. SW3 SELA1 SW3 and SW11 set the output divider for the QA outputs. See Table 3 for more information. SW4 QAC_OE Set HIGH to enable the LVCMOS output, QA_C. Set LOW to disable QA_C. SW6 BYPASS Set LOW to bypass the PLL. Set HIGH to engage the PLL. Note that when the PLL is bypassed the output dividers are automatically set to divide by 1. SW7 FB_SEL1 SW7 and SW8 set the PLL divider. See Table 2 for more information. SW8 FB_SEL0 SW7 and SW8 set the PLL divider. See Table 2 for more information. J4 shunts the power-supply inductor. Normal operation is J4 shunted. SW9 QA_OE Set HIGH to enable LVPECL output QA. Set LOW to force a logic zero at QA. SW11 SELA0 SW3 and SW11 set the output divider for the QA outputs. See Table 3 for more information. SW12 QB1_OE SW13 IN_SEL SW15 QB0_OE Set HIGH to enable LVPECL output QB1. Set LOW to force a logic zero at QB1. Set HIGH to select the crystal as the frequency source. Set LOW to select the REF_IN as the frequency source. Set HIGH to enable LVPECL output QB0. Set LOW to force a logic zero at QB0. Table 2. PLL Divider Settings INPUT Table 3. Output Divider Settings INPUT M DIVIDER FB_SEL1 FB_SEL0 LOW LOW ÷25 LOW HIGH ÷24 SELA1/ SELB1 SELA0/ SELB0 NA/NB DIVIDER OUTPUT FREQUENCY (MHz) M = 25 AND XTAL = 25MHz HIGH LOW ÷32 LOW LOW ÷2 312.5 HIGH HIGH ÷16 LOW HIGH ÷3 208.33 HIGH LOW ÷4 156.25 HIGH HIGH ÷5 125 HIGH OPEN ÷6 104.16 78.125 OPEN HIGH ÷8 LOW OPEN ÷10 62.5 OPEN LOW ÷12 52.08 OPEN OPEN ÷1 625 Note: 625MHz is beyond maximum specified operating frequency. 2   _ QB0 QA_C R7 150Ω C25 J16 0.1µF QB0 J43 C4 0.1µF R3 150Ω C26 J15 0.1µF QB1 C9 0.1µF VCC C65 4.7pF R42 499Ω 1% TP5 QAC_OE SELB0 SELB1 QB0_OE R2 150Ω C27 J14 0.1µF C58 0.01µF C57 0.01µF R61 36Ω 31 QB0 32 QB0 QB1 30 9 QA 11 C29 0.1µF R4 150Ω J18 C10 0.1µF 10 28 IN_SEL 27 26 25 12 VCCA VCC GND QA_OE 14 J19 R5 150Ω C30 0.1µF 13 QA 15 16 QA BYPASS FB_SEL1 FB_SEL0 MAX3624A SELA0 SELA1 QB1_OE GND J36 17 18 19 20 21 22 23 24 R57 49.9Ω 1% QB1 IN_SEL REF_IN X_IN X_OUT 29 QA_C VDDO_A VCCO_A QA GNDO_A MR QAC_OE SELB0 SELB1 QB0_OE GND VCCO_B C59 0.01µF 8 7 6 5 4 3 2 1 R1 150Ω C8 VCC 0.1µF QB1 C19 0.1µF C1 0.1µF C23 33pF C22 27pF C54 0.1µF REF_IN R9 OPEN R8 OPEN BYPASS FB_SEL1 FB_SEL0 C2 R59 10µF 10.5Ω 1% QA_OE SELA0 SELA1 QB1_OE Y1 R6 OPEN ALT GND J5 ALT GND J1 ALT GND J3 SELB1 SELA1 C3 0.1µF VCC QAC_OE QA_OE QB1_OE QB0_OE J2 GND J48 +3.3V SW1 SW3 C60 0.01µF SW4 SW9 SW12 SW15 VCC VCC C7 0.1µF VCC VCC VCC VCC L1 2.7µH J4 SELB0 SELA0 BYPASS IN_SEL FB_SEL1 FB_SEL0 TP7 C5 0.1µF TP6 SW2 SW11 SW6 SW13 SW7 SW8 VCC VCC VCC VCC VCC VCC C6 0.01µF VCC Evaluates: MAX3624A C28 J13 0.1µF MAX3624A Evaluation Kit Figure 1. MAX3624A EV Kit Schematic _______________________________________________________________________________________   3 Evaluates: MAX3624A MAX3624A Evaluation Kit Figure 2. MAX3624A EV Kit Assembly Drawing—Top Side 4   _ MAX3624A Evaluation Kit Evaluates: MAX3624A Figure 3. MAX3624A EV Kit Layout—Component Side    5 Evaluates: MAX3624A MAX3624A Evaluation Kit Figure 4. MAX3624A EV Kit Layout—Ground Plane 6   _ MAX3624A Evaluation Kit Evaluates: MAX3624A Figure 5. MAX3624A EV Kit Layout—Power Plane    7 Evaluates: MAX3624A MAX3624A Evaluation Kit Figure 6. MAX3624A EV Kit Layout—Solder Side 8   _ MAX3624A Evaluation Kit Evaluates: MAX3624A Figure 7. MAX3624A EV Kit Assembly Drawing—Bottom Side 9 Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 © 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.