MAX3636EVKIT+

Rev 0; 2/12 EVALUATION KIT AVAILABLE MAX3636 Evaluation Kit The MAX3636 evaluation kit (EV kit) is a fully assembled and tested demonstration board that simplifies evaluation of the MAX3636 low-jitter, wide-frequency range, clock generator. The EV kit includes an on-board 25MHz crystal and switches for selecting different modes of operation. The reference inputs and clock outputs use SMA connectors and are AC-coupled to simplify connection to test equipment. EV Kit Contents S MAX3636 EV Kit Board Features S Fully Assembled and Tested S On-Board 25MHz Crystal S Switches for Selecting Modes of Operation S SMA Connectors and AC-Coupled Clock I/Os Ordering Information PART TYPE MAX3636EVKIT+ EV Kit +Denotes lead(Pb)-free and RoHS compliant. Component List DESIGNATION QTY DESCRIPTION C1–C10, C14, C15, C16, C18–C24, C27– C32, C34–C37 30 0.1FF Q10% ceramic capacitors (0402) C11 1 2.2FF Q10% ceramic capacitor (0603) C12 1 0.1FF Q10% ceramic capacitor (0603) C13 1 33FF Q10% tantalum capacitor (B case) AVX TAJB336K010R DESIGNATION QTY L2, L3, L6, L7, L10, L12, L14, L15, L18, L19, L22, L23, L26, L27, L30, L31, L33, L34 DESCRIPTION 18 4.7FH ±10% inductors (0805) Murata LQM21NN4R7K10 R1–R10, R12, R15–R18, R20, R21, R22 18 150I Q1% resistors (0402) R11 1 49.9I Q1% resistor (0402) R13 1 10.5I Q1% resistor (0402) R14 1 33.2I Q1% resistor (0402) R19 1 499I Q1% resistor (0402) C17 1 27pF Q10% ceramic capacitor (0402) C25 1 33pF Q10% ceramic capacitor (0402) S1–S17 17 Switches, SP3T, slide ALPS SSS211900 C26 1 10FF Q10% ceramic capacitor (0603) S18–S21 4 Switches, SPDT, slide E-Switch EG1218 C33 1 3pF Q10% ceramic capacitor (0402) TP1, TP2 2 Test points Keystone 5000 J1–J9, J11, J13–J24 U1 1 22 SMA connectors, edge-mount, tab contact Johnson 142-0701-851 Clock generator (48 TQFN-EP*) Microsemi MAX3636ETM+ U2 1 25MHz crystal NDK EXS00A-AT00429 J10, J12 2 — 1 PCB: MAX3636 EVALUATION BOARD+, REV A L1, L4, L5, L8, L9, L11, L13, L16, L17, L20, L21, L24, L25, L28, L29, L32, L35, L36 Test points Keystone 5000 *EP = Exposed pad. 18 _ Ferrite beads (0402) Murata BLM15HD102SN1   1 Evaluates: MAX3636 General Description Evaluates: MAX3636 MAX3636 Evaluation Kit Quick Start 1) S  et the switches to the following settings to generate a 156.25MHz LVDS output from the 25MHz crystal reference: IN_SEL = XO PLL_BP = LOW Differential Clock Input The differential clock input, DIN, is AC-coupled at the SMA connectors and has an internal 100I differential termination. For optimal performance it is important to use a low-jitter, differential, square-wave clock source. Clock signals should be applied to DIN only when the switch IN_SEL is set to DIN. DM = LOW LVDS/LVPECL Clock Outputs DP1 = LOW, DP0 = HIGH DF1 = LOW, DF0 = LOW DA1 = HIGH, DA0 = LOW DB1 = HIGH, DB0 = LOW DC1 = HIGH, DC0 = LOW QA_CTRL1 = LVDS QA_CTRL2 = DISABLED QB_CTRL = DISABLED QC_CTRL = DISABLED The LVDS/LVPECL clock outputs (QA[4:0], QB[2:0], QC) are configured using switches S14–S21. Each output has an on-board bias-T, which provides DC bias when configured as LVPECL and AC-coupling for direct connection to 50I-terminated test equipment. Unused outputs should be disabled (using switches S14–S17) or have 50I terminations placed on the SMA connectors. For optimal jitter measurements, a balun is recommended for differential to single-ended conversion when connected to single-ended test equipment such as a phase noise analyzer. See Figure 1 for the measurement setup. QA_TERM1 = LVDS QA_TERM2 = LVDS PHASE NOISE ANALYZER QB_TERM = LVDS QC_TERM = LVDS 2) C  onnect a 3.3V supply to VCC (J10) and GND (J12). Set the supply current limit to 500mA. MAX3636 EVALUATION BOARD Q_ BALUN Q_ 3) U  sing SMA cables, connect QA0 (J11) and QA0 (J13) to a phase noise analyzer or scope. Terminate all unused enabled outputs, QA1 (J14), QA1 (J15), QA2 (J16), and QA2 (J17). SCOPE Detailed Description The MAX3636 EV kit simplifies evaluation by providing the hardware needed to evaluate all the MAX3636 functions. Table 1 contains functional descriptions for the switches. Table 2 provides the divider settings for various frequency configurations. MAX3636 EVALUATION BOARD Q_ Q_ LVCMOS Clock Input The LVCMOS clock input, CIN, is AC-coupled at the SMA connector and has an on-board 50I termination. For optimal performance it is important to use a low-jitter square-wave clock source. Clock signals should be applied to CIN only when the switch IN_SEL is set to CIN. 2 Figure 1. Measurement Setup MAX3636 Evaluation Kit ment, or a high-Z (1MI) scope probe. If connected to 50I test equipment, the output swing at the termination is approximately 275mVP-P. Table 1. Switch Descriptions COMPONENT NAME FUNCTION IN_SEL Selects input reference clock source. DIN = Differential input DIN, DIN CIN = LVCMOS input CIN XO = Crystal reference (25MHz on-board) S2 PLL_BP Selects PLL bypass mode. HIGH = All outputs PLL bypass OPEN = C output bank PLL bypass LOW = All outputs PLL enabled S3 DM Selects input divider M. See Table 2. S4, S5 DP1, DP0 Selects VCO prescale divider P. See Table 2. S6, S7 DF1, DF0 Selects feedback divider F. See Table 2. S8, S9 DA1, DA0 Selects output divider A. See Table 2. S10, S11 DB1, DB0 Selects output divider B. See Table 2. S12, S13 DC1, DC0 Selects output divider C. See Table 2. S14 QA_CTRL1 Selects QA[2:0] output interface (LVPECL, LVDS, or DISABLED). S15 QA_CTRL2 Selects QA[4:3] output interface (LVPECL, LVDS, or DISABLED). S16 QB_CTRL Selects QB[2:0] output interface (LVPECL, LVDS, or DISABLED). S17 QC_CTRL Selects QC and QCC output interface. LVPECL = QC output LVPECL, QCC output LVCMOS DISABLED = QC and QCC disabled LVDS = QC output LVDS, QCC output LVCMOS S18 QA_TERM1 Selects QA[2:0] output termination. Provides DC path to GND for QA[2:0] bias-Ts when switched to LVPECL. DC path to GND is open when switched to LVDS. S19 QA_TERM2 Selects QA[4:3] output termination. Provides DC path to GND for QA[4:3] bias-Ts when switched to LVPECL. DC path to GND is open when switched to LVDS. S20 QB_TERM Selects QB[2:0] output termination. Provides DC path to GND for QB[2:0] bias-Ts when switched to LVPECL. DC path to GND is open when switched to LVDS. S21 QC_TERM Selects QC output termination. Provides DC path to GND for QC bias-Ts when switched to LVPECL. DC path to GND is open when switched to LVDS. S1 3 Evaluates: MAX3636 LVCMOS Clock Output The LVCMOS clock output, QCC, has a 500I series load resistor and is AC-coupled at the SMA connector. This output can be connected to 50I-terminated test equip- Evaluates: MAX3636 MAX3636 Evaluation Kit Table 2. Divider Settings for Various Frequency Configurations INPUT INPUT DIVIDER FREQUENCY (MHz) DM 19.44 LOW FEEDBACK DIVIDER DF1 DF0 HIGH HIGH 38.88 LOW HIGH LOW 155.52 OPEN HIGH LOW VCO FREQUENCY (MHz) 3732.48 PRESCALE DIVIDER DP1 LOW DP0 HIGH OUTPUT DIVIDER OUTPUT FREQUENCY APPLICATIONS (MHz) DA1 DB1 DA0 DB0 OPEN OPEN 622.08 LOW LOW 311.04 LOW HIGH 155.52 HIGH OPEN 77.76 LOW OPEN 38.88 25 LOW LOW LOW OPEN OPEN 625 31.25 LOW LOW HIGH LOW LOW 312.5 62.5 OPEN LOW OPEN 125 HIGH LOW LOW 3750 LOW HIGH LOW HIGH 156.25 HIGH LOW 125 62.5 156.25 HIGH LOW HIGH OPEN HIGH 26.04166 LOW HIGH OPEN OPEN LOW 25 25 LOW OPEN HIGH OPEN OPEN 750 31.25 LOW HIGH OPEN LOW LOW 375 62.5 OPEN OPEN LOW 125 OPEN HIGH OPEN 156.25 HIGH HIGH OPEN 15.36 LOW OPEN LOW 30.72 LOW HIGH OPEN 61.44 OPEN OPEN LOW 122.88 OPEN HIGH OPEN 15.36 LOW LOW 19.2 LOW 30.72 3750 3686.4 LOW LOW LOW LOW LOW HIGH 187.5 HIGH LOW 150 HIGH HIGH 125 OPEN HIGH 75 OPEN LOW 30 OPEN OPEN 737.28 LOW LOW 368.64 LOW HIGH 184.32 HIGH HIGH 122.88 HIGH OPEN 92.16 OPEN OPEN OPEN 614.4 HIGH HIGH LOW LOW 307.2 LOW LOW HIGH LOW HIGH 153.6 3686.4 LOW HIGH 38.4 LOW HIGH LOW HIGH LOW 122.88 61.44 OPEN LOW OPEN HIGH HIGH 102.4 76.8 OPEN HIGH HIGH HIGH OPEN 76.8 122.88 OPEN LOW HIGH OPEN HIGH 61.44 30.72 LOW HIGH LOW OPEN OPEN 491.52 LOW LOW 245.76 122.88 153.6 OPEN HIGH HIGH HIGH LOW LOW 3932.16 OPEN OPEN LOW HIGH 122.88 HIGH OPEN 61.44 LOW OPEN 30.72 cdma2000 is a registered trademark of the Telecommunications Industry Association. WiMAX is a trademark of WiMAX Forum. 4  _ SONET/SDH, STM-N Ethernet Various Wireless Base Station: WCDMA, cdma2000®, LTE, TD_SCDMA, WiMAX™, GSM MAX3636 Evaluation Kit INPUT INPUT DIVIDER FREQUENCY (MHz) DM 26 LOW FEEDBACK DIVIDER DF1 DF0 HIGH LOW VCO FREQUENCY (MHz) 3744 52 26.5625 OPEN LOW 26.5625 LOW 33.3 LOW 133.33 OPEN 166.67 HIGH 25 LOW 100 OPEN 125 HIGH 33.3 LOW 133.33 OPEN 166.67 HIGH 25 LOW 100 OPEN 125 HIGH 31.25 LOW 125 OPEN 156.25 HIGH 15.625 LOW 62.5 OPEN 78.125 HIGH 66.67 OPEN 33.3 LOW 133.33 OPEN 166.67 HIGH 32.76 LOW HIGH HIGH HIGH HIGH OPEN LOW HIGH HIGH OPEN LOW 3825 3825 LOW LOW LOW DP0 OPEN HIGH LOW OPEN OPEN OPEN HIGH HIGH HIGH HIGH OPEN 4000 HIGH LOW HIGH HIGH 4000 OPEN DP1 HIGH 4000 HIGH PRESCALE DIVIDER OPEN OPEN HIGH HIGH HIGH 4000 3931.2 HIGH HIGH OPEN OPEN OUTPUT DIVIDER OUTPUT FREQUENCY APPLICATIONS (MHz) DA1 DB1 DA0 DB0 OPEN OPEN 416 LOW HIGH 104 HIGH OPEN 52 LOW OPEN 26 LOW LOW 318.75 LOW HIGH 159.375 HIGH HIGH 106.25 LOW LOW 212.5 LOW HIGH 106.25 HIGH OPEN 53.125 LOW LOW 400 LOW HIGH 200 HIGH HIGH 133.333 HIGH OPEN 100 LOW OPEN 50 LOW LOW 500 LOW HIGH 250 HIGH LOW 200 HIGH HIGH 166.67 HIGH OPEN 125 OPEN HIGH 100 OPEN LOW 40 LOW LOW 250 LOW HIGH 125 HIGH LOW 100 HIGH OPEN 62.5 OPEN HIGH 50 OPEN LOW 20 LOW LOW 333.33 LOW HIGH 166.67 HIGH LOW 133.33 83.33 HIGH OPEN OPEN HIGH 66.67 HIGH LOW 131.04 OPEN HIGH 65.52 GSM FC-SAN Server, FB-DIMM, Network Processor, DDR/ QDR Memory, PCIe®, SATA Server, FB-DIMM, Network Processor, DDR/ QDR Memory, PCIe, SATA Various Microwave Radio Link PCIe is a registered trademark of PCI-SIG Corp.   5 Evaluates: MAX3636 Table 2. Divider Settings for Various Frequency Configurations (continued) C23 0.1uF DP1 DP0 10 11 12 DB1 C26 10uF QC_CTRL DP1 VCC DP0 VCC S5 DF1 S6 VCC VCC DA1 S8 VCC DF0 DA0 DB1 S10 QA_CTRL1 38 37 VCCQB 40 39 QB0 QB0 43 42 41 QB2 QB1 QB1 36 35 34 33 32 L10 L9 R5 4.7uH 150Ω 1% FERRITE BEAD QB_TERM 31 30 29 28 27 26 25 S11 VCC S12 DC1 VCC DC0 L14 L13 R7 4.7uH 150Ω 1% FERRITE BEAD QA_TERM1 VCC QA_CTRL1 VCC QA_CTRL2 S15 VCC QB_CTRL S16 QA_TERM1 C28 0.1uF QB_TERM S18 S20 QA_TERM2 QC_TERM S19 S21 L19 R10 L20 4.7uH 150Ω 1% FERRITE BEAD L22 L21 R12 4.7uH 150Ω 1% FERRITE BEAD S13 C5 0.1uF C6 0.1uF C7 0.1uF C8 0.1uF C9 0.1uF QB2 J4 QB2 J5 QB1 J6 QB1 J7 QB0 J8 QB0 J9 QA0 C10 J11 0.1uF C14 0.1uF QA0 J13 L23 R15 L24 4.7uH 150Ω 1% FERRITE BEAD QA1 C15 J14 0.1uF C16 0.1uF QA1 J15 QA2 C22 J16 0.1uF C29 0.1uF QA2 J17 VCC QC_CTRL QC J22 QC J23 C35 0.1uF C36 0.1uF L26 L25 R16 4.7uH 150Ω 1% FERRITE BEAD R19 499Ω 1% S17 QCC J21 QA_TERM1 L15 R8 L16 4.7uH 150Ω 1% FERRITE BEAD L18 L17 R9 4.7uH 150Ω 1% FERRITE BEAD QA_TERM1 S14 L12 R6 L11 4.7uH 150Ω 1% FERRITE BEAD C4 0.1uF EP C27 0.1uF R14 33.2Ω 1% L7 R4 L8 4.7uH 150Ω 1% FERRITE BEAD C21 0.1uF VCC VCC DB0 MAX3636ETM+ S7 VCC S9 QB_CTRL 13 14 15 VCC S4 QA2 QA2 QA3 QA3 QA4 QA4 VCCQA VCCQC R13 10.5Ω 1% QA0 QA0 QA1 QA1 U1 PLL_BP DF1 DF0 QC_CTRL VCCA DP1 DP0 QB_TERM VCC VCCQA L3 R2 L4 4.7uH 150Ω 1% FERRITE BEAD L6 L5 R3 4.7uH 150Ω 1% FERRITE BEAD C20 0.1uF 23 24 DM S3 6 7 8 9 XIN XOUT VCC IN_SEL QC QC S2 IN_SEL PLL_BP DF1 DF0 DM 21 22 PLL_BP C24 0.1uF VCC 1 2 3 4 5 QA_CTRL2 VCC VCC QA_CTRL2 VCCQCC QCC DM C25 33pF VCC 18 19 20 S1 CIN U2 25MHz CRYSTAL 45 44 48 47 46 C17 27pF VCC IN_SEL C18 0.1uF R11 C19 49.9Ω 0.1uF 1% DC1 DC0 VCC C1 0.1uF 16 17 J12 CIN J1 QB_TERM QA_CTRL1 QB2 DIN J2 C12 0.1uF TP2 DC1 DC0 C11 2.2uF L2 L1 R1 4.7uH 150Ω 1% FERRITE BEAD C2 0.1uF DIN DIN QB_CTRL GND C3 0.1uF DIN J3 DB0 DA1 DA0 C13 33uF J10 VCC TP1 +3.3V DB0 DA1 DA0 VCC DB1 Evaluates: MAX3636 MAX3636 Evaluation Kit C34 0.1uF QA_TERM2 C33 3pF L32 L33 R20 FERRITE BEAD 150Ω 1% 4.7uH L35 R21 L34 FERRITE BEAD 150Ω 1% 4.7uH L27 R17 L28 4.7uH 150Ω 1% FERRITE BEAD L30 L29 R18 4.7uH 150Ω 1% FERRITE BEAD QC_TERM QA_TERM2 L31 R22 L36 4.7uH 150Ω 1% FERRITE BEAD Figure 2. MAX3636 EV Kit Schematic 6  _______________________________________________________________________________________ QA3 C30 J18 0.1uF C31 0.1uF QA3 J19 QA4 C32 J20 0.1uF C37 0.1uF QA4 J24 MAX3636 Evaluation Kit Evaluates: MAX3636 7125mil 5930mil Figure 3. MAX3636 EV Kit Component Placement Guide—Component Side _______________________________________________________________________________________  7 Evaluates: MAX3636 MAX3636 Evaluation Kit Figure 4. MAX3636 EV Kit PCB Layout—Component Side 8  _______________________________________________________________________________________ MAX3636 Evaluation Kit Evaluates: MAX3636 Figure 5. MAX3636 EV Kit PCB Layout—Ground Plane _______________________________________________________________________________________  9 Evaluates: MAX3636 MAX3636 Evaluation Kit Figure 6. MAX3636 EV Kit PCB Layout—Power Plane 10   ������������������������������������������������������������������������������������� MAX3636 Evaluation Kit Evaluates: MAX3636 Figure 7. MAX3636 EV Kit PCB Layout—Solder Side ______________________________________________________________________________________  11 Evaluates: MAX3636 MAX3636 Evaluation Kit Revision History REVISION NUMBER REVISION DATE 0 2/12 DESCRIPTION Initial release 12 PAGES CHANGED — Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at www.microsemi.com. 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