MAX3638EVKIT+

19-5270; Rev 1; 5/10 EVALUATION KIT AVAILABLE MAX3638 Evaluation Kit The MAX3638 evaluation kit (EV kit) is a fully assembled and tested demonstration board that simplifies evaluation of the MAX3638 low-jitter, wide-frequency range clock generator. The EV kit includes an on-board 25MHz crystal and switches for selecting different modes of operation. The reference inputs and clock outputs use SMA connectors and are AC-coupled to simplify connection to test equipment. EV Kit Contents S MAX3638 EV Kit Board Features S Fully Assembled and Tested S On-Board 25MHz Crystal S Switches for Selecting Modes of Operation S SMA Connectors and AC-Coupled Clock I/Os Ordering Information PART TYPE MAX3638EVKIT+ EV Kit +Denotes lead(Pb)-free and RoHS compliant. Component List DESIGNATION QTY DESCRIPTION C1–C10, C14, C15, C16, C18–C24, C27– C32, C34–C37 30 0.1FF Q10% ceramic capacitors (0402) C11 1 2.2FF Q10% ceramic capacitor (0603) C12 1 0.1FF Q10% ceramic capacitor (0603) C13 1 33FF Q10% tantalum capacitor (B case) AVX TAJB336K010R DESIGNATION QTY L2, L3, L6, L7, L10, L12, L14, L15, L18, L19, L22, L23, L26, L27, L30, L31, L33, L34 DESCRIPTION 18 4.7FH Q10% inductors (0805) Murata LQM21NN4R7K10 R1–R10, R12, R15–R18, R20, R21, R22 18 150I Q1% resistors (0402) R11 1 49.9I Q1% resistor (0402) R13 1 10.5I Q1% resistor (0402) R14 1 33.2I Q1% resistor (0402) R19 1 499I Q1% resistor (0402) S1, S2, S3, S5–S17 16 Switches, SP3T, slide ALPS SSS211900 C17 1 27pF Q10% ceramic capacitor (0402) C25 1 33pF Q10% ceramic capacitor (0402) C26 1 10FF Q10% ceramic capacitor (0603) S18–S21 4 Switches, SPDT, slide E-Switch EG1218 C33 1 3pF Q10% ceramic capacitor (0402) TP1, TP2 2 Test points Keystone 5000 J1–J9, J11, J13–J24 U1 1 22 SMA connectors, edge-mount, tab contact Johnson 142-0701-851 Clock generator (48 TQFN-EP*) Microsemi Maxim MAX3638ETM+ U2 1 25MHz crystal NDK EXS00A-AT00429 J10, J12 2 — 1 PCB: MAX3638 EVALUATION BOARD+, REV B L1, L4, L5, L8, L9, L11, L13, L16, L17, L20, L21, L24, L25, L28, L29, L32, L35, L36 Test points Keystone 5000 *EP = Exposed pad. 18 Ferrite beads (0402) Murata BLM15HD102SN1    1 Evaluates: MAX3638 General Description Evaluates: MAX3638 MAX3638 Evaluation Kit Quick Start 1) S  et the switches to the following settings to generate a 125MHz LVDS output from the 25MHz crystal reference: IN_SEL = XO PLL_BP = LOW Differential Clock Input The differential clock input, DIN, is AC-coupled at the SMA connectors and has an internal 100I differential termination. For optimal performance it is important to use a low-jitter, differential, square-wave clock source. Clock signals should be applied to DIN only when the switch IN_SEL is set to DIN. DM = LOW LVDS/LVPECL Clock Outputs DP = LOW DF1 = LOW, DF0 = OPEN DA1 = OPEN, DA0 = HIGH DB1 = OPEN, DB0 = HIGH DC1 = HIGH, DC0 = LOW QA_CTRL1 = LVDS QA_CTRL2 = DISABLED QB_CTRL = DISABLED QC_CTRL = DISABLED The LVDS/LVPECL clock outputs (QA[4:0], QB[2:0], QC) are configured using switches S14–S21. Each output has an on-board bias-T, which provides DC bias when configured as LVPECL and AC-coupling for direct connection to 50I-terminated test equipment. Unused outputs should be disabled (using switches S14–S17) or have 50I terminations placed on the SMA connectors. For optimal jitter measurements, a balun is recommended for differential to single-ended conversion when connected to single-ended test equipment such as a phase noise analyzer. See Figure 1 for the measurement setup. QA_TERM1 = LVDS QA_TERM2 = LVDS PHASE NOISE ANALYZER QB_TERM = LVDS QC_TERM = LVDS 2) C  onnect a +3.3V supply to VCC (J10) and GND (J12). Set the supply current limit to 500mA. MAX3638 EVALUATION BOARD Q_ BALUN Q_ 3) U  sing SMA cables, connect QA0 (J11) and QA0 (J13) to a phase noise analyzer or scope. Terminate all unused enabled outputs, QA1 (J14), QA1 (J15), QA2 (J16), and QA2 (J17). SCOPE Detailed Description The MAX3638 EV kit simplifies evaluation by providing the hardware needed to evaluate all the MAX3638 functions. Table 1 contains functional descriptions for the switches. Table 2 provides the divider settings for various frequency configurations. MAX3638 EVALUATION BOARD Q_ Q_ LVCMOS Clock Input The LVCMOS clock input, CIN, is AC-coupled at the SMA connector and has an on-board 50I termination. For optimal performance it is important to use a low-jitter square-wave clock source. Clock signals should be applied to CIN only when the switch IN_SEL is set to CIN. 2   _ Figure 1. Measurement Setup MAX3638 Evaluation Kit ment, or a high-Z (1MI) scope probe. If connected to 50I test equipment, the output swing at the termination is approximately 275mVP-P. Table 1. Switch Descriptions COMPONENT NAME FUNCTION IN_SEL Selects input reference clock source. DIN = Differential input DIN, DIN CIN = LVCMOS input CIN XO = Crystal reference (25MHz on-board) S2 PLL_BP Selects PLL bypass mode. HIGH = All outputs PLL bypass OPEN = C output bank PLL bypass LOW = All outputs PLL enabled S3 DM Selects input divider M. See Table 2. Selects VCO prescale divider P. See Table 2. S1 S5 DP S6, S7 DF1, DF0 Selects feedback divider F. See Table 2. S8, S9 DA1, DA0 Selects output divider A. See Table 2. S10, S11 DB1, DB0 Selects output divider B. See Table 2. S12, S13 DC1, DC0 Selects output divider C. See Table 2. S14 QA_CTRL1 Selects QA[2:0] output interface (LVPECL, LVDS, or DISABLED). S15 QA_CTRL2 Selects QA[4:3] output interface (LVPECL, LVDS, or DISABLED). S16 QB_CTRL Selects QB[2:0] output interface (LVPECL, LVDS, or DISABLED). S17 QC_CTRL Selects QC and QCC output interface. LVPECL = QC output LVPECL, QCC output LVCMOS DISABLED = QC and QCC disabled LVDS = QC output LVDS, QCC output LVCMOS S18 QA_TERM1 Selects QA[2:0] output termination. Provides DC path to GND for QA[2:0] bias-Ts when switched to LVPECL. DC path to GND is open when switched to LVDS. S19 QA_TERM2 Selects QA[4:3] output termination. Provides DC path to GND for QA[4:3] bias-Ts when switched to LVPECL. DC path to GND is open when switched to LVDS. S20 QB_TERM Selects QB[2:0] output termination. Provides DC path to GND for QB[2:0] bias-Ts when switched to LVPECL. DC path to GND is open when switched to LVDS. S21 QC_TERM Selects QC output termination. Provides DC path to GND for QC bias-Ts when switched to LVPECL. DC path to GND is open when switched to LVDS.    3 Evaluates: MAX3638 LVCMOS Clock Output The LVCMOS clock output, QCC, has a 500I series load resistor and is AC-coupled at the SMA connector. This output can be connected to 50I-terminated test equip- Evaluates: MAX3638 MAX3638 Evaluation Kit Table 2. Divider Settings for Various Frequency Configurations INPUT FREQUENCY (MHz) INPUT DIVIDER FEEDBACK DIVIDER VCO FREQUENCY (MHz) PRESCALE DIVIDER DA0 DB0 DC0 LOW LOW 491.52 HIGH LOW 245.76 HIGH 122.88 DF1 DF0 30.72 LOW HIGH HIGH 61.44 HIGH HIGH HIGH 122.88 OPEN HIGH HIGH OPEN LOW OUTPUT* FREQUENCY (MHz) DA1 DB1 DC1 DM 3932.16 DP OUTPUT DIVIDER 33.3 LOW HIGH OPEN LOW LOW 400 66.7 HIGH HIGH OPEN LOW HIGH 266.67 133.3 OPEN HIGH OPEN 25 LOW HIGH HIGH 4000 HIGH HIGH LOW 200 HIGH OPEN 133.333 50 HIGH HIGH HIGH OPEN HIGH 100 100 OPEN HIGH HIGH OPEN LOW 66.67 33.3 LOW OPEN HIGH LOW LOW 500 66.7 HIGH OPEN HIGH LOW HIGH 333.33 133.3 OPEN OPEN HIGH HIGH LOW 250 25 LOW LOW OPEN HIGH HIGH 200 50 HIGH LOW OPEN HIGH OPEN 166.67 100 OPEN LOW OPEN OPEN HIGH 125 31.25 LOW HIGH HIGH LOW OPEN 100 62.5 HIGH HIGH HIGH OPEN OPEN 66.67 125 OPEN HIGH HIGH 32.76 LOW HIGH OPEN 20.82857 LOW HIGH HIGH 41.6571 LOW HIGH LOW 25.78125 LOW LOW 27.392578 LOW 20.916 LOW 41.8329 LOW 4000 LOW 3931.2 HIGH 3999.084 OPEN LOW 3867.1875 HIGH OPEN HIGH HIGH HIGH LOW OPEN 50** OPEN LOW 33.33** HIGH OPEN 131.04 OPEN LOW 65.52 Wireless Base Station: WCDMA, cdma2000®, LTE, TD_SCDMA Server, FB-DIMM, Network Processor, DDR/ QDR Memory, PCIe®, SATA Microwave Radio Link LOW LOW 333.257 HIGH LOW 166.6285 OPEN HIGH LOW 161.1328125 10Gbps Ethernet with FEC 3944.531232 OPEN HIGH LOW 164.355468 10Gbps FC LOW LOW 334.66 4015.95949 OPEN HIGH LOW 167.33 LOW *All output divider settings applicable only for A and B output banks, unless otherwise noted. **Output divider settings applicable only for C output bank. cdma2000 is a registered trademark of the Telecommunications Industry Association. PCIe is a registered trademark of PCI-SIG Corp. 4   _ APPLICATIONS OTU1, 10Gbps SONET with FEC OTU2, 10Gbps SONET with Digital Wrapper MAX3638 Evaluation Kit DP DF1 VCC DA1 S8 VCC VCC DF0 DA0 DB1 S10 38 37 VCCQB 40 39 QB0 QB0 QB2 QB1 QB1 QB_CTRL QA_CTRL1 QA4 QA4 VCCQA 36 35 34 33 32 L10 L9 R5 4.7uH 150Ω 1% FERRITE BEAD QB_TERM 31 30 29 28 27 26 25 S11 VCC S12 DC1 VCC DC0 L14 L13 R7 4.7uH 150Ω 1% FERRITE BEAD QA_TERM1 VCC QA_CTRL1 VCC QA_CTRL2 S15 VCC QB_CTRL S16 QA_TERM1 C28 0.1uF QB_TERM S18 S20 QA_TERM2 QC_TERM S19 S21 L19 R10 L20 4.7uH 150Ω 1% FERRITE BEAD L22 L21 R12 4.7uH 150Ω 1% FERRITE BEAD S13 C5 0.1uF C6 0.1uF C7 0.1uF C8 0.1uF C9 0.1uF QB2 J4 QB2 J5 QB1 J6 QB1 J7 QB0 J8 QB0 J9 QA0 C10 J11 0.1uF C14 0.1uF QA0 J13 L23 R15 L24 4.7uH 150Ω 1% FERRITE BEAD QA1 C15 J14 0.1uF C16 0.1uF QA1 J15 QA2 C22 J16 0.1uF C29 0.1uF QA2 J17 VCC QC_CTRL QC J22 QC J23 C35 0.1uF C36 0.1uF L26 L25 R16 4.7uH 150Ω 1% FERRITE BEAD R19 499Ω 1% S17 QCC J21 QA_TERM1 L15 R8 L16 4.7uH 150Ω 1% FERRITE BEAD L18 L17 R9 4.7uH 150Ω 1% FERRITE BEAD QA_TERM1 S14 L12 R6 L11 4.7uH 150Ω 1% FERRITE BEAD C4 0.1uF EP C27 0.1uF R14 33.2Ω 1% L7 R4 L8 4.7uH 150Ω 1% FERRITE BEAD C21 0.1uF VCC VCC DB0 43 42 41 VCCA RES DP QA2 QA3 QA3 S7 VCC S9 MAX3638ETM+ DF1 DF0 QC_CTRL DB1 DP VCC S6 U1 13 14 15 VCC S5 QA0 QA0 QA1 QA1 QA2 VCCQC C23 0.1uF 9 10 11 12 DB1 C26 10uF DF1 DF0 QC_CTRL QB_TERM VCC VCCQA L3 R2 L4 4.7uH 150Ω 1% FERRITE BEAD L6 L5 R3 4.7uH 150Ω 1% FERRITE BEAD C20 0.1uF 23 24 R13 10.5Ω 1% 6 7 8 XIN XOUT VCC IN_SEL PLL_BP QC QC DM S3 4 5 DM QA_CTRL2 VCCQCC QCC S2 IN_SEL PLL_BP 2 3 21 22 PLL_BP C24 0.1uF VCC 1 QA_CTRL2 VCC VCC 18 19 20 DM C25 33pF VCC DC1 DC0 S1 CIN U2 25MHz CRYSTAL 45 44 48 47 46 C17 27pF VCC IN_SEL C18 0.1uF R11 C19 49.9Ω 0.1uF 1% DC1 DC0 VCC 16 17 J12 CIN J1 C1 0.1uF QA_CTRL1 QB2 DIN J2 C12 0.1uF TP2 QB_TERM DIN DIN QB_CTRL C11 2.2uF L2 L1 R1 4.7uH 150Ω 1% FERRITE BEAD C2 0.1uF DB0 DA1 DA0 GND C3 0.1uF DIN J3 DB0 DA1 DA0 C13 33uF J10 VCC TP1 +3.3V C34 0.1uF QA_TERM2 C33 3pF L30 L29 R18 4.7uH 150Ω 1% FERRITE BEAD L32 L33 R20 FERRITE BEAD 150Ω 1% 4.7uH L35 R21 L34 FERRITE BEAD 150Ω 1% 4.7uH L27 R17 L28 4.7uH 150Ω 1% FERRITE BEAD QC_TERM QA_TERM2 L31 R22 L36 4.7uH 150Ω 1% FERRITE BEAD QA3 C30 J18 0.1uF C31 0.1uF QA3 J19 QA4 C32 J20 0.1uF C37 0.1uF QA4 J24 Figure 2. MAX3638 EV Kit Schematic    5 Evaluates: MAX3638 VCC Evaluates: MAX3638 MAX3638 Evaluation Kit Figure 3. MAX3638 EV Kit Component Placement Guide—Component Side 6   _ MAX3638 Evaluation Kit Evaluates: MAX3638 Figure 4. MAX3638 EV Kit PCB Layout—Component Side    7 Evaluates: MAX3638 MAX3638 Evaluation Kit Figure 5. MAX3638 EV Kit PCB Layout—Ground Plane 8   _ MAX3638 Evaluation Kit Evaluates: MAX3638 Figure 6. MAX3638 EV Kit PCB Layout—Power Plane    9 Evaluates: MAX3638 MAX3638 Evaluation Kit Figure 7. MAX3638 EV Kit PCB Layout—Solder Side 10   MAX3638 Evaluation Kit REVISION NUMBER REVISION DATE 0 5/10 Initial release 5/10 Changed R13 from 10.0Ω to 10.5Ω in the Component List and Figure 2; corrected the label for L28 in Figure 2 1 DESCRIPTION PAGES CHANGED — 1, 5 11 Evaluates: MAX3638 Revision History Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 © 2012 Microsemi Corporation. All rights reserved. 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