MAX3678UTN+

19-4115; Rev 0; 5/08 EVALUATION KIT AVAILABLE Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching Features The MAX3678 is a low-jitter frequency synthesizer with intelligent dynamic clock switching optimized for systems where redundant clock failover switching is needed. It contains a monolithic phase-locked loop (PLL) that accepts two reference clock inputs and generates nine phase-aligned outputs. The device continuously monitors the signal status for both reference clock inputs. In the event that the primary clock fails, the PLL automatically switches to the secondary clock input without generating a phase bump at the clock outputs, using a glitchless switchover mechanism. A manual switch mode is also provided for user-controlled switching. The device features ultra-low jitter generation of 0.3psRMS (integrated 12kHz to 20MHz) and excellent power-supply noise rejection. The MAX3678 operates from a single +3.3V supply and typically consumes 400mW. The operating temperature range is from 0°C to +85°C, and is available in a 8mm x 8mm, 56-pin TQFN package. ♦ Two Reference Clock Inputs: LVPECL ♦ Nine Phase-Aligned Clock Outputs: LVPECL ♦ Automatic or Manual Dynamic Switching Between Two Reference Clock Inputs ♦ Input Frequencies: 66.67MHz, 133.33MHz, 266.67MHz, 333.33MHz ♦ Output Frequencies: 66.67MHz, 133.33MHz, 266.67MHz, 333.33MHz ♦ Low-Jitter Generation: 0.3psRMS (12kHz to 20MHz) ♦ Clock Failure Indicator for Both Reference Clocks ♦ External Feedback Provides Zero-Delay Capability ♦ Low Output Skew: 20ps Typical ♦ Typical Power Dissipation: 400mW at +3.3V ♦ Operating Temperature: 0°C to +85°C Ordering Information Applications Redundant Clock Distribution in Servers PART TEMP RANGE PIN-PACKAGE MAX3678UTN+ 0°C to +85°C 56 TQFN-EP* Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching Frequency Translation Jitter Cleanup and Frequency Synchronization Functional Diagram DM CPLL 0.1μF CREG 0.22μF DA REFCLK0 0 REFCLK0 DIV M REFCLK1 1 REFCLK1 PFD LPF VCO 66.67MHz DIV A PLL_BYPASS OUTA_EN 1 OUTA3 0 OUTA3 OUTA2 2.667GHz OUTA2 OUTA1 IN0FAIL OUTA1 IN1FAIL OUTA0 LOCK BUSY CLK_SELECTED OUTA0 INTELLIGENT DYNAMIC SWITCH (IDS) CONTROL DIV N OUTB_EN 1 OUTB4 0 OUTB4 SEL_CLK DIV B IDS_MODE OUTB3 MR OUTB3 OUTB2 1 OUTB2 0 OUTB1 OUTB1 MAX3678 OUTB0 OUTB0 FB_SEL FB_IN FB_IN DB 1 MAX3678 General Description MAX3678 Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching ABSOLUTE MAXIMUM RATINGS Supply Voltage Range (VCC, VCC_VCO)..............-0.3V to +4.0V LVPECL Output Current (OUTA[3:0], OUTA[3 : 0], OUTB[4:0], OUTB[4 : 0]) .............................-56mA All Other Pins (REFCLK0, REFCLK0, REFCLK1, REFCLK1, IN0FAIL, IN1FAIL, LOCK, BUSY, CLK_SELECTED, SEL_CLK, IDS_MODE, MR, RSVD, FB_SEL, FB_IN, FB_IN, DM, DA, DB, CPLL, CREG, PLL_BYPASS, OUTA_EN, OUTB_EN) ..............................................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70°C) 56-Pin TQFN (derate 47.6mW/°C above 70°C)..........3808mW Operating Junction Temperature (TJ)................-55°C to +150°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = 0°C to +85°C, CPLL = 0.1µF, CREG = 0.22µF. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) PARAMETER TYP MAX UNITS LVPECL outputs unterminated 120 175 mA VCC Rising (Note 1) 2.55 V VCC Falling (Note 1) 2.45 V Supply Current SYMBOL ICC CONDITIONS MIN POWER-ON RESET LVCMOS/LVTTL INPUTS (MR, SEL_CLK, IDS_MODE, PLL_BYPASS, FB_SEL) Input High Voltage VIH Input Low Voltage VIL 2.0 Input High Current I IH VIN = VCC Input Low Current IIL VIN = GND V 0.8 75 -75 V μA μA LVCMOS/LVTTL OUTPUTS (CLK_SELECTED, IN0FAIL, IN1FAIL, BUSY, LOCK) Output High Voltage VOH I OH = -8mA Output Low Voltage VOL I OL = +8mA 2.4 V 0.4 V VCC 0.7 V LVPECL INPUTS (REFCLK0, REFCLK0, REFCLK1, REFCLK1, FB_IN, FB_IN) (Note 2) Input High Voltage VIH Input Low Voltage VIL VCC 2.0 Input Bias Voltage VCMI VCC 1.8 Differential-Input Swing V VCC 1.34 0.15 V 1.9 VP-P Differential-Input Impedance > 40 k Common-Mode Input Impedance > 14 k Input Capacitance Input Current 2 1.5 VIH = VCC - 0.7V, VIL = VCC - 2.0V -100 _______________________________________________________________________________________ pF +100 μA Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching (VCC = +3.0V to +3.6V, TA = 0°C to +85°C, CPLL = 0.1µF, CREG = 0.22µF. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL Input Inrush Current When Power is Off (Steady State) IDC Input Inrush Current Overshoot When Power is Off CONDITIONS MIN TYP MAX UNITS (Notes 3, 4) 8 mA IOVERSHOOT (Notes 3, 4) 6 mA Table 1 MHz REFERENCE CLOCK INPUTS (REFCLK0, REFCLK0, REFCLK1, REFCLK1) Reference Clock Frequency fREF Reference Clock Frequency Tolerance (Note 5) Reference Clock Duty Cycle Reference Clock Amplitude Detection Assert Threshold VDT Differential swing (Notes 5, 6, 7) -25 +25 ppm 40 60 % 100 200 400 mVP-P LVPECL OUTPUTS (OUTA[3:0], OUTA[3:0], OUTB[4:0], OUTB[4:0]) (Note 8) Output High Voltage VOH VCC 1.13 VCC 0.98 VCC 0.83 V Output Low Voltage VOL VCC 1.85 VCC 1.70 VCC 1.55 V 1.1 1.45 1.8 VP-P 130 μA Differential-Output Swing Output Current When Disabled VO = VCC - 2.0V to VCC - 0.7V Output Frequency f OUT Output Rise/Fall Time tR, tF Output Duty Cycle Output-to-Output Skew Tables 2, 3 20% to 80% (Note 5) 150 MHz 600 ps PLL_BYPASS = 0 48 52 % PLL_BYPASS = 1 (Note 9) 45 55 % t SKEW 20 ps PLL Jitter Transfer Bandwidth 55 kHz Jitter Peaking 0.1 dB PFD Compare Frequency 66.67 MHz VCO Center Frequency 2.667 OTHER AC ELECTRICAL SPECIFICATIONS Random Jitter Generation Integrated 12kHz to 20MHz (Notes 5, 6) Determinisitic Jitter Caused by Power-Supply Noise (Note 10) Phase-Error Detection Window err Rate of Output Period Change Per Cycle
t/cycle Output Frequency Transient Relative to the Initial Lock Frequency |
f/f O| (Notes 5, 11) 0.3 GHz 1.0 5 ±0.5 ±0.75 psP-P ±1.0 150 ns ppm/ cycle 100 During PLL switching (Notes 5, 12) psRMS 600 ppm _______________________________________________________________________________________ 3 MAX3678 ELECTRICAL CHARACTERISTICS (continued) MAX3678 Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, TA = 0°C to +85°C, CPLL = 0.1µF, CREG = 0.22µF. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Frequency Difference Between Reference Clock and VCO Within Which the PLL is Considered in Lock 500 ppm Frequency Difference Between Reference Clock and VCO at Which the PLL is Considered Out-of-Lock 800 ppm 400 μs 100 ns PLL Lock Time tLOCK Figure 2 Master Reset (MR) Minimum Pulse Width Propagation Delay from Input to FB_IN FB_SEL = 1 (Notes 5, 13) Propagation Delay from Input to Any Output PLL_BYPASS = 1 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: 4 -100 +100 1.0 ps ns See the Power-On-Reset (POR) section for more information. LVPECL inputs can be AC- or DC-coupled. For hot-pluggable purposes, the device can receive LVPECL inputs when no supply voltage is applied. Measured with VCC pins connected to GND. See Figure 1. Measured with LVPECL input (VIH, VIL) as specified. Guaranteed by design and characterization. Measured using reference clock input with 550ps rise/fall time (20% to 80%). When input differential swing is below the specified threshold, a clock failure is declared. See Figure 8. LVPECL outputs terminated 50Ω to VTT = VCC - 2V. Measured with 50% duty cycle at reference clock input. Measured with 50mVP-P sinusoidal noise on the power supply, fNOISE = 100kHz. See the Phase Qualification section for more information. This specification is not met when the intelligent dynamic switch (IDS) operation follows that of Case 2b (Figure 4). Measured using 133.33MHz clock at reference input and feedback input with matched slew rates. _______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching MAX3678 INRUSH CURRENT (mA) IOVERSHOOT IDC t Figure 1. LVPECL Input Inrush Current Typical Operating Characteristics (VCC = 3.3V, TA = +25°C, unless otherwise noted.) -100 -110 -120 -130 -90 -100 -110 -120 -130 -80 -90 -100 -110 -120 -130 -140 -140 -150 -150 -150 -160 -160 -160 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (Hz) OFFSET FREQUENCY (Hz) JITTER TRANSFER RANDOM JITTER GENERATION vs. DIFFERENTIAL-INPUT SWING REFERENCE CLOCK AMPLITUDE DETECTION ASSERT THRESHOLD vs. INPUT FREQUENCY -5 -10 -15 -20 -25 fOUT = 133.33MHz INTEGRATED 12kHz TO 20MHz MANUAL SWITCH MODE 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 10k 100k JITTER FREQUENCY (Hz) 1M 280 260 INPUT RISE/FALL TIME = 540ps 240 220 200 180 INPUT RISE/FALL TIME = 270ps 160 140 120 0.0 -30 300 MAX3678 toc06 0 1.0 ASSERT THRESHOLD (mVP-P) MAX3678 toc04 5 1k 100 OFFSET FREQUENCY (Hz) MAX3678 toc05 1k RANDOM JITTER = 0.34psRMS INTEGRATED 12kHz TO 20MHz -70 -140 100 JITTER TRANSFER (dB) -80 PHASE NOISE (dBc/Hz) -90 RANDOM JITTER GENERATION (psRMS) PHASE NOISE (dBc/Hz) -80 RANDOM JITTER = 0.37psRMS INTEGRATED 12kHz TO 20MHz -70 PHASE NOISE (dBc/Hz) RANDOM JITTER = 0.31psRMS INTEGRATED 12kHz TO 20MHz PHASE NOISE AT 333.33MHz -60 MAX3678 toc03 MAX3678 toc01 -70 PHASE NOISE AT 266.67MHz -60 MAX3678 toc02 PHASE NOISE AT 133.33MHz -60 100 10 100 1000 DIFFERENTIAL INPUT SWING (mVP-P) 10,000 50 100 150 200 250 300 350 REFERENCE CLOCK INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 5 Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25°C, unless otherwise noted.) SWITCHING TRANSIENT (Δφ φ = 180°) (fREFCLK0 = fREFCLK1) SWITCHING TRANSIENT (Δf = 50ppm) fREFCLK1 = (fREFCLK0 + 50ppm) 150 100 50 0 PLL LOCKED TO REFCLK1 -50 PLL LOCKED TO REFCLK0 -100 FREQUENCY TRANSIENT 100 0 PHASE TRANSIENT 0 -90 PLL LOCKED TO REFCLK1 -180 -150 -270 PLL LOCKED TO REFCLK0 -200 -360 -25 0 25 50 75 125 100 -50 -25 0 25 TIME (μs) JITTER HISTOGRAM WITH SUPPLY NOISE (SUPPLY NOISE = 50mVP-P, 100kHz) MAX3678 toc09 DJ = 5psP-P 300 250 ALL OUTPUTS ENABLED AND UNTERMINATED 150 100 30 0 20 10 10 20 30 40 50 60 70 80 90 0 2ps/div TEMPERATURE (°C) -30 -40 SUPPLY NOISE = 100mVP-P -50 -60 -70 -80 100 150 SUPPLY NOISE = 50mVP-P -90 35 VCC 30 SUPPLY NOISE = 100mVP-P 25 OUTxx 20 15 SUPPLY NOISE = 50mVP-P 10 LOCK 0 100k 1M SUPPLY NOISE FREQUENCY (Hz) 250 300 POWER-ON-RESET TIMING 5 -100 10k 200 MAX3678 toc14 40 MAX3678 toc13 -20 DETERMINISTIC JITTER vs. POWER-SUPPLY NOISE FREQUENCY DETERMINISTIC JITTER (psP-P) MAX3678 toc12 fOUT = 133.33MHz 50 SUPPLY NOISE AMPLITUDE (mVP-P) SPURS CAUSED BY POWER-SUPPLY NOISE vs. SUPPLY NOISE FREQUENCY 6 fNOISE = 1MHz 15 0 0 -10 fNOISE = 200kHz 25 5 50 0 fNOISE = 100kHz 35 350 200 125 40 DETERMINISTIC JITTER (psP-P) SUPPLY CURRENT (mA) 400 100 DETERMINISTIC JITTER vs. POWER-SUPPLY NOISE AMPLITUDE MAX3678 toc10 ALL OUTPUTS ENABLED AND TERMINATED 75 TIME (μs) SUPPLY CURRENT vs. TEMPERATURE 500 50 MAX3678 toc11 -50 450 RELATIVE OUTPUT PHASE (degrees) 200 RELATIVE OUTPUT FREQUENCY (ppm) 250 MAX3678 toc08 200 MAX3678 toc07 RELATIVE OUTPUT FREQUENCY (ppm) 300 SPUR POWER (dBc) MAX3678 Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching 10M 10k 100k 1M 10M 200μs/div SUPPLY NOISE FREQUENCY (Hz) _______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching IDS-INITIATED SWITCH TIMING (fREFCLK1 = fREFCLK0 + 50ppm) CLOCK HOLDOVER TIMING (REFCLK0 OPEN, REFCLK1 TOGGLED ON/OFF) MASTER RESET TIMING MAX3678 toc15 MAX3678 toc17 MAX3678 toc16 REFCLK0 REFCLK1 MR IN0FAIL OUTxx IN1FAIL BUSY LOCK LOCK CLK_SELECTED 10μs/div 200μs/div 200μs/div Pin Description PIN NAME FUNCTION 1 IN0FAIL REFCLK0 Failure Indicator, LVCMOS/LVTTL Output. Low indicates REFCLK0 fails the clock qualification. Once a failed clock is detected, the indicator status is latched and updated every 128 PFD cycles (~ 2μs). 2 CLK_SELECTED Selected Reference Clock Indicator, LVCMOS/LVTTL Output. High indicates PLL is locked to REFCLK1. Low indicates PLL is locked to REFCLK0. 3 4 5 6 RSVD REFCLK0 REFCLK0 DM 7, 22, 30, 41, 49, 52 VCC Power Supply. Connect to +3.3V. 8, 14, 23, 29, 42, 48, 53 GND Supply Ground Reserved. Connect to GND. Reference Clock Input 0, Differential LVPECL Four-Level Control Input for Reference Clock Input Divider. See Table 1. Master Reset, LVCMOS/LVTTL Input. Connect this pin high or leave open for normal operation. Has internal 90k
pullup to VCC. Connect low to reset the device. A reset is not required at power-up. If the output divider settings are changed on the fly, a reset is required to phase align the outputs. This input has a 100ns minimum pulse width and is asynchronous to the reference clock. While in reset, all clock outputs are held to logiclow. See Table 6. 9 MR 10 11 REFCLK1 REFCLK1 Reference Clock Input 1, Differential LVPECL SEL_CLK Reference Clock Select, LVCMOS/LVTTL Input. Connect low or leave open to select REFCLK0 as the reference clock. Has internal 90k
pulldown to GND. Connect high to select REFCLK1 as the reference clock. In manual switch mode (IDS_MODE = 1), the PLL locks to a reference clock selected by the SEL_CLK pin. In automatic switch mode (IDS_MODE = 0), the PLL initially locks to a reference clock selected by the SEL_CLK pin, but the internal circuit can override this control input for automatic switchover when a reference clock failure is detected. See the Detailed Description section for more information. 12 _______________________________________________________________________________________ 7 MAX3678 Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25°C, unless otherwise noted.) Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching MAX3678 Pin Description (continued) PIN NAME 13 VCC_VCO 15 CPLL Connection for PLL Filter Capacitor. Connect a 0.1μF capacitor between this pin and GND. 16 CREG Connection for VCO Regulator Capacitor. Connect a 0.22μF capacitor between this pin and GND. 17 FB_SEL External Feedback Select, LVCMOS/LVTTL Input. Connect high to select external feedback for zero-delay buffer configuration. Connect low or leave open for internal feedback. Has internal 90k
pulldown to GND. 18 19 20 21 24 25 26 27 28 31 32 33 34 35 36 37 38 39 40 43 44 45 46 47 FB_IN FB_IN OUTB0 OUTB0 OUTB1 OUTB1 OUTB2 OUTB2 DB OUTB3 OUTB3 OUTB4 OUTB4 OUTB_EN OUTA_EN OUTA3 OUTA3 OUTA2 OUTA2 DA OUTA1 OUTA1 OUTA0 OUTA0 Power Supply for VCO. Connect to +3.3V. External Feedback Clock Input, Differential LVPECL. Used for zero-delay buffer configuration. Clock Output B0, Differential LVPECL Clock Output B1, Differential LVPECL Clock Output B2, Differential LVPECL Four-Level Control Input for B-Group Output Divider. See Table 3. Clock Output B3, Differential LVPECL Clock Output B4, Differential LVPECL Three-Level Control Input for B-Group Output Enable. See Table 5. Three-Level Control Input for A-Group Output Enable. See Table 4. Clock Output A3, Differential LVPECL Clock Output A2, Differential LVPECL Four-Level Control Input for A-Group Output Divider. See Table 2. Clock Output A1, Differential LVPECL Clock Output A0, Differential LVPECL PLL_BYPASS PLL Bypass Control, LVCMOS/LVTTL Input. Connect low or open for normal operation. Has internal 90k
pulldown to GND. Connect high to bypass the PLL, connecting the selected reference clock directly to the clock outputs. In this mode, the clock qualification function is not valid, and the device operates in manual mode for reference clock selection. 51 IDS_MODE Intelligent Dynamic Switch (IDS) Mode Control, LVCMOS/LVTTL Input. Connect high for manual switch mode. The internal automatic switch function is disabled, and the PLL locks to the reference clock selected by SEL_CLK. Connnect low or leave open for automatic switch mode. Has internal 90k
pulldown to GND. In automatic switch mode, the PLL initially locks to the reference clock selected by SEL_CLK, and automatically switches to the valid secondary clock input when the primary clock fails. See the Detailed Description section for more information. 54 BUSY Intelligent Dynamic Switch (IDS) Activity Indicator, LVCMOS/LVTTL Output. Low indicates the IDS is busy switching reference clocks. 55 LOCK PLL Lock Indicator, LVCMOS/LVTTL Output. Low indicates PLL is locked. 50 8 FUNCTION _______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching PIN NAME FUNCTION 56 IN1FAIL REFCLK1 Failure Indicator, LVCMOS/LVTTL Output. Low indicates REFCLK1 fails the clock qualification. Once a failed clock is detected, the indicator status is latched and updated every 128 PFD cycles (~ 2μs). — EP Exposed Pad. Connect to supply ground for proper electrical and thermal performance. Detailed Description The MAX3678 is a frequency synthesizer with intelligent dynamic clock switching designed specifically for systems with redundant clock routing. The device integrates two differential LVPECL reference inputs, IDS control, a PLL with configurable dividers, nine differential LVPECL clock outputs, and a selectable external feedback input for zero-delay buffer applications (see the Functional Diagram). The two reference clock inputs are continuously monitored for clock failure by the internal PLL and associated logic. If the primary clock fails, the PLL automatically switches to the secondary clock using a glitchless switchover mechanism. A manual switch mode is also provided for user-controlled switching. The PLL accepts reference input frequencies of 66.67MHz, 133.33MHz, 266.67MHz, or 333.33MHz and generates output frequencies of 66.67MHz, 133.33MHz, 266.67MHz, or 333.33MHz. The nine clock outputs are organized into two groups (A and B). Each group has a configurable frequency divider and output-enable control. Phase-Locked Loop (PLL) The PLL contains a phase-frequency detector (PFD), lowpass filter (LPF), and voltage-controlled oscillator (VCO). The PFD compares the divided reference frequency to the divided VCO output at 66.67MHz, and generates a control signal to keep the VCO phase and frequency locked to the selected reference clock. Using a high-frequency VCO (2.667GHz) and low-loop bandwidth (55kHz), the MAX3678 attenuates reference clock jitter while maintaining lock and generates low-jitter clock outputs at multiple frequencies. Typical jitter generation is 0.3psRMS (integrated 12kHz to 20MHz). To minimize supply noise-induced jitter, the VCO supply (VCC_VCO) is isolated from the core logic and output buffer supplies. Additionally, the MAX3678 uses an internal low-dropout (LDO) regulator to attenuate noise from the power supply. This allows the device to achieve excellent power-supply noise rejection, significantly reducing the impact on jitter generation. Intelligent Dynamic Switch (IDS) The MAX3678 continuously monitors both the primary reference input and secondary reference input and provides a clock failure indicator for each of them (IN0FAIL, IN1FAIL). It is assumed that both reference inputs, REFCLK0 and REFCLK1, are at the same frequency (within ±25ppm), but there is no phase relationship. See the following definitions for clarification. • Primary Reference Clock: The input reference clock selected by SEL_CLK. • Secondary Reference Clock: The input reference clock not selected by SEL_CLK. • PLL Reference Clock: The reference clock that the PLL locks to, selected by either SEL_CLK or the IDS control block. IDS can override SEL_CLK. The IDS control has two modes of operation—automatic switch mode and manual switch mode—controlled by the IDS_MODE input. Automatic switch mode requires that the PLL not be bypassed (PLL_BYPASS = 0). Automatic Switch Mode (IDS_MODE = 0 and PLL_BYPASS = 0) When the IDS_MODE pin is set low or left open, the automatic switch mode is enabled. The PLL initially locks to the primary reference clock selected by SEL_CLK. Upon the detection of the primary reference clock failure, the IDS control block overrides the SEL_CLK for switch control, and the PLL automatically switches over to the secondary qualified reference clock input and changes the CLK_SELECTED output. When an input clock switch occurs, the output clock phase alignment to the new reference clock occurs over an extended period of time. During this time period, the maximum rate of output period change per cycle is typically 100ppm/cycle. The following are case examples that demonstrate the IDS operations with REFCLK0 selected as the primary reference clock (SEL_CLK = 0). _______________________________________________________________________________________ 9 MAX3678 Pin Description (continued) MAX3678 Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching Case 1. Power-Up, PLL Locks to REFCLK0 During power-up, the REFCLK0 input is selected as the PLL reference clock. The PLL locks to REFCLK0 if it is valid (IN0FAIL = 1) and makes CLK_SELECTED = 0 (Figure 2). The LOCK output goes from initially unlocked status (LOCK = 1) to locked status (LOCK = 0). The device continues to run in this loop and monitors the signal status for both REFCLK0 and REFCLK1. POWER-ON-RESET (~ 20μs) VCC REFCLK0 REFCLK1 OUTxx IN0FAIL IN1FAIL BUSY HIGH HIGH HIGH tLOCK LOCK SEL_CLK CLK_SELECTED PLL LOCKED TO REFCLK0 LOW LOW Figure 2. Power-Up, PLL Locks to REFCLK0 10 ______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching When IN0FAIL is asserted low (IN0FAIL = 0), the IDS initiates a switch, making CLK_SELECTED = 1, and REFCLK1 becomes the PLL reference clock if it is valid (IN1FAIL = 1) (Figure 3). Note that a switch happens only if the other reference clock input is valid. During the switching process, the BUSY signal is asserted as 0 and deasserted as 1 when the switch is completed, meaning that the output clock phase is realigned to the REFCLK0 new reference clock. During this period of time, the PLL lock indicator (LOCK) indicates that the PLL is in lock. The PLL remains locked to REFCLK1 as long as REFCLK1 is valid. Once a clock failure is detected on the reference clock (REFCLK0 in this example), the failure indicator is latched for 128 PFD cycles (~ 2µs) and is updated every 128 PFD cycles. This latch function is released when a valid signal is detected. INVALID REFCLK1 OUTxx IN0FAIL IN1FAIL HIGH IDS-INITIATED SWITCH BUSY LOCK SEL_CLK CLK_SELECTED LOW LOW PLL LOCKED TO REFCLK0 PLL LOCKS TO REFCLK1 Figure 3. REFCLK0 Becomes Invalid, IDS Initiates a Switch ______________________________________________________________________________________ 11 MAX3678 Case 2a. REFCLK0 Becomes Invalid, IDS Initiates a Switch MAX3678 Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching Case 2b. REFCLK0 Becomes Invalid, IDS Initiates a Switch, IDS Sequence Includes Holdover Mode When REFCLK0 fails, IDS initiates a switch to REFCLK1 if it is valid. While the PLL is in the process of switching, random clock-phase variation may cause internal qualification circuits to temporarily disqualify REFCLK1, resulting in the PLL being forced to enter holdover mode. While in holdover mode, IDS continues monitor- REFCLK0 ing the signal status for both REFCLK0 and REFCLK1. When REFCLK1 is requalified, IDS selects REFCLK1, and the PLL locks to REFCLK1 to exit holdover mode (Figure 4). Note that the specification for output frequency transient is not met when the IDS operation follows a sequence that includes holdover mode. INVALID REFCLK1 OUTxx IN0FAIL REFCLK1 TEMPORARILY DISQUALIFIED IN1FAIL IDS-INITIATED SWITCH BUSY HOLDOVER MODE LOCK SEL_CLK CLK_SELECTED LOW PLL LOCKED TO REFCLK0 PLL ATTEMPTS TO LOCK TO REFCLK1 PLL LOCKS TO REFCLK1 Figure 4. REFCLK0 Becomes Invalid, IDS Initiates a Switch, IDS Sequence Includes Holdover Mode 12 ______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching After REFCLK0 fails, the PLL switches from REFCLK0 to REFCLK1, no longer making the primary reference clock selected by SEL_CLK the PLL reference clock. The PLL remains locked to REFCLK1 even if REFCLK0 becomes valid during or after switching to REFCLK1, given REFCLK1 remains valid (Figure 5). Case 4. User-Requested PLL Switch in Automatic Switch Mode In automatic switch mode, the MAX3678 allows the user to redefine the primary reference clock by toggling the SEL_CLK input. The PLL monitors the SEL_CLK REFCLK0 transition and initiates a switch if the new reference clock selected by SEL_CLK is different from the current reference clock (CLK_SELECTED) and is valid. For example, the user can request the PLL to switch back to REFCLK0 by toggling the SEL_CLK pin 0 to 1, then back to 0. The PLL monitors SEL_CLK and responds to the user-requested switch given that REFCLK0 is valid (Figure 5). The minimum SEL_CLK toggling pulse width is 2 PFD cycles (~ 30ns). It is recommended to verify the CLK_SELECTED state to ensure that the requested switch did occur correctly. If the desired switch did not occur, the SEL_CLK pin should be toggled again. INVALID REFCLK1 OUTxx IN0FAIL IN1FAIL HIGH LOCK USER-REQUESTED SWITCH IDS-INITIATED SWITCH BUSY LOW > 30ns SEL_CLK CLK_SELECTED PLL LOCKED TO REFCLK0 PLL LOCKS TO REFCLK1 PLL LOCKS TO REFCLK0 Figure 5. PLL Switches to REFCLK1 and REFCLK0 Becomes Valid, User Requests Switch ______________________________________________________________________________________ 13 MAX3678 Case 3. PLL Switches to REFCLK1 and REFCLK0 Becomes Valid MAX3678 Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching Case 5: Both REFCLK0 and REFCLK1 Fail, PLL in Holdover Mode If both REFCLK0 and REFCLK1 are not valid, the PLL goes into holdover mode, where the VCO frequency smoothly drifts from the previously locked frequency to the trimmed center frequency. When this happens, the clock output frequency accuracy is dominated by the on-chip VCO, which is approximately ±0.5% at room REFCLK0 temperature and may change -100ppm/°C over temperature. The IDS continues monitoring the signal status for both REFCLK0 and REFCLK1. If both REFCLK0 and REFCLK1 are detected valid at the same time, the PLL locks to the reference clock selected by SEL_CLK. If only one of them is valid, the PLL locks to the valid reference clock (Figure 6). INVALID REFCLK1 INVALID OUTxx IN0FAIL LOW IN1FAIL BUSY HIGH HOLDOVER MODE LOCK SEL_CLK LOW CLK_SELECTED Figure 6. REFCLK0 and REFCLK1 Become Invalid, PLL in Holdover Mode 14 ______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching In manual switch mode, the IN0FAIL and IN1FAIL status indicators are still valid, but the manual-requested switch happens whether or not the selected reference clock is valid. cycles. Note that phase qualification only applies to the reference input currently being used by the PLL. Frequency Qualification A reference clock input becomes frequency qualified if the input frequency is within ±2.4% of the nominal frequency. The reference input becomes frequency disqualified if the input frequency moves away from the nominal frequency by more than ±8%. BOTH INPUTS OPEN Clock Failure Conditions 130Ω The MAX3678 clock failure detection is performed using the combination of amplitude qualification and PLL frequency and phase error qualification. The failure status is indicated for REFCLK0 and REFCLK1 at IN0FAIL and IN1FAIL, respectively. Once an indicator is asserted low, it is latched and updated every 128 PFD cycles (~ 2µs). It should be noted that when the PLL is locked to a reference clock, the clock failure indicator for the other reference clock is only valid for amplitude qualification and frequency qualification. Amplitude Qualification A reference clock input fails amplitude qualification if any of the following conditions occur: A) Either one or both inputs (REFCLKx, REFCLKx) are shorted to VCC or GND. B) Both inputs (REFCLKx, REFCLKx) are disconnected from the source and have the following terminations connected: (a) 100Ω differential, (b) 130Ω to VCC and 82Ω to GND at each input. See Figure 7 for positions of open circuits that can be detected. C) Input reference clock differential swing is below the clock failure assert threshold as specified in the Electrical Characteristics. See Figure 8. The response time for conditions A through C is typically between 50ns and 300ns. Phase Qualification A reference clock input fails phase qualification when the phase error at the PFD output exceeds the error window (φerr) for more than 5 of 8 PFD cycles, as specified in the Electrical Characteristics. A reference clock input is qualified when phase error at the PFD output is within the phase error window for 8 consecutive PFD VCC VCC 130Ω MAX3678 LVPECL 82Ω 82Ω BOTH INPUTS OPEN MAX3678 100Ω LVPECL Figure 7. Positions for Open-Circuit Detection DIFFERENTIAL INPUT: (REFCLKx - REFCLKx) 0V VDT Figure 8. Input Amplitude Detection Threshold ______________________________________________________________________________________ 15 MAX3678 Manual Switch Mode (IDS_MODE = 1) The manual switch mode is provided for user-controlled switching. In manual switch mode, the PLL locks to a reference clock selected by SEL_CLK. For example, if SEL_CLK = 0, the PLL locks to REFCLK0 and forces CLK_SELECTED = 0; if SEL_CLK is changed to SEL_CLK = 1, the PLL switches to REFCLK1 and makes CLK_SELECTED = 1. MAX3678 Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching PLL Out-of-Lock Condition Table 1. Divider M Configuration for Input Frequencies CONNECTION FROM DM PIN If the frequency difference between the reference clock input and the VCO at the PFD input becomes within 500ppm, the PLL is considered to be in lock (LOCK = 0). When the frequency difference between the reference clock input and the VCO at the PFD input becomes greater than 800ppm, the PLL is considered out-of-lock. It should be noted that the LOCK indicator is not part of the frequency qualification used to initiate switching between reference clocks. INPUT FREQUENCY (MHz) GND 66.67 VCC 133.33 Open 266.67 10k
to GND 333.33 Table 2. Divider A Configuration for A-Group Output Frequencies CONNECTION FROM DA PIN Input and Output Frequencies The MAX3678 input and output dividers are configured using four-level control inputs DM, DA, and DB. Each divider is independent and can have a unique setting. The input connection and associated frequencies are listed in Tables 1, 2, and 3. OUTPUT FREQUENCY AT OUTA[3:0] (MHz) GND 66.67 VCC 133.33 Open 266.67 10k
to GND 333.33 Output-Enable Controls Each output group (A and B) has a three-level control input OUTA_EN and OUTB_EN. See Tables 4 and 5 for configuration settings. When clock outputs are disabled, they are high impedance. Unused enabled outputs should be left open. Table 3. Divider B Configuration for B-Group Output Frequencies CONNECTION FROM DB PIN Clock Holdover OUTPUT FREQUENCY AT OUTB[4:0] (MHz) GND 66.67 VCC 133.33 Open 266.67 10k
to GND 333.33 In automatic switch mode (IDS_MODE = 0), if both REFCLK0 and REFCLK1 are not valid, the lock indicator deasserts (LOCK = 1) and the PLL goes into holdover mode, where the VCO frequency smoothly drifts from the previously locked frequency to the trimmed center frequency. When this happens, the clock output frequency accuracy is dominated by the Table 4. OUTA[3:0] Enable Control CONNECTION FROM OUTA_EN PIN A-GROUP OUTPUT ENABLED A-GROUP OUTPUT DISABLED TO HIGH IMPEDANCE GND OUTA0, OUTA1, OUTA2, OUTA3 — VCC* — OUTA0, OUTA1, OUTA2, OUTA3 Open OUTA0, OUTA1 OUTA2, OUTA3 *Connecting both OUTA_EN and OUTB_EN to VCC enables a factory test mode and forces all indicators to GND. This is not a valid mode of operation. Table 5. OUTB[4:0] Enable Control B-GROUP OUTPUT DISABLED TO HIGH IMPEDANCE CONNECTION FROM OUTB_EN PIN B-GROUP OUTPUT ENABLED GND OUTB0, OUTB1, OUTB2, OUTB3, OUTB4 — VCC* OUTB0 OUTB1, OUTB2, OUTB3, OUTB4 Open OUTB0, OUTB1, OUTB2 OUTB3, OUTB4 *Connecting both OUTA_EN and OUTB_EN to VCC enables a factory test mode and forces all indicators to GND. This is not a valid mode of operation. 16 ______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching Power-On-Reset (POR) At power-on, an internal signal is generated to hold the MAX3678 in a reset state. This internal reset time is about 20µs after VCC reaches 3.0V (Figure 2). During the power-on-reset time, the outputs are held to logiclow (OUTxx = low and OUTxx = high). See Table 6 for output signal status during power-on-reset. After this internal reset time, the PLL starts to lock to the reference clock selected by SEL_CLK. Master Reset After power-up, an external master reset (MR) can be provided to reset the internal dividers. This input requires a minimum reset pulse width of 100ns (active low) and is asynchronous to the reference clock. While MR is low, all clock outputs are held to logic-low (OUTxx = low, OUTxx = high). See Table 6 for the output signal status during master reset. When the master reset input is deasserted (MR = 1), the PLL starts to lock to the reference clock selected by SEL_CLK. Master reset is only needed for applications where divider configurations are changed on the fly and the clock outputs need to maintain phase alignment. A master reset is not required at power-up. External Feedback for Zero-Delay Buffer The MAX3678 can be operated with either internal or external PLL feedback path, controlled by the FB_SEL input. Connecting FB_SEL to GND selects internal feedback. For applications where a known phase relationship between the reference clock input and the external feedback input (FB_IN, FB_IN) are needed for phase synchronization, connect FB_SEL to V CC for zero-delay buffer configuration and provide external feedback to the FB_IN input. PLL Bypass Mode PLL bypass mode is provided for test purposes. In this mode, the device receives two reference clocks to the 2:1 mux, controlled by the SEL_CLK input. The selected primary reference clock is connected to the LVPECL clock outputs directly. In PLL bypass mode (PLL_BYPASS = 1), the output clock frequency is the same as the input clock frequency. In this case, the clock amplitude and frequency qualifications are still valid, but the phase qualification is not available and the device is running in manual switch mode. BUSY Indicator A BUSY signal is generated to indicate that the PLL is in the process of phase aligning to the new reference clock. When BUSY = 0, the PLL is in switch mode; when BUSY = 1, the PLL operates normally. Table 6. Output Signal Status During Power-On-Reset or Master Reset OUTPUT DURING POWER-ON-RESET (FOR ~ 20μs AFTER VCC > 3.0V) DURING MASTER RESET (MR = 0) NOTES CLK_SELECTED 0 — IN0FAIL 1 Forced high regardless of reference input qualification. IN1FAIL 1 Forced high regardless of reference input qualification. LOCK 1 PLL out-of-lock. BUSY 1 No switch happens. OUTA[3:0] Logic-Low — OUTB[4:0] Logic-Low — ______________________________________________________________________________________ 17 MAX3678 on-chip VCO, which is approximately ±0.5% at room temperature and may change -100ppm/°C over temperature. While in holdover mode, IDS continues monitoring the signal status for both REFCLK0 and REFCLK1 using amplitude and frequency qualification (phase qualification is not valid). The CLK_SELECTED indicator is low and BUSY remains high. To exit holdover mode, at least one of the reference clocks must be valid and selected as the PLL reference clock. In manual switch mode (IDS_MODE = 1), if the selected reference clock is not valid, the PLL does not go into holdover mode. MAX3678 Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching Applications Information Interfacing with LVPECL Inputs Figure 9 shows the equivalent LVPECL input circuit for REFCLK0, REFCLK1, and FB_IN. These inputs are internally biased to allow AC- or DC-coupling and have > 40kΩ differential input impedance. When AC-coupled, these inputs can accept LVDS, CML, and LVPECL signals. Interfacing with LVPECL Outputs Figure 10 shows the equivalent LVPECL output circuit. These outputs are designed to drive a pair of 50Ω transmission lines terminated with 50Ω to VTT = VCC 2V. If a separate termination voltage (VTT) is not available, other termination methods can be used such as shown in Figures 11 and 12. Unused outputs, enabled or disabled, can be left open or properly terminated. For more information on LVPECL terminations and how to interface with other logic families, refer to Maxim Application Note HFAN-01.0: Introduction to LVDS, PECL, and CML. Layout Considerations The clock inputs and outputs are critical paths for the MAX3678, and care should be taken to minimize discontinuities on the transmission lines. Maintain 100Ω differential (or 50Ω single-ended) impedance in and out of the MAX3678. Avoid using vias and sharp corners. Termination networks should be placed as close as possible to receiving clock inputs. Provide space between differential output pairs to reduce crosstalk, especially if the A and B group outputs are operating at different frequencies. Power Supply and Ground Connections The MAX3678 has seven supply connection pins; installation of a bypass capacitor at each supply pin is recommended. All seven supply connections should be driven from the same source to eliminate the possibility of independent power-supply sequencing. Excessive supply noise can result in increased jitter. The 56-pin TQFN package features an exposed pad (EP), which provides a low-resistance thermal path for heat removal from the IC and must be connected to the circuit board ground plane for proper operation. VCC VCC VCC - 1.34V > 20kΩ > 20kΩ 200Ω REFCLKx, FB_IN 200Ω REFCLKx, FB_IN ESD STRUCTURES MAX3678 Figure 9. Equivalent LVPECL Input Circuit 18 ______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching +3.3V +3.3V 130Ω MAX3678 VCC +3.3V +3.3V 130Ω Z = 50Ω LVPECL OUTxx LVPECL Z = 50Ω 82Ω 82Ω OUTxx ESD STRUCTURES Figure 11. Thevenin Equivalent LVPECL Termination +3.3V +3.3V MAX3678 0.1μF Figure 10. Equivalent LVPECL Output Circuit Z = 50Ω LVPECL 0.1μF 100Ω LVPECL Z = 50Ω 143Ω 143Ω Figure 12. AC-Coupled LVPECL Termination ______________________________________________________________________________________ 19 Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching OUTA1 DA OUTA1 OUTA0 OUTA0 GND PLL_BYPASS VCC IDS_MODE VCC BUSY GND IN1FAIL TOP VIEW LOCK MAX3678 Pin Configuration 56 55 54 53 52 51 50 49 48 47 46 45 44 43 IN0FAIL 1 42 GND CLK_SELECTED 2 41 VCC RSVD 3 40 OUTA2 REFCLK0 4 39 OUTA2 REFCLK0 5 38 OUTA3 DM 6 37 OUTA3 VCC 7 36 OUTA_EN MAX3678 GND 8 35 OUTB_EN MR 9 34 OUTB4 REFCLK1 10 33 OUTB4 REFCLK1 11 32 OUTB3 SEL_CLK 12 31 OUTB3 EP* VCC_VCO 13 30 VCC GND 14 29 GND DB OUTB2 OUTB2 OUTB1 GND OUTB1 VCC OUTB0 FB_IN OUTB0 FB_IN FB_SEL CPLL CREG 15 16 17 18 19 20 21 22 23 24 25 26 27 28 THIN QFN (8mm × 8mm × 0.8mm) *THE EXPOSED PAD OF THE TQFN PACKAGE MUST BE SOLDERED TO GROUND FOR PROPER THERMAL AND ELECTRICAL OPERATION. Chip Information TRANSISTOR COUNT: 28,366 PROCESS: BiCMOS 20 Package Information For the latest package outline information and land patterns (footprints), go to http://www.microsemi.com . PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 56 TQFN-EP T5688+3 21-0135 ______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching Typical Application Circuit +3.3V Z = 50Ω 133.33MHz XO 0.1μF REFCLK0 VCC 0.1μF 0.1μF 143Ω 100Ω PROCESSOR Z = 50Ω OUTA3 REFCLK0 133.33MHz Z = 50Ω OUTA3 100Ω Z = 50Ω 143Ω VCC_VCO CPLL 0.1μF 0.22μF CREG 0.1μF 0.1μF 143Ω 143Ω 0.1μF 133.33MHz Z = 50Ω OUTA0 0.1μF Z = 50Ω Z = 50Ω 143Ω 143Ω PROCESSOR 143Ω MAX3678 OUTA_EN OUTB_EN +3.3V 0.1μF DM DA DB 0.1μF 100Ω 143Ω 143Ω 0.1μF 0.1μF 100Ω ASIC Z = 50Ω OUTB0 GND EP IDS_MODE PLL_BYPASS IN0FAIL CLK_SELECTED 133.33MHz Z = 50Ω OUTB0 LOCK ASIC Z = 50Ω OUTB4 FB_IN FB_IN FB_SEL MR 133.33MHz Z = 50Ω OUTB4 SEL_CLK 143Ω REFCLK1 100Ω Z = 50Ω OUTA0 100Ω BUSY 0.1μF 0.1μF IN1FAIL 133.33MHz XO REFCLK1 143Ω 143Ω FPGA   21 Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. 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