MT8806APR1

MT8806 ISO-CMOS 8 x 4 Analog Switch Array Data Sheet Features September 2011 • Internal control latches and address decoder • Short set-up and hold times • Wide operating voltage: 4.5 V to 13.2 V • 12Vpp analog signal capability • RON 65  max. @ VDD=12 V, 25C • RON  10  @ VDD=12 V, 25C • Full CMOS switch for low distortion • Minimum feedthrough and crosstalk • Separate analog and digital reference supplies • Low power consumption ISO-CMOS technology Ordering Information MT8806APR1 MT8806AP1 MT8806AE1 Key systems • PBX systems • Mobile radio • Test equipment/instrumentation • Analog/digital multiplexers • Audio/Video switching CS STROBE Tape & Reel Tubes Tubes * Pb free Matte Tin -40C to +85C Description The Zarlink MT8806 is fabricated in Zarlink’s ISOCMOS technology providing low power dissipation and high reliability. The device contains a 8 x 4 array of crosspoint switches along with a 5 to 32 line decoder and latch circuits. Any one of the 32 switches can be addressed by selecting the appropriate five address bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input. VSS is the ground reference of the digital inputs. The range of the analog signal is from VDD to VEE. Chip Select (CS) allows the crosspoint array to be cascaded for matrix expansion. Applications • 28 Pin PLCC* 28 Pin PLCC* 24 Pin PDIP* DATA RESET VDD 1 VEE VSS 1 AX0 AY0 5 to 32 Decoder 8 x 4 Switch Array Latches AY1 AY2 32 32 ••••••••••••••••••• Yi I/O (i=0-7) Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved. •••••••••••••••• AX1 Xi I/O (i=0-3) MT8806 NC Y0 Y1 Y2 VDD Y3 Y4 Data Sheet 4 3 2 1 28 27 26 VDD Y3 Y4 Y5 Y6 Y7 RESET STROBE AY2 AY1 AY0 VEE NC DATA X0 AX0 X1 AX1 X2 5 6 7 8 9 10 11  12 13 14 15 16 17 18 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 25 24 23 22 21 20 19 Y5 Y6 Y7 RESET STROBE AY2 NC CS X3 VSS VEE AY0 AY1 NC Y2 Y1 Y0 DATA X0 AX0 X1 AX1 X2 CS X3 VSS 28 PIN PLCC 24 PIN PLASTIC DIP Figure 2 - Pin Connections Change Summary Changes from the May 2005 issue to the September 2011 issue. Page Item 1 Ordering Information Change Removed leaded packages as per PCN notice. Pin Description Pin # Name Description 1-3 Y2-Y0 Y2-Y0 Analog (Inputs/Outputs): these are connected to the Y2-Y0 columns of the switch array. 4 6 DATA DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High. 5 7 X0 X0 Analog (Input/Output): this is connected to the X0 row of the switch array. 6 8 AX0 7 9 X1 8 10 AX1 9 11 X2 X2 Analog (Input/Output): this is connected to the X2 row of the switch array. 10 12 CS Chip Select (Input): this is used to select the device. Active High. 11 13 X3 X3 Analog (Input/Output): this is connected to the X3 row of the switch array. 12 14 VSS Digital Ground Reference PDIP PLCC 1-3 X0 Address Line (Input) X1 Analog (Input/Output): this is connected to the X1 row of the switch array. X1 Address Line (Input) 2 Zarlink Semiconductor Inc. MT8806 Data Sheet Pin Description Pin # Name Description PDIP PLCC 13 15 14-16 16,17, 20 17 21 18 22 RESET Master RESET (Input): this is used to turn off all switches regardless of the condition of CS. Active High. 19-23 23-27 Y7-Y3 Y7-Y3 Analog (Inputs/Outputs): these are connected to the Y7-Y3 columns of the switch array. 24 28 VDD 4, 5, 18, 19 NC VEE Negative Power Supply AY0-AY2 Y0 -Y2 Address Lines (Inputs) STROBE STROBE (Input): enables function selected by address and data. Address must be stable before STROBE goes high and DATA must be stable on the falling edge of the STROBE. Active High. Positive Power Supply No Connect Functional Description The MT8806 is an analog switch matrix with an array size of 8 x 4. The switch array is arranged such that there are 8 columns by 4 rows. The columns are referred to as the Y inputs/outputs and the rows are the X inputs/outputs. The crosspoint analog switch array will interconnect any X I/O with any Y I/O when turned on and provide a high degree of isolation when turned off. The control memory consists of a 32 bit write only RAM in which the bits are selected by the address inputs (AY0-AY2, AX0 & AX1). Data is presented to the memory on the DATA input. Data is asynchronously written into memory whenever both the CS (Chip Select) and the STROBE inputs are high and is latched on the falling edge of STROBE. A logical “1” written into a memory cell turns the corresponding crosspoint switch on and a logical “0” turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memory. The remaining switches retain their previous states. Any combination of X and Y inputs/outputs can be interconnected by establishing appropriate patterns in the control memory. A logical “1” on the RESET input will asynchronously return all memory locations to logical “0” turning off all crosspoint switches regardless of whether CS is high or low. Two voltage reference pins (VSS and VEE) are provided for the MT8806 to enable switching of negative analog signals. The range for digital signals is from VDD to VSS while the range for analog signals is from VDD to VEE. VSS and VEE pins can be tied together if a single voltage reference is needed. Address Decode The five address inputs along with the STROBE and CS (Chip Select) inputs are logically ANDed to form an enable signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a location, RESET must be low and CS must go high while the address and data are set up. Then the STROBE input is set high and then low causing the data to be latched. The data can be changed while STROBE is high, however, the corresponding switch will turn on and off in accordance with the DATA input. DATA must be stable on the falling edge of STROBE in order for correct data to be written to the latch. 3 Zarlink Semiconductor Inc. MT8806 Data Sheet Absolute Maximum Ratings*- Voltages are with respect to VEE unless otherwise stated. Parameter Symbol Min. Max. Units 1 Supply Voltage VDD VSS -0.3 -0.3 15.0 VDD+0.3 V V 2 Analog Input Voltage VINA -0.3 VDD+0.3 V 3 Digital Input Voltage VIN VSS-0.3 VDD+0.3 V 4 Current on any I/O Pin 15 mA 5 Storage Temperature +150 C 0.6 W I -65 TS 6 Package Power Dissipation PLASTIC DIP PD * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to VEE unless otherwise stated. Characteristics Sym. Min. Typ. Max. Units TO -40 25 85 C 1 Operating Temperature 2 Supply Voltage VDD VSS 4.5 VEE 13.2 VDD-4.5 V V 3 Analog Input Voltage VINA VEE VDD V 4 Digital Input Voltage VIN VSS VDD V Test Conditions DC Electrical Characteristics†- Voltages are with respect to VEE=VSS=0V, VDD =12V unless otherwise stated. Characteristics 1 Quiescent Supply Current Sym. Min. Typ.‡ Max. Units Test Conditions 1 100 A All digital inputs at VIN=VSS or VDD 0.4 1.5 mA All digital inputs at VIN=2.4 + VSS; VSS =7.0V 5 15 mA All digital inputs at VIN=3.4V 1 500 nA IVXi - VYjI = VDD - VEE See Appendix, Fig. A.1 0.8+VS V VSS =7.5V; VEE=0V VSS =6.5V; VEE=0V IDD 2 Off-state Leakage Current (See G.9 in Appendix) IOFF 3 Input Logic “0” level VIL S 4 Input Logic “1” level VIH 2.0+VSS V 5 Input Logic “1” level VIH 3.3 V 6 Input Leakage (digital pins) 0.1 ILEAK 10 A All digital inputs at VIN = VSS or VDD † DC Electrical Characteristics are over recommended temperature range. ‡ Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. 4 Zarlink Semiconductor Inc. MT8806 Data Sheet DC Electrical Characteristics- Switch Resistance - VDC is the external DC offset applied at the analog I/O pins. Characteristics Sym. 25C 70C 85C Units Test Conditions Typ. Max. Typ. Max. Typ. Max. 1 On-state VDD=12V Resistance VDD=10V VDD= 5V (See G.1, G.2, G.3 in Appendix) RON 45 55 120 65 75 185 75 85 215 80 90 225    VSS=VEE=0V,VDC=VDD/2, IVXi-VYjI = 0.4V See Appendix, Fig. A.2 2 Difference in on-state resistance between two switches (See G.4 in Appendix) RON 5 10 10 10  VDD=12V, VSS=VEE=0, VDC=VDD/2, IVXi-VYjI = 0.4V See Appendix, Fig. A.2 AC Electrical Characteristics† - Crosspoint Performance - Voltages are with respect to VDD=5V, VSS=0V, VEE=-7V, unless otherwise stated. Characteristics Sym. Typ.‡ Min. Max. Units Test Conditions 1 Switch I/O Capacitance CS 20 pF f=1 MHz 2 Feedthrough Capacitance CF 0.2 pF f=1 MHz 3 Frequency Response Channel “ON” 20LOG(VOUT/VXi)=-3dB F3dB 45 MHz Switch is “ON”; VINA = 2Vpp sinewave; RL = 1k See Appendix, Fig. A.3 4 Total Harmonic Distortion (See G.5, G.6 in Appendix) THD 0.01 % Switch is “ON”; VINA = 2Vpp sinewave f= 1kHz; RL=1k 5 Feedthrough Channel “OFF” Feed.=20LOG (VOUT/VXi) (See G.8 in Appendix) FDT -95 dB All Switches “OFF”; VINA= 2Vpp sinewave; f= 1kHz; RL= 1k See Appendix, Fig. A.4 6 Crosstalk between any two channels for switches Xi-Yi and Xj-Yj. Xtalk -45 dB VINA=2Vpp sinewave f= 10MHz; RL = 75 -90 dB VINA=2Vpp sinewave f= 10kHz; RL = 600 -85 dB VINA=2Vpp sinewave f= 10kHz; RL = 1k -80 dB VINA=2Vpp sinewave f= 1kHz; RL = 10k Refer to Appendix, Fig. A.5 for test circuit. ns RL=1k; CL=50pF Xtalk=20LOG (VYj/VXi). (See G.7 in Appendix). 7 Propagation delay through switch tPS 30 † Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. ‡ Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5 dB better. 5 Zarlink Semiconductor Inc. MT8806 Data Sheet AC Electrical Characteristics† - Control and I/O Timings- Voltages are with respect to VDD=5V, VSS=0V, VEE=-7V, unless otherwise stated. Min. Typ.‡ Characteristics Sym. Max. Units Test Conditions 1 Control Input crosstalk to switch (for CS, DATA, STROBE, Address) CXtalk 30 mVpp VIN=3V squarewave; RIN=1k, RL=10k See Appendix, Fig. A.6 2 Digital Input Capacitance CDI 10 pF 3 Switching Frequency FO 4 Setup Time DATA to STROBE tDS 10 ns RL= 1k, CL=50pF Å 5 Hold Time DATA to STROBE tDH 10 ns RL= 1k, CL=50pF Å 6 Setup Time Address to STROBE tAS 10 ns RL= 1k, CL=50pF Å 7 Hold Time Address to STROBE tAH 10 ns RL= 1k, CL=50pF Å 8 Setup Time CS to STROBE tCSS 10 ns RL= 1k, CL=50pF Å 9 Hold Time CS to STROBE tCSH 10 ns RL= 1k, CL=50pF Å 10 STROBE Pulse Width tSPW 20 ns RL= 1k, CL=50pF Å 11 RESET Pulse Width tRPW 40 ns RL= 1k, CL=50pF Å 12 STROBE to Switch Status Delay 13 14 20 f=1MHz MHz tS 40 100 ns RL= 1k, CL=50pF Å DATA to Switch Status Delay tD 50 100 ns RL= 1k, CL=50pF Å RESET to Switch Status Delay tR 35 100 ns RL= 1k, CL=50pF Å † Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. Digital Input rise time (tr) and fall time (tf) = 5 ns. ‡ Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. Å Refer to Appendix, Fig. A.7 for test circuit. tCSS tCSH 50% 50% tRPW CS 50% RESET 50% tSPW 50% STROBE 50% 50% tAS 50% ADDRESS 50% tAH 50% DATA 50% tDS tDH ON SWITCH* OFF tS tD Figure 3 - Control Memory Timing Diagram * See Appendix, Fig. A.7 for switching waveform 6 Zarlink Semiconductor Inc. tR tR MT8806 Data Sheet AX0 AX1 AY0 AY1 AY2 Connection 0 0 0 0 0 X0-Y0 0 0 1 0 0 X0-Y1 0 0 0 1 0 X0-Y2 0 0 1 1 0 X0-Y3 0 0 0 0 1 X0-Y4 0 0 1 0 1 X0-Y5 0 0 0 1 1 X0-Y6 0 0 1 1 1 X0-Y7 1  1 0  0 0  1 0  1 0  1 X1-Y0   X1-Y7 0  0 1  1 0  1 0  1 0  1 X2-Y0   X2-Y7 1  1 1  1 0  1 0  1 0  1 X3-Y0   X3-Y7 Table 1 - Address Decode Truth Table 7 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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