ISO2 - CMOS
MT8880C
Integrated DTMF Transceiver
Data Sheet
Features
September 2005
•
Complete DTMF transmitter/receiver
•
Central office quality
•
Low power consumption
•
Microprocessor port
•
Adjustable guard time
•
Automatic tone burst mode
•
Call progress mode
Ordering Information
MT8880CE
MT8880CS
MT8880CN
MT8880CP
MT8880CP1
MT8880CS1
MT8880CE1
MT8880CN1
MT8880CSR
MT8880CPR
MT8880CPR1
MT8880CSR1
Applications
Credit card systems
•
Paging systems
•
Repeater systems/mobile radio
•
Interconnect dialers
•
Personal computers
The MT8880C is a monolithic DTMF transceiver with
call progress filter. It is fabricated in Zarlink
Semiconductor’s ISO2-CMOS technology, which
Tone Burst
Gating Cct.
IN-
-
Row and
Column
Counters
D/A
Converters
∑
+
Dial
Tone
Filter
High Group
Filter
OSC2
Low Group
Filter
Oscillator
Circuit
VDD VRef
VSS
Data
Bus
Buffer
D0
D1
D2
Status
Register
D3
Interrupt
Logic
IRQ/CP
Control
Register
A
Digital
Algorithm
and Code
Converter
Control
Logic
Bias
Circuit
Transmit Data
Register
Control
Logic
GS
OSC1
Reel
Reel
Reel
Reel
provides low power dissipation and high reliability. The
DTMF receiver is based upon the industry standard
MT8870 monolithic DTMF receiver; the transmitter
utilizes a switched capacitor D/A converter for low
distortion, high accuracy DTMF signalling. Internal
counters provide a burst mode such that tone bursts
can be transmitted with precise timing. A call progress
filter can be selected allowing a microprocessor to
analyze
call
progress
tones.
A
standard
microprocessor bus is provided and is directly
compatible with 6800 series microprocessors.
Description
IN+
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tape &
Tape &
Tape &
Tape &
-40°C to +85°C
•
TONE
20 Pin PDIP
20 Pin SOIC
24 Pin SSOP
28 Pin PLCC
28 Pin PLCC*
20 Pin SOIC*
20 Pin PDIP*
24 Pin SSOP*
20 Pin SOIC
28 Pin PLCC
28 Pin PLCC*
20 Pin SOIC*
*Pb Free Matte Tin
Control
Register
B
I/O
Control
Receive Data
Register
Steering
Logic
ESt
Φ2
St/GT
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2001-2005, Zarlink Semiconductor Inc. All Rights Reserved.
CS
R/W
RS0
MT8880C
20 PIN PLASTIC DIP/SOIC
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
Φ2
RS0
GS
NC
ININ+
VDD
St/GT
EST
IN+
INGS
VRef
VSS
OSC1
OSC2
NC
NC
TONE
R/W
CS
4
3
2
1
28
27
26
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
Φ2
RS0
NC
VRef
VSS
OSC1
OSC2
NC
NC
24 PIN SSOP
5
6
7
8
9
10
11
•
12
13
14
15
16
17
18
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
25
24
23
22
21
20
19
NC
NC
NC
D3
D2
D1
D0
TONE
R/W
CS
RS0
NC
Φ2
IRQ/CP
IN+
INGS
VRef
VSS
OSC1
OSC2
TONE
R/W
CS
Data Sheet
28 PIN PLCC
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
20
24
28
1
1
1
IN+ Non-inverting op-amp input.
2
2
2
IN-
Inverting op-amp input.
3
3
4
GS
Gain Select. Gives access to output of front end differential amplifier for connection of feedback
resistor.
4
4
6
VRef Reference Voltage output, nominally VDD/2 is used to bias inputs at mid-rail (see Fig. 13).
5
5
7
VSS Ground input (0 V).
6
6
8
OSC1 DTMF clock/oscillator input. Connect a 4.7 MΩ resistor to VSS if crystal oscillator is used.
7
7
9
OSC2 Clock output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the
internal oscillator circuit. Leave open circuit when OSC1 is clock input.
8
10
12
TONE Tone output (DTMF or single tone).
9
11
13
10
12
14
CS
11
13
15
RS0 Register Select input. See register decode table. TTL compatible.
12
14
17
Φ2
13
15
18
R/W Read/Write input. Controls the direction of data transfer to and from the MPU and the transceiver
registers. TTL compatible.
Chip Select, TTL input (CS=0 to select the chip).
System Clock input. TTL compatible. N.B. Φ2 clock input need not be active when the device
is not being accessed.
IRQ/C Interrupt Request to MPU (open drain output). Also, when call progress (CP) mode has been
P selected and interrupt enabled the IRQ/CP pin will output a rectangular wave signal representative
of the input signal applied at the input op-amp. The input signal must be within the bandwidth
limits of the call progress filter. See Figure 8.
14- 18-21 19-22 D0-D3 Microprocessor Data Bus (TTL compatible). High impedance when CS = 1 or Φ2 is low.
17
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Zarlink Semiconductor Inc.
MT8880C
Data Sheet
Pin Description
Pin #
Name
Description
ESt
Early Steering output. Presents a logic high once the digital algorithm has detected a valid tone
pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic
low.
20
24
28
18
22
26
19
23
27
St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than VTSt detected at St
causes the device to register the detected tone pair and update the output latch. A voltage less than
VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering
time-constant; its state is a function of ESt and the voltage on St.
20
24
28
VDD Positive power supply input (+5 V typical).
8, 9, 3,5,10,1
16,17 1, 16,
23-25
NC
No Connection.
Functional Description
The MT8880C Integrated DTMF Transceiver architecture consists of a high performance DTMF receiver with
internal gain setting amplifier and a DTMF generator which employs a burst counter such that precise tone bursts
and pauses can be synthesized. A call progress mode can be selected such that frequencies within the specified
passband can be detected. A standard microprocessor interface allows access to an internal status register, two
control registers and two data registers.
Input Configuration
The input arrangement of the MT8880C provides a differential-input operational amplifier as well as a bias source
(VRef) which is used to bias the inputs at VDD/2. Provision is made for connection of a feedback resistor to the opamp output (GS) for adjustment of gain. In a single-ended configuration, the input pins are connected as shown in
Figure 3.
Figure 4 shows the necessary connections for a differential input configuration.
IN+
C
IN-
RIN
RF
GS
VRef
MT8880C
VOLTAGE GAIN
(AV) = RF / RIN
Figure 3 - Single-Ended Input Configuration
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Zarlink Semiconductor Inc.
MT8880C
Data Sheet
Receiver Section
Separation of the low and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order
switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies
(see Fig. 7). These filters also incorporate notches at 350 Hz and 440 Hz for exceptional dial tone rejection. Each
filter output is followed by a single order switched capacitor filter section which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted
low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF
signals.
C1
R1
IN+
INC2
R4
R5
GS
R2
R3
VRef
MT8880C
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 kΩ
R2 = 60kΩ, R3 = 37.5 kΩ
R3 = (R2R5)/(R2 + R5)
VOLTAGE GAIN
(AV diff) = R5/R1
INPUT IMPEDANCE
(ZINdiff) = 2 R12 + (1/ωC)2
Figure 4 - Differential Input Configuration
Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the
incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm
protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency
deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the
detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry
specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition
will cause ESt to assume an inactive state.
Steering Circuit
Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character
recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt
causes vc (see Figure 5) to rise as the capacitor discharges. Provided that the signal condition is maintained (ESt
remains high) for the validation period (tGTP), vc reaches the threshold (VTSt) of the steering logic to register the
tone pair, latching its corresponding 4-bit code (see Figure 7) into the Receive Data Register. At this point the GT
output is activated and drives vc to VDD. GT continues to drive high as long as ESt remains high. Finally, after a
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Zarlink Semiconductor Inc.
MT8880C
Data Sheet
short delay to allow the output latch to settle, the delayed steering output flag goes high, signalling that a received
tone pair has been registered. The status of the delayed steering flag can be monitored by checking the appropriate
bit in the status register. If Interrupt mode has been selected, the IRQ/CP pin will pull low when the delayed
steering flag is active.
The contents of the output latch are updated on an active delayed steering transition. This data is presented to the
four bit bidirectional data bus when the Receive Data Register is read. The steering circuit works in reverse to
validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the
receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together
with the capability of selecting the steering time constants externally, allows the designer to tailor performance to
meet a wide variety of system requirements.
VDD
C1
VDD
Vc
St/GT
ESt
R1
tGTA = (R1C1) In (VDD / VTSt)
MT8880C
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
Figure 5 - Basic Steering Circuit
Guard Time Adjustment
The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen
according to the formula:
tREC = tDP+tGTP
tID=tDA+tGTA
The value of tDP is a device parameter (see AC Electrical Characteristics) and tREC is the minimum signal duration
to be recognized by the receiver. A value for C1 of 0.1 µF is recommended for most applications, leaving R1 to be
selected by the designer. Different steering arrangements may be used to select independently the guard times for
tone present (tGTP) and tone absent (tGTA). This may be necessary to meet system specifications which place both
accept and reject limits on both tone duration and interdigital pause. Guard time adjustment also allows the
designer to tailor system parameters such as talk off and noise immunity.
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Zarlink Semiconductor Inc.
MT8880C
Data Sheet
tGTP = (RPC1) In [VDD / (VDD-VTSt)]
tGTA = (R1C1) In (VDD/VTSt)
RP = (R1R2) / (R1 + R2)
VDD
C1
St/GT
R1
R2
ESt
a) decreasing tGTP; (tGTP < tGTA)
tGTP = (R1C1) In [VDD / (VDD-VTSt)
tGTA = (RpC1) In (VDD/VTSt)
RP = (R1R2) / (R1 + R2)
VDD
C1
St/GT
R1
R2
ESt
b) decreasing tGTA; (tGTP > tGTA)
Figure 6 - Guard Time Adjustment
Increasing tREC improves talk-off performance since it reduces the probability that tones simulated by speech will
maintain a valid signal condition long enough to be registered. Alternatively, a relatively short tREC with a long tDO
would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs
are required. Design information for guard time adjustment is shown in Figure 6. The receiver timing is shown in
Figure 9 with a description of the events in Figure 11.
Call Progress Filter
A call progress mode, using the MT8880C, can be selected allowing the detection of various tones which identify
the progress of a telephone call on the network. The call progress tone input and DTMF input are common,
however, call progress tones can only be detected when CP mode has been selected. DTMF signals cannot be
detected if CP mode has been selected (see Table 5). Figure 8 indicates the useful detect bandwidth of the call
progress filter. Frequencies presented to the input, which are within the ‘accept’ bandwidth limits of the filter, are
hard-limited by a high gain comparator with the IRQ/CP pin serving as the output. The squarewave output obtained
from the schmitt trigger can be analyzed by a microprocessor or counter arrangement to determine the nature of
the call progress tone being detected. Frequencies which are in the ‘reject’ area will not be detected and
consequently the IRQ/CP pin will remain low.
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Zarlink Semiconductor Inc.
MT8880C
Data Sheet
DTMF Generator
The DTMF transmitter employed in the MT8880C is capable of generating all sixteen standard DTMF tone pairs
with low distortion and high accuracy. All frequencies are derived from an external 3.579545 MHz crystal. The
sinusoidal waveforms for the individual tones are digitally synthesized using row and column programmable
dividers and switched capacitor D/A converters. The row and column tones are mixed and filtered providing a
DTMF signal with low total harmonic distortion and high accuracy. To specify a DTMF signal, data conforming to the
encoding format shown in Figure 7 must be written to the transmit Data Register. Note that this is the same as the
receiver output code. The individual tones which are generated (fLOW and fHIGH) are referred to as Low Group and
High Group tones. As seen from the table, the low group frequencies are 697, 770, 852 and 941 Hz. The high group
frequencies are 1209, 1336, 1477 and 1633 Hz. Typically, the high group to low group amplitude ratio (preemphasis) is 2 dB to compensate for high group attenuation on long loops.
FLOW
FHIGH
DIGIT
D3
D2
D1
D0
697
1209
1
0
0
0
1
697
1336
2
0
0
1
0
697
1477
3
0
0
1
1
770
1209
4
0
1
0
0
770
1336
5
0
1
0
1
770
1477
6
0
1
1
0
852
1209
7
0
1
1
1
852
1336
8
1
0
0
0
852
1477
9
1
0
0
1
941
1336
0
1
0
1
0
941
1209
*
1
0
1
1
941
1477
#
1
1
0
0
697
1633
A
1
1
0
1
770
1633
B
1
1
1
0
852
1633
C
1
1
1
1
941
1633
D
0
0
0
0
0= LOGIC LOW, 1= LOGIC HIGH
Figure 7 - Functional Encode/Decode Table
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Zarlink Semiconductor Inc.
MT8880C
Data Sheet
LEVEL
(dBm)
-25
0
250
500
FREQUENCY (Hz)
750
= Reject
= May Accept
= Accept
Figure 8 - Call Progress Response
The period of each tone consists of 32 equal time segments. The period of a tone is controlled by varying the length
of these time segments. During write operations to the Transmit Data Register the 4 bit data on the bus is latched
and converted to 2 of 8 coding for use by the programmable divider circuitry. This code is used to specify a time
segment length which will ultimately determine the frequency of the tone. When the divider reaches the appropriate
count, as determined by the input code, a reset pulse is issued and the counter starts again. The number of time
segments is fixed at 32, however, by varying the segment length as described above the tone output signal
frequency will be varied. The divider output clocks another counter which addresses the sinewave lookup ROM.
EVENTS
A
B
C
tREC
tREC
D
TONE
#n + 1
TONE
#n + 1
tDA
tDP
ESt
F
tDO
tID
TONE #n
Vin
E
tGTP
tGTA
VTSt
St/GT
tPStRX
RX0-RX3
DECODED TONE # (n-1)
#n
tPStb3
b3
b2
Read
Status
Register
IRQ/CP
Figure 9 - Receiver Timing Diagram
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Zarlink Semiconductor Inc.
# (n + 1)
MT8880C
Data Sheet
The lookup table contains codes which are used by the switched capacitor D/A converter to obtain discrete and
highly accurate DC voltage levels. Two identical circuits are employed to produce row and column tones which are
then mixed using a low noise summing amplifier. The oscillator described needs no “start-up” time as in other
DTMF generators since the crystal oscillator is running continuously thus providing a high degree of tone burst
accuracy. A bandwidth limiting filter is incorporated and serves to attenuate distortion products above 8 kHz. It can
be seen from Figure 10 that the distortion products are very low in amplitude.
Scaling Information
10 dB/Div
Start Frequency = 0 Hz
Stop Frequency = 3400 Hz
Marker Frequency = 697 Hz and
1209 Hz
Figure 10 - Spectrum Plot
Burst Mode
In certain telephony applications it is required that DTMF signals being generated are of a specific duration
determined either by the particular application or by any one of the exchange transmitter specifications currently
existing. Standard DTMF signal timing can be accomplished by making use of the Burst Mode. The transmitter is
capable of issuing symmetric bursts/pauses of predetermined duration. This burst/pause duration is 51 ms±1 ms
which is a standard interval for autodialer and central office applications. After the burst/pause has been issued, the
appropriate bit is set in the Status Register indicating that the transmitter is ready for more data. The timing
described above is available when DTMF mode has been selected. However, when CP mode (Call Progress mode)
is selected, a second burst/pause time of 102 ms ±2 ms is available. This extended interval is useful when precise
tone bursts of longer than 51 ms duration and 51 ms pause are desired. Note that when CP mode and Burst mode
have been selected, DTMF tones may be transmitted only and not received.
In applications where a non-standard burst/pause duration is required, burst mode must be disabled and the
transmitter gated on and off by an external hardware or software timer.
Single Tone Generation
A single tone mode is available whereby individual tones from the low group or high group can be generated. This
mode can be used for DTMF test equipment applications, acknowledgment tone generation and distortion
measurements. Refer to Control Register B description for details.
Distortion Calculations
The MT8880C is capable of producing precise tone bursts with minimal error in frequency (see Table 1). The
internal summing amplifier is followed by a first-order lowpass switched capacitor filter to minimize harmonic
components and intermodulation products. The total harmonic distortion for a single tone can be calculated using
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Zarlink Semiconductor Inc.
MT8880C
Data Sheet
Equation 1, which is the ratio of the total power of all the extraneous frequencies to the power of the fundamental
frequency expressed as a percentage. The Fourier components of the tone output correspond to V2f.... Vnf as
measured on the output waveform. The total harmonic distortion for a dual tone can be calculated using Equation 2.
VL and VH correspond to the low group amplitude and high group amplitude, respectively, and V2IMD is the sum of all the
intermodulation components. The internal switched-capacitor filter following the D/A converter keeps distortion products
down to a very low level as shown in Figure 10.
EXPLANATION OF EVENTS
A)
TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED.
B)
TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
C)
END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER RETAINED
UNTIL NEXT VALID TONE PAIR.
D)
TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
E)
ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED.
F)
END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER
RETAINED UNTIL NEXT VALID TONE PAIR.
EXPLANATION OF SYMBOLS
Vin
DTMF COMPOSITE INPUT SIGNAL.
ESt
EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.
St/GT
STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.
RX 0-RX 3
4-BIT DECODED DATA IN RECEIVE DATA REGISTER
b3
DELAYED STEERING. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE REQUIRED
GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A VALID DTMF
SIGNAL.
b2
INDICATES THAT VALID DATA IS IN THE RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS
REGISTER IS READ.
IRQ/CP
INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS CLEARED
AFTER THE STATUS REGISTER IS READ.
tREC
MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID.
tREC
MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION.
tID
MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS.
tDO
MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL.
tDP
TIME TO DETECT VALID FREQUENCIES PRESENT.
tDA
TIME TO DETECT VALID FREQUENCIES ABSENT.
tGTP
GUARD TIME, TONE PRESENT.
tGTA
GUARD TIME, TONE ABSENT.
Figure 11 - Description of Timing Events
V22f + V23f + V24f + .... V2nf
THD(%) =
100
Vfundamental
Equation 1. THD (%) For a Single Tone
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Zarlink Semiconductor Inc.
MT8880C
Data Sheet
V22L + V23L + .... V2nL + V22H +
V23H + .. V2nH + V2IMD
THD (%) = 100
V2L + V2H
Equation 2. THD (%) For a Dual Tone
ACTIVE
INPUT
OUTPUT FREQUENCY
(Hz)
%ERROR
SPECIFIED
ACTUAL
L1
697
699.1
+0.30
L2
770
766.2
-0.49
L3
852
847.4
-0.54
L4
941
948.0
+0.74
H1
1209
1215.9
+0.57
H2
1336
1331.7
-0.32
H3
1477
1471.9
-0.35
H4
1633
1645.0
+0.73
Table 1 - Actual Frequencies Versus Standard Requirements
DTMF Clock Circuit
The internal clock circuit is completed with the addition of a standard television colour burst crystal. The crystal
specification is as follows:
Frequency:
Frequency Tolerance:
Resonance Mode:
Load Capacitance:
Maximum Series Resistance:
Maximum Drive Level:
e.g.
3.579545 MHz
±0.1%
Parallel
18 pF
150 ohms
2 mW
CTS Knights MP036S
Toyocom TQC-203-A-9S
A number of MT8880C devices can be connected as shown in Figure 12 such that only one crystal is required.
Alternatively, the OSC1 inputs on all devices can be driven from a TTL buffer with the OSC2 outputs left
unconnected.
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Zarlink Semiconductor Inc.
MT8880C
MT8880C
OSC1
Data Sheet
MT8880C
OSC2
OSC1
MT8880C
OSC2
OSC1 OSC2
3.579545 MHz
Figure 12 - Common Crystal Connection
Microprocessor Interface
The MT8880C employs a microprocessor interface which allows precise control of transmitter and receiver
functions. There are five internal registers associated with the microprocessor interface which can be subdivided
into three categories, i.e., data transfer, transceiver control and transceiver status. There are two registers
associated with data transfer operations.
The Receive Data Register contains the output code of the last valid DTMF tone pair to be decoded and is a read
only register. The data entered in the Transmit Data Register will determine which tone pair is to be generated (see
Figure 7 for coding details). Data can only be written to the transmit register. Transceiver control is accomplished
with two Control Registers (CRA and CRB) which occupy the same address space. A write operation to CRB can
be executed by setting the appropriate bit in CRA. The following write operation to the same address will then be
directed to CRB and subsequent write cycles will then be directed back to CRA. A software reset must be included
at the beginning of all programs to initialize the control and status registers after power up or power reset (see
Figure 16). Refer to Tables 3, 4, 5 and 6 for details concerning the Control Registers. The IRQ/CP pin can be
programmed such that it will provide an interrupt request signal upon validation of DTMF signals or when the
transmitter is ready for more data (Burst mode only). The IRQ/CP pin is configured as an open drain output device
and as such requires a pull-up resistor (see Figure 13).
FUNCTION
RS0
R/W
0
0
Write to Transmit
Data Register
0
1
Read from Receive
Data Register
1
0
Write to Control
Register
1
1
Read from Status
Register
Table 2 - Internal Register Functions
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Zarlink Semiconductor Inc.
MT8880C
Data Sheet
b3
b2
b1
b0
RSEL
IRQ
CP/DTMF
TOUT
Table 3 - CRA Bit Positions
b3
b2
b1
b0
C/R
S/D
TEST
BURST
Table 4 - CRB Bit Positions
BIT
NAME
FUNCTION
DESCRIPTION
b0
TOUT
TONE OUTPUT
A logic ‘1’ enables the tone output. This function can be
implemented in either the burst mode or non-burst mode.
b1
CP/DTMF
MODE CONTROL
In DTMF mode (logic ‘0’) the device is capable of generating and
receiving Dual Tone Multi-Frequency signals. When the CP (Call
Progress) mode is selected (logic ‘1’) a 6th order bandpass filter is
enabled to allow call progress tones to be detected. Call progress
tones which are within the specified bandwidth
will
be
presented at the IRQ/CP pin in rectangular wave format if
the IRQ bit has been enabled (b2=1). Also, when the CP mode and
BURST mode have both been selected, the transmitter will issue
DTMF signals with a burst and pause of 102 ms (typ) duration. This
signal duration is twice that obtained from the DTMF transmitter if
DTMF mode had been selected. Note that DTMF signals cannot be
decoded when the CP mode of operation has been selected.
b2
IRQ
INTERRUPT ENABLE
A logic ‘1’ enables the INTERRUPT mode. When this mode is active
and the DTMF mode has been selected (b1=0) the IRQ/CP pin will
pull to a logic ‘0’ condition when either 1) a valid DTMF signal has
been received and has been present for the guard time duration or 2)
the transmitter is ready for more data (BURST mode only).
b3
RSEL
REGISTER SELECT
A logic ‘1’ selects Control Register B on the next Write cycle to the
Control Register address. Subsequent Write cycles to the Control
Register are directed back to Control Register A.
Table 5 - Control Register A Description
13
Zarlink Semiconductor Inc.
MT8880C
Data Sheet
BIT
NAME
FUNCTION
DESCRIPTION
b0
BURST
BURST MODE
A logic ‘0’ enables the burst mode. When this mode is selected,
data corresponding to the desired DTMF tone pair can be written to
the Transmit Register resulting in a tone burst of a specific duration
(see AC Characteristics). Subsequently, a pause of the same
duration is induced. Immediately following the pause, the Status
Register is updated indicating that the Transmit Register is ready
for further instructions and an interrupt will be generated if the
interrupt mode has been enabled. Additionally, if call progress
(CP) mode has been enabled, the burst and pause duration is
increased by a factor of two. When the burst mode is not selected
(logic ‘1’) tone bursts of any desired duration may be generated.
b1
TEST
TEST MODE
By enabling the test mode (logic’1’), the IRQ/CP pin will present
the delayed steering (inverted) signal from the DTMF receiver.
Refer to Figure 9 (b3 waveform) for details concerning the output
waveform. DTMF mode must be selected (CRA b1=0) before test
mode can be implemented.
b2
S/D
SINGLE /DUAL TONE
GENERATION
A logic ‘0’ will allow Dual Tone Multi-Frequency signals to be
produced. If single tone generation is enabled (logic ‘1’), either
row or column tones (low group or high group) can be generated
depending on the state of b3 in Control Register B.
b3
C/R
COLUMN/ROW TONES
When used in conjunction with b2 (above) the transmitter can be
made to generate single row or single column frequencies. A logic
‘0’ will select row frequencies and a logic ‘1’ will select column
frequencies.
Table 6 - Control Register B Description
BIT
NAME
STATUS FLAG SET
STATUS FLAG CLEARED
b0
IRQ
Interrupt has occurred. Bit one (b1) or
bit two (b2) is set.
Interrupt is inactive. Cleared after
Status Register is read.
b1
TRANSMIT DATA
REGISTER EMPTY
(BURST MODE ONLY)
Pause duration has terminated and
transmitter is ready for new data.
Cleared after Status Register is read or
when in non-burst mode.
b2
RECEIVE DATA REGISTER
FULL
Valid data is in the Receive Data
Register.
Cleared after Status Register is read.
b3
DELAYED STEERING
Set upon the valid detection of the
absence of a DTMF signal.
Cleared upon the detection of a valid
DTMF signal.
Table 7 - Status Register Description
14
Zarlink Semiconductor Inc.
MT8880C
Data Sheet
VDD
MT8880C
C1
R1
DTMF/CP
INPUT
R2
VDD
IN-
St/GT
GS
ESt
DTMF
OUTPUT
C4
RL
VRef
D3
VSS
D2
OSC1
D1
OSC2
D0
TONE
IRQ/CP
R3
Φ2
R/W
RS0
CS
Notes:
R1, R2 = 100 kΩ 1%
R3 = 374 kΩ 1%
R4 = 3.3 kΩ 10%
R5 = 4.7 MΩ 10%
RL = 10 k Ω (min.)
C1 = 100 nF 5%
C2 = 100 nF 5%
C3 = 100 nF 10%*
C4 = 10 nF 10%
X-tal = 3.579545 MHz
C2
R4
R5
X-tal
C3
IN+
* Microprocessor based systems can inject undesirable noise into
the supply rails. The performance of the MT8880 can be optimized
by keeping noise on the supply rails to a minimum. The decoupling
capacitor (C3) should be connected close to the device and ground
loops should be avoided.
Figure 13 - Application Circuit (Single-Ended Input)
15
Zarlink Semiconductor Inc.
To µP
or µC
MT8880C
Data Sheet
5.0 VDC
TEST POINT
130 pF
MMD6150
(or equivalent)
5.0 VDC
2.4 kΩ
3 kΩ
TEST POINT
24 kΩ
70 pF
MMD7000
(or equivalent)
Test load for D0-D3 pins
Test load for IRQ/CP pin
Figure 14 - Test Circuit
+5 V
3.3k
6802
MT8880C
IRQ
RS0
IRQ
Address
CS
Peripheral decode
VMA
R/W
R/W
Φ2
E
Data
Data
Figure 15 - MT8880C to 6802 Interface
16
Zarlink Semiconductor Inc.
MT8880C
Data Sheet
EXAMPLE 1: A software reset must be included at the beginning of all programs to initialize the control registers
after power up. The initialization procedure should be implemented 100ms after power up.
Description
Control
Data
RS0 R/W
b3
b2
b1
b0
CS
1) Read Status Register
0
1
1
X
X
X
X
2) Write to Control Register
0
1
0
0
0
0
0
3) Write to Control Register
0
1
0
0
0
0
0
4) Write to Control Register
0
1
0
1
0
0
0
5) Write to Control Register
0
1
0
0
0
0
0
6) Read Status Register
0
1
1
X
X
X
X
EXAMPLE 2: Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones
Description
RS0 R/W
b3
b2
b1
b0
CS
1) Write to Control Register A
0
1
0
1
1
0
1
(tone out, DTMF, IRQ, Select Control Register B)
2) Write to Control Register B
0
1
0
0
0
0
0
(burst mode)
3) Write to Transmit Data Register
0
0
0
0
1
1
1
(send a digit 7)
--------------------------------------wait for an interrupt or poll Status Register ---------------------------------------------4) Read the Status Register
0
1
1
X
X
X
X
-if bit 1 is set, the Tx is ready for the next tone, in which case...
Write to Transmit Register
0
0
(send a digit 5)
0
0
1
0
1
-if bit 2 is set, a DTMF tone has been received, in which case....
Read the Receive Data Register
0
0
1
X
X
X
X
-if both bits are set...
Read the Receive Data Register
Write to Transmit Data Register
1
0
X
0
X
1
X
0
X
1
0
0
0
0
NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms (±2 ms) AFTER THE DATA IS
WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms).
Figure 16 - Application Hints
17
Zarlink Semiconductor Inc.
MT8880C
Data Sheet
Absolute Maximum Ratings*
Parameter
Min.
Max.
Units
6
V
VSS-0.3
VDD+0.3
V
10
mA
-65
+150
°C
5 Package power dissipation
PD
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
1000
mW
1
Power supply voltage VDD-VSS
2
Voltage on any pin
3
Current at any pin (Except VDD and VSS)
4
Storage temperature
Symbol
VDD
VI
TST
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter
Sym.
Min.
Typ.‡
Max.
Units
5.00
5.25
V
+85
°C
1
Positive power supply
VDD
4.75
2
Operating temperature
TO
-40
3.575965
3.579545
3.583124
3 Crystal clock frequency
fCLK
‡ Typical figures are at 25 °C and for design aid only: not guaranteed and not subject to production testing.
Test Conditions
MHz
DC Electrical Characteristics† - VSS=0 V.
1
2
S
U
P
3
4
5
6
I
N
P
U
T
S
7
8
9
O
U
T
P
U
T
S
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Operating supply voltage
VDD
4.75
5.0
5.25
V
Operating supply current
IDD
7.0
11
mA
Power consumption
PC
57.8
mW
High level input voltage
(OSC1)
VIHO
Low level input voltage
(OSC1)
VILO
Steering threshold voltage
VTSt
Low level output voltage
(OSC2)
VOLO
High level output voltage
(OSC2)
VOHO
IOZ
10
VRef output voltage
VRef
11
VRef output resistance
ROR
Low level input voltage
VIL
High level input voltage
VIH
Input leakage current
IIZ
13
14
D
i
g
i
t
a
l
2.2
V
2.3
1.5
V
2.5
V
0.1
V
VDD=5 V
No load
Output leakage current
(IRQ)
12
3.5
Test Conditions
4.9
2.4
V
No load
VDD=5 V
1
10
µA
VOH=2.4 V
2.5
2.6
V
No load, VDD=5 V
1.3
kΩ
0.8
2.0
V
10
18
Zarlink Semiconductor Inc.
V
µA
VIN=VSS to VDD
MT8880C
Data Sheet
DC Electrical Characteristics† - VSS=0 V.
Sym.
Min.
Typ.‡
Source current
IOH
-1.4
-6.6
mA
VOH=2.4 V
Sink current
IOL
2.0
4.0
mA
VOL=0.4 V
Source current
IOH
-0.5
-3.0
mA
VOH=4.6 V
Sink current
IOL
2
4
mA
VOL=0.4 V
Sink current
IOL
4
16
mA
VOL=0.4 V
Characteristics
15
16
17
18
19
Data
Bus
ESt
and
St/Gt
IRQ/
CP
Max.
Units
Test Conditions
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25 °C, VDD =5 V and for design aid only: not guaranteed and not subject to production testing.
Electrical Characteristics
Gain Setting Amplifier - Voltages are with respect to ground (VSS) unless otherwise stated, VSS= 0V.
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
100
nA
VSS ≤ VIN ≤ VDD
1
Input leakage current
IIN
2
Input resistance
RIN
3
Input offset voltage
VOS
4
Power supply rejection
PSRR
50
dB
5
Common mode rejection
CMRR
40
dB
6
DC open loop voltage gain
AVOL
40
dB
CL = 20 p
7
Unity gain bandwidth
BW
1.0
MHz
CL = 20 p
8
Output voltage swing
VO
0.5
VDD-0.5
V
RL ≥ 100 kΩ to VSS
9
Allowable capacitive load (GS)
CL
100
pF
PM>40°
10
Allowable resistive load (GS)
RL
50
kΩ
VO = 4 Vpp
11
Common mode range
VCM
1.0
V
RL = 50 kΩ
10
MΩ
25
mV
VDD-1.0
1 kHz
Figures are for design aid only: not guaranteed and not subject to production testing.
Characteristics are over recommended operating conditions unless otherwise stated.
MT8880C AC Electrical Characteristics†- Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
1
R
X
Valid Input signal levels
(each tone of composite
signal)
Sym
Min.
Typ.‡
Max.
Units
Notes*
-29
dBm
1,2,3,5,6,9
27.5
mVRMS
1,2,3,5,6,9
dBm
1,2,3,5,6,9
+1
1,2,3,5,6,9
869
mVRMS
† Characteristics are over recommended operating conditions (unless otherwise stated) using the test circuit shown in Figure 13.
19
Zarlink Semiconductor Inc.
MT8880C
Data Sheet
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. fC=3.579545 MHz.
Characteristics
Sym.
Typ.‡
Min.
Max.
Units
Notes*
1
Positive twist accept
8
dB
2,3,6,9
2
Negative twist accept
8
dB
2,3,6,9
3
4
R
X
Freq. deviation accept
±1.5%±2Hz
Freq. deviation reject
±3.5%
2,3,5,9
2,3,5
5
Third tone tolerance
-16
dB
2,3,4,5,9,10
6
Noise tolerance
-12
dB
2,3,4,5,7,9,10
7
Dial tone tolerance
22
dB
2,3,4,5,8,9,11
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD = 5 V, and for design aid only: not guaranteed and not subject to production testing.
* See “Notes” following AC Electrical Characteristics Tables.
AC Electrical Characteristics† - Call Progress - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym.
Typ.‡
Min.
Max.
Units
Notes*
1
Lower freq. (ACCEPT)
fLA
320
Hz
@ -25 dBm
2
Upper freq. (ACCEPT)
fHA
510
Hz
@ -25 dBm
3
Lower freq. (REJECT)
fLR
290
Hz
@ -25 dBm
4
Upper freq. (REJECT)
fHR
540
Hz
@ -25 dBm
5
Call progress tone detect level
(total power)
-30
dBm
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD = 5 V, and for design aid only: not guaranteed and not subject to production testing
* See “Notes” AC Electrical Characteristics Tables
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Conditions
1
Tone present detect time
tDP
3
11
14
ms
Note 12
2
Tone absent detect time
tDA
0.5
4
8.5
ms
Note 12
3
Tone duration accept
tREC
40
ms
User adjustable#
Tone duration reject
tREC
ms
User adjustable#
ms
User adjustable#
ms
User adjustable#
4
5
R
X
20
Minimum interdigit pause duration
tID
6
Maximum tone drop-out duration
tDO
7
Delay St to b3
tPStb3
13
µs
See figure 9
8
Delay St to RX0-RX3
tPStRX
8
µs
See figure 9
9
Tone burst duration
tBST
50
52
ms
DTMF mode
Tone pause duration
tPS
50
52
ms
DTMF mode
Tone burst duration (extended)
tBSTE
100
104
ms
Call Progress mode
Tone pause duration (extended)
tPSE
100
104
ms
Call Progress mode
10
11
12
T
X
40
20
20
Zarlink Semiconductor Inc.
MT8880C
Data Sheet
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
13
14
15
16
17
T
O
N
E
O
U
T
18
21
22
23
Min.
High group output level
VHOUT
Low group output level
Typ.‡
Max.
Units
-6.1
-2.1
dBm
RL=10 kΩ
VLOUT
-8.1
-4.1
dBm
RL=10 kΩ
Pre-emphasis
dBP
0
3
dB
RL=10 kΩ
Output distortion (Single Tone)
THD
-35
dB
25 kHz Bandwidth
RL=10 kΩ
fD
±0.7
±1.5
%
fC=3.579545 MHz
50
kΩ
Frequency deviation
Output load resistance
RLT
2
10
Φ2 cycle period
tCYC
250
ns
M
P
U
Φ2 high pulse width
tCH
115
ns
Φ2 low pulse width
tCL
110
ns
I
N
T
E
R
F
A
C
E
Φ2 rise and fall time
tR, tF
19
20
Sym.
25
Conditions
ns
Address, R/W hold time
tAH,tRWH
26
ns
Address, R/W setup time (before Φ2)
tAS,tRWS
23
ns
Data hold time (read)
tDHR
22
ns
*
Φ2 to valid data delay (read)
tDDR
ns
200 pF load
27
Data setup time (write)
tDSW
45
ns
28
Data hold time (write)
tDHW
10
ns
29
Input Capacitance (data bus)
CIN
5
pF
30
Output Capacitance (IRQ/CP)
COUT
5
pF
fC
3.5759 3.5795 3.5831
MHz
24
25
26
31
32
33
34
35
D
T
M
F
C
L
K
Crystal/clock frequency
100
Clock input rise time
tLHCL
110
ns
Ext. clock
Clock input duty cycle
tHLCL
110
ns
Ext. clock
Clock input duty cycle
DCCL
60
%
Ext. clock
Capacitive load (OSC2)
CLO
30
pF
40
50
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.
* The data bus output buffers are no longer sourcing or sinking current by tDHR.
# See Figure 6 regarding guard time adjustment.
NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load.
2) Digit sequence consists of all 16 DTMF tones.
3) Tone duration=40 ms. Tone pause=40 ms.
4) Nominal DTMF frequencies are used.
5) Both tones in the composite signal have an equal amplitude.
6) The tone pair is deviated by ±1.5% ±2 Hz.
7) Bandwidth limited (3 kHz) Gaussian noise.
8) The precise dial tone frequencies are 350 and 440 Hz ( ±2%).
9) For an error rate of less than 1 in 10,000.
10) Referenced to the lowest amplitude tone in the DTMF signal.
11) Referenced to the minimum valid accept level.
12) For guard time calculation purposes.
21
Zarlink Semiconductor Inc.
MT8880C
Data Sheet
tCYC
tF
tR
Φ2
tCH
tCL
Figure 17 - Φ2 Pulse
Φ2
tAS
tDDR
tAH
CS
RS0
tRWS
tRWH
R/W
tDHR
Valid
Data
DATA BUS
Figure 18 - MPU Read Cycle
22
Zarlink Semiconductor Inc.
MT8880C
Data Sheet
Φ2
tAH
tAS
CS
RS0
tRWS
tRWH
R/W
tDSW
tDHW
Valid
Data
DATA BUS
Figure 19 - MPU Write Cycle
23
Zarlink Semiconductor Inc.
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However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
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This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
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any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
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Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
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