NX2119ACSTR

Evaluation board available. NX2119/2119A SYNCHRONOUS PWM CONTROLLER WITH CURRENT LIMIT PROTECTION PRELIMINARY DATA SHEET Pb Free Product DESCRIPTION FEATURES n n n n n n Bus voltage operation from 2V to 25V The NX2119 controller IC is a synchronous Buck conFixed 300kHz and 600kHz troller IC designed for step down DC to DC converter Internal Digital Soft Start Function applications. It is optimized to convert bus voltages from Prebias Startup 2V to 25V to outputs as low as 0.8V voltage. The Less than 50 nS adaptive deadband NX2119 operates at fixed 300kHz, while NX2119A operCurrent limit triggers latch out by sensing Rdson of ates at fixed 600kHz, making it ideal for applications Synchronous MOSFET requiring ceramic output capacitors. The NX2119 emn No negative spike at Vout during startup and ploys fixed loss-less current limiting by sensing the Rdson shutdown of synchronous MOSFET followed by latch out feature. n Pb-free and RoHS compliant Feedback under voltage triggers Hiccup. Other features of the device are: 5V gate drive, Adaptive deadband control, Internal digital soft start, Vcc n Graphic Card on board converters undervoltage lock out and shutdown capability via the n Memory Vddq Supply comp pin. n On board DC to DC such as 12V to 3.3V, 2.5V or 1.8V n ADSL Modem APPLICATIONS TYPICAL APPLICATION Vin +5V C4 100uF L2 1uH C5 1uF D1 MBR0530T1 1 Cin 280uF 18mohm R5 10 5 C3 1uF Vcc 7 BST Hdrv 2 C6 0.1uF M1 L1 1.5uH HI=SD M3 NX2119 COMP R4 37.4k C7 27pF SW Ldrv 8 C2 2.2nF 4 M2 R1 4k R2 10k Co 2 x (1500uF,13mohm) Vout +1.8V 9A 6 FB Gnd 3 C1 4.7nF R3 8k Figure1 - Typical application of 2119 ORDERING INFORMATION Device NX2119CSTR NX2119ACSTR NX2119ACUTR Rev.3.2 04/10/08 Temperature 0 to 70oC 0 to 70o C 0 to 70o C Package SOIC - 8L SOIC - 8L MSOP - 8L Frequency 300kHz 600kHz 600kHz Pb-Free Yes Yes Yes 1 NX2119/2119A ABSOLUTE MAXIMUM RATINGS VCC to GND & BST to SW voltage .................... -0.3V to 6.5V BST to GND Voltage ........................................ -0.3V to 35V SW to GND ...................................................... -2V to 35V All other pins .................................................... -0.3V to VCC+0.3V or 6.5V Storage Temperature Range ............................... -65oC to 150oC Operating Junction Temperature Range ............... -40oC to 125oC ESD Susceptibility ........................................... 2kV CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. PACKAGE INFORMATION 8-LEAD PLASTIC SOIC(S) θJA ≈ 130o C/W 8-LEAD PLASTIC MSOP θJA ≈ 216o C/W BST 1 HDrv 2 Gnd 3 LDrv 4 8 SW 7 Comp 6 Fb 5 Vcc BST HDrv Gnd LDrv 1 2 3 4 8 7 6 5 SW Comp Fb Vcc ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over Vcc = 5V, and TA= 0 to 70oC. Typical values refer to Ta = 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. PARAMETER Reference Voltage Ref Voltage Ref Voltage line regulation Supply Voltage(Vcc) VCC Voltage Range VCC Supply Current (Static) VCC Supply Current (Dynamic) Supply Voltage(VBST) VBST Supply Current (Static) VBST Supply Current (Dynamic) SYM VREF Test Condition Min TYP 0.8 0.2 4.5 5 3 TBD 5.5 MAX Units V % V mA mA VCC ICC (Static) Outputs not switching ICC CLOAD=3300pF FS=300kHz (Dynamic) IBST (Static) Outputs not switching IBST CLOAD=3300pF (Dynamic) FS=300kHz 0.2 TBD mA mA Rev.3.2 04/10/08 2 NX2119/2119A PARAMETER Under Voltage Lockout VCC-Threshold VCC-Hysteresis Oscillator (Rt) Frequency Ramp-Amplitude Voltage Max Duty Cycle Min Duty Cycle Min LDRV on time Controllable Min on time Error Amplifiers Transconductance Input Bias Current Comp SD Threshold Soft Start Soft Start time High Side Driver(CL=3300pF) Sourcing Output Impedance , Current Output Impedance , Sinking Current Rise Time Fall Time Deadband Time SYM TEST CONDITION MIN 3.8 TYP 4 0.2 300 600 1.5 93 0 250 100 2000 10 0.3 FS=300kHz I=200mA I=200mA 6.8 0.9 0.65 50 50 30 MAX 4.2 UNITS V V kHz kHz V % % nS nS umho nA V mS ohm ohm ns ns ns VCC_UVLO VCC Rising VCC_Hyst VCC Falling FS VRAMP 2119 2119A Ib Tss Rsource(Hdrv) Rsink(Hdrv) THdrv(Rise) VBST-VSW=4.5V THdrv(Fall) VBST-VSW=4.5V Tdead(L to Ldrv going Low to Hdrv going H) High, 10%-10% Low Side Driver (CL=3300pF) Output Impedance, Sourcing CurrentImpedance, Sinking Output Current Rise Time Fall Time Deadband Time OCP OCP voltage Rsource(Ldrv) I=200mA Rsink(Ldrv) I=200mA TLdrv(Rise) 10% to 90% TLdrv(Fall) 90% to 10% Tdead(H to SW going Low to Ldrv going L) High, 10% to 10% 0.9 0.5 50 50 30 ohm ohm ns ns ns 320 mV Rev.3.2 04/10/08 3 NX2119/2119A PIN DESCRIPTIONS PIN # 5 PIN SYMBOL VCC PIN DESCRIPTION Power supply voltage. A high freq 1uF ceramic capacitor is placed as close as possible to and connected to this pin and ground pin. 1 BST This pin supplies voltage to high side FET driver. A high freq 0.1uF ceramic capacitor is placed as close as possible to and connected to these pins and respected SW pins. Ground pin. This pin is the error amplifier inverting input. This pin is connected via resistor divider to the output of the switching regulator to set the output DC voltage. When FB pin voltage is lower than 0.6V, hiccup circuit starts to recycle the soft start circuit after 2048 switching cycles. This pin is the output of the error amplifier and together with FB pin is used to compensate the voltage control feedback loop. This pin is also used as a shut down pin. When this pin is pulled below 0.3V, both drivers are turned off and internal soft start is reset. This pin is connected to source of high side FET and provides return path for the high side driver. It is also used to hold the low side driver low until this pin is brought low by the action of high side turning off. LDRV can only go high if SW is below 1V threshold . High side gate driver output. Low side gate driver output. 3 GND 6 FB 7 COMP 8 SW 2 4 HDRV LDRV Rev.3.2 04/10/08 4 NX2119/2119A BLOCK DIAGRAM VCC FB 0.6V Bias Generator 1.25V 0.8V UVLO POR START Hiccup Logic OC BST HDRV COMP 0.3V START 0.8V OSC Digital start Up ramp S R FB 0.6V CLAMP COMP START GND Q PWM OC Control Logic VCC SW LDRV 1.3V CLAMP latch out OCP comparator 320mV Figure 2 - Simplified block diagram of the NX2119 Rev.3.2 04/10/08 5 NX2119/2119A APPLICATION INFORMATION Symbol Used In Application Information: VIN VOUT IOUT FS - Input voltage - Output voltage - Output current ∆IRIPPLE = = VIN -VOUT VOUT 1 × × LOUT VIN FS ...(2) 5V-1.8V 1.8v 1 × × = 2.56A 1.5uH 5v 300kHz DVRIPPLE - Output voltage ripple - Working frequency DIRIPPLE - Inductor current ripple Output Capacitor Selection Output capacitor is basically decided by the amount of the output voltage ripple allowed during steady state(DC) load condition as well as specification for the load transient. The optimum design may require a couple of iterations to satisfy both condition. Based on DC Load Condition The amount of voltage ripple during the DC load condition is determined by equation(3). Design Example The following is typical application for NX2119, the schematic is figure 1. VIN = 5V VOUT=1.8V FS=300kHz IOUT=9A DVRIPPLE