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NX2141

NX2141

  • 厂商:

    MICROSEMI(美高森美)

  • 封装:

  • 描述:

    NX2141 - SINGLE CHANNEL MOBILE PWM CONTROLLER WITH FEEDFORWARD AND ENABLE - Microsemi Corporation

  • 数据手册
  • 价格&库存
NX2141 数据手册
NX2141 SINGLE CHANNEL MOBILE PWM CONTROLLER WITH FEEDFORWARD AND ENABLE ADVANCE DATA SHEET Pb Free Product DESCRIPTION The NX2141 controller IC is a compact synchronous Buck controller IC designed for step down DC to DC converter applications with voltage feedforward functionality. Voltage feedforward provides fast response, good line regulation and nearly constant power stage gain under wide voltage input range. The NX2141 controller is optimized to convert single supply up to 24V bus voltage to as low as 0.8V output voltage. Internal UVLO keeps the regulator off until the supply voltage exceeds 7V where internal digital soft starts get initiated to ramp up output. The NX2141 employs fixed current limiting and FB UVLO followed by hiccup feature. Other features includes: 5V gate drive capability , Adaptive dead band control, available in 16 lead MLPQ and 10 lead MSOP package. FEATURES n Bus voltage operation from 7V to 24V n Less than 1uA shutdown current with Enable low n Excellent dynamic response with input voltage feedforward and voltage mode control n Internal Digital Soft Start Function n Fixed internal hiccup current limit n FB UVLO followed by hiccup feature n Power Good indicator available n Start into precharged output n Pb-free and RoHS compliant APPLICATIONS n n n n Notebook PC Graphic Card on board converters On board DC to DC such as 12V to 3.3V, 2.5V or 1.8V Set Top Box and LCD Display TYPICAL APPLICATION Vin1 +8 to 20V 100uF MBR0530T1 1uF 13 14 8 16 1uH 1uF 25TQC33M 25V,33uF Vin2 +5V 10 1uF PVCC VIN VCC BST Hdrv 1 0.1uF M1 10k ON OFF 5 9 12 PGOOD EN COMP 1uH NX2141 SW 15 Co 2*2R5TPE220MC (220uF,12mohm) Vout +1.05V 10A Ldrv 3 M2 2.3k 1nF 15nF 11 1.5k 10k 2.2nF FB Pgnd 2 Gnd 17 32k Figure1 - Typical application of NX2141(MLPQ) ORDERING INFORMATION Device NX2141CMTR NX2141CUTR Rev. 1.6 05/15/07 Temperature -40o C to 85o C -40o C to 85o C Package MLPQ-16L MSOP-10L Frequency 200kHz 200kHz Pb-Free Yes Yes 1 NX2141 ABSOLUTE MAXIMUM RATINGS VCC to GND & BST to SW voltage ...................... -0.3V to 6.5V VIN to GND ........................................................ -0.3V to 30V BST to GND Voltage .......................................... -0.3V to 35V SW to GND ....................................................... -2V to 35V All other pins ..................................................... -0.3V to 6.5V Storage Temperature Range ................................ -65oC to 150oC Operating Junction Temperature Range ................ -40oC to 125oC ESD Susceptibility ............................................ 2kV CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. PACKAGE INFORMATION 16-LEAD PLASTIC MLPQ PVCC VCC BST SW 10-LEAD PLASTIC MSOP θJA ≈ 200o C/W 16 HDRV 1 PGND 2 LDRV 3 NC 4 5 PGOOD 15 14 13 12 COMP BST 1 10 SW 9 COMP 8 FB 7 VCC 6 EN 17 AGND 11 FB 10 NC 9 EN θJA ≈ 46o C/W HDRV 2 GND 3 LDRV 4 VIN 5 6 NC 7 NC 8 VIN ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over Vcc =5V, VIN=12V and TA = -40oC to 85oC. Typical values refer to TA = 25oC. PARAMETER Reference Voltage Ref Voltage Ref Voltage line regulation Supply Voltage(Vcc) VCC Voltage Range Operating quiescent current Shut down current Vcc UVLO VCC-Threshold VCC-Hysteresis Supply Voltage(Vin) Vin Voltage Range Input Voltage Current Shut Down Current Rev. 1.6 05/15/07 SYM VREF Test Condition Min TYP 0.8 0.2 MAX Units V % VCC IQ ISD 4.75 EN=HIGH EN=LOW 1.5 5.25 5 1 V mA uA V V VCC_UVLO VCC Rising VCC_Hyst VCC Falling Vin Vin=24V EN=LOW 7 4.4 0.2 25 40 1 24 V uA uA 2 NX2141 PARAMETER Vin UVLO Vin-Threshold Vin-Hysteresis Oscillator (Rt) Frequency Frequency Over Vin Ramp-Amplitude Voltage Ramp Offset Ramp/Vin Gain Max Duty Cycle Min on time Error Amplifiers Transconductance Input Bias Current Comp SD threshold Vref and Soft Start Soft Start time High Side Driver (CL=3300pF) Output Impedance , Sourcing Current Output Impedance , Sinking Current Rise Time Fall Time Deadband Time Low N Side Driver (CL=3300pF) Output Impedance, Sourcing Current Output Impedance, Sinking Current Rise Time Fall Time Deadband Time Fixed OCP OCP voltage Threshold Enable Enable HI Threshold Enable LOW Threshold Rsource(Ldrv) Rsink(Ldrv) I=200mA I=200mA 1 0.5 50 50 30 ohm ohm ns ns ns SYM Vin_UVLO Vin_Hyst FS -5 VRAMP Vin=20V 2 0.8 0.1 88 150 2500 Ib 0.3 Tss FS=200kHz 10 100 Test Condition VCC Rising VCC Falling Min TYP 6 0.5 200 5 MAX Units V V KHz % V V V/V % nS umho nA V mS Rsource(Hdrv) Rsink(Hdrv) I=200mA I=200mA 1 0.8 50 50 30 ohm ohm ns ns ns THdrv(Rise) 10% to 90% THdrv(Fall) 90% to 10% Tdead(L to Ldrv going Low to Hdrv going H) High, 10% to 10% TLdrv(Rise) 10% to 90% TLdrv(Fall) 90% to 10% Tdead(H to SW going Low to Ldrv going L) High, 10% to 10% 320 1.4 0.4 mV V V Rev. 1.6 05/15/07 3 NX2141 PARAMETER Power Good(MLPQ only) Threshold Voltage as % of Vref Hysteresis FBUVLO Feedback UVLO threshold Over temperature Threshold Hysteresis SYM Test Condition FB ramping up Min TYP 90 5 percent of nominal 65 70 150 20 75 MAX Units % % % °C °C PIN DESCRIPTIONS PIN SYMBOL VCC PIN DESCRIPTION This pin supplies the internal 5V bias circuit. A 1uF ceramic capacitor is placed as close as possible to this pin and ground pin. This pin supplies voltage to high side FET driver. A high freq minimum 0.1uF ceramic capacitor is placed as close as possible to and connected to this pin and SW pin. Power ground. This pin is the error amplifiers inverting input. This pin is connected via resistor divider to the output of the switching regulator to set the output DC voltage. BST GND FB COMP This pin is the output of the error amplifier and together with FB pin is used to compensate the voltage control feedback loop. SW This pin is connected to source of high side FETs and provide return path for the high side driver. HDRV LDRV High side gate driver output. Low side gate driver output. Pull up this pin to Vcc for normal operation. Pulling this pin down below 0.4V shuts down the controller and resets the soft start. Bus voltage input provides power supply to oscillator and VIN UVLO signal. An open drain output that requires a pull up resistor to Vcc or a voltage lower than Vcc. When FB pin reaches 90% of the reference voltage, PGOOD changes from LO to HI state. Supply voltage for the low side fet drivers. A high frequency 1uF ceramic cap must be connected from this pin to the PGND pin as close as possible. EN VIN PGOOD (MLPQ only) PVCC Rev. 1.6 05/15/07 4 NX2141 BLOCK DIAGRAM FB 0.85Vref /0.90Vref PGOOD VCC Bias Generator 1.25V 0.8V UVLO POR START BST VIN 6V/ 5.5V HDRV COMP 0.3V VIN OC Control Logic OSC Digital start Up ramp S R Q DISABLE OC LDRV PWM PVCC SW START 0.8V FB 0.6V CLAMP START POR 1.3V CLAMP Hiccup Logic OCP comparator EN DISABLE SS_half_done 70%*Vp FB 320mV PGND COMP AGND Figure 2 - Simplified block diagram of the NX2141(MLPQ) Rev. 1.6 05/15/07 5 NX2141 Vin1 +8 to 20V 100uF 1uH 10 0.1uF 1uF 13 14 8 MBR0530T1 16 0.1uF 1 1uF 25TQC33M 25V,33uF Vin2 +5V 10 1uF PVCC VIN BST VCC Hdrv PGOOD M1 10k 5 9 12 1uH NX2141 SW 15 EN COMP Co 2*2R5TPE220MC (220uF,12mohm) Vout +1.05V 10A Ldrv 3 M2 2.3k 1nF 15nF 11 1.5k 10k 2.2nF FB Pgnd 2 Gnd 17 32k Figure 3 - Simplified Demo board schematic(MLPQ) Rev. 1.6 05/15/07 6 NX2141 Figure 4 - Demo board schematic based on ORCAD Rev. 1.6 05/15/07 7 NX2141 Bill of Materials Item number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Quantity 4 4 1 2 1 1 1 1 2 1 1 1 1 4 3 1 1 1 1 1 1 1 1 Reference C1,C5,C6,C18 C2,C4,C7,C9 C3 C19,C8 C10 C13 C14 C15 C17,C16 D1 L2 M1 M2 R1,R2,R3,R11 R4,R6,R14 R5 R8 R10 R12 R13 R15 U1 U2 Part 0.1u 1u 25TQC33M 47u 15nF 1000pF 2.2n 470p 2R5TPE220MC MBR0530T1 MLC1550-102ML FDS6294 FDS6676AS 0 10 100k 2.3k 32k 10k 1.5k 1k NX2141CMTR L78L05AB/sot89 Manufacturer SANYO SANYO Coilcraft Fairchildsemi Fairchildsemi NEXSEM INC. Rev. 1.6 05/15/07 8 NX2141 Demoboard waveforms Figure 5 - Output ripple(CH1 Vout ripple(50mV/ div),CH2 output current(5A/div), CH3 SW(5V/div)) Figure 6 - Transient response(CH1 Vout AC(50mV/div), CH2 output current(5A/div)) Figure 7 - Enlarged transient response(CH1 Vout AC(50mV/div), CH2 output current(5A/div)) Figure 8 - Enlarged transient response(CH1 Vout AC(50mV/div), CH2 output current(5A/div)) Figure 9 - Over Current Protection(CH2 output current(10A/ Figure 10 - Power Good(CH4 Vout(500mV/div), CH3 PGOOD(5V/div)) div), CH4 VOUT(500mV/div)) Rev. 1.6 05/15/07 9 NX2141 Demoboard waveforms(cont'd) Figure 11 - Step VIN response(CH1 Vout AC(50mV/ div), CH3 VIN(5V/div), CH4 SW(5V/div)) Figure 12 - Enlarged Figure 11 (CH1 Vout AC(50mV/ div), CH3 VIN(5V/div), CH4 SW(5V/div)) Figure 13 - Step into precharged output (CH1 EN (2V/ div), CH3 OUTPUT CURRENT(10A/div), CH4 VOUT(500mV/div)) efficinecy vs Iout(VIn=12V) 89.00% 88.00% 87.00% Efficiency(%) 86.00% 85.00% 84.00% 83.00% 82.00% 81.00% 80.00% 79.00% 0 2 4 6 Iout(A) 8 10 12 Figure 14 - Soft start(CH1 EN(2V/div),CH2 output current(10A/div), CH3 VOUT(500mV/div)) efficinecy vs Iout(VIn=19V) 86.00% 84.00% Efficiency(%) 82.00% 80.00% 78.00% 76.00% 74.00% 0 2 4 6 Iout(A) 8 10 12 Figure 15 - Efficiency(VIN=12V, VOUT=1V) Figure 16 - Efficiency(VIN=19V, VOUT=1V) Rev. 1.6 05/15/07 10 NX2141 Current Ripple @ maximum input voltage is APPLICATION INFORMATION Symbol Used In Application Information: VIN VOUT IOUT FS DIRIPPLE - Input voltage - Output voltage - Output current - Switching frequency - Inductor current ripple calculated as IRIPPLE = = VIN -VOUT VOUT 1 × × LOUT VIN FS ...(2) 20V-1.05V 1.05V 1 × × = 4.97A 1uH 20V 200kHz DVRIPPLE - Output voltage ripple Output Capacitor Selection Output capacitor is basically decided by the amount of the output voltage ripple allowed during steady state(DC) load condition as well as specification for the load transient. The optimum design may require a couple of iterations to satisfy both condition. Based on DC Load Condition The amount of voltage ripple during the DC load condition is determined by equation(3). Design Example Power stage design requirements: VINMIN=8V VINMAX=20V VOUT=1.05V IOUT_max =10A DVRIPPLE
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