NX2601CMTR

Evaluation board available. NX2601 DUAL SYNCHRONOUS PWM CONTROLLER WITH NMOS LDO CONTROLLER & 5V BIAS REGULATOR PRELIMINARY DATA SHEET Pb Free Product DESCRIPTION The NX2601 controller IC is a triple controller with a dual channel synchronous Buck controller IC and an LDO controller designed for multiple converters such as PCIe graphic card applications .The two synchronous PWM controllers are 180 degree out of phase which reduces the input ripple current, allowing to reduce the # of input capacitors.Another main feature of the part is that it can operate from single 12V supply while maintaining a regulated 5V supply for the biasing and the internal drivers. Other features of NX2601 are: programmable frequency from 200kHz to 1MHz, independent digital soft start and enable pins for each controller which allows for different power sequencing, Adaptive driver provides optimized efficiency while maintain sufficient deadband, Vcc undervoltage lock out and current limiting using an Rdson of the external MOSFET with HICCUP feature. n Two channel PWM with out of phase operation n Individual digital soft start for two PWM output and LDO controller n Bus voltage operation from 2V to 25V n Hiccup Current limit by sensing Rdson of MOSFET n Adjustable frequency up to 1Mhz per channel n Adaptive deadband time n Three enable pin available allows for independent power sequencing n MLPQ-32L package offers small size n Pb-free and RoHS compliant n n n n PCI Graphic Card on board converters Vddq Supply in mother board applications On board DC to DC such as 12V to 3.3V, 2.5V or 1.8V FPGA and Set Top Box Applications FEATURES APPLICATIONS +5V C17 68uF R11 10 R12 5k C15 1uF 5 VCC PVCC1 23 C1 1uF TYPICAL APPLICATION +5V D1 BST1 HDRV1 SW1 24 25 26 R1 10.5k R2 1.5k M2 C6 2.7nF R4 20.8k R3 10.4k C4 0.1uF M1 C2 180uF C3 100uF VIN1 2N3904 47pF C16 5k C24 C20 150uF M5 0 R16 C19 5k 150uF 1uF 11 REG FB R13 1.65k 10 9 REG OUT AUXVCC L1 1uH VIN1 +12V VIN2 +3.3V VOUT3 +2.5V/2A R15 C18 8 LDO OUT 7 OCP1 27 LDRV1 22 21 L2 0.78uH 150pF R17 2.35k LDO FB C7 2 x (2R5TPD680M6,680uF,6mohm) VOUT1 +1.2V@15A NX2601 R18 1.5k PGND1 3 OFF R25 10k ON 2N3904 R26 10k ENLDO R19 1.25k Fb1 29 28 Comp1 18 R5 5k 8.2nF C5 C22 220pF C25 1uF PVCC2 C8 1uF +5V D2 C9 180uF M3 L4 1.5uH R20 VIN1 6.8k R21 1.25k 2N3904 R28 10k 1 ENSW1 BST2 HDRV2 2 ENSW2 SW2 17 16 15 R6 6k M4 C11 0.1uF OFF R27 10k ON OCP2 14 6 RT R24 62k 30 C21 1nF VP 31 VREF LDRV2 PGND2 19 20 R7 820 C13 3.3nF C14 3 x (4TPE150M,150uF,18mohm) R8 8.7k VOUT2 +1.8V/10A GND 4 Fb2 12 13 Comp2 R10 5k C23 C12 10nF 220pF R9 6.97k PATENT PENDING Figure1 - Typical application of 2601 ORDERING INFORMATION Temperature 0 to 70oC Package MLPQ-32L Frequency 200kHz to 1MHz Pb-Free Yes 1 Device NX2601CMTR Rev. 2.3 12/01/06 NX2601 ABSOLUTE MAXIMUM RATINGS Vcc,PVcc & BST to SW voltage ......................... 6.5V BST Voltage ...................................................... 35V SW ................................................................... -5V(Note1) to 35V AUXVCC .......................................................... 35V All other pins .................................................... GND to Vcc+0.3V Storage Temperature Range ............................... -65oC to 150oC Operating Junction Temperature Range ............... -40oC to 125oC CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. PACKAGE INFORMATION 32-LEAD 5x5 PLASTIC MLPQ COMP1 OCP1 VREF SW1 VP HDRV1 24 BST1 23 PVCC1 22 LDRV1 FB1 NC ENSW1 1 ENSW2 2 ENLDO 3 GND VCC 4 5 32 31 30 29 28 27 26 25 NX2601 21 PGnd1 20 PGnd2 19 LDRV2 18 PVCC2 17 BST2 θJA ≈ 35o C / W RT 6 LDO FB 7 LDO OUT 8 9 10 11 12 13 14 15 16 AUXVCC REG FB FB2 COMP2 REG OUT OCP2 SW2 HDRV2 ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over Vcc = 5V, VBST-VSW =5V, ENSW1=HIGH, ENSW2=HIGH, ENLDO=HIGH, and T A = 0 to 70oC. Typical values refer to T A = 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS Reference Voltage VREF 4.5 < Vcc < 5.5 FB Voltage 0.800 V FB Voltage Line Regulation 0.4 % Vcc Supply Voltage VCC Vcc Voltage Range 5.5 5.0 4.5 V ICC_STA Outputs not switching Vcc Static Supply Current 2.0 mA ICC_DYN Freq=600kHz, Vcc Dynamic Supply 8 mA CLOAD = 3300pF Current 4. VBST VBST Voltage Range 5.5 5.0 4.5 V IBST_STA Outputs not switching VBST Static Supply Current 2.0 mA IBST_DYN Freq = 600KHz, VBST Dynamic Supply TBD mA CLOAD = 3300pF Current Rev. 2.3 12/01/06 2 NX2601 PARAMETER Under Voltage Lockout UVLO Threshold - Vcc UVLO Hysteresis - Vcc UVLO Threshold - VAUXVcc UVLO Hysteresis - VAUXVcc Error Amplifiers Open Loop Gain Input Bias Current Input Offset Voltage Oscillator Frequency SYM VCC_UVLO VCC__HYST VAUX_UVLO VAUX_HYST TEST CONDITION Supply Ramping Up Supply Ramping Down Supply Ramping Up Supply Ramping Down MIN TYP 4 0.2 7 0.7 65 0.3 0 FS Rt=30k,measured at the output drive 600 1 Fs=600KHz Enable ramp up LDOOUT=LDOFB AUXVCC=24V,LDO FB=0.7V IO_SOURCE=1.4mA AUXVCC=24V,LDO FB=0.9V IO_SINK=1.4mA GBNT(Note2) REGOUT=REGFB AUXVCC=24V,REG FB=1.1V IO_SOURCE=1.4mA AUXVCC=24V,REG FB=1.4V IO_SINK=1.4mA GBNT(Note2) -0.2 22 -0.2 22 3.41 1.25 100 0.8 0 23.5 0.2 50 1.25 0 23.5 0.2 50 MAX UNITS V V V V dB uA mV KHz V mS V mV V µA V V dB V µA V V dB Ramp Amplitude VRAMP EN & SS Soft Start Time TSS Enable Threshold Voltage Enable Hysterises LDO Controller LDO FB Voltage FB Pin Bias Current LDO_out Output Voltage High LDO_out Output Voltage Low Open Loop Gain 5V AUX REG REG FB Voltage FB Pin Bias Current REG_out Output Voltage High REG_out Output Voltage Low Open Loop Gain High Side driver (CL=3300pF) Output Impedance, Sourcing Current Output Impedance , Sinking Current Rise Time Fall Time Deadband Time Rsource_H R sink_H THDRV_RISE 10% to 90% THDRV_FALL 90% to 10% TDEAD_LH LDRV going Low to HDRV going High, 10% to 10% 0.85 ohm 0.65 25 20 30 ohm ns ns ns Rev. 2.3 12/01/06 3 NX2601 PARAMETER Low Side driver (CL=3300pF) Output Impedance, Sourcing Current Output Impedance , Sinking Current Rise Time Fall Time Deadband Time SYM TEST CONDITION MIN TYP MAX UNITS Rsource_L 0.85 R sink_L TLDRV_RISE 10% to 90% TLDRV_FALL 90% to 10% TDEAD_HL SW going Low to LDRV going High, 10% to 10% 0.5 25 20 20 ohm ns ns ns ohm Note 1: 500ns transient. This pin can withstand -2V DC. Note 2: This parameter is guaranteed by design but not tested in production(GBNT). Rev. 2.3 12/01/06 4 NX2601 PIN DESCRIPTIONS PIN # 1 2 PIN SYMBOL ENSW1 ENSW2 PIN DESCRIPTION A resistor divider is connected from the respective switcher BUS voltages to these pins that holds off the controllers soft start until this threshold is reached. An external low cost MOSFET or NPN transisitor can be connected to this pin for external enable control. A resistor divider is connected from the LDO bus voltage to this pin that holds off the LDO soft start until this threshold is reached. An external low cost MOSFET can be connected to this pin for external enable control. Analog ground. IC's supply voltage. This pin biases the internal logic circuits. A high freq 1uF ceramic capacitor is placed as close as possible to and connected to this pin and ground pin. Oscillator's frequency can be set by using an external resistor from this pin to GND. This frequency is the master clock frequency which is internally divided by two to set each controller frequency. LDO controller feedback input. If the LDOFB pin is pulled below 0.5*Vref, an internal comparator after certain delay and pulls down LDOOUT pin and initiates the HICCUP circuitry. During the startup this latch is not activated, allowing the LDOFB pin to come up and follow the Soft started Vref voltage. LDO controller output. This pin is controlling the gate of an external NCH MOSFET. The maximum rating of this pin is 16V. This pin is the supply voltage for the LDO controller as well as the 5V regulator controller that regulates the voltage at Vcc derived from the BUS voltage. The maximum voltage applied to this pin is 30V. The output of the 5V regulator controller that drives a low current low cost external BIPOLAR transistor or an external MOSFET to regulate the voltage at Vcc pin derived from BUS voltage. This eliminates an otherwise external regulator needed in applications where 5V is not available. Feedback pin of the 5V regulator controller. A resistor divider is connected from the output of the 5V regulator to this pin to complete the loop. This pin is the error amplifiers inverting input. These pins are connected via resistor dividers to the output of the switching regulators to set the output DC voltage. These pins are the outputs of error amplifiers and are used to compensate the respective voltage control feedback loops. 3 ENLDO 4 GND 5 VCC 6 RT 7 LDO FB 8 LDO OUT 9 AUXVCC 10 REGOUT RER 11 REGFB 12 29 13 28 FB2 FB1 COMP2 COMP1 Rev. 2.3 12/01/06 5 NX2601 PIN DESCRIPTIONS PIN # 14 PIN SYMBOL OCP2 PIN DESCRIPTION This pin is connected to the drain of the external low side MOSFET and is the input of the over current protection(OCP) comparator. An internal current source which equals 1.25V divided by Rt resistor is flown to the external resistor which sets the OCP voltage across the Rdson of the low side MOSFET. Current limit point is this voltage divided by the Rds-on. Once this threshold is reached the Hdrv and Ldrv pins are switched low and an internal hiccup circuit is set that recycles the soft start circuit after 2048 switching cycles. 27 OCP1 15 26 16 25 17 24 18 23 19 22 20 21 SW2 SW1 HDRV2 HDRV1 BST2 BST1 PVCC2 PVCC1 LDRV2 LDRV1 PGND2 PGND1 Thesepi ar connect t sour ofhi si FETsandpr de r ur pat f ns e ed o ce gh de ovi et n h or t hi si drver Theyar al used t hol t l si drver l untlt s he gh de i s. e so o d he ow de i s ow i hi pi i br n s oughtl by t acton ofhi si t ni of.LDRVs can onl go hi i ow he i gh de ur ng f y gh f SW i bel 1V t eshol . s ow hr d Hi si gat drverout s. gh de e i put Thi pi suppl volage t hi si FET drverA hi feq 1uF cer i capaci sn i es t o gh de i . gh r am c t i pl or s aced as cl as possi e t and connect t t ose bl o ed o hese pi and r ns espect ed SW pi ns. Suppl volage f t l si f drver A hi fequency1uF cer i capm ust y t or he ow de et i s. gh r am c be connect fom t s pi t t PGND1 and PGND2 pi as cl as possi e t ed r hi n o he n ose bl o t pi he ns. Low si gat drverout s. de e i put Powergr ound pi f l si drver n orow de i s. Thi pi i t fr eroram pli non-nveri i . spi shoul becons n s he ist r ier i tng nput Thi n f d nect eihert anext nal ef encevolage (r ng appl i ort t ed t o er r er t tacki i on) o he cat i er r er nt nalef encevolagepr dedbyt sdevi t ovi hi ce. Ref encevolage avai e. 100pFcapaciorcan be connect fom t spi t er t l abl A t ed r hi n o GND.Thi pi i hel l unt i er VccUVLO and t ENSW 1 pi ar good, s n s d ow i nt nal l he ne al ng i t sof st t l owi t o t ar. 30 VP 31 VREF 32 NC Rev. 2.3 12/01/06 6 NX2601 BLOCK DIAGRAM AUXVCC Bias REGFB 9.6/9.2 REGOUT VCC Vref ENSW1 1.25/1.15 two phase OSC Digital start Up ramp1 S R FB1 PGND1 COMP1 OCP1 Channel 1 PWM Controller OCP comparator BST2 Channel 2 PWM controller (exclude oscillator) DrvH2 SW2 PVCC2 DrvL2 PGND2 OCP2 ENLDO 1.25/1.15 POR_LDO GND digital start up Q POR_SW DRVL1 set1 SW1 Control Logic PVCC1 Bias Generator 1.25V 0.8V 4/3.8 UVLO POR_LDO UVLO POR_SW BST1 DRVH1 RT VP ENSW2 FB2 COMP2 LDO control logic LDOOUT 0.4 FBLDO Rev. 2.3 12/01/06 7 NX2601 +5V C17 68uF R19 10 R16 5k C7 47pF C8 33uF R13 5k Q2 C10 1uF 5 VCC PVCC1 23 C41 1uF VIN1 11 REG FB R15 1.65k 10 9 REG OUT AUXVCC +5V D1 C24 1uF L2 1uH C23 180uF C21 39uF BST1 HDRV1 SW1 24 25 26 R22 10.5k C11 0.1uF Q4 VIN1 +12V VIN3 +3.3V VOUT3 +2.5V/2A C5 150uF M5 0 C4 150uF R11 5k R7 1.5k R10 C3 8 LDO OUT 7 OCP1 27 LDRV1 22 21 5k R24 C18 C42 1uF L1 0.78uH R23 20k C12 470pF C13,C14 680uF,6mohm R27 10.4k 150pF R6 2.35k VOUT1 +1.2V@15A LDO FB R26 1.5k C19 2.7nF Q5 NX2601 PGND1 3 R5 1.25k ENLDO Fb1 29 28 Comp1 8.2nF C17 220pF R25 20.8k R8 VIN1 6.8k R4 1.25k 1 ENSW1 PVCC2 18 +5V D2 C38 1uF L4 1uH C36 180uF C33 39uF BST2 2 HDRV2 SW2 6 RT 17 16 15 R32 3k C31 0.1uF Q6 VIN2 +5V R9 VIN2 2.7k R3 1.25k ENSW2 L3 1.5uH R34 20k OCP2 14 R2 62k 30 C1 100pF R1 1k 31 VREF C2 100pF GND 4 VP LDRV2 PGND2 19 20 Q7 R33 5k C32 C34 470pF R28 330 C25 8.2nF C26,27,28 150uF,18mohm R29 3.5k VOUT2 +1.8V@10A Fb2 12 13 Comp2 C37 10nF 220pF R35 2.7k Simplified Demo board schematic Rev. 2.3 12/01/06 8 NX2601 TP3 Q3 OP R 19 10 J6 1 2 3 4 5 C 10 1u J7 SW 1 2 3 4 5 1 SW 2 TP4 S W 1 _ IN R 17 0 R 18 Q2 C 8 2N3904 0 PVC C TP7 5 16TQ C 33M C9 R 1 6 6 T P B 68M U 1 4.99k Vcc1 C 24 PVC C D 1N 5819 1u L2 DO1603C-102 S W 1 _ IN C 21 16S V P A 39M A A VCC R 13 TP1 L D O _ IN 4.99k 0 D1 BST1 24 C 11 C 23 C 22 11 R 14 R 15 1.65k REG_Fb 16S V P A 180M P O Q4 R 20 0 IR F 3706 .1u Hdrv 1 SW1 REG_OUT OCP1 AUX_VCC LDO_OUT 25 26 27 C 20 SW1 C7 47p L1 DO5010P-781HC Q5 R 23 20k J2 SW1_OUT 1 2 10 C5 4TP E 150M R 22 10.5k 9 Q1 M T D 3055E R 1 2 0 8 C3 150pf N X 2601_M L P Q 2R 5T P D 680M 6 470p LD O _O U T TP2 J1 1 2 3 4 5 C4 4 T P E 150M 32 PVC C C 41 PGND1 Fb1 21 29 C 17 Comp1 28 C 18 8.2n 1u 2R 5T P D 680M 6 IR F 3706 C 12 R 27 10.4k OP op 22 Ldrv 1 23 PVCC1 R 21 0 C 13 C 14 C 15 C 16 Op J4 1 5 4 3 2 C 39 .1u NC R 10 0 R 26 1.5k 220p 20.8k C 19 2.7n R 11 4.99k 7 R6 2.35k LDO_FB TP5 R 25 Vcc2 C 38 1u C6 .1u R 24 L4 DO1603C-102 C 36 C 35 OP S W 2 _ IN C 33 16S V P A 39M A A L D O _ IN J9 1 2 LD O _O U T S W 1 _ IN R7 1.5k D2 BST2 Hdrv 2 17 D 1N 5819 R5 1.25k PVC C R 30 0 8 7 6 5 3 4.99k EN_LDO R8 6.8k 16 C 31 .1u 4 Q6 IR F 7822 16S V P A 180M 1 EN_SW1 R4 1.25k SW2 2 EN_SW2 OCP2 15 14 SW2 C 30 R 32 3k L3 DO5010P-222HC R 34 20k 1 2 3 J3 SW2_OUT 1 2 S W 2 _ IN J8 L D O _ IN L D O _ IN 1 2 3 S W 2 _ IN 4 5 S W 2 _ IN 6 7 8 9 S W 1 _ IN 10 11 12 13 14 15 16 17 18 19 20 S W 2 _ IN S W 2 _ IN 1k R9 2.7k 8 7 6 5 R3 L D O _ IN TP6 1.25k C 26 C 27 C 28 C 29 op 4T P E 150M 4T P E 150M 4T P E 150M op 6 19 Ldrv 2 18 PVCC2 Rt R 31 0 4 Q7 R2 62k C 34 470p PVC C C 42 20 12 C 32 AGND 1u IR F 7822 C1 100p 30 R1 1k Vp PGND2 Fb2 1 2 3 R 29 3.5k 220p J5 1 C 25 C 40 8.2nF .1u R 36 C2 100p C 37 10n 2.7k R 28 R 35 330 31 Vref Comp2 13 R 33 4.99k PACKAGE:MLPQ32L Size Date: Document Number 4 NX2601- 2EVL BRD SCHEMATI 0 C 1 of 1 T h u rsday, M a rc h 2 4 , 2 0 0 5 Sheet Figure 2 - Demo board schematic based on ORCAD 5 4 3 2 Rev A Rev. 2.3 12/01/06 9 NX2601 Bill of Materials Item number Quantity 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev. 2.3 12/01/06 2 1 5 5 1 1 1 5 2 2 9 2 1 1 2 2 1 1 2 5 3 1 1 2 1 1 1 2 2 1 1 3 1 2 1 2 8 5 1 1 1 2 1 1 1 1 1 1 7 1 C2,C1 C3 C4,C5,C26,C27,C28 C6,C11,C31,C39,C40 C7 C8 C9 C10,C24,C38,C41,C42 C12,C34 C14,C13 Q3,R14,C15,C16,C20,C22, C29,C30,C35 C17,C32 C18 C19 C21,C33 C36,C23 C25 C37 D1,D2 J1,J4,J5,J6,J7 J2,J3,J9 J8 L1 L2,L4 L3 Q1 Q2 Q4,Q5 Q7,Q6 R1 R2 R3,R4,R5 R6 R7,R26 R8 R35,R9 R10,R12,R17,R18,R20,R21, R30,R31 R11,R13,R16,R24,R33 R15 R19 R22 R34,R23 R25 R27 R28 R29 R32 R36 TP1,TP2,TP3,TP4,TP5,TP6, TP7 U1 Value 100p 150pf 4TPE150M .1u 47p 16TQC33M 6TPB68M 1u 470p 2R5TPD680M6 OP 220p 8.2n 2.7n 16SVPA39MAA 16SVPA180M 8.2nF 10n D1N5819 SCOPE TP CON2 CON20B DO5010P-781HC DO1603C-102 DO5010P-222HC MTD3055E 2N3904 IRF3706 IRF7822 1k 62k 1.25k 2.35k 1.5k 6.8k 2.7k 0 4.99k 1.65k 10 10.5k 20k 20.8k 10.4k 330 3.5k 3k 10k TP NX2601_MLPQ Manufacture SANYO SANYO SANYO SANYO SANYO SANYO Tektronics Coilcraft International Rectifier International Rectifier NEXSEM INC. 10 NX2601 Demoboard waveforms Figure 3 - Start up waveform of VCC by internal regulator. Ch1(AUXVCC), Ch3( VCC&PVCC) Figure 6 - Output ripple for power output CH1 and CH2 Figure 4 - Soft start for Channel 1 1.2V and chanel 2 1.8V output Figure 7-Transient response for first channel 1.2V output Figure 5 - Soft start for Channel 1 1.2V and LDO output Rev. 2.3 12/01/06 Figure 8 -Transient reponse for Channel 1. (zoomed) 11 NX2601 Demo Board Waveforms (Cont') Figure 9 - Ch2 1.8V output transient 0 to 9A. Figure 12 - Ch1 is short. All channels go into hiccup. Figure 10 - Ch2 1.8V transient (zoomed) Figure 13 - Ch2 is in short. All channels are in hiccup. Figure 11 - Transient response for 2.5V LDO output Figure 14 - LDO in short. All channels go into hiccup. Rev. 2.3 12/01/06 12 NX2601 APPLICATION INFORMATION Symbol Used In Application Information: VIN VOUT IOUT FS - Input voltage - Output voltage - Output current ∆IRIPPLE = = VIN -VOUT VOUT 1 × × L OUT VIN FS ...(2) 12V-1.2V 1.2V 1 × × = 4.6A 0.78uH 12V 300kHz DVRIPPLE - Output voltage ripple - Switching frequency DIRIPPLE - Inductor current ripple Output Capacitor Selection Output capacitor is basically decided by the amount of the output voltage ripple allowed during steady state(DC) load condition as well as specification for the load transient. The optimum design may require a couple of iterations to satisfy both condition. Based on DC Load Condition The amount of voltage ripple during the DC load condition is determined by equation(3). Design Example Power stage design requirements: VIN=12V VOUT=1.2V IOUT =15A DVRIPPLE