PD671xxx - 8 / 12 / 24-Channel PoE AF and AT DIMM
Data Sheet (Non-confidential)
DESCRIPTION
Microsemi’s™ new and unique family of Power over Ethernet
(PoE) modules enable next-generation network devices to
share data and power over the same cable. The PD671xxx
PoE PSE modules are fit / form compatible with the standard
plug-in memory modules used in personal computers (Dual
Inline Memory Modules - DIMMs) (see Figure 1 and Figure 12).
Thus, the use of these modules permit network devices to be
designed for up to 96 ports, with fewer ports actually installed.
Additional modules can be inserted in the field at any time.
KEY FEATURES
The PD671xxx (8, 12 or 24 ports DIMM) includes a wide range
of functions. Some of these modules include the PD69000
micro-controller unit (PoE controller) for Enhanced features and
a flexible work environment in a DIMM master or DIMM slave
configuration (refer to Ordering Information, page 2).
Microsemi’s PoE PD671xxx DIMMs implement real time
mechanisms including detection, classification, port real-time
protection and system level functions (power management and
MIB support).
Microsemi’s PD69012 IC, 12-channel PoE Manager IC is at the
heart of these modules. PD671xxx DIMMs enable the
detection of IEEE802.3at-2009 Type 1 (low power) or Type 2
(high power) Powered Devices (PDs), ensuring safe power
feeding and removal over Ethernet ports. The PD69012-based
DIMMs detect and disable disconnected ports, using DC or AC
disconnection methods. The DIMMs are embedded in multiport and highly populated Ethernet switches, requiring a
minimum of external components.
The PD671xxx DIMM is fully backwards compatible with the
PD670xx DIMM and can be dropped into existing designs.
Figure 1: PoE PD67124 DIMM
IMPORTANT: For the most current data, consult Microsemi’s website:
http://www.microsemi.com
IEEE 802.3AT-2009 and
IEEE802.3AF-2003 compliant
Up to 30 W per port power PoE
solution
RoHS compliant
Supports IETF PoE MIB (RFC 3621)
Up to 24 power ports per single DIMM
Up to 96 ports in a system, using
master and slave configuration
Thermal protection per port
Thermal monitoring capabilities
Pre-standard detection methods
(Cisco Inline Power and Power over
LAN Legacy)
Non-standard terminals supported
DC disconnect with DC modulation
AC disconnect function utilizing
external diodes
PD 2-events classification function
Operates using a single input (44 to
57 VDC)
I2C or UART host interface
Host communication is backward
compatible with PD67024M
communication, or Marvell® ISSR
Programmable over current protection
per port
Built-in power management algorithm
Internal power-on reset mechanism
Fast port shutdown on power supply
failure
Supports Backplane Power
Management
Automatic on/off sequencer for 96
ports
Disable/enable power per port
Continuous port current monitoring
Serial interface for LED indicator
support
Backwards compatible with PD670xx
Fit/form compliant with168-pin DIMM
JEDEC MO-161F, 3.3 V
Space efficient compact design
Factory pre-tested, for plug-and-play
integration
Safety standard compliant: UL / cUL
per UL60950-1 (mounted on
Microsemi evaluation board)
PD671xxx - 8 / 12 / 24-Channel PoE AF and AT DIMM
Data Sheet (Non-confidential)
Ordering Information
Part Number
Port Disconnect
Method
DIMM
Master/Slave
Mode
Enhanced/Auto [3]
24
DC
Master
Enhanced
24
PD67112MDC-gggg
12
DC
Master
Enhanced
PD67108MDC-gggg
8
DC
Master
Enhanced
PD67124MAC-gggg
24
AC
Master
Enhanced
PD67112MAC-gggg
12
AC
Master
Enhanced
PD67108MAC-gggg
8
AC
Master
Enhanced
Master
Auto
PD67124AS
PD67112AM
PD67108AM
24
24
12
8
Slave
[2]
PD67124S
PD67124AM
AC/DC
[4]
Enhanced
AC/DC
[5]
AC/DC
[5]
AC/DC
[5]
Master
Auto
AC/DC
[5]
Master
Auto
Slave
[2]
WWW . Microsemi .C OM
PD67124MDC-gggg [1]
Ports
Auto
Note:
[1] – gggg: MCU software version.
[2] – DIMM Slave should be used in conjunction with DIMM Master (for systems require more than 24 ports).
[3] – Enhanced and Auto mode of operation stand for the PoE system features. The Enhanced mode system includes the PD69000 PoE
controller.
[4] – DIMM Slave port disconnection method is determined by the DIMM Master which controllers it.
[5] – DIMM functioning at the Auto Mode Configuration can be configured to AC or DC port disconnection method by the system host.
Further details can be found in the Auto Mode User Guide, Catalogue Number 06-1200-056.
APPLICABLE DOCUMENTS
IEEE 802.3at-2009 standard, DTE Power via MDI
PD69012 Data Sheet, Catalogue Number 06-0069-058
PD69000 Data Sheet, Catalogue Number 06-0070-058
Serial Communication Protocol User Guide 06-0032-056
Auto Mode User Guide, Catalogue Number 06-1200-056
Layout Design Guidelines for DIMM-based PoE Systems, AN-132 Catalogue Number 06-0010-080
Designing a DIMM-based PoE System, AN-133 Catalogue Number 06-0011-080
♦
PD671xx DIMM
Copyright © 2009
Microsemi
Page 2
Rev. 1.0 / 17-March-10
Analog Mixed Signal Group
2381 Morse Avenue, Irvine, CA 92614, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD671xxx - 8 / 12 / 24-Channel PoE AF and AT DIMM
Data Sheet (Non-confidential)
ABSOLUTE MAXIMUM RATINGS
-0.3 to 80 VDC (1)
-0.3 to 0.3 VDC (2)
-0.3 to 80 VDC (1)
3.8 VDC
-0.3 to 6 VDC
-0.3 to (3_3Vout + 0.3 VDC)
-0.3 to (3_3Vout + 0.3 VDC)
± 2 kV (3)
-40° to +125° C
(1) 80 VDC is the transient voltage that can be applied for up to one minute.
(2) Maximum voltage value between grounds.
(3) ESD Human Body Model is: (CZap = 100 pF, RZap = 1500 Ω).
Stresses beyond those listed above can cause permanent damage to the device. Exposure to absolute maximum rating
conditions for extended periods could affect device reliability.
CALCULATED MTBF DATA
WWW . Microsemi .C OM
Vmain
DGND, AGND, QGND
VPORT_POSx, VPORT_NEGx
3_3Vout
EXT_REG
I2C_Addr_M.
MISO, MOSI, SCK, CS, SCL, SDA, SSn, Led_Cs, Asic_Reset
ESD (Human Body Model)
Storage temperature
Notes: “x” defines port numbers, 0 to 11, inclusive.
[1]
Operation mode
Failures per 10^6 Hours
MTBF(Hours)
PD67124M @ 25°C Ambient
IEEE 802.3AT-2009
0.5181
1930000
PD67124M @ 25°C Ambient
IEEE802.3AF-2003
0.5128
1950000
Notes:
[1] – MTBF calculation made for the worst case PoE DIMM populated with 24 fully loaded ports
PD671xx DIMM
Copyright © 2009
Microsemi
Page 3
Rev. 1.0 / 17-March-10
Analog Mixed Signal Group
2381 Morse Avenue, Irvine, CA 92614, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD671xxx - 8 / 12 / 24-Channel PoE AF and AT DIMM
Data Sheet (Non-confidential)
OPERATING CONDITIONS
MIN.
-10
40 to 44
NOM.
44 to 55
MAX.
+70
55 to 57
95
UNIT
°C
VDC
%
Notes:
Operating functions depend on the input voltage.
Operating voltage range for IEEE802.3AF is 44 to 57 VDC
Operating voltage range for IEEE802.3AT (High Power) is 50 to 57 VDC
WWW . Microsemi .C OM
PARAMETER
Operating ambient temperature
Operating voltage (see Figure 2)
Operating humidity (non-condensing, Per IEC 68-2-56)
Figure 2: Operational voltage Ranges
Airflow
Power per Port
To prevent overheating, the application designer should supply a minimal airflow to the PD671xxx DIMMs.
Figure 3 shows the power handling capability versus air velocities in meter/second, as measured at all points of
the DIMM envelope, prior to insertion into the connector(s). As shown in Figure 12, the connectors are spaced
by 35 mm; 1 m/s = 197 LFM (linear feet per minute). Maximum allowed temperature is +85° C for the MCU
(PD69000) and +125° C for the PD69012.
35
30
25
20
15
10
5
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
Air flow
0m/S
Ambient temperature
0.5m/S
1m/S
Figure 3: Power per Port for two DIMMs (48 ports)
Copyright © 2009
Microsemi
Page 4
Rev. 1.0 / 17-March-10
Analog Mixed Signal Group
2381 Morse Avenue, Irvine, CA 92614, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD671xx DIMM
0
PD671xxx - 8 / 12 / 24-Channel PoE AF and AT DIMM
Data Sheet (Non-confidential)
Electrical Characteristics _________________________________
The following sections detail the DC and analog characteristics.
PARAMETER
Pin Name
Type
High level input voltage
Low level input voltage
Input voltage hysteresis
Input high current
Input low current
Pin Name
Type
High level input voltage
Low level input voltage
Input voltage hysteresis
Input high current
Input low current
High level output voltage
Low level output voltage
Tri state output current
Pin Name
Type
High level input voltage
Low level output voltage
Low level input voltage
Input voltage hysteresis
OFF state output current
SYMBOL
MIN.
MAX.
UNIT
REMARKS
SCL, xDisable_Ports, Rx (without internal pull-up/pull-down resistor)
Schmitt Trigger CMOS input, TTL level
VIH
2.0
V
VIL
0.8
V
0.3
V
IIH
-1
+1
μA
IIL
-1
+1
μA
MOSI, MISO, CS, Tx (without internal pull-up/down resistor)
SCK (with internal resistor)
CMOS I/O, TTL level
VIH
2.0
V
VIL
0.8
V
0.3
V
IIH
-1
+1
μA
IIL
-1
+1
μA
VPERI-0.4V
V
Iout = 3 mA
0.4
V
Iout = 3 mA
-1
+1
μA
xAsic_Reset (with internal resistor)
SDA (without internal resistor)
CMOS open drain output with Schmitt Trigger input, TTL level
VIH
2.0
V
VOH
0.4
V
Iout = 3mA
VIL
0.8
V
0.3
V
-1
+1
μA
WWW . Microsemi .C OM
DC Characteristics for Digital Inputs and Outputs
Electrical Characteristics for Analog I/O Pads
PARAMETER
Pin Name
Operating voltage
Pin current consumption
MIN
MAX UNIT
VPORT_POSx
44
62
-5
+10
REMARKS
V
μA
Port driver, Vport measurement and AC generator are off
Recommended Range 48v to 55v
Recommended Range 51v to 55v
Total on Vmain
Without external NPN (see Q1 in Figure 8)
When using external NPN for VPERI (see Q1 in Figure 8)
Copyright © 2009
Microsemi
Page 5
Rev. 1.0 / 17-March-10
Analog Mixed Signal Group
2381 Morse Avenue, Irvine, CA 92614, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD671xx DIMM
Pin Name
VPORT_NEGx
Operating voltage
0
Vmain
V
Pin current consumption
-5
+10
μA
Pin Name
Vmain
Operating voltage – AF mode
40
57
V
Operating voltage – AT mode
50
57
V
Vmain current consumption
40
mA
Pin Name
3_3Vout
Voltage
3.13
3.46
V
Output current
6
mA
30
mA
Port driver, Vport measurement and AC generator are
off
PD671xxx - 8 / 12 / 24-Channel PoE AF and AT DIMM
Data Sheet (Non-confidential)
Dynamic Characteristics____________
DC Disconnect
Output current consumption below Imin for more
than TPMDO (UDL_S to UDL) is categorized as
‘no-load’ and is shutdown.
AC Disconnect
A port maintains power if Zac < 27 KΩ
A port shutdowns power if Zac > 1980 KΩ for a
time period greater than TPMDO.
PARAMETER
CONDITIONS
Automatic
recovery from
Automatic
recovery from noInrush current
Output current
operating range
Output power
available,
operating range
DC disconnect
OFF mode
TOVLREC value, measured from port shutdown
(can be modified via control port)
TUDLREC value, measured from port shutdown
point (can be modified via control port)
IInrsh
For t = 50 ms, Cload =180 uF max.
Iport
Continuous operation after startup
period
Continuous operation after startup
Pport
period, at port output (@ Vport =
57 VDC)
Imin1
Must disconnect for t greater than TUVL
May or may not disconnect for t greater
Imin2
than TUVL
Zac1 Does not remove power
Zac2 Remove power
TPMD
Buffer period to handle transitions
AC Disconnect
OFF mode
PD power
maintenance
Over load current
detection range
Over load time
limit
Turn on rise time
Port turn off time
MIN.
s
1
s
700
mA
0.57
30
W
0
5
mA
10
mA
27
KΩ
KΩ
400
ms
700
mA
75
ms
5
7.5
1980
300
TOVL
Typical timer accuracy is 2 ms
50
From 10% to 90% of Vport (specified for
PD load consisting of 100 uF capacitor
From Vport to 5 Vdc
15
T
5
10
660
O VL_S
UNIT
mA
Time limited to TOVL
Toff
MAX.
750
Icut
Trise
TYP.
680
WWW . Microsemi .C OM
The PD671xxx DIMMs utilize three programmable
current level thresholds (Imin, Icut, Ilim) and two timers
(Tmin, Tcut), to operate as shown in Figure 4. Loads
that consume more than Icut for longer than Tcut
(OVL_S to OVL) are categorized as ‘overloads’ and
are automatically shutdown. Automatic recovery
from overload and no-load conditions is attempted
every TOVLREC and TUDLREC periods (typically 5 and 1
seconds, respectively). Output current is limited to
Ilim, which is the maximum peak current allowed at
each port.
us
500
ms
cut
I lim
Ic u t
O VL
Ich an n e l
P o rt 1
P o rt 2
UDL
in
P o rt o ff
T
m in
Figure 4: Power Limits
Copyright © 2009
Microsemi
Page 6
Rev. 1.0 / 17-March-10
Analog Mixed Signal Group
2381 Morse Avenue, Irvine, CA 92614, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD671xx DIMM
UDL_S
Im
PD671xxx - 8 / 12 / 24-Channel PoE AF and AT DIMM
Data Sheet (Non-confidential)
Pin Designations __________
WWW . Microsemi .C OM
The PD671xxx DIMMs have a fit/form based on a
JEDEC MO-161f outline.
Conventions used in the design are as follows:
Power and ground connections are
reproduced a number of times to carry
heavy currents.
Signals are categorized as analog (input
or output) or digital (input, output and
I/O).
All lines which are identified with an “x”
prefix are active when logical is low.
Refer to Figure 5.
Copyright © 2009
Microsemi
Page 6
Rev. 1.0 / 17-March-10
Analog Mixed Signal Group
2381 Morse Avenue, Irvine, CA 92614, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD671xx DIMM
Figure 5: Pinout
PD671xxx - 8 / 12 / 24-Channel PoE AF and AT DIMM
Data Sheet (Non-confidential)
Pin Description
Signals are categorized as ‘analog’ (input or output) or ‘digital’ (input, output and I/O).
Pin
Pin Name
Pin Type
Pin Description
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
44
45
46
47
48
49
Pin Description
86
Vmain
Main V+ input
Power input
Vmain_ret
Port_P0
Port_N0
Port_P1
Port_N1
Port_P2
Port_N2
Port_P3
Port_N3
Port_P4
Port_N4
Port_P5
Port_N5
Port_P6
Port_N6
Port_P7
Port_N7
Port_P8
Port_N8
Port_P9
Port_N9
Port_P10
Port_N10
Port_P11
Port_N11
Main V return
Channel 1 positive output
Channel 1 negative output
Channel 2 positive output
Channel 2 negative output
Channel 3 positive output
Channel 3 negative output
Channel 4 positive output
Channel 4 negative output
Channel 5 positive output
Channel 5 negative output
Channel 6 positive output
Channel 6 negative output
Analog output Channel 7 positive output
Channel 7 negative output
Channel 8 positive output
Channel 8 negative output
Channel 9 positive output
Channel 9 negative output
Channel 10 positive output
Channel 10 negative output
Channel 11 positive output
Channel 11 negative output
Channel 12 positive output
Channel 12 negative output
TBD
TBD
TBD
TBD
ASICINI_4_
Out
ASICINI_5_
Out
xLed_Cs
TBD
BKGD
Determine DIMM 3 managers
ESPI address
Analog output
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
100
111
112
113
114
115
116
117
118
119
120
121
122
123
124
Digital input
CS for LED support
TBD
Factory use only
DGND
Ground
Digital ground
xAsic_Reset
Digital I/O
Internal reset to PD69012
xReset_In
Digital input
ASICINI_0_
Out
ASICINI_1_
Out
ASICINI_2_
Out
87
Digital output
A reset signal driven by the
Host CPU to PoE DIMM
Determine DIMM 1 manager
Analog output
ESPI address
Determine DIMM 1 managers
Analog output
ESPI address
Determine DIMM 2 managers
Analog output
ESPI address
125
126
127
128
129
130
131
132
133
Vmain
Main V+ input
Power input
Vmain_ret
Main V return
Spare
TBD
TBD
TBD
TBD
I2C_Addr_0
Qgnd0
CP_0
ASICINI_6_
Out
ASICINI_7_
Out
xExist
Ext_reg
3_3Vout
TBD
TBD
TBD
TBD
Digital input Auto mode; sets I2C address
Ground
Quiet ground
Analog output NC (not in use)
Determine DIMM 4 managers
ESPI address
Analog output
Digital output Grounded internally- DIMM is
present
Analog output External regulation for 3.3 V
ASICINI_0_
In
ASICINI_1_
In
CS0
Analog output 3.3 V output to support opto
couplers (5 V tolerant)
Digital output Connect to MCU
Ground
Digital ground
Digital I/O
SPI clock – PD69012 internal
comm
Digital I/O
SPI I/O – PD69012 internal
comm
Digital I/O
SPI I/O – PD69012 internal
comm
Analog input Determine DIMM managers
ESPI address
Analog input Determine DIMM managers
ESPI address
Digital I/O
CS for ESPI
DGND
Ground
XHswp_On
DGND
SCK
MISO
MOSI
Digital ground
Copyright © 2009
Microsemi
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Rev. 1.0 / 17-March-10
Analog Mixed Signal Group
2381 Morse Avenue, Irvine, CA 92614, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD671xx DIMM
43
Pin Type
85
2
3
Pin
Name
WWW . Microsemi .C OM
1
Pin
PD671xxx - 8 / 12 / 24-Channel PoE AF and AT DIMM
Data Sheet (Non-confidential)
Pin
Pin Name
51
52
TBD
SCL
DGND
Rx2
Digital I/O
Ground
Digital input
141
142
Tx2
Port_P12
Port_N12
Port_P13
Port_N13
Port_P14
Port_N14
Port_P15
Port_N15
Port_P16
Port_N16
Port_P17
Digital output NC (not in use)
Analog output Channel 13 positive output
Analog output Channel 13 negative output
Channel 14 positive output
Channel 14 negative output
Channel 15 positive output
Channel 15 negative output
Channel 16 positive output
Channel 16 negative output
Channel 17 positive output
Channel 17 negative output
Channel 18 positive output
144
145
146
147
148
149
150
151
152
153
154
155
Port_N17
Channel 18 negative output
156
Port_P18
Channel 19 positive output
157
Port_N18
Channel 19 negative output
158
Port_P19
Channel 20 positive output
159
Port_N19
Channel 20 negative output
160
Port_P20
Channel 21 positive output
161
Port_N20
Channel 21 negative output
162
Port_P21
Channel 22 positive output
163
Port_N21
Channel 22 negative output
164
Port_P22
Channel 23 positive output
165
Port_N22
Channel 23 negative output
166
Port_P23
Channel 24 positive output
167
Port_N23
Channel 24 negative output
168
I2C_Addr_M
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
134
135
PG2
54
Pin
Analog input
Receives the hardware version
Analog output Reports on the hardware
version
Digital input
Indicates PS 1 is good; low=
PS bad.
Digital input
Indicates PS 2 is good; low=
PS bad.
Analog input
Enhanced mode – sets I2C
address
TBD
PG1
53
Pin Description
I2C clock
Digital ground
NC (not in use)
136
137
138
139
140
143
Pin
Name
Pin Type
Pin Description
Rx
Digital input
UART input
Tx
xInt_In
Digital output UART output
Digital input
NC (not in use)
xInt_Out
Digital output Interrupt out signal
ESPI_CS
Digital I/O
CS for ESPI between DIMMs
xDisable_Port Digital input
Low=disable from host
s
xSystem_ok Digital output Main DC input status indicator;
low = Vmain is out of range.
SDA
Digital I/O
I2C data
DGND
Ground
Digital ground
PG3
Digital input
Indicates PS 3 is good, low= PS
bad
TBD
TBD
CP_1
Analog output NC (not in use)
TBD
TBD
I2C_Addr_1 Digital input
Auto mode; sets I2C address
Qgnd1
Ground
Quiet ground
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
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ASICINI_3_
Out
HW_Ver_in
HW_Ver_out
50
Pin Type
Spare
PD671xx DIMM
Copyright © 2009
Microsemi
Page 8
Rev. 1.0 / 17-March-10
Analog Mixed Signal Group
2381 Morse Avenue, Irvine, CA 92614, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD671xxx - 8 / 12 / 24-Channel PoE AF and AT DIMM
Data Sheet (Non-confidential)
Functional Description____________________________________
The following sections detail the PD671xxx DIMM Master functions.
System Level
PD69012
HOST
CPU
ISOLATION
I/O
Control
Lines
UART / I 2C
PoE
Controller
PD69000
ENHANCED
DIMM
PD67124M
Control Lines
PD69012
PD
(1 of 24)
Master
SPI
Bus
PD69012
ENHANCED
DIMM
PD67124S
Ethernet
Switch
PD69012
PoE
System
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Figure 6 illustrates a 24-port Enhanced mode system based on the PD671xxx DIMM Master.
PD
(25 of 48)
Slave
Figure 6: PD67124M/S DIMM Configuration
Figure 7 illustrates a 24-port Auto mode system based on the PD671xxx DIMM Master.
PD69012
HOST
CPU
ISOLATION
I/O
Control
Lines
I2C
ENHANCED
DIMM
PD67124AM
Control Lines
PD69012
PD
(1 of 24)
Master
SPI
Bus
PD69012
ENHANCED
DIMM
PD67124AS
Ethernet
Switch
PoE
System
PD69012
PD
(25 of 48)
Slave
Figure 7: PD67124AM/AS DIMM Configuration
PD671xx DIMM
Copyright © 2009
Microsemi
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Rev. 1.0 / 17-March-10
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2381 Morse Avenue, Irvine, CA 92614, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD671xxx - 8 / 12 / 24-Channel PoE AF and AT DIMM
Data Sheet (Non-confidential)
Enhanced Mode PD671xxx DIMM Block Diagram
Figure 8 illustrates the internal circuitry of the Enhanced Mode DIMM Master. PD69012 appears only in one of
the 12 port circuits.
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Figure 8: PD67124M DIMM, Internal Block Diagram
Top Assembly Description
The following sections detail the top assembly
components.
Power Supply
The entire circuit is powered by a nominal 48 VDC
potential (Vmain can range from 44 to 57 VDC for
AF mode and 50 to 57 VDC for AT high power
mode).
3.3 VDC Regulator
Grounds
The overall circuit includes two physical ground
planes, analog and digital, which are electrically
connected at a single point on the motherboard
(see Figure 9 and Figure 10). This method, used
throughout the design, improves noise immunity
and coupling. Application note AN-132, Catalogue
Control Signals
Several control signals are utilized between the
switch and the PoE circuitry:
xReset_In: Driven by the switch circuitry
to reset the PoE circuit.
xDISABLE_PORTS: Driven by the
switch, to disable all PoE ports
immediately.
Indication Signals
Int_out: Enables the Host CPU to
reduce the communication volume
whenever a PoE event masked by the
Host CPU occurs. The PoE Controller
sends an interrupt for indication.
System_ok: (Enhanced mode only) An
optional hardware single line, driven by
the Master DIMM to the Host CPU; this
signal provides the Host CPU with a
warning that a major failure such as
Vmain out of range has occurred.
Copyright © 2009
Microsemi
Page 10
Rev. 1.0 / 17-March-10
Analog Mixed Signal Group
2381 Morse Avenue, Irvine, CA 92614, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD671xx DIMM
Each of the PD69012 includes a 3.3 VDC regulator
(EXT_REG and 3_3Vout) for up to 6 mA. This
current is utilized for powering external components
in the PoE domain. There is an option of adding a
driver to this output to drive higher loads. Q1
provides up to 30 mA to the PoE controller and to
the opto-couplers in the interface circuit. The total
capacitance on the 3.3 VDC should be less then
4.7 uF (with and without an external driver).
Number 06-0010-080 provides further details about
this design technique.
PD671xxx - 8 / 12 / 24-Channel PoE AF and AT DIMM
Data Sheet (Non-confidential)
PD69012 Circuitry
AC Disconnect Diodes
When deploying an application that utilizes the AC
disconnect method, carefully select the diode type
and diode location on the mother board. The diode
should be located away from the DIMM to prevent
mutual heating and the ventilation should be
doubled to deal with higher power dissipation. The
AC disconnect diode should be connected as
shown in Figure 9.
DC Disconnect
Using the DC disconnect method, the mother board
should contain a short circuit between Vmain
coming from the power supply and Port_P[0-23] as
illustrated in Figure 10.
The Evaluation Board allows the designer to
evaluate all of the DIMMs accessible functions.
Enhanced mode configuration for up to 48 ports is
supported.
Applications_______________
The DIMMs can be integrated into a number of
applications, ranging from daughter boards to full
integration into Ethernet switches.
Examples of such applications are as follows:
Integrated directly into a switch:
Facilitates the entire PoE concept by
including the DIMMs on the main switch
PCB.
Daughter board add-on: DIMMs are
integrated into a small PCB for PoE,
mounted on top of the switch’s main
PCB.
Midspan units: Stand-alone devices,
installed between the Ethernet switch
and powered devices (telephone,
camera, wireless LAN, etc.). These
Midspan units include the DIMMs as a
PoE control element, injecting power
over the communication lines.
Figure 10: Overall PD671xxx DIMM at DC Disconnect
Wiring Diagram
Copyright © 2009
Microsemi
Page 11
Rev. 1.0 / 17-March-10
Analog Mixed Signal Group
2381 Morse Avenue, Irvine, CA 92614, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD671xx DIMM
Figure 9: Overall PD671xxx DIMM at AC Disconnect
Wiring Diagram
The performance features of Microsemi’s PoE
DIMMs can be fully appreciated using the
PD671xxx - DIMM Evaluation Board.
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All PD69012s work in slave mode, under control of
the PD69000G. The PoE Managers, each
controlling 12 output ports, are further detailed in
Figure 8. The ports can be disabled by the
Ethernet switch via the xDisable_Ports signal or by
the PoE controller, as required during operation.
For further details on the PoE manager, refer to the
PoE manager PD69012 Data Sheet, Catalogue
Number 06-0072-058.
PD671xxx DIMM Evaluation
Board __________________
PD671xxx - 8 / 12 / 24-Channel PoE AF and AT DIMM
Data Sheet (Non-confidential)
Power Dissipation______________________________________
COMPONENT
DESCRIPTION
Rs
Senses resistor
Mosfet
PoE switching Mosfet
PD69012
PoE manager
PD69000
PoE controller
Total
* Enhanced mode Master board only
UNITS
24
24
2
1*
POWER DISSIPATION [W]
IEEE802.3AF IEEE802.3AT IEEE802.3AT
0.35A/PORT
0.6A/PORT
0.65A/PORT
1.43
0.56
1.15
0.02
3.16
4.21
1.64
1.15
0.02
7.02
4.94
1.93
1.15
0.02
8.04
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The PD671xxx power dissipation is concentrated within a few components distributed along the board as
follows. These power dissipation calculations are based on a 24 port DIMM supplied by a 48 VDC power
supply and located at ambient temperature of 70° C.
Important: When deploying an application utilizing the AC disconnect method, carefully select the diode type
and diode location on the mother board. The diode should be located away from the DIMM to prevent mutual
heating and the ventilation should be doubled to deal with higher power dissipation.
AC disconnect diodes power dissipation is based on 1 VDC forward voltage.
COMPONENT
Diode
DESCRIPTION
AC disconnect diode
UNITS
24
POWER DISSIPATION [W]
IEEE802.3AF IEEE802.3AT IEEE802.3AT
0.35A/PORT
0.6A/PORT
0.65A/PORT
8.4
14.4
15.6
Physical Information ___________________________________
Figure 11 shows the PD671xxx DIMM mechanical outline, which can be used in printed circuit layout design.
PD671xxx DIMMs are designed to be mounted onto a 168-contact DIMM connector, capable of accepting
JEDEC MO-161 modules. All units are in millimeters.
Figure 11: DIMM Dimensions
PD671xx DIMM
Figure 12: Mechanical Outline of the PD671xxx DIMM
Copyright © 2009
Microsemi
Page 12
Rev. 1.0 / 17-March-10
Analog Mixed Signal Group
2381 Morse Avenue, Irvine, CA 92614, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
PD671xxx - 8 / 12 / 24-Channel PoE AF and AT DIMM
Data Sheet (Non-confidential)
WWW . Microsemi .C OM
Revision History
Revision Level /
Date
0.1 / Oct. 1 , 2009
Para. Affected
0.2 / Oct. 29 , 2009
Overall doc
Description
Initial release
1.0 / 17-March-10
Formal release
© 2009 Microsemi Corp.
All rights reserved.
For support contact: sales_AMSG@microsemi.com
Visit our web site at: www.microsemi.com
Catalogue Number: 06-0021-058
PD671xx DIMM
Copyright © 2009
Microsemi
Page 13
Rev. 1.0 / 17-March-10
Analog Mixed Signal Group
2381 Morse Avenue, Irvine, CA 92614, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308
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