SG1526B/SG2526B/SG3526B
REGULATING PULSE WIDTH MODULATOR
DESCRIPTION
FEATURES
The SG1526B is a high-performance pulse width modulator
for switching power supplies which offers improved
functional and electrical characteristics over the industrystandard SG1526. A direct pin-for-pin replacement for the
earlier device with all its features, it incorporates the
following enhancements: a bandgap reference circuit for
improved regulation and drift characteristics, improved
undervoltage lockout, lower temperature coefficients on
oscillator frequency and current-sense threshold, tighter
tolerance on softstart time, much faster SHUTDOWN
response, improved double-pulse supperession logic for
higher speed operation, and an improved output driver
design with low shoot-through current, and faster rise and
fall times. This versatile device can be used to implement
single-ended or push-pull switching regulators of either
polarity, both transformerless and transformer-coupled. The
SG1526B is specified for operation over the full military
ambient temperature range of -55°C to 150°C. The
SG2526B is characterized for the industrial range of -25°C
to 150°C, and the SG3526B is designed for the commercial
range of 0°C to 125°C.
BLOCK DIAGRAM
8V to 35V Operation
5V Low drift 1% Bandgap Reference
1Hz to 500kHz Oscillator Range
Dual 100mA Source/Sink
Digital Current Limiting
Double Pulse Suppression
Programmable Deadtime
Improved Undervoltage Lockout
Single Pulse Metering
Programmable Soft-start
Wide current Limit Common Mode Range
TTL/CMOS Compatible Logic Ports
Symmetry Correction Capability
Guaranteed 6 Unit Synchronization
Shoot-through Currents Less than 100mA
Improved Shutdown Delay
Improved Rise and Fall Time
HIGH RELIABILITY FEATURES
Available To MIL-STD-883, ¶ 1.2.1
Available to DSCC - Standard Microcircuit
Drawing (SMD)
MIL-M38510/12603BVA - SG1526BJ-JAN
Radiation data available
MSC-AMS Level "S" Processing Available
VREF
+VIN
Reference
Regulator
+VC
Undervoltage
Lockout
GROUND
To Internal
Circuitry
RD
RT
SYNC
Oscillator
OUTPUT A
CT
RESET
CSOFTSTART
COMPENSATION
Soft
Start
S
+VIN
R
Q
T
S
+ ERROR
Q
D
Amp
Q
Q
MEMORY
F/F
TOGGLE
F/F
Q
— ERROR
METERING
F/F
OUTPUT B
+ C.S.
— C.S.
SHUTDOWN
December 2014 Rev1.2
www.microsemi.com
© 2014 Microsemi Corporation
1
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Input Voltage (VIN ) ............................................................... 40V
Collector Supply Voltage (VC) ............................................. 40V
Logic Inputs ......................................................... -0.3V to 5.5V
Analog Inputs .......................................................... -0.3V to V IN
Source/Sink Load Current (each output) ....................... 200mA
Reference Load Current .................................................. 50mA
Logic Sink Current ........................................................... 15mA
Operating Junction Temperature
Hermetic (J, L Packages) ............................................. 150°C
Plastic (N, DW Packages) ............................................ 150°C
Storage Temperature Range ............................ -65°C to 150°C
Lead Temperature (Soldering, 10 Seconds) ................... 300°C
RoHS Peak Package Solder Reflow Temp. (40 sec. max. exp.)...... 260°C (+0, -5)
Note 1. Exceeding these ratings could cause damage to the device.
THERMAL DATA
J Package:
Thermal Resistance-Junction to Case, θ JC .................. 25°C/W
Thermal Resistance-Junction to Ambient, θ JA .............. 70°C/W
N Package:
Thermal Resistance-Junction to Case, θ JC .................. 30°C/W
Thermal Resistance-Junction to Ambient, θ JA ............. 60°C/W
DW Package:
Thermal Resistance-Junction to Case, θ JC .................. 35°C/W
Thermal Resistance-Junction to Ambient, θ JA ............. 90°C/W
L Package:
Thermal Resistance-Junction to Case, θ JC ................... 35°C/W
Thermal Resistance-Junction to Ambient, θ JA ........... 120°C/W
Note A. Junction Temperature Calculation: TJ = TA + (PD x θJA).
Note B. The above numbers for θ JC are maximums for the limiting
thermal resistance of the package in a standard mounting configuration. The θ JA numbers are meant to be
guidelines for the thermal performance of the device/pcboard system. All of the above assume no ambient
airflow.
RECOMMENDED OPERATING CONDITIONS (Note 2)
Input Voltage ............................................................. 8V to 35V
Collector Supply Voltage ........................................ 4.5V to 35V
Sink/Source Load Current (each output) ................ 0 to 100mA
Reference Load Current ........................................... 0 to 20mA
Oscillator Frequency Range .............................. 1Hz to 500kHz
Oscillator Timing Resistor .................................. 2kΩ to 150kΩ
Oscillator Timing Capacitor ............................... 470pF to 20µF
Available Deadtime Range at 40kHz ...................... 5% to 50%
Operating Junction Temperature Range:
SG1526B ....................................................... -55°C to 125°C
SG2526B ......................................................... -25°C to 85°C
SG3526B ............................................................ 0°C to 70°C
Note 2. Range over which the device is functional.
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG1526B with -55°C ≤ T A ≤ 125°C, SG2526B with
-25°C ≤ TA ≤ 85°C, SG3526B with 0°C ≤ TA ≤ 70°C, and VIN = 15V. Low duty cycle pulse testing techniques are used which maintains junction and
case temperatures equal to the ambient temperature.)
Parameter
Reference Section (Note 3)
Output Voltage
Line Regulation
Load Regulation
Temperature Stability (Note 9)
Total Output Voltage Range (Note 9)
Short Circuit Current
Undervoltage Lockout Section
RESET Output Voltage
RESET Output Voltage
Test Conditions
TJ = 25°C
VIN = 8 to 35V
IL = 0 to 20mA
Over Operating TJ
SG1526B/2526B
SG3526B
Units
Min. Typ. Max. Min. Typ. Max.
VREF = 0V
4.95 5.00 5.05 4.90 5.00 5.10
20
10
10
7
10
20
10
25
50
15
50
15
4.90 5.00 5.10 4.85 5.00 5.15
25
50 125 25
50 125
VREF = 3.8V
VREF = 4.8V
2.4
2
0.2
4.8
0.4
2.4
0.2
4.8
0.4
V
mV
mV
mV
V
mA
V
V
ELECTRICAL CHARACTERISTICS
(continued)
Parameter
Oscillator Section (Note 4)
Initial Accuracy
Voltage Stability
Temperature Stability (Note 9)
Minimum Frequency (Note 9)
Maximum Frequency
Sawtooth Peak Voltage
Sawtooth Valley Voltage
SYNC Pulse Width
Error Amplifier Section (Note 5)
Input Offset Voltage
Input Bias Current
Input Offset Current
DC Open Loop Gain
High Output Voltage
Low Output Voltage
Common Mode Rejection
Supply Voltage Rejection
PWM Comparator Section (Note 4)
Minimum Duty Cycle
Maximum Duty Cycle
Test Conditions
TJ = 25°C
VIN = 8 to 35V
Over Operating TJ
RT = 150kΩ, CT = 20µF
RT = 2kΩ, CT = 470pF
VIN = 35V
VIN = 8V
RL = 2.0kΩ to VREF
500
2.5
0.5
RS ≤ 2kΩ
RL ≥ 10MΩ
VPIN1 - VPIN2 ≥ 150mV, ISOURCE = 100µA
VPIN2 - VPIN1 ≥ 150mV, ISINK = 100µA
RS ≤ 2kΩ
VIN = 8V to 35V
64
3.6
70
66
±3
0.5
7
±8
1.0
10
1.0
3.0
1.0
1.0
3.5
1.1
2
500
2.5
0.5
5
2
-350 -1000
35 100
72
60
3.6
4.2
0.2 0.4
70
94
66
80
±3
0.5
3
±8
1.0
5
1.0
3.0
1.0
1.0
3.5
1.1
2
2
10
-350 -2000
35 200
72
4.2
0.2 0.4
94
80
0
VCOMPENSATION = 0.4V
VCOMPENSATION = 3.6V
45
Digital Ports (SYNC, SHUTDOWN, and RESET)
HIGH Output Voltage
ISOURCE = 40µA
LOW Output Voltage
ISINK = 3.6mA
VIH = 2.4V
HIGH Input Current
VIL = 0.4V
LOW Input Current
(Note9)
SHUTDOWN Delay to Output
Current Limit Comparator Section (Note 6)
Sense Voltage
RS ≤ 50Ω
Input Bias Current
Delay to Output (Note 9)
Soft-Start Section
Error Clamp Voltage
RESET = 0.4V
CS Charging Current
RESET = 2.4V
Output Drivers (each output) (Note 7)
HIGH Output Voltage
ISOURCE = 20mA
ISOURCE = 100mA
LOW Output Voltage
ISINK = 20mA
ISINK = 100mA
Collector Leakage
VC = 40V
Rise Time
CL = 1000pF
Fall Time
CL = 1000pF
Power Consumption Section (Note 8)
Standby Current
SHUTDOWN = 0.4V
Note 3.
Note 4.
Note 5.
Note 6.
SG3526B
SG1526B/2526B
Units
Min. Typ. Max. Min. Typ. Max.
49
49
mV
nA
nA
dB
V
V
dB
dB
%
%
2.4
4
0.2 0.4
-125 -200
-225 -360
200
2.4
4
0.2 0.4
-125 -200
-225 -360
200
V
V
µA
µA
ns
90
100
-3
110
-10
400
80
100
-3
120
-10
400
mV
µA
ns
0.1
100
0.4.
150
0.1
100
0.4.
150
V
µA
12.5 13.5
12.5 13.5
12
13
12
13
0.2 0.3
0.2 0.3
2
1.2
1.2
2
50 150
50 150
0.3 0.4
0.3 0.4
0.1 0.15
0.1 0.15
V
V
V
V
µA
µs
µs
50
18
IL = 0mA
FOSC = 40kHz (RT = 4.12kΩ ±1%, CT = .01µF ±1%, RD = 0Ω)
VCM = 0 to 5.2V
VCM = 0 to 12V
0
45
%
%
%
Hz
kHz
V
V
µs
30
50
18
30
mA
Note 7. VC = 15V
Note 8. VIN = 35V
Note 9. These parameters, although guaranteed over the recommended operating conditions, are not tested in production.
3
CHARACTERISTIC CURVES
FIGURE 1.
REFERENCE VOLTAGE VS. SUPPLY VOLTAGE
1k
10k
FIGURE 2.
REFERENCE TEMPERATURE STABILITY
FIGURE 3.
REFERENCE SHORT CIRCUIT
1k
100k
10k
100k
FIGURE 4.
REFERENCE RIPPLE REJECTION
FIGURE 5.
UNDER VOLTAGE LOCKOUT
FIGURE 6.
ERROR AMPLIFIER OPEN LOOP GAIN
VS. FREQUENCY
FIGURE 7.
SOFTSTART TIME CONSTANT VS. CS
FIGURE 8.
CURRENT LIMIT TRANSFER FUNCTION
FIGURE 9.
COMPARATOR INPUT TO DRIVER OUTPUT DELAY
4
CHARACTERISTIC CURVES
(continued)
FOSC = 40kHz
Rt = 2.7k
CT = 0.01µF
RD = 0Ω
FIGURE 10.
STANDBY CURRENT VS. SUPPLY VOLTAGE
FIGURE 11.
OUTPUT DRIVER DEADTIME VS. CT VALUE
FIGURE 12.
OUTPUT DRIVER DEADTIME VS. RD VALUE
Rt = 2.2k - 155k
Rt = 2.2k - 155k
Rt = 2.2k - 155k
(kHz)
(kHz)
FIGURE 13.
SUPPLY CURRENT VS. OUTPUT FREQUENCY
kHz
FIGURE 14.
SUPPLY CURRENT VS. OUTPUT FREQUENCY
FIGURE 15.
SUPPLY CURRENT VS. OUTPUT FREQUENCY
FIGURE 17.
OUTPUT DRIVER SATURATION VOLTAGE
FIGURE 18.
SHUTDOWN INPUT TO DRIVER OUTPUT DELAY
FOSC = 40kHz
Rt = 4.12k
FIGURE 16.
OSCILLATOR FREQUENCY
TEMPERATURE STABILITY
5
(continued)
RT - (kΩ)
CHARACTERISTIC CURVES
FIGURE 19.
OSCILLATOR PERIOD VS. RT AND CT
APPLICATION INFORMATION
VOLTAGE REFERENCE
The reference regulator of the SG1526B is a “band-gap” type; that is, the precision +5 volt
output is derived from the very predictable base-emitter voltage of an NPN transistor.
Since this is a sub-surface phenomenon, the resulting output exhibits excellent stability
compared to earlier surface-breakdown Zener designs.
The reference output is stabilized at input voltages as low as +8 volts, and can provide
up to 20mA of load current to external circuitry. An external PNP transistor can be used
to boost the available current to many hundreds of mA. A rugged low-frequency audiotype transistor should be used, and lead lengths between the PWM and transistor should
be as short as possible to minimize the risk of oscillation.
FIGURE 20.
EXTENDING REFERENCE OUTPUT CURRENT
UNDERVOLTAGE LOCKOUT
The undervoltage lockout circuit protects the SG1526B and the power devices it controls
from inadequate supply voltage. If +VIN is too low, the circuit disables the output drivers
and holds the RESET pin LOW. This prevents spurious output pulses while the control
circuitry is stabilizing, and holds the soft-start timing capacitor in a discharged state.
The circuit consists of a merged bandgap reference and comparator circuit which is
active when the reference voltage has risen to 2VBE or 1.2 volts at 25oC. When the
reference voltage rises to approximately +4.4 volts, the circuit enables the output drivers
and releases the RESET pin, allowing a normal softstart. The comparator has 200mV
of hysteresis to minimize oscillation at the trip point. When +VIN to the PWM is removed
and the reference drops to +4.2 volts, the undervoltage circuit pulls RESET LOW again.
The soft-start capacitor is immediately discharged, and the PWM is ready for another
soft-start cycle.
The SG1526B can operate from a +5 volt supply regulated to within ±4% by connecting
the VREF pin to the +VIN pin.
FIGURE 21.
SIMPLIFIED UNDERVOLTAGE LOCKOUT
SOFT-START CIRCUIT
The soft-start circuit protects the power transistors and rectifier diodes from high current
surges during power supply turn-on. When supply voltage is first applied to the
SG1526B, the undervoltage lockout circuit holds RESET LOW with Q3. Q1 is turned on,
which holds the soft-start capacitor voltage at zero. The second collector of Q1 clamps
the output of the error amplifier to ground, guaranteeing zero duty cycle at the driver
outputs. When the supply voltage reaches normal operating range, RESET will go HIGH.
Q1 turns off, allowing the internal 100µA current source to charge CS. Q2 clamps the error
amplifier output to 1.0 VBE above the voltage on CS. As the soft-start voltage ramps up
to +5 volts, the duty cycle of the PWM linearly increases to whatever value the voltage
regulation loop requires for an error null. Figure 7 gives the timing relationship between
CS ramp time to 100% duty cycle.
6
FIGURE 22.
SOFT-START CIRCUIT SCHEMATIC
APPLICATION INFORMATION
(continued)
DIGITAL CONTROL PORTS
The three digital control ports of the SG1526B are bidirectional. Each pin can drive TTL and 5 volt CMOS logic
directly, up to a fan-out of 10 low-power Schottky gates.
Each pin can also be directly driven by open-collector TTL,
open-drain CMOS, and open-collector voltage comparators,
fan-in is equivalent to 1 low-power Schottky gate. Each port
is normally HIGH; the pin is pulled LOW to activate the
particular function. Driving SYNC LOW initiates a discharge
cycle in the oscillator. Pulling SHUTDOWN LOW immediately inhibits all PWM output pulses. Holding RESET LOW
discharges the soft-start capacitor. The logic threshold is
+1.1 volts at +25oC. Noise immunity can be gained at the
expense of fan-out with an external 2k pull-up resistor to
+5V.
40k
20k
TO
INTERNAL
LOGIC
FIGURE 23
DIGITAL CONTROL PORT SCHEMATIC
OSCILLATOR
The oscillator is programmed for frequency and dead time
with three components: RT CT, and RD. Two waveforms are
generated: a sawtooth waveform at pin 10 for pulse width
modulation, and a logic clock at pin 12. The following
procedure is recommended for choosing timing values:
1. With RD = 0Ω (pin 11 shorted to ground) select values
for RT and CT from Figure 19 to give the desired
oscillator period. Remember that the frequency at
each driver output is half the oscillator frequency, and
the frequency at the +VC terminal is the same as the
oscillator frequency.
2. If more dead time is required, select a larger value of
RD using Figure 12 as a guide. At 40 kHz dead time
increases by 300 ns/Ω.
3. Increasing the dead time will cause the oscillator
frequency to decrease slightly. Go back and decrease the value of RT slightly to bring the frequency
back to the nominal design value.
The SG1526B can be synchronized to an external logic clock
by programming the oscillator to free-run at a frequency 10%
slower than the sync frequency. A periodic LOW logic pulse
approximately 0.5 µSec wide at the SYNC pin will then lock
the oscillator to the external frequency.
Multiple devices can be synchronized together by programming one master unit for the desired frequency, and then
sharing its sawtooth and clock waveforms with the slave
units. All CT terminals are connected to the CT pin of the
master, and all SYNC terminals are likewise connected to
the SYNC pin of the master. Slave RT terminals should not
be left open; at least 50k should be connected from each pin
to ground. Slave RD terminals may be either left open or
grounded.
FIGURE 24.
OSCILLATOR CONNECTIONS AND WAVEFORMS
ERROR AMPLIFIER
The error amplifier is a transconductance design, with an
output impedance of 2 megohms. Since all voltage gain
takes place at the output pin, the open-loop gain/frequency
characteristics can be controlled with shunt reactance to
ground. When compensated for unity-gain stability with 100
pF, the amplifier has an open-loop pole at 400 Hz.
The input connections to the error amplifier and determined
by the polarity of the switching supply output voltage. For
positive supplies, the common-mode voltage is +5.0 volts
and the feedback connections in Figure 25A are used. With
negative supplies, the common-mode voltage is ground and
the feedback divider is connected between the negative
output and the +5.0 volt reference voltage, as shown in
Figure 25B.
(A)
FIGURE 25.
ERROR AMPLIFIER CONNECTIONS
7
(B)
APPLICATION INFORMATION
(continued)
OUTPUT DRIVERS
The totem-pole output drivers of the SG1526B are designed
to source and sink 100mA continuously and 200mA peak.
Loads can be driven either from the output pins 13 and 16,
FIGURE 26.
PUSH-PULL CONFIGURATION
or from the +VC pin, as required. Curves for the saturation
voltage at these outputs as a function of load current are
found in Figure 17.
FIGURE 27.
SINGLE-ENDED CONFIGURATION
FIGURE 28.
DRIVING N-CHANNEL POWER MOSFETS
2k
4.12k
150k
SG1526B LAB TEST FIXTURE
2k
2k
33k
1k
1k
10k
665k
750Ω
1k
-IB
10k
+IB
10k
8
CONNECTION DIAGRAMS & ORDERING INFORMATION
Package
18-PIN CERAMIC DIP
J - PACKAGE
Part No.
SG1526BJ-883B
SG1526BJ-JAN
SG1526BJ-DESC
SG1526BJ
SG2526BJ
SG3526BJ
(See Notes Below)
Ambient
Temperature Range
-55°C to 125°C
-55°C to 125°C
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
0°C to 70°C
18-PIN PLASTIC DIP
N - PACKAGE
SG2526BN
SG3526BN
-25°C to 85°C
0°C to 70°C
18-PIN WIDE BODY
PLASTIC SOIC
DW - PACKAGE
SG2526BDW
SG3526BDW
-25°C to 85°C
0°C to 70°C
Connection Diagram
+ ERROR
- ERROR
COMPENSATION
1
18
2
17
3
16
CSOFTSTART
RESET
- CURRENT SENSE
+ CURRENT SENSE
SHUTDOWN
RT
4
15
5
14
6
13
7
12
8
11
9
10
VREF
+VIN
OUTPUT B
GROUND
VCOLLECTOR
OUTPUT A
SYNC
RDEADTIME
CT
N Package: RoHS Compliant / Pb-free Transition DC: 0503
N Package: RoHS / Pb-free 100% Matte Tin Lead Finish
+ERROR
-ERROR
COMPENSATION
CSOFTSTART
RESET
- CURRENT SENSE
+ CURRENT SENSE
SHUTDOWN
1
18
2
17
VREF
+VIN
3
16
4
15
5
14
6
13
7
12
8
11
RDEADTIME
RT
9
10
CT
OUTPUT B
GROUND
+VCOLLECTOR
OUTPUT A
SYNC
DW Package: RoHS Compliant / Pb-free Transition DC: 0516
DW Package: RoHS / Pb-free 100% Matte Tin Lead Finish
20-PIN CERAMIC
LEADLESS CHIP CARRIER
L- PACKAGE
SG1526BL-883B
SG1526BL
-55°C to 125°C
-55°C to 125°C
3
1. N.C.
2. +ERROR
3. -ERROR
4. COMP
5. CSOFTSTART
6. RESET
7. - C.S.
8. + C.S.
9. SHUTDOWN
10. RT
2
1
20 19
4
18
5
17
6
16
7
15
8
14
9
10 11 12 13
Note 1. Contact factory for JAN and DESC product availability.
Note 2. All parts are viewed from the top.
Note 3. Hermetic Packages J and L use Pb37/SN63 hot solder lead finish, contact factory for availability of RoHS versions.
9
11. CT
12. RDEADTIME
13. SYNC
14. OUTPUT A
15. +VCOLLECTOR
16. N.C.
17. GROUND
18. OUTPUT B
19. +VIN
20. VREF
PACKAGE OUTLINE DIMENSIONS
Controlling dimensions are in inches, metric equivalents are shown for general information.
MILLIMETERS
MIN
MAX
DIM
A
10
1
9
A
24.38
0.960
B
5.59
7.11
0.220
0.280
C
5.08
0.200
D
0.38
0.51
0.015
0.020
F
1.02
1.77
0.040
0.070
G
2.54 BSC
0.100 BSC
H
2.03
0.080
J
0.20
0.38
0.008
0.015
K
3.18
5.08
0.125
0.200
L
7.37
7.87
0.290
0.310
M
15°
15°
Note: Dimensions do not include protrusions; these shall
B
18
L
C
F
K
Seating Plane
H
J
M
D
G
INCHES
MIN
MAX
not exceed 0.155mm (0.006″) on any side. Lead
dimension shall not include solder coverage.
Figure 29 · J 18-Pin CERDIP Package Dimensions
E3
D
Dim
D/E
E3
E
e
B1
A
A1
L2
8.64
9.14
0.340
0.360
-
8.128
-
0.320
1.270 BSC
0.050 BSC
0.635 TYP
0.025 TYP
1.02
1.52
0.040
0.060
A
1.626
2.286
0.064
0.090
A1
3
INCHES
MIN
MAX
L
h
L
8
MILLIMETERS
MIN
MAX
1.016 TYP
1.372
1.68
A2
-
L2
1.91
B3
0.040 TYP
0.054
0.066
1.168
-
0.046
2.41
0.075
0.95
0.203R
60 µ-inch minimum thickness over nickel plated
unless otherwise specified in purchase order.
13
h
A2
0.008R
Note: All exposed metalized area shall be gold plated
1
18
B1
e
B3
Figure 30 · L 20-Pin Ceramic LCC Package Dimensions
10
PACKAGE OUTLINE DIMENSIONS (continued)
DIM
D
18
A
A1
A2
B
c
D
E
e
H
L
θ
*LC
10
H
E
9
1
e
L
B
A2
A
c
S e a tin g Pla n e
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.30
2.20
2.55
0.33
0.51
0.23
0.32
11.40
11.70
7.40
7.60
1.27 BSC
10.00
10.65
0.40
1.27
0°
8°
0.10
* Lead Coplanarity
A1
INCHES
MIN
MAX
0.093
0.104
0.004
0.012
0.086
0.100
0.013
0.020
0.009
0.013
0.449
0.461
0.291
0.299
0.05 BSC
0.394
0.419
0.016
0.050
0°
8°
0.004
Note: Dimensions do not include mold flash or
protrusions; these shall not exceed 0.155mm (0.006″)
on any side. Lead dimension shall not include solder
coverage.
Figure 31 · DW 18-Pin Plastic Wide-body SOIC (SOWB) Package Dimensions
Dim
D
1
b1
E
A2
A
c
A1
L
SEATING PLANE
MAX
M
INCHES
MIN
5.33
0.38
A2
E1
b
MIN
A
A1
e
MILLIMETERS
3.30 Typ
MAX
0.210
0.015
0.130 Typ
b
0.36
0.56
0.014
0.022
b1
1.14
1.78
0.045
0.070
c
0.20
0.36
0.008
0.014
D
22.35
23.34
0.880
0.920
e
2.54 BSC
0.100 BSC
E
7.62
8.26
0.300
0.325
E1
6.10
7.11
0.240
0.280
L
2.92
3.81
0.115
0.150
M
-
15°
-
15°
Note: Dimensions do not include mold flash or protrusions;
these shall not exceed 0.155mm (0.006″) on any side.
Lead dimension shall not include solder coverage.
Figure 32 · N 18-Pin Plastic Dual Inline Package Dimensions
11
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Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor
and system solutions for communications, defense and security, aerospace, and industrial
markets. Products include high-performance and radiation-hardened analog mixed-signal
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