SG1524B/SG2524B/SG3524B
Datasheet
Regulating Pulse Width Modulator
July 2018
Regulating Pulse Width Modulator
Contents
1 Revision History ............................................................................................................................. 1
1.1 Revision 2.0 ........................................................................................................................................ 1
1.2 Revision 1.4 ........................................................................................................................................ 1
1.3 Revision 1.1 ........................................................................................................................................ 1
2 Product Overview .......................................................................................................................... 2
2.1 Features .............................................................................................................................................. 2
2.2 High Reliability Features ..................................................................................................................... 2
2.3 Block Diagram ..................................................................................................................................... 3
3 Electrical Specifications .................................................................................................................. 4
3.1 Recommended Operating Conditions ................................................................................................ 6
3.2 Typical Performance Curves ............................................................................................................... 7
3.3 Absolute Maximum Ratings ................................................................................................................ 8
4 Package Information ...................................................................................................................... 9
4.1 Thermal Data .................................................................................................................................... 13
5 Ordering Information ................................................................................................................... 14
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Regulating Pulse Width Modulator
1
Revision History
The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the most current publication.
1.1
Revision 2.0
Revision 2.0 was published in July 2018. In revision 2.0 of this document, the format was updated to the
latest template. The following is the summary of changes in revision 2.0 of this document
Corrected a typo in the title of the document.
Formatting edits were done.
1.2
Revision 1.4
Revision 1.4 was published in December 2014. The following is the summary of changes in revision 1.4
of this document.
Corrected a typo in the Features (see page 2) section.
Corrected a typo in the Ordering Information (see page 14) section.
1.3
Revision 1.1
Revision 1.1 was published in February 1994. It was the first publication of this document.
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Regulating Pulse Width Modulator
2
Product Overview
The SG1524B is a pulse width modulator for switching power supplies, that gives improved performance
over industry standards, like the SG1524. This is a direct pin-for-pin replacement for the earlier device,
and combines advanced processing techniques and circuit design to provide improved reference
accuracy, and extended common mode range at the error amplifier and current limit inputs. A
DC-coupled flip-flop eliminates triggering and glitch problems, and a pulse width modulator data latch
prevents edge oscillations. The circuit incorporates true digital shutdown for high speed response, while
an under voltage lockout circuit prevents spurious outputs when the supply voltage is too low for stable
operation. Full double-pulse suppression logic insures alternating output pulses when the shutdown pin
is used for pulse-by-pulse current limiting. SG1524B is specified for operation over the full military
ambient temperature range of –55 °C to 125 °C. It is characterized for the industrial range of
–25 °C to 85 °C, and is designed for the commercial range of 0 °C to 70 °C.
2.1
Features
The main features of SG1524B are as follows.
7 V to 40 V operation
5 V reference trimmed to ±1%
100 Hz to 400 kHz oscillator range
Excellent external sync capability
Dual 100 mA output transistors
Wide current limit common mode range
DC-coupled toggle flip-flop
PWM data latch
Undervoltage lockout
Full double pulse suppression logic
60 V output collectors
2.2
High Reliability Features
The high reliability features of SG1524B are as follows.
Available to MIL-STD-883
MSC-AMS level "S" processing available
Available to DSCC-standard microcircuit drawing (SMD)
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2.3
Block Diagram
The following figure shows the block diagram of SG1524B.
Figure 1 • SG1524B Block Diagram
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3
Electrical Specifications
This section shows the electrical characteristics of SG1524B/SG2524B/SG3524B. If not specified, these
specifications apply over the operating ambient temperatures for SG1524B with
–55 °C ≤ TA ≤ 125 °C, SG2524B with –25 °C ≤ T A ≤ 85 °C, SG3524B with 0 °C ≤ T A ≤ 70 °C, and VIN = 20 V.
Low duty cycle pulse testing techniques are used, that maintain junction and case temperatures equal to
the ambient temperature.
The following table shows the parameters and test conditions of SG1524B/SG2524B/SG3524B.
Table 1 • Electrical Characteristics
Parameter
Test Conditions
SG1524B/2524B
SG3524B
Units
Min
Typical
Max
Min
Typical
Max
4.95
4.90
Reference Section (IL = 0 mA)
Output voltage
TJ = 25 °C
5.00
5.05
5.00
5.10
V
Line regulation
VIN = 7 V to 40 V
3
20
3
30
mV
Load regulation
IL = 0 mA to 20 mA
5
30
5
50
mV
Temperature
stability1
Over operating temperature
range
15
50
15
50
mV
Total output
voltage range
Over line, load and
temperature
4.90
5.20
V
Short circuit
current
VREF–0 V
25
5.10
4.80
50
120
25
50
120
mA
4.3
4.5
4.7
4.2
4.5
4.9
V
42
45
48
40
45
50
kHz
Undervoltage Lockout Section
Threshold
voltage
Oscillator Section (FOSC = 45 kHz, RT = 2700 Ω, CT = 0.01 μF)
Initial accuracy
TJ = 25 °C
Voltage stability
VIN = 7 V to 40 V
0.1
1
0.1
1
%
Temperature
stability1
Over operating range
1
2
1
2
%
Minimum
frequency1
RT = 150 kΩ, CT = 0.1 μF
50
140
400
50
120
Hz
Maximum
frequency
RT = 2 kΩ, CT = 470 pF
400
600
Sawtooth peak
voltage
VIN = 40 V
Sawtooth valley
voltage
VIN = 7 V
400
600
3.5
3.9
3.5
kHz
3.9
V
0.6
1
0.6
1
V
Clock amplitude
3.0
4.0
3.0
4.0
V
Clock pulse
width
0.2
0.5
1.2
0.2
0.5
1.2
µs
0.5
5
2
10
mV
1
5
1
10
µA
Error Amplifier Section (VCM = 2.3 V to VREF)
Input offset
voltage
Input bias
current
RS ≤ 2 kΩ
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Parameter
Test Conditions
SG1524B/2524B
Input offset
current
SG3524B
Units
1
DC open loop
gain
RL ≥ 10 MΩ
Output low level
ISINK = 100 μA
60
78
0.2
1
60
0.5
78
0.2
µA
dB
0.5
V
VPIN 1 - VPIN 2 ≥ 150 mV
Output high level
ISource = 100 μA
VPIN 2 - VPIN 1 ≥ 150 mV
3.8
4.2
3.8
4.2
V
Common mode
rejection
VCM = 2.3 V to VREF
70
90
70
90
dB
Supply voltage
rejection
VIN = 7 V to 40 V
76
100
76
100
dB
Gain-bandwidth
product1
TJ = 25 °C
1
2
1
2
MHz
P.W.M. Comparator ( FOSC = 45 kHz, RT = 2700 Ω, CT = 0.01 μF)
Minimum duty
cycle
VCOMP = 0.5 V
Maximum duty
cycle
VCOMP = 3.9 V
0
45
49
180
200
220
–3
–10
0
%
45
49
%
170
200
230
mV
–3
–10
µA
Current Limit Amplifier Section (VCM = 0 V to 17.5 V)
Sense voltage
Input bias
current
Shutdown Input Section
High input
voltage
High input
current
2.0
VSHUTDOWN = 5 V
2.0
0.10.1
Low input
voltage
11
V
0.10.1
11
mA
0.6
0.6
50
50
μA
0.4
2.0
V
V
Output Section for each Transistor
Collector leakage
current
VCE = 60 V
Collector
saturation
voltage
IC = 10 mA
IC = 100 mA
Emitter output
voltage
IE = 10 mA
IE = 100 mA
Emitter voltage
rise time1
RE = 2 kΩ, TA = 25 °C
0.2
0.5
0.2
0.5
μs
Collector voltage
fall time
RC = 2 kΩ, TA = 25 °C
0.1
0.2
0.1
0.2
μs
VIN = 40 V, VSHUTDOWN = 2.0 V
5
12
5
12
mA
0.2
1.0
17.5
17
0.4
2.0
19
18
0.2
1.0
17.5
17
19
18
V
V
Power Consumption
Standby current
Note:
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Note:
1. These parameters, although guaranteed over the recommended operating conditions, are not
tested in production.
3.1
Recommended Operating Conditions
The following table shows recommended operating conditions of SG1524B/SG2524B/SG3524B. Here,
the operating conditions refer to ranges over which the device is functional.
Table 2 • Recommended Operating Conditions
Parameter
Value
Unit
Input voltage (VIN)
7 to 40
V
Collector voltage
0 to 60
V
Error A common mode range
2.3 to VREF
V
Current limit sense common mode range
0 to VIN to 2.5 V
V
Output current (each transistor)
0 to 100
mA
Reference load current
0 to 20
mA
Oscillator charging current
25 to 1.8
μA/mA
Oscillator frequency range
100 to 400
Hz/kHz
Oscillator timing resistor (RT)
2 to 150
kΩ
Oscillator timing capacitor (CT)
1 to 0.1
nF/μF
SG1524B
–55 to 125
°C
SG2524B
–25 to 85
°C
SG3524B
0 to 70
°C
Operating Ambient Temperature Range
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3.2
Typical Performance Curves
The following figures show characteristic curves of SG1524B. The conditions are, VIN = 20 V, TA = 25 °C.
Figure 2 • Oscillator Frequency vs. Timing Resistor and Capacitor
Figure 3 • SG1524B Dead Times vs. Timing Capacitance (RT = 2.7 kΩ)
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Figure 4 • SG1524B Error Amplitude Voltage Gain vs. Frequency over Rf
3.3
Absolute Maximum Ratings
The following table shows the absolute maximum ratings of SG1524B/SG2524B/SG3524B. The absolute
maximum ratings refer to values beyond which damage may occur.
Table 3 • Absolute Maximum Ratings
Parameter
Value
Units
Input voltage (+VIN)
42
V
Collector voltage
60
V
Logic inputs
–0.3 to 5.5
V
Current limit sense inputs
–0.3 to VIN
V
Output current (each transistor)
200
mA
Reference load current
50
mA
Oscillator charging current
5
mA
Hermetic (J, and L Packages)
150
°C
Plastic (N, and DW Packages)
150
°C
Storage temperature range
–65 to 150
°C
Lead temperature (soldering, 10 seconds)
300
°C
RoHS peak package solder reflow temperature (40 seconds
maximum exposure)
260 (0, –5)
°C
Operating Junction Temperature
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4
Package Information
This section shows the package outline dimensions and thermal specifications of
SG1524B/SG2524B/SG3524B. Controlling dimensions are in inches, and metric equivalents are shown
for general information.
The following figure and table show DW 16-pin SOWB package and its dimensions. Dimensions do not
include protrusions and should not exceed 0.155 mm (0.006 in.) on any side. Lead dimension should not
include solder coverage.
Figure 5 • DW 16-Pin SOWB Package
Table 4 • DW 16-Pin SOWB Package Dimensions
Dimensions
Millimeters
Inches
Minimum
Maximum
Minimum
Maximum
A
A1
A2
1.35
0.10
1.25
1.75
0.25
1.52
0.053
0.004
0.049
0.069
0.010
0.060
b
c
D
0.33
0.19
9.78
0.51
0.25
10.01
0.013
0.007
0.385
0.020
0.010
0.394
E
5.79
6.20
0.228
0.244
e
H
1.27 BSC
3.81
4.01
0.150
0.158
L
Θ
Lead coplanarity
0.40
0
-
1.27
8
0.10
0.016
0
-
0.050
8
0.004
0.050 BSC
The following figure and table show N 16-pin plastic dual inline package and its dimensions. Dimensions
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The following figure and table show N 16-pin plastic dual inline package and its dimensions. Dimensions
do not include protrusions and should not exceed 0.155 mm (0.006 in.) on any side. Lead dimension
should not include solder coverage.
Figure 6 • N 16-Pin Plastic Dual Inline Package
Table 5 • N 16-Pin Plastic Dual Inline Package Dimensions
Dimensions
Millimeters
Inches
Minimum
Maximum
Minimum
Maximum
A
A1
0.38
5/08
0.51
0.015
0.200
0.040
A2
3.30 typical
b
b2
c
0.38
0.76
0.20
0.51
1.52
0.38
0.015
0.030
0.008
0.020
0.060
0.015
D
18.54
20.57
0.730
0.810
e
2.54 BSC
E1
6.10
E
7.62 BSC
L
3.05
-
0.120
-
θ
-
15°
-
15°
0.130 typical
0.100 BSC
6.60
0.240
0.260
0.300 BSC
The following figure and table show J 16-pin ceramic dual inline package and its dimensions. Dimensions
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The following figure and table show J 16-pin ceramic dual inline package and its dimensions. Dimensions
do not include protrusions and should not exceed 0.155 mm (0.006 in.) on any side. Lead dimension
should not include solder coverage.
Figure 7 • J 16-Pin Ceramic Dual Inline Package
Table 6 • J 16-Pin Ceramic Dual Inline Package Dimensions
Dimensions
Millimeters
Inches
Minimum
Maximum
Minimum
Maximum
A
b
b2
0.38
1.04
5.08
0.51
1.65
0.015
0.045
0.200
0.020
0.065
c
D
E
0.20
19.30
5.59
0.38
19.94
7.11
0.008
0.760
0.220
0.015
0.785
0.280
e
2.54 BSC
eA
H
7.37
0.63
7.87
1.78
0.290
0.025
0.310
0.070
L
α
Q
3.18
0.51
5.08
15°
1.02
0.125
0.020
0.200
15°
0.040
0.100 BSC
The following figure and table show L 20-pin ceramic leadless chip carrier (LCC) package and its outline
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The following figure and table show L 20-pin ceramic leadless chip carrier (LCC) package and its outline
dimensions. All exposed metalized area should be gold plated, 60 micro-inch minimum thickness over
nickel plated base, if not specified in purchase order.
Figure 8 • L 20-Pin Ceramic Leadless Chip Carrier (LCC) Package
Table 7 • L 20-Pin Ceramic Leadless Chip Carrier (LCC) Package Outline Dimensions
DIM
Millimeters
Inches
Minimum
Maximum
Minimum
Maximum
D/E
8.64
9.14
0.340
0.360
E3
-
8.128
-
0.320
e
1.270 BSC
0.050 BSC
B1
0.635 typical
0.025 typical
L
A
1.02
1.626
h
1.016 typical
A1
A2
1.372
-
1.68
1.168
0.054
-
0.066
0.046
L2
1.91
2.41
0.075
0.95
B3
0.203 R
1.52
2.286
0.040
0.064
0.060
0.090
0.040 typical
0.008 R
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4.1
Thermal Data
The following table shows the thermal data specifications of SG1524B/SG2524B/SG3524B.
Table 8 • Thermal Data Specifications
Parameter
Value
Units
Thermal resistance-junction to case, θJC
30
°C/W
Thermal resistance-junction to ambient, θJA
80
°C/W
Thermal resistance-junction to case, θJC
40
°C/W
Thermal resistance-junction to ambient, θJA
65
°C/W
Thermal resistance-junction to case, θJC
40
°C/W
Thermal resistance-junction to ambient, θJA
95
°C/W
Thermal resistance-junction to case, θJC
35
°C/W
Thermal resistance-junction to ambient, θJA
120
°C/W
J Package
N Package
DW Package
L Package
Notes:
Junction temperature calculation: TJ = TA + (PD x θJA).
The above numbers for θJC are maximum for the limiting thermal resistance of the package in a
standard mounting configuration. The θJA numbers are meant to be guidelines for the thermal
performance of the device or pc-board system. All of the them assume no ambient airflow.
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5
Ordering Information
The following figures and tables show the connection diagrams and ordering information of SG1524B.
Figure 9 • 16-Pin Dual Inline Package
N Package: RoHS complaint/Pb-free transition DC: 0503
N Package: RoHS/Pb-free 100% matte tin lead finish
Table 9 • Ordering Information of 16-Pin Dual Inline Package
Ambient
Temperature
Type
Package
Part Number
Packaging Type
55 °C to 125 °C
J
16-pin ceramic dual
inline package
SG1524BJ
CERDIP
(ceramic dual in-line
package)
SG1524BJ-883B
SG2524BJ-DESC
–25 °C to 85 °C
0 °C to 70 °C
N
16-pin dual inline plastic
package
SG2524BN
SG3524BN
PDIP
(plastic dual in-line
package)
Figure 10 • 16-Pin Small Outline Wide Body Package
DW Package: RoHS complaint/Pb-free transition DC: 0516
DW Package: RoHS/Pb-free 100% matte tin lead finish
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Table 10 • Ordering Information of 16-Pin Small Outline Wide Body Package
Ambient Temperature
Type
Package
Part Number
Packaging Type
–25 °C to 85 °C
DW
16-pin dual inline
plastic package
SG2524BDW
SOWB
20-pin ceramic
leadless chip carrier
SG1524BL-883B
0 °C to 70 °C
–55 °C to 125 °C
L
SG3524BDW
SG1524BL
CLCC
(Ceramic leadless chip carrier)
Figure 11 • 20-Pin Ceramic Leadless Chip Carrier
Table 11 • Ordering Information of 20-Pin Ceramic Leadless Chip Carrier
Ambient Temperature
Type
Package
Part Number
Packaging Type
–55 °C to 125 °C
L
20-pin ceramic leadless
chip carrier
SG1524BL-883B
CLCC
SG1524BL
Notes:
Contact your Microsemi representative for DESC product availability.
All packages are viewed from the top.
Hermetic packages, J and L use Sn63/Pb37 hot solder lead finish. Contact your Microsemi
representative for availability of RoHS versions.
Available in tape and reel. Append the letters "TR" to the part number: SG3524BDW-TR.
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SG1524B-2.00-0718
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