ZL30130GGG

ZL30130 OC-12/STM-4 SONET/SDH/GbE Stratum 2/3/3E System Synchronizer/SETS Short Form Data Sheet March 2013 Features • Ordering Information Supports the requirements of ITU-T G.8262 for synchronous Ethernet Equipment slave Clocks (EEC option 1 and 2) ZL30130GGG 100 Pin CABGA Trays ZL30130GGG2 100 Pin CABGA* Trays *Pb Free Tin/Silver/Copper -40oC to +85oC • Supports the requirements of Telcordia GR-1244 Stratum 2/3/3E and GR-253, ITU-T G.812, G.813, and G.781 SETS • Supports the requirements of Telcordia GR-1244 Stratum 2/3/3E and GR-253, ITU-T G.812, G.813, and G.781 SETS • Generates several styles of telecom frame pulses with selectable pulse width, polarity and frequency • Meets the SONET/SDH jitter generation requirements up to OC-12/STM-4 • Provides two DPLLs which are independently configurable through a serial interface • Synchronizes to telecom reference clocks (2 kHz, N*8 kHz up to 77.76 MHz, 155.52 MHz) or to Ethernet reference clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz) • Internal state machine automatically controls mode of operation (free-run, locked, holdover) • Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities • Provides automatic reference switching and holdover during loss of reference input • Supports master/slave configuration and dynamic input to output delay compensation for AdvancedTCATM • Configurable input to output delay and output to output phase alignment • Supports composite clock inputs (64 kHz, 64 kHz + 8 kHz, 64kHz + 8 kHz + 400 Hz) • Generates standard SONET/SDH clock rates (e.g. 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, 622.08 MHz) or Ethernet clock rates (e.g. 25 MHz, 50 MHz, 125 MHz) for synchronizing Gigabit Ethernet PHYs • Programmable output synthesizers (P0, P1) generate telecom clock frequencies from any multiple of 8 kHz up to 100 MHz Figure 1 - Functional Block Diagram 1 Copyright 2013, Microsemi Corporation. All Rights Reserved. ZL30130 Short Form Data Sheet Applications • ITU-T G.8262 System Timing Cards which support 1 GbE interfaces • Telcordia GR-253 Carrier Grade SONET/SDH Stratum 2/3E/3 System Timing Cards • System Timing Cards which support ITU-T G.781 SETS (SDH Equipment Timing Source) Changes Summary The following table captures the changes from July 2009 issue to March 2013 issue. Page Item Change Multiple Zarlink logo and name reference Updated to Microsemi® logo and name. The following table captures the changes from the February 2008 issue to the July 2009 issue. Page Item Change 1 Features Added support for G.823, G.824 and G.8261 to features list. 4 p0_clkn and p1_clkn maximum clock frequency Changed max frequency of the P0 and P1 clocks from 77.76 MHz to 100 MHz. 2 Microsemi Corporation ZL30130 Short Form Data Sheet Pin Description Pin # Name I/O Type Description Input Reference C1 B2 A3 C3 B3 B4 C4 A4 ref0 ref1 ref2 ref3 ref4 ref5 ref6 ref7 Iu Input References [7:0] (LVCMOS, Schmitt Trigger). These input references are available to both DPLL1 and DPLL2 for synchronizing output clocks. All eight input references can lock to any multiple of 8 kHz up to 77.76 MHz including 25 MHz and 50 MHz. Input ref0 and ref1 have additional configurable predividers allowing input frequencies of 62.5 MHz, 125 MHz, and 155.52 MHz. These pins are internally pulled up to Vdd. B1 A1 A2 sync0 sync1 sync2 Iu Frame Pulse Synchronization References [2:0] (LVCMOS, Schmitt Trigger). These are optional frame pulse synchronization inputs associated with input references 0, 1, and 2. These inputs accept frame pulses in a clock format (50% duty cycle) or a basic frame pulse format with minimum pulse width of 5 ns. These pins are internally pulled up to Vdd. C5 ref8/ext_fb_clk Iu Input Reference 8/External DPLL Feedback Clock (LVCMOS, Schmitt Trigger). This pin acts as either an ext_fb_clk input or as the ref8 input. The desired function for the pin is selectable through the software interface with a programmable register bit. This pin is internally pulled up to Vdd. Leave open when not in use. B5 sync8/ext_fb_fp Iu Frame Pulse Synchronization Reference 8/External DPLL Feedback Frame Pulse (LVCMOS, Schmitt Trigger). This pin acts as either an ext_fb_fp input or as the sync8 input. The desired function for the pin is selectable through the software interface with a programmable register bit. This pin is internally pulled up to Vdd. Leave open when not in use. Output Clocks and Frame Pulses A9 B10 diff0_p diff0_n O Differential Output Clock 0 (LVPECL). When in SONET/SDH mode, this output can be configured to provide any one of the available SONET/SDH clocks (6.48 MHz, 19.44 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz, 622.08 MHz). When in Ethernet mode, this output can be configured to provide any of the Ethernet clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz). A10 B9 diff1_p diff1_n O Differential Output Clock 1 (LVPECL). When in SONET/SDH mode, this output can be configured to provide any one of the available SONET/SDH clocks (6.48 MHz, 19.44 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz, 622.08 MHz). When in Ethernet mode, this output can be configured to provide any of the Ethernet clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz). D10 apll_clk0 O APLL Output Clock 0 (LVCMOS). This output can be configured to provide any one of the SONET/SDH clock outputs up to 77.76 MHz or any of the Ethernet clock rates up to 125 MHz. The default frequency for this output is 77.76 MHz. G10 apll_clk1 O APLL Output Clock 1 (LVCMOS). This output can be configured to provide any one of the SONET/SDH clock outputs up to 77.76 MHz or any of the Ethernet clock rates up to 125 MHz. The default frequency for this output is 19.44 MHz. 3 Microsemi Corporation ZL30130 Short Form Data Sheet Pin # Name I/O Type Description E10 apll_fp0 O APLL Output Frame Pulse 0 (LVCMOS). This output can be configured to provide virtually any style of output frame pulse synchronized with an associated SONET/SDH family output clock. The default frequency for this frame pulse output is 8 kHz. F10 apll_fp1 O APLL Output Frame Pulse 1 (LVCMOS). This output can be configured to provide virtually any style of output frame pulse synchronized with an associated SONET/SDH family output clock. The default frequency for this frame pulse output is 2 kHz. K9 p0_clk0 O Programmable Synthesizer 0 - Output Clock 0 (LVCMOS). This output can be configured to provide any frequency with a multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz. The default frequency for this output is 2.048 MHz. K7 p0_clk1 O Programmable Synthesizer 0 - Output Clock 1 (LVCMOS). This is a programmable clock output configurable as a multiple or division of the p0_clk0 frequency within the range of 2 kHz to 77.76 MHz. The default frequency for this output is 8.192 MHz. K8 p0_fp0 O Programmable Synthesizer 0 - Output Frame Pulse 0 (LVCMOS). This output can be configured to provide virtually any style of output frame pulse associated with the p0 clocks. The default frequency for this frame pulse output is 8 kHz. J7 p0_fp1 O Programmable Synthesizer 0 - Output Frame Pulse 1 (LVCMOS). This output can be configured to provide virtually any style of output frame pulse associated with the p0 clocks. The default frequency for this frame pulse output is 8 kHz J10 p1_clk0 O Programmable Synthesizer 1 - Output Clock 0 (LVCMOS). This output can be configured to provide any frequency with a multiple of 8 kHz up to 100 MHz in addition to 2 kHz. The default frequency for this output is 1.544 MHz (DS1). K10 p1_clk1 O Programmable Synthesizer1 - Output Clock 1 (LVCMOS). This is a programmable clock output configurable as a multiple or division of the p1_clk0 frequency within the range of 2 kHz to 100 MHz. The default frequency for this output is 3.088 MHz (2x DS1). H10 fb_clk O Feedback Clock (LVCMOS). This output is a buffered copy of the feedback clock for DPLL1. The frequency of this output always equals the frequency of the selected reference. E1 dpll2_ref O DPLL2 Selected Output Reference (LVCMOS). This is a buffered copy of the output of the reference selector for DPLL2. Switching between input reference clocks at this output is not hitless. Control H5 rst_b J5 dpll1_hs_en I Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. To ensure proper operation, the device must be reset after power-up. Reset should be asserted for a minimum of 300 ns. Iu DPLL1 Hitless Switching Enable (LVCMOS, Schmitt Trigger). A logic high at this input enables hitless reference switching. A logic low disables hitless reference switching and re-aligns DPLL1’s output phase to the phase of the selected reference input. This feature can also be controlled through software registers. This pin is internally pulled up to Vdd. 4 Microsemi Corporation ZL30130 Short Form Data Sheet Pin # Name I/O Type C2 D2 dpll1_mod_sel0 dpll1_mod_sel1 Iu DPLL1 Mode Select 1:0 (LVCMOS, Schmitt Trigger). During reset, the levels on these pins determine the default mode of operation for DPLL1 (Automatic, Normal, Holdover or Freerun). After reset, the mode of operation can be controlled directly with these pins, or by accessing the dpll1_modesel register (0x1F) through the serial interface. This pin is internally pulled up to Vdd. D1 slave_en Iu Master/Slave control (LVCMOS, Schmitt Trigger). This pin selects the mode of operation for the device. If set high, slave mode is selected. If set low, master mode is selected. This feature can also be controlled through software registers. This pin is internally pulled up to Vdd. K1 diff0_en Iu Differential Output 0 Enable (LVCMOS, Schmitt Trigger). When set high, the differential LVPECL output 0 driver is enabled. When set low, the differential driver is tristated reducing power consumption. This pin is internally pulled up to Vdd. D3 diff1_en Iu Differential Output 1 Enable (LVCMOS, Schmitt Trigger). When set high, the differential LVPECL output 1 driver is enabled. When set low, the differential driver is tristated reducing power consumption.This pin is internally pulled up to Vdd. H1 dpll1_lock O Lock Indicator (LVCMOS). This is the lock indicator pin for DPLL1. This output goes high when DPLL1’s output is frequency and phase locked to the input reference. J1 dpll1_holdover O Holdover Indicator (LVCMOS). This pin goes high when DPLL1 enters the holdover mode. Description Status Serial Interface E2 sck_scl I/B Clock for Serial Interface (LVCMOS). Serial interface clock. When i2c_en = 0, this pin acts as the sck pin for the serial interface. When i2c_en = 1, this pin acts as the scl pin (bidirectional) for the I2C interface. F1 si_sda I/B Serial Interface Input (LVCMOS). Serial interface data pin. When i2c_en = 0, this pin acts as the si pin for the serial interface. When i2c_en = 1, this pin acts as the sda pin (bidirectional) for the I2C interface. G1 so O Serial Interface Output (LVCMOS). Serial interface data output. When i2c_en = 0, this pin acts as the so pin for the serial interface. When i2c_en = 1, this pin is unused and should be left unconnected. E3 cs_b_asel0 Iu Chip Select/Address Select 0 for the Serial Interface (LVCMOS). Serial interface chip select. When i2c_en = 0, this pin acts as the cs pin (active low) for the serial interface. When i2c_en = 1, this pin acts as the asel0 pin for the I2C interface. G2 int_b O Interrupt Pin (LVCMOS). Indicates a change of device status prompting the processor to read the enabled interrupt service registers (ISR). This pin is an open drain, active low and requires an external pulled up to VDD. J2 i2c_en Iu I2C Interface Enable (LVCMOS). If set high, the I2C interface is enabled, if set low, the SPI interface is enabled. Internally pull-up to Vdd. 5 Microsemi Corporation ZL30130 Pin # Name I/O Type Short Form Data Sheet Description APLL Loop Filter A6 apll_filter A External Analog PLL Loop Filter terminal. B6 filter_ref0 A Analog PLL External Loop Filter Reference. C6 filter_ref1 A Analog PLL External Loop Filter Reference. JTAG and Test J4 tdo O Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of tck. This pin is held in high impedance state when JTAG scan is not enabled. K2 tdi Iu Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to Vdd. If this pin is not used then it should be left unconnected. H4 trst_b K3 tck I Test Clock (LVCMOS): Provides the clock to the JTAG test logic. If this pin is not used then it should be pulled down to GND. tms Iu Test Mode Select (LVCMOS). JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to VDD. If this pin is not used then it should be left unconnected. J3 Iu Test Reset (LVCMOS). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on powerup to ensure that the device is in the normal functional state. This pin is internally pulled up to Vdd. If this pin is not used then it should be connected to GND. Master Clock K4 osci I Oscillator Master Clock Input (LVCMOS). This input accepts a 20 MHz reference from a clock oscillator (TCXO, OCXO). The stability and accuracy of the clock at this input determines the free-run accuracy and the long term holdover stability of the output clocks. K5 osco O Oscillator Master Clock Output (LVCMOS). This pin must be left unconnected when the osci pin is connected to a clock oscillator. Miscellaneous J6 G3 IC Internal Connection. Connect to ground. K6 IC Internal Connection. Leave unconnected. F2 F3 H7 NC No Connection. Leave unconnected. 6 Microsemi Corporation ZL30130 Pin # Name I/O Type Short Form Data Sheet Description Power and Ground D9 E4 G8 G9 J8 J9 H6 H8 VDD P P P P P P P P Positive Supply Voltage. +3.3VDC nominal. E8 F4 VCORE P P Positive Supply Voltage. +1.8VDC nominal. A5 A8 C10 AVDD P P P Positive Analog Supply Voltage. +3.3VDC nominal. B7 B8 H2 AVCORE P P P Positive Analog Supply Voltage. +1.8VDC nominal. D4 D5 D6 D7 E5 E6 E7 F5 F6 F7 G4 G5 G6 G7 E9 F8 F9 H9 VSS G G G G G G G G G G G G G G G G G G Ground. 0 Volts. A7 C7 C8 C9 D8 H3 AVSS G G G G G G Analog Ground. 0 Volts. I - Input Id Iu OAPG- Input, Internally pulled down Input, Internally pulled up Output Analog Power Ground 7 Microsemi Corporation ZL30130 1.0 Short Form Data Sheet Pin Diagram TOP VIEW 1 1 2 3 4 5 6 7 8 9 10 sync1 sync2 ref2 ref7 AVDD apll_filter AVSS AVDD diff0_p diff1_p sync0 ref1 ref4 ref5 sync8/ ext_fb_fp filter_ref0 AVCORE AVCORE diff1_n diff0_n ref0 dpll1_mod_ sel0 ref3 ref6 ref8/ ext_fb_clk filter_ref1 AVSS AVSS AVSS AVDD slave_en dpll1_mod_ sel1 diff1_en VSS VSS VSS VSS AVSS VDD apll_clk0 dpll2_ref sck/ scl cs_b/ asel0 VDD VSS VSS VSS VCORE VSS apll_fp0 si/ sdh NC IC VCORE VSS VSS VSS VSS VSS apll_fp1 so int_b IC VSS VSS VSS VSS VDD VDD apll_clk1 dpll1_lock AVCORE AVSS trst_b rst_b VDD IC VDD VSS fb_clk dpll1_hold i2c_en tms tdo dpll1_hs_en IC p0_fp1 VDD VDD p1_clk0 diff0_en tdi tck osci osco IC p0_clk1 p0_fp0 p0_clk0 p1_clk1 A B C D E F G H J K 1 - A1 corner is identified by metallized markings. 8 Microsemi Corporation ZL30130 2.0 Short Form Data Sheet High Level Overview The ZL30130 SONET/SDH/GbE Stratum 2/3E/3 System Synchronizer and SETS device is a highly integrated device that provides all of the functionality that is required for a central timing card in carrier grade network equipment. The basic functions of a central timing card include: • Input reference monitoring for both frequency accuracy and phase irregularities • Automatic input reference selection • Support of both external timing and line timing modes • Hitless reference switching • Wander and jitter filtering • Optional Input phase transient filtering (Stratum 3E phase build-out) • Master/slave crossover for minimizing phase alignment between redundant timing cards • Independent derived output timing path for support of the SETS functionality In a typical application, the main timing path uses DPLL1 to synchronize to either an external BITS source or to a recovered line timed source. DPLL1 monitors all references and automatically selects the best available reference based on configurable priority and revertive properties. DPLL1 provides the wander filtering function and the P0 synthesizer generates a jitter filtered clock and frame pulse for the system timing bus which supplies all line cards with a common timing reference. A derived output timing path using DPLL2 is available to support the SETS function. In this case DPLL2 uses a filter above 10 Hz to prevent it from filtering wander. 9 Microsemi Corporation ZL30130 Short Form Data Sheet Figure 2 - Typical Application of the ZL30130 Alternatively, the ZL30130 could be used in systems that were not designed with central timing cards in mind. In this case, the ZL30130 provides all of the features required to meet both the timing card and the line card functions in one package. This application is shown in Figure 3. DPLL1 recovers the reference clock from the backplane and filters wander. The APLL and the P0 synthesizer filter jitter and generate transmit clocks for a SONET/SDH/GbE PHY (up to OC-12/STM-4) and/or a PDH PHY (T1/E1, DS3/E3, etc). DPLL2 is used to recover the line timing reference, filter jitter, and translate its frequency to the rate required by the backplane. 10 Microsemi Corporation ZL30130 Short Form Data Sheet Figure 3 - The ZL30130 as a Timing Card and a Line Card Device 11 Microsemi Corporation Copyright 2013, Microsemi Corporation. All Rights Reserved. Information relating to products and services furnished herein by Microsemi Corporation or its subsidiaries (collectively “Microsemi”) is believed to be reliable. However, Microsemi assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Microsemi or licensed from third parties by Microsemi, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Microsemi, or non-Microsemi furnished goods or services may infringe patents or other intellectual property rights owned by Microsemi. This publication is issued to provide information only and (unless agreed by Microsemi in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Microsemi without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical and other products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Microsemi’s conditions of sale which are available on request. For more information about all Microsemi products visit our website at www.microsemi.com TECHNICAL DOCUMENTATION – NOT FOR RESALE Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 © 2013 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.