ZL30142GGG2

ZL30142 SyncE SONET/SDH G.8262/Stratum 3 System Synchronizer Short Form Data Sheet March 2013 Features Ordering Information • Supports the requirements of ITU-T G.8262 for synchronous Ethernet Equipment slave Clocks (EEC option 1 and 2) • Supports the requirements of Telcordia GR-1244 Stratum 3 and GR-253, ITU-T G.812, G.813 • Supports ITU-T G.823, G.824 and G.8261 for 2048 kbit/s and 1544 kbit/s interfaces • Meets the SONET/SDH jitter generation requirements up to OC-48/STM-16 • Synchronizes to telecom reference clocks (2 kHz, N*8 kHz up to 77.76 MHz, 155.52 MHz) or to Ethernet reference clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz) • ZL30142GGG 64 Pin CABGA Trays ZL30142GGG2 64 Pin CABGA* Trays *Pb Free Tin/Silver/Copper -40oC to +85oC Generates standard SONET/SDH clock rates (e.g., 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, 622.08 MHz) or Ethernet clock rates (e.g., 25 MHz, 50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for synchronizing Gigabit Ethernet PHYs • Programmable output synthesizer generates telecom clock frequencies from any multiple of 8 kHz up to 100 MHz • Generates several styles of telecom frame pulses with selectable pulse width, polarity and frequency • Internal state machine automatically controls mode of operation (free-run, locked, holdover) • Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities • Provides automatic reference switching and holdover during loss of reference input • Supports master/slave configuration and dynamic input to output delay compensation for AdvancedTCATM • Configurable input to output delay and output to output phase alignment Applications • ITU-T G.8262 System Timing Cards which support 1 GbE interfaces • Telcordia GR-253 Carrier Grade SONET/SDH Stratum 3 System Timing Cards Figure 1 - Functional Block Diagram 1 Copyright 2013, Microsemi Corporation. All Rights Reserved. ZL30142 1.0 Short Form Data Sheet High Level Overview The ZL30142 SONET/SDH/GbE Stratum 3 System Synchronizer and SETS device is a highly integrated device that provides all of the functionality that is required for a central timing card in carrier grade network equipment. The basic functions of a central timing card include: • • • • • • • Input reference monitoring for both frequency accuracy and phase irregularities Automatic input reference selection Support of both external timing and line timing modes Hitless reference switching Wander and jitter filtering Master/slave crossover for minimizing phase alignment between redundant timing cards Independent derived output timing path for support of the SETS functionality In a typical application, the main timing path uses the DPLL to synchronize to either an external BITS source or to a recovered line timed source. The DPLL monitors the references and automatically selects the best available reference based on configurable priority and revertive properties. the DPLL provides the wander filtering function and the P0 synthesizer generates a jitter filtered clock and frame pulse for the system timing bus which supplies all line cards with a common timing reference. Figure 2 - Typical Application of the ZL30142 2 Microsemi Corporation Package Code c Copyright Zarlink Semiconductor 2005 AllCorporation. rights reserved. 2013, Microsemi All Rights Reserved. ISSUE ACN DATE APPRD. Previous package codes Information relating to products and services furnished herein by Microsemi Corporation or its subsidiaries (collectively “Microsemi”) is believed to be reliable. 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