ZL30164
Triple Channel Network Synchronization
Clock Translator
Short Form Data Sheet
March 2014
Features
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Ordering Information
Flexible two-stage architecture translates between
arbitrary data rates, line coding rates and FEC
rates
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Automatic hitless reference switching and digital
holdover on reference fail
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-40oC to +85oC
Package Size: 13 x 13 mm
Four programmable synthesizers generate any
clock rate from 1 Hz to 750 MHz with low jitter for
10G PHYs
Digital PLLs filter jitter from 0.1 mHz up to 1 kHz
Trays
Pb Free Tin/Silver/Copper
Three programmable digital PLLs/Numerically
Controlled Oscillators (NCOs)
Synchronize to any clock rate from 1 Hz to
750 MHz
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ZL30164GDG2 144 Pin LBGA
Fully compliant SEC (G.813), EEC (G.8262) and
Stratum 3E flexible rate conversion DPLL
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Programmable DPLLs can synchronize to sync
pulse and sync pulse/clock pair
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Eight LVPECL outputs and eight LVCMOS outputs
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Operates from a single crystal resonator or clock
oscillator
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Field programmable via SPI/I2C interface
Applications
Nine input references configurable as single ended
or differential and two single ended input
references
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SyncE/SONET/SDH Timing Cards
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Synchronous Ethernet, 10 GBASE-R and
10 GBASE-W
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SONET/SDH, Fibre Channel, XAUI
Any input reference can be fed with sync (frame
pulse) or clock
Figure 1 - Functional Block Diagram
1
Microsemi Corporation
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