ZL30254LDG1

ZL30254 2-In, 2-Out 8kHz/25MHz to 125/156.25MHz Clock Multiplier and Jitter Attenuator Data Sheet April 2016 Ordering Information Features ZL30254LDG1 ZL30254LDF1 Input Clocks 32 Pin QFN 32 Pin QFN  Two CMOS inputs, both 8kHz or 25MHz Trays Tape and Reel Matte Tin  Inputs continually monitored for frequency accuracy (±1%) Package size: 5 x 5 mm -40C to +85C  Automatic revertive reference switching Low-Bandwidth DPLL  25Hz bandwidth for jitter attenuation General Features  ±120ppm tracking range  Operates from low-cost 49.152MHz fundamental-mode crystal  Digital hold on loss of all inputs  Status output pins indicate selected input clock, holdover, and locked/unlocked states Clock Multiplier APLL and Output Clocks  Easy-to-configure, encapsulated design requires no external VCXO or loop filter components  Input clock selection control pin  Two CML outputs, both 125MHz or 156.25MHz Applications  Outputs easily interface with CML, LVDS or LVPECL components   Output jitter 2.5V, connect the signal directly to the pin. For input signal amplitude ≤2.5V, AC-couple the signal to the pin. Crystal Pins An on-chip crystal driver circuit is designed to work with an external crystal connected to the XA and XB pins. See section 4.1.2 for crystal characteristics and recommended external components. Output Clock Pins CML signal format. See Table 8 and Figure 6 for electrical specifications and recommended external circuitry for interfacing to LVDS, LVPECL or CML input pins on neighboring devices. Reset (Active Low). When this global asynchronous reset is pulled low, all internal circuitry is reset to default values. The device is held in reset as long as RSTN is low. Minimum low time is 100ms. Auto-Configure [1:0] Inputs / DPLL Tracking and Loss-of-Lock Outputs Auto Configure: On the rising edge of RSTN these pins behave as AC[1:0] and specify one of four I/O frequency combinations: AC1 0 0 1 1 28 27 AC0/TRK AC1/LOL I/O AC0 0 1 0 1 IC1 8kHz 8kHz 25MHz 25MHz IC2 8kHz 8kHz 25MHz 25MHz OC1 125MHz 156.25MHz 125MHz 156.25MHz OC2 125MHz 156.25MHz 125MHz 156.25MHz DPLL Tracking and Loss-of-Lock Outputs: After reset these pins are TRK and LOL. They indicate DPLL state as follows: TRK 0 0 1 1 LOL 0 1 0 1 DPLL State Digital hold Digital hold Tracking and locked to selected input Tracking but not locked to selected input. IC1OK pin indicates which input (1=IC1, 0=IC2). Any pullup or pulldown resistors used to set the values of these pins at reset should be 1k. Factory Test Input / IC1 OK Status Output 26 TEST/IC1OK I/O Factory Test: On the rising edge of RSTN the pin behaves as TEST. Factory test mode is enabled when TEST is high. For normal operation TEST must be low on the rising edge of RSTN. A pulldown resistor used to set the value of this pin at reset should be 1k. IC1OK Status Output: 0=IC1 is invalid, 1=IC1 is valid 3 Microsemi Confidential ZL30254 Pin # Name Type 4 NOIC1 I/O 32 TST0 I/O 1 TST1 I/O 2 TST2 I/O 31 TST3 I/O 7 CAP1 A 5 12 13 17 18 22 29 3 25 19 16 9 14 15 E-pad Data Sheet Description No (Invalidate) IC1 Input 0 = IC1 status determined normally by internal monitor 1 = IC1 forced invalid, DPLL switches to IC2 (if IC2 valid) or digital hold (if IC2 invalid) Factory Test Pin. Pin must be wired to DVDD33 through a resistor (10k recommended). Factory Test Pin. Pin must be wired to DVDD33 through a resistor (10k recommended). Factory Test Pin. Pin must be wired to DVDD33 through a resistor (10k recommended). Factory Test Pin. Pin must be wired to DVDD33 through a resistor (10k recommended). Capacitor 1 to VSS Connect a 0.1F capacitor between this pin and VSS. Pin is internally biased to approximately 1.3V. Do not connect to anything else including other CAP pin. CAP2 A Capacitor 2 to VSS Connect a 0.1F capacitor between this pin and VSS. Pin is internally biased to approximately 1.3V. Do not connect to anything else including other CAP pin. AVDD18 P Analog Power Supply. 1.8V 5%. AVDD33 DVDD18 DVDD33 VDDO1 VDDO2 VDD33 VDDXO33 P P P P P P P Analog Power Supply. 3.3V 5%. Digital Power Supply. 1.8V 5%. Digital Power Supply. 3.3V 5%. Output OC1 Power Supply. 3.3V ±5%. Output OC2 Power Supply. 3.3V ±5%. Power Supply. 3.3V ±5%. Analog Power Supply for Crystal Driver Circuitry. 3.3V 5%. Do Not Connect to these pins. DNC VSS P Ground. 0 Volts. 4. Functional Description 4.1 Local Oscillator or Crystal Section 4.1.1 describes how to connect an external oscillator and the required characteristics of the oscillator. Section 4.1.2 describes how to connect an external crystal to the on-chip crystal driver circuit and the required characteristics of the crystal. 4.1.1 External Oscillator A signal from an external oscillator can be connected to the XA pin (XB must be left unconnected). Table 6 specifies the range of possible frequencies for the XA input. Several vendors including Vectron, Rakon and TXC offer low-cost, low-jitter XOs with output frequencies in this range. To minimize jitter, the signal must be properly terminated and must have very short trace length. A poorly terminated single-ended signal can greatly increase output jitter, and long single-ended trace lengths are more susceptible to noise. 4 Microsemi Confidential ZL30254 Data Sheet The jitter on output clock signals depends on the phase noise and frequency of the external oscillator. For the device to operate with the lowest possible output jitter, the external oscillator should have the following characteristics:  Phase Jitter: less than 0.1ps RMS over the 12kHz to 5MHz integration band  Frequency: The higher the better, all else being equal 4.1.2 External Crystal and On-Chip Driver Circuit The on-chip crystal driver circuit is designed to work with a fundamental mode, AT-cut crystal resonator. See Table 2 for recommended crystal specifications. See Figure 4 for the crystal equivalent circuit and the recommended external capacitor connections. To achieve a crystal load (CL) of 10pF, an external 16pF is placed in parallel with the 4pF internal capacitance of the XA pin, and an external 16pF is placed in parallel with the 4pF internal capacitance of the XB pin. The crystal then sees a load of 20pF in series with 20pF, which is 10pF total load. Note that the 16pF capacitance values in Figure 4 include all capacitance on those nodes. If, for example, PCB trace capacitance between crystal pin and IC pin is 2pF then 14pF capacitors should be used to make 16pF total. The crystal, traces, and two external capacitors should be placed on the board as close as possible to the XA and XB pins to reduce crosstalk of active signals into the oscillator. Also no active signals should be routed under the crystal circuitry. Note: Crystals have temperature sensitivies that can cause frequency changes in response to ambient temperature changes. In applications where significant temperature changes are expected near the crystal, it is recommended that the crystal be covered with a thermal cap, or an external XO or TCXO should be used instead. XTAL 4pF 16pF XA CO Crystal (CL = 10pF) R1 XB RS LS CS 16pF R2 4pF R1=1M. The value of R2 is a function of crystal frequency, loading and power rating. Contact the factory for guidance in choosing the right R2 resistor for a specific crystal. Figure 4 - Crystal Equivalent Circuit / Recommended Crystal Circuit Table 2 - Crystal Selection Parameters Parameter 1 Crystal oscillation frequency Shunt capacitance Load capacitance Equivalent series resistance fOSC < 40MHz 2 (ESR) fOSC > 40MHz Maximum crystal drive level Note 1: Note 2: Symbol fOSC CO CL RS RS Min. Typ. 49.152 2 10 Max. 5 60 50 100 Units MHz pF pF   W Higher frequencies give lower output jitter, all else being equal. These ESR limits are chosen to constrain crystal drive level to less than 100W. If the crystal can tolerate a drive level greater than 100W then proportionally higher ESR is acceptable. Parameter Crystal Frequency Stability vs. Power Supply Symbol fFVD 5 Microsemi Confidential Min. Typ. 0.2 Max. Units 0.5 ppm per 10%  in VDD ZL30254 4.1.3 Data Sheet Clock Doubler Figure 1 shows the clock doubler (“x2” block) following the crystal driver block. The doubler is used to double the frequency of the internal crystal driver circuit or a clock signal on the XA pin. The duty cycle of the input clock to the doubler must be as close to 50% as possible because a non-50% duty cycle causes cycle-to-cycle jitter in the doubler’s output signal. 4.2 Input Clocks The IC1 and IC2 input clocks signals are CMOS signal format. The frequency of the two inputs is either 8kHz or 25MHz as specified by the setting of the AC0 and AC1 pins at device reset. See Table 1 for details. 4.2.1 Input Clock Monitoring Each ICx input clock is continuously monitored for activity and frequency accuracy. The activity monitor counts the number of input clock cycles that occur during a configurable interval. This provides the fastest detection when the input clock is stopped or far off frequency. Frequency monitoring is handled by a percent frequency monitor (±1%). Any input clock that fails activity monitoring or frequency monitoring is declared invalid. 4.2.2 Input Clock Selection During normal operation, the device automatically selects input clock IC1 if it is valid; otherwise it selects IC2 if it is valid; otherwise the device goes into digital hold (see section 4.3.1). Switching among inputs is revertive, i.e. if the device is locked to IC2 and IC1 becomes valid then the device will automatically switch back to IC1. The NOIC1 pin can be used to perform manual selection of an input clock. When NOIC1 is high, IC1 is forced invalid. The device then switches to IC2 if it is valid; otherwise the device goes into digital hold. 4.3 DPLL Digital PLLs have stable, repeatable performance that is insensitive to process variations, temperature, and voltage. The DPLL in this device uses a digitally controlled oscillator (DCO) to generate the DPLL output clock. The DPLL output clock is then provided to an APLL for clock multiplication. The DPLL in the device has a fixed 25Hz bandwidth and a ±120ppm tracking range. (Note that the crystal is the measurement reference for this tracking range. A ppm offset of the crystal causes a corresponding ppm offset of the tracking range.) No knowledge of loop equations or gain parameters is required to configure and operate the device. No external components are required for the DPLL except a crystal or XO connected to the XA pin to provide the DPLL’s master clock (see section 4.1). 4.3.1 DPLL States Tracking (Locked and Unlocked). When a valid input clock is available, the DPLL transitions to the tracking state (TRK=1) and is either locked to an input clock (LOL=0) or unlocked (LOL=1). Digital-Hold. When all input clocks become invalid, the DPLL enters the digital-hold state (TRK=0) in which the output frequency has the same fractional frequency offset it had previously when the DPLL was locked to an input clock. The DPLL automatically transitions from the digital-hold state back to the tracking state when an input clock is declared valid. 4.4 Clock Multiplier APLL The low-jitter clock-multiplier APLL in the device is self-contained and requires no external components and no knowledge of loop equations. It is factory-configured for 125MHz or 156.25MHz output clocks. 6 Microsemi Confidential ZL30254 4.5 Data Sheet Output Clock Signals The OC1 and OC2 output clock signals are CML signal format. The frequency of the two outputs is either 125MHz or 156.25MHz as specified by the setting of the AC0 and AC1 pins at device reset. See Table 1 for details. 4.6 Reset Logic The RSTN pin asynchronously resets the entire device. When the RSTN pin is low all internal registers are reset to their default values. The RSTN pin must be asserted once after power-up. Reset should be asserted for at least 100ms. After reset is deasserted the device requires approximately 100ms to configure itself and be ready to operate. 4.7 Power-Supply Considerations Due to the multi-power-supply nature of the device, some I/Os have parasitic diodes between a 1.8V supply and a 3.3V supply. When ramping power supplies up or down, care must be taken to avoid forward-biasing these diodes because it could cause latchup. Two methods are available to prevent this. The first method is to place a Schottky diode external to the device between the 1.8V supply and the 3.3V supply to force the 3.3V supply to be within one parasitic diode drop of the 1.8V supply. The second method is to ramp up the 3.3V supply first and then ramp up the 1.8V supply. 7 Microsemi Confidential ZL30254 Data Sheet 5. Electrical Characteristics Absolute Maximum Ratings Parameter Symbol Min. Max. Units Supply voltage, nominal 1.8V VDD18 -0.3 1.98 V Supply voltage, nominal 3.3V VDD33 -0.3 3.63 V VPIN -0.3 5.5 V TST -55 +125 °C Voltage on any I/O pin Storage Temperature Range * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. * Voltages are with respect to ground (VSS) unless otherwise stated. Note 1: Note 2: The typical values listed in the tables of Section 5 are not production tested. Specifications to -40C and 85C are guaranteed by design or characterization and not production tested. Table 3 - Recommended DC Operating Conditions Parameter Symbol Min. Typ. Max. Units Supply voltage, nominal 1.8V VDD18 1.71 1.8 1.89 V Supply voltage, nominal 3.3V VDD33 3.135 3.3 3.465 V TA -40 +85 °C Operating temperature Table 4 - Electrical Characteristics: Supply Currents Characteristics Symbol Total current, all 1.8V supply pins Total current, all 3.3V supply pins Note 1: Min. IDD18 IDD33 Max Units 155 153 TBD TBD mA mA Notes Note 1 Note 1 Typical values measured at 1.80V and 3.30V supply voltages and 25C ambient temperature. Table 5 - Electrical Characteristics: Non-Clock CMOS Pins Characteristics Symbol Min. Input high voltage, all digital inputs VIH Input low voltage, all digital inputs VIL Input leakage current, RSTN pin IILPU Input leakage current, all other digital inputs IIL Input capacitance CIN Output leakage (when high impedance) ILO -10 Output high voltage VOH 2.4 Output low voltage VOL Note 1: Typ. Typ. Max. 2.0 Units Notes V 0.8 V -85 10 A Note 1 -10 10 A Note 1 10 pF 10 A Note 1 V IO = -3.0mA V IO = 3.0mA 3 0.4 0V < VIN < VDD33 for all other digital inputs. Table 6 - Electrical Characteristics: XA Clock Input This table covers the case when there is no external crystal connected and an external oscillator or clock signal is connected to the XA pin. Symbol Min. Input high voltage, XA Input low voltage, XA Characteristics VIH VIL 1.65 Input frequency on XA pin fIN 49.152 MHz tH, tL 3 ns Minimum input clock high, low time 8 Microsemi Confidential Typ. Max. Units 0.8 V V Notes ZL30254 Data Sheet Table 7 - Electrical Characteristics: Clock Inputs, IC1 and IC2 Characteristics Symbol Min. Typ. Max. Units Input high voltage, all digital inputs VIH Input low voltage, all digital inputs VIL Minimum input clock high, low time tH, tL 3 ns RINVDD18 50 k RINVSS 130 k Input resistance, single-ended to VDD18 Input resistance, single-ended to VSS Note 1: 2.0 V 0.8 Note 1 V Signals with amplitude greater than 2.5V must be DC-coupled. Signals with amplitudes less than 2.5V should be AC coupled. Table 8 - Electrical Characteristics: Clock Outputs Characteristics Symbol Min. fOCML Typ. Output frequency Output high voltage, single-ended, OCxP or OCxN Output low voltage, single-ended, OCxP or OCxN VOH,S VOL,S VDDOx – 0.2 VDDOx – 0.6 Output common mode voltage VCM,S VDDOx – 0.4 Output differential voltage Output differential voltage, peak-to-peak Difference in Magnitude of Differential Voltage for Complementary States Output Rise/Fall Time Output Duty Cycle 320 640 400 800 VDOS tR, tF 150 50 45 ROUT Mismatch in a pair ROUT Max. 125 or 156.25 |VOD,S| |VOD,S,PP| Output Impedance Note 1: Notes Units Notes MHz V V V AC coupled to 50 termination 500 1000 mV mVP-P 50 mV ps % 20%-80% 55  Single Ended, to VDDOx 50 10 % The differential CML outputs can easily be interfaced to LVDS, LVPECL, CML and other differential inputs on neighboring ICs using a few external passive components. See Figure 6 for details. 1/fOCML VOCxP VOH VCM VOL VOCxN |VOD| VOCxP - VOCxN |VOD,PP| 0 Figure 5 - Electrical Characteristics: CML Clock Outputs 9 Microsemi Confidential ZL30254 Data Sheet Microsemi LVDS Receiver 3.3V Microsemi 82 CML Tx 82 CML Tx 50 integrated in some receivers MIcrosemi 50 - CML Receiver 50 VDDOx (3.3V) 130 internal bias assumed 100 - LVPECL Receiver 50 50 50 50 50 + VDDOx (3.3V) + 50 50 VDDOx (3.3V) 50 + 130 CML Tx internal bias and termination assumed 50 - can be AC or DC coupled Figure 6 – Example External Components for CML Output Signals Table 9 - Electrical Characteristics: Output Jitter Performance Characteristics Min. Typ. 125MHz output 156.25MHz output Max. 1 1 Units ps rms ps rms Notes 12kHz - 20MHz 12kHz - 20MHz 6. Package and Thermal Information Table 10 - 5x5mm QFN Package Thermal Properties PARAMETER SYMBOL TA Maximum Ambient Temperature T Maximum Junction Temperature JMAX Junction to Ambient Thermal Resistance (Note 1) JA Junction to Board Thermal Resistance Junction to Case Thermal Resistance Junction to Pad Thermal Resistance (Note 2) Junction to Top-Center Thermal Characterization Parameter JB JC Note 1: Note 2: Note 3: CONDITIONS still air 1m/s airflow 2.5m/s airflow VALUE 85 125 29.6 23.3 20.6 9.8 17.5 UNITS C C C/W C/W C/W JP Still air 3.4 C/W JT Still air 0.2 C/W Theta-JA (JA) is the thermal resistance from junction to ambient when the package is mounted on an 4-layer JEDEC standard test board and dissipating maximum power. Theta-JP (JP) is the thermal resistance from junction to the center exposed pad on the bottom of the package. For all numbers in the table, the exposed pad is connected to the ground plane with a 5x5 array of thermal vias; via diameter 0.33mm; via pitch 0.76mm. 10 Microsemi Confidential ZL30254 7. Mechanical Drawing 11 Microsemi Confidential Data Sheet ZL30254 Data Sheet 8. Data Sheet Revision History Revision 23-Jun-2013 Description First general release In Table 1 and section 4.6 changed the minium reset active time to 100ms. In Table 1 added requirement to AC[1:0] and TEST pins that any pullup or pulldown resistors used to set the values of these pins at reset should be 1k. 23-Mar-2015 Changed the VDDO1 and VDDO2 descriptions in Table 1 to clearly indicate that VDDO1 is for output OC1 and VDDO2 is for output OC2. Modified Figure 6. In the LVDS diagram removed the 5k resistors to ground, which are only appropriate for one type of LVDS receiver design. Added 100 differential termination and note about how it may be integrated in some receivers. Added note that internal bias and termination is assumed for the CML receiver diagram. 19-Apr-2016 Corrected Figure 3 to have square corners rather than chamfered corners to match the mechanical drawing in section 7. Added Note 3 to Table 10. 12 Microsemi Confidential Microsemi Corporate Headquarters One Enterprise Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 E-mail: sales.support@microsemi.com ©2016 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense & security, aerospace and industrial markets. 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