ZL30415GGG2

ZL30415 SONET/SDH Clock Multiplier PLL Data Sheet Features September 2006 • Meets jitter requirements of Telcordia GR-253CORE for OC-12, OC-3, and OC-1 rates • Meets jitter requirements of ITU-T G.813 for STM4, and STM-1 rates • Provides one differential LVPECL output clock selectable to 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, or 622.08 MHz • Provides a single-ended CMOS output clock at 19.44 MHz • Accepts a single-ended CMOS reference at 19.44 MHz or a differential LVDS, LVPECL, or CML reference at 19.44 MHz or 77.76 MHz • Provides a LOCK indication • 3.3 V supply Ordering Information ZL30415GGC ZL30415GGF Trays Tape & Reel, Bake & Drypack ZL30415GGG2 64 Ball CABGA** Trays, Bake & Drypack ZL30415GGF2 64 Ball CABGA** Tape & Reel, Bake & Drypack **Pb Free Tin/Silver/Copper -40°C to +85°C Description The ZL30415 is an analog phase-locked loop (APLL) designed to provide jitter attenuation and rate conversion for SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The ZL30415 generates low jitter output clocks that meet the jitter requirements of Telcordia GR-253-CORE OC-12, OC-3, OC-1 rates and ITU-T G.813 STM-4 and STM-1 rates. Applications • The ZL30415 accepts a CMOS compatible reference at 19.44 MHz or a differential LVDS, LVPECL, or CML reference at 19.44 MHz or 77.76 MHz and generates a differential LVPECL output clock selectable to 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, or 622.08 MHz, and a single-ended CMOS clock at 19.44 MHz. The ZL30415 provides a lock indication. SONET/SDH line cards LPF REF_SEL C19i REFinP/N Reference Selection MUX Frequency & Phase Detector FS3 Loop Filter VCO 19.44 MHz and 77.76 MHz C19i or C77i CML, LVDS, LVPECL input State Machine REF_FREQ 64 Ball CABGA 64 Ball CABGA LOCK FS2 FS1 Frequency Dividers and Clock Drivers C19o, C38o, C77o, C155o, C622o, LVPECL output OC-CLKoP/N C19o Reference and Bias Circuit BIAS VCC GND VDD C19oEN 03 Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved. ZL30415 1 1 2 3 NC NC NC NC VCC1 GND VCC2 GND BIAS LPF LOCK NC 4 Data Sheet 5 6 7 8 NC NC A NC OC-CLKoP OC-CLKoN GND B NC GND GND VCC GND NC VDD GND GND VCC VCC GND GND FS2 VCC VDD NC REFinN C19i C19o GND REFinP VDD VDD GND GND GND C GND D NC E NC F NC NC REF_FREQ C19oEN GND VDD REF_SEL NC NC NC G FS3 GND GND FS1 VDD H 1 VDD - A1 corner is identified by metallized markings. 8 mm x 8 mm Ball Pitch 0.8 mm Figure 2 - BGA 64 Ball Package (Top View) 1.0 Ball Description Ball Description Table Ball # Name Description A1, A2 A3 NC A4 A5 OC-CLKoP OC-CLKoN A6 GND A7, A8 B1, B2 NC B3 VCC1 Positive Analog Power Supply. +3.3 V +/-10% B4 GND Ground. 0 volt B5 NC No internal bonding Connection. Leave unconnected. SONET/SDH Clock (LVPECL Output). These outputs provide a selectable differential LVPECL clock at 19.44 Hz, 38.88 MHz, 77.76 MHz, 155.52 MHz, and 622.08 MHz. The output frequency is selected with FS3, FS2 and FS1 inputs. Ground. 0 volt No internal bonding Connection. Leave unconnected. No internal bonding Connection. Leave unconnected. 2 Zarlink Semiconductor Inc. ZL30415 Data Sheet Ball Description Table (continued) Ball # Name Description B6, B7 GND Ground. 0 volt B8 VCC Positive Analog Power Supply. +3.3 V ±10% C1 GND Ground. 0 volt C2 VCC2 Positive Analog Power Supply. +3.3 V ±10% C3, C4 C5 GND C6 NC C7 VDD Positive Digital Power Supply. +3.3 V ±10% C8 GND Ground. 0 volt D1 BIAS Bias Circuit. D2 LPF External Low-Pass Filter (Analog). Connect external RC network for the lowpass filter. D3 NC No internal bonding Connection. Leave unconnected. D4 GND Ground. 0 volt D5, D6 VCC Positive Analog Power Supply. +3.3 V ±10% D7, D8 GND Ground. 0 volt E1 LOCK Lock Indicator (CMOS Output). This output goes high when the PLL is frequency locked to the selected input reference. E2, E3 NC No internal bonding Connection. Leave unconnected. E4 G4 H5 FS2 FS3 FS1 Frequency Select 3-1 (CMOS Input). These inputs select the clock frequency on the OC-CLKo output. The possible output frequencies are: 19.44 MHz (000), 38.88 MHz (001), 77.76 MHz (010), 155.52 MHz (011), 622.08 (100) E5 VCC Positive Analog Power Supply. +3.3 V ±10% E6 VDD Positive Digital Power Supply. +3.3 V ±10% E7 NC E8 F8 REFinN REFinP F1, F2 NC F3 REF_FREQ F4 C19oEN Ground. 0 volt No internal bonding Connection. Leave unconnected. No internal bonding Connection. Leave unconnected. Differential Reference Clock Input (CML/LVDS/LVPECL Compatible Input). These inputs accept a differential clock at 77.76 MHz or 19.44 MHz as the reference for synchronization. These inputs do not have on-chip AC coupling capacitors. No internal bonding Connection. Leave unconnected. Reference Frequency (CMOS Input). This input selects the rate of the differential input clock (REFinP/N) to be either 77.76 MHz or 19.44 MHz. C19o Output Enable (CMOS Input). If tied high this control input enables the C19o output clock. Pulling this pin low forces the output driver into a high impedance state. 3 Zarlink Semiconductor Inc. ZL30415 Data Sheet Ball Description Table (continued) Ball # Name F5 Description C19i C19 Reference Input (CMOS Input). This is a single-ended input reference source used for synchronization. This input accepts 19.44 MHz. C19o Clock 19.44 MHz (CMOS Output). This output provides a single-ended CMOS clock at 19.44 MHz. F7, G1 GND Ground. 0 volt G2 VDD Positive Digital Power Supply. +3.3 V ±10% G3 REF_SEL G4 FS3 See E4 ball description. G5, G6 GND Ground. 0 volt G7, G8 VDD Positive Digital Power Supply. +3.3 V ±10% H1, H2 H3 NC H4 VDD Positive Digital Power Supply. +3.3 V ±10% H5 FS1 See E4 ball description. H6 VDD Positive Digital Power Supply. +3.3 V ±10% H7, H8 GND Ground. 0 volt. F6 2.0 Reference Select (CMOS Input). If tied low then the C19i single-ended reference is used as the input reference source. If tied high then the REFinP/N differential pair is used as the input reference source. No internal bonding Connection. Leave unconnected. Functional Description The ZL30415 is an analog phased-locked loop which provides rate conversion and jitter attenuation for SONET/SDH OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the ZL30415 is shown in Figure 1 and a brief description is presented in the following sections. 2.1 Reference Selection Multiplexer The ZL30415 accepts two types of input reference clocks: - differential: operating at 19.44 MHz or 77.76 MHz, compatible with LVDS/LVPECL/CML threshold levels - single-ended: operating at 19.44 MHz, compatible with CMOS switching levels. The REF_SEL input determines whether the single-ended CMOS reference input (REFin) or the differential reference inputs (REFinP/N) are used as input reference clocks. The REF_FREQ input selects the rate of the differential input clock to be either 19.44 MHz, or 77.76 MHz. See Table 1 for details. REF_SEL REF_FREQ Selected Input Reference Reference Frequency 0 x C19i 19.44 MHz (CMOS) 1 0 REFin 77.76 MHz (Differential) 1 1 REFin 19.44 MHz (Differential) Table 1 - Input Reference Selection 4 Zarlink Semiconductor Inc. ZL30415 2.2 Data Sheet Frequency/Phase Detector The Frequency/Phase Detector compares the frequency/phase of the input reference signal with the feedback signal from the Frequency Divider circuit and provides an error signal equal to the frequency/phase difference between the two. This error signal is passed to the Loop Filter circuit. 2.3 Lock Indicator The ZL30415 has a built-in LOCK detector that measures frequency difference between input reference clock C19i and the VCO frequency. When the VCO frequency is less than ±300 ppm apart from the input reference frequency then the LOCK output is set high. The LOCK output is pulled low if the frequency difference exceeds ±1000 ppm. 2.4 Loop Filter The Loop Filter is a low-pass filter. This low-pass filter eliminates high frequency spectral components from a phase error signal produced by the Phase Detector. This ensures low output jitter that meets network jitter requirements. The corner frequency of the Loop Filter is configurable with an external capacitor and resistor connected to the LPF ball and ground as shown in Figure 3. ZL30415 Frequency and Phase Detector LPF Loop Filter RF VCO RF=8.2 kΩ, CF=470 nF CF Figure 3 - Loop Filter Elements 2.5 VCO The voltage-controlled oscillator (VCO) receives the filtered error signal from the Loop Filter, and based on the voltage of the error signal generates a primary frequency. The VCO output is connected to the "Frequency Dividers and Clock Drivers" block that divides VCO frequency and buffer generated clocks. 5 Zarlink Semiconductor Inc. ZL30415 2.6 Data Sheet Frequency Dividers and Clock Drivers The output of the VCO feeds the high frequency clock to the "Frequency Dividers and Clock Drivers" circuit to provide one differential LVPECL compatible clock with selectable frequency and one single-ended 19.44 MHz C19o output clock. The C19o clock can be enabled or disabled with the associated C19oEN Output Enable ball. Internally, this block provides a feedback clock that closes the PLL loop. The frequency of the OC-CLKo differential output clock is selected with FS3, FS2 and FS1 inputs as is shown in the following table. FS3 FS2 FS1 OC-CLKo Frequency 0 0 0 19.44 MHz 0 0 1 38.88 MHz 0 1 0 77.76 MHz 0 1 1 155.52 MHz 1 0 0 622.08 MHz 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Table 2 - OC-CLKo Clock Frequency Selection 6 Zarlink Semiconductor Inc. ZL30415 3.0 Data Sheet ZL30415 Performance The following are some of the ZL30415 performance indicators that complement results listed in the Characteristics section of this data sheet. 3.1 Input Jitter Tolerance Jitter tolerance is a measure of the PLL’s ability to operate properly (i.e., remain in lock and/or regain lock in the presence of large jitter magnitudes at various jitter frequencies) in the presence of jitter applied to its input reference. The input jitter tolerance of the ZL30415 is shown in Figure 4. On this graph, the single line at the top represents the input jitter tolerance and the three overlapping lines below represent the specification for minimum input jitter tolerance for OC-192, OC-48 and OC-12 network interfaces. The jitter tolerance is expressed in picoseconds (pk-pk) to accommodate requirements for interfaces operating at different rates. Figure 4 - Input Jitter Tolerance 3.2 Jitter Transfer Characteristic Jitter Transfer Characteristic represents a ratio of the jitter at the output of a PLL to the jitter applied to the input of a PLL. This ratio is expressed in dB and it characterizes the PLL’s ability to attenuate (filter) jitter. The ZL30415 jitter transfer characteristic complies with the maximum 0.1 dB jitter gain specified in Telcordia’s GR-253-CORE. 7 Zarlink Semiconductor Inc. ZL30415 Data Sheet 4.0 Applications 4.1 Generation of Low Jitter SONET/SDH Equipment Clocks The functionality and performance of the ZL30415 complements the entire family of the Zarlink’s advanced network synchronization PLL’s. Its jitter filtering characteristics exceed requirements of SONET/SDH optical interfaces operating up to OC-12/STM-4 rates (622 Mbit/s). The ZL30415 in combination with the MT90401 or the ZL30407 (SONET/SDH Network Element PLL’s) provides the core building blocks for high quality equipment clocks suitable for network synchronization (see Figure 5). REFinP/N OC-CLKoP/N LVPECL ZL30415 C19i C19o CMOS 622.08 MHz 155.52 MHz 77.76 MHz 38.88 MHz 19.44 MHz 19.44 MHz FS1 C19oEN RF FS2 CF FS3 LOCK REF_SEL REF_FREQ LPF C19o PRI C155o SEC Synchronization Reference Clocks RF = 1 kΩ CF = 470 nF RefSel RefAlign ZL30407 PRIOR SECOR LVDS 19.44 MHz 155.52 MHz C34o/C44o CMOS C16o CMOS 16.384 MHz C8o CMOS 8.192 MHz 34.368 MHz or 44.736 MHz C6o CMOS 6.312 MHz C4o CMOS 4.096 MHz C2o CMOS 2.048 MHz C1.5o CMOS 1.544 MHz F16o CMOS F8o CMOS F0o CMOS D0 - D7 A0 - A6 CS R/W 20 MHz OCXO DS C20i LOCK HOLDOVER CMOS Data Port uP Controller Port Note: Only main functional connections are shown. Figure 5 - SONET/SDH Equipment Clock 8 Zarlink Semiconductor Inc. 8 kHz 8 kHz 8 kHz ZL30415 Data Sheet The ZL30415 in combination with the MT9046 provides an optimum solution for SONET/SDH line cards (see Figure 6). OC-CLKoP/N LVPECL REFinP/N ZL30415 C19i C19o CMOS 622.08 MHz 155.52 MHz 77.76 MHz 38.88 MHz 19.44 MHz 19.44 MHz FS1 C2 PRI SEC Synchronization Reference Clocks RSEL MT9046 LOCK HOLDOVER R1 = 680 Ω C1 = 820 nF C2 = 22 nF C19o CMOS C16o CMOS 16.384 MHz C8o CMOS 8.192 MHz 19.44 MHz C6o CMOS 6.312 MHz C4o CMOS 4.096 MHz C2o CMOS 2.048 MHz C1.5o CMOS 1.544 MHz 8 kHz F16o CMOS F8o CMOS F0o CMOS TCLR FLOCK FS1 FS2 MS1 MS2 20 MHz TCXO PCCi C20i C19oEN R1 C1 FS2 FS3 LOCK REF_SEL REF_FREQ LPF LPF uC Hardware Control Note: Only main functional connections are shown. Figure 6 - SONET/SDH Line Card 9 Zarlink Semiconductor Inc. 8 kHz 8 kHz ZL30415 4.2 Data Sheet Recommended Interface circuit 4.2.1 4.2.1.1 Interfacing to REFin Receiver Interfacing REFin Receiver to LVPECL Driver The ZL30415 REFin differential receiver can be connected to LVPECL compatible driver with an interface circuit, as shown in Figure 8. The R1s and R2s terminating resistors should be placed close to the REFin input balls. ZL30415 VCC=+3.3 V VDD/2 R1 R1 Cc Z=50Ω Receiver REFinP LVPECL Driver REFinN Z=50Ω R2 Cc R2 Typical resistor values: R1 = 127 Ω, R2 = 82.5 Ω Figure 7 - Interfacing to LVPECL Driver 4.2.1.2 Interfacing REFin Receiver to LVDS or CML Drivers The ZL30415 REFin differential receiver can be connected to LVDS or CML driver with an interface circuit, as shown in Figure 8. The 100 Ω terminating resistors should be placed close to the REFin input balls. ZL30415 VDD/2 LVDS or CML Driver Receiver Cc Z=50Ω REFinP 100Ω REFinN Z=50Ω Cc Figure 8 - Interfacing to LVDS or CML Driver 10 Zarlink Semiconductor Inc. ZL30415 4.2.2 4.2.2.1 Data Sheet Interfacing to OC-CLKo Output LVPECL to LVPECL Interface The OC-CLKo outputs provide differential LVPECL clocks at 622.08 MHz, 155.52 MHz, 77.76 MHz, 38.88 MHz and 19.44 MHz selectable with FS3, FS2 and FS1 frequency select inputs. The LVPECL output drivers require a 50 Ω termination connected to the Vcc-2V source for each output terminal at the terminating end as shown below. The terminating resistors should be placed close to the LVPECL receiver. Typical resistor values: R1 = 127Ω, R2 =82.5Ω +3.3 V 0.1uF ZL30415 VCC=+3.3 V VCC LVPECL Driver OC-CLKoP Z=50Ω R1 R1 R2 R2 Z=50Ω OC-CLKoN GND Figure 9 - LVPECL to LVPECL Interface 11 Zarlink Semiconductor Inc. LVPECL Receiver ZL30415 4.3 Data Sheet Power Supply and BIAS Circuit Filtering Recommendations Figure 10 presents a complete filtering arrangement that is recommended for applications requiring maximum jitter performance. The level of required filtering is subject to further optimization and simplification. Please check Zarlink’s web site for updates. Ferrite Bead 0.1uF 0.1 uF 10uF 1 1 2 3 NC NC NC NC VCC1 GND VCC2 GND BIAS LPF LOCK NC 4 5 6 7 8 NC NC A 4.7Ω 33uF 220Ω NC OC-CLKoP OC-CLKoN GND B 0.1uF 33uF 0.1uF NC GND GND VCC GND NC VDD GND GND VCC VCC GND GND FS2 VCC VDD NC REFinN C19o GND REFinP VDD VDD GND GND GND C GND 0.1uF 0.1uF D 33uF 0.1uF NC E NC 0.1uF 0.1uF F +3.3V Power Rail NC NC REF_FREQ C19oEN C19i GND VDD REF_SEL GND GND NC NC NC FS1 VDD G FS3 H VDD 0.1uF 0.1uF 0.1uF 0.1uF Notes: 1. All the ground pins (GND) are connected to the same ground plane. 2. Select Ferrite Bead with IDC > 400 mA and RDC in a range from 0.10 Ω to 0.15 Ω. Figure 10 - Power Supply and BIAS Circuit Filtering 12 Zarlink Semiconductor Inc. 0.1uF 0.1uF 0.1uF ZL30415 5.0 Data Sheet Characteristics Absolute Maximum Ratings† Characteristics Sym. Min.‡ Max.‡ Units VDDR, VCCR TBD TBD V 1 Supply voltage 2 Voltage on any ball VBALL -0.5 VCC + 0.5 VDD + 0.5 V 3 Current on any ball IBALL -0.5 30 mA 4 ESD rating VESD 1250 V 5 Storage temperature TST 125 °C 6 Package power dissipation PPD 1.0 W -55 † Voltages are with respect to ground unless otherwise stated. ‡ Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions† Characteristics 1 Operating temperature 2 Positive supply Sym. Min. Typ.‡ Max. Units TOP -40 25 +85 °C VDD, VCC 3.0 3.3 3.6 V Max. Units Notes mA Note 1 Note 2 Notes † Voltages are with respect to ground unless otherwise stated. ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. DC Electrical Characteristics† Characteristics Sym. Min. IDD+ICC Typ.‡ 1 Supply current 2 CMOS: High-level input voltage VIH 0.7VDD VDD V 3 CMOS: Low-level input voltage VIL 0 0.3VDD V 4 CMOS: Input leakage current IIL 1 5 uA VI = VDD or 0V 5 CMOS: Input bias current for pulled-down inputs: FS1, FS2 and FS3 IB-PU 300 uA VI = VDD 6 CMOS: Input bias current for pulled-up inputs: C19oEN IB-PD 90 uA VI = 0 V 7 CMOS: High-level output voltage VOH V IOH = 8 mA 185 2.4 13 Zarlink Semiconductor Inc. ZL30415 Data Sheet DC Electrical Characteristics† (continued) Characteristics Sym. Min. Typ.‡ Max. Units Notes 0.4 V IOL = 4 mA 8 CMOS: Low-level output voltage VOL 9 CMOS: C19o output rise time TR 1.8 3.3 ns 18 pF load 10 CMOS: C19o output fall time TF 1.1 1.4 ns 18 pF load 11 LVPECL: Differential output voltage IVOD_LVPECLI 1.30 V for 622 MHz Note 2 12 LVPECL: Offset voltage VOS_LVPECL V for 622 MHz Note 2 13 LVPECL: Output rise/fall times ps for 622 MHz Note 2 Vcc1.38 Vcc1.27 Vcc1.15 260 TRF † Voltages are with respect to ground unless otherwise stated. ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. Supply voltage and operating temperature are as per Recommended Operating Conditions. Note 1: The ILVPECL current is determined by the external termination network connected to LVPECL outputs. More than 25% of this current (10 mA) flows outside the chip and it does not contribute to the internal power dissipation. The Supply Current value listed in the table includes this current to reflect total current consumption of the ZL30415 and the attached LVPECL termination network. Note 2: LVPECL outputs terminated with ZT = 50 Ω resistors biased to VCC -2V (see Figure 9). AC Electrical Characteristics† - Output Timing Parameters Measurement Voltage Levels Characteristics Sym. CMOS LVPECL Units VT-CMOS VT-LVPECL 0.5VDD 0.5VOD_LVPECL V 1 Threshold voltage 2 Rise and fall threshold voltage high VHM 0.7VDD 0.8VOD_LVPECL V 3 Rise and fall threshold voltage low VLM 0.3VDD 0.2VOD_LVPECL V † Voltages are with respect to ground unless otherwise stated. Timing Reference Points VHM VT VLM All Signals tIF, tOF tIR, tOR Figure 11 - Output Timing Parameter Measurement Voltage Levels 14 Zarlink Semiconductor Inc. ZL30415 Data Sheet AC Electrical Characteristics† - C19i Input to C19o Output Timing Characteristics 1 C19i to C19o delay Sym. Min. Typ.‡ Max. Units tC19D 4.4 6.7 9.4 ns Notes † Supply voltage and operating temperature are as per Recommended Operating Conditions. ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. C19i V T-CMOS (19.44 MHz) tC19D C19o V T-CMOS (19.44 MHz) Note: All output clocks have nominal 50% duty cycle. Figure 12 - C19i Input to C19o Output Timing AC Electrical Characteristics† - REFin to C19o Output Timings Characteristics Sym. Min. Typ.‡ Max. Units 1 REFin (19.44 MHz) to C19o (19.44 MHz) delay tR19OC19D 1.4 7.8 10 ns 2 REFin (77.76 MHz) to C19o (19.44 MHz) delay tR77OC77D 7.9 9.9 13 ns Notes tR19OC19D REFin VT-LVPECL (19.44 MHz) tRW REFin tR77OC77D (77.76 MHz) VT-LVPECL C19o VT-CMOS (19.44 MHz) Figure 13 - REFin Input to C19o Output Timing 15 Zarlink Semiconductor Inc. ZL30415 Data Sheet AC Electrical Characteristics† - C19i Input to OC-CLKo Output Timing Characteristics Sym. Min. Typ.‡ Max. Units 1 C19i(CMOS) to C19o(LVPECL) delay tC19D 1.4 3.3 5.1 ns 2 C19i(CMOS) to OC-CLKo(38) delay tC38D 1.2 3.0 4.8 ns 3 C19i(CMOS) to OC-CLKo(77) delay tC77D 0.9 2.6 4.4 ns 4 C19i(CMOS) to OC-CLKo(155) delay tC155D 0.6 2.3 4.1 ns 5 C19i(CMOS) to OC-CLKo(622) delay tC622D 0 0.8 1.6 ns 6 All Output Clock duty cycle dC 48 50 52 % Notes † Supply voltage and operating temperature are as per Recommended Operating Conditions. ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. C19i VT-CMOS (19.44 MHz) tC19D OC-CLKo(19) VT-LVPECL (19.44 MHz) tC38D OC-CLKo(38) VT-LVPECL (38.88 MHz) tC77D VT-LVPECL OC-CLKo(77) (77.76 MHz) tC155D OC-CLKo(155) VT-LVPECL (155.52 MHz) tC622D OC-CLKo(622) VT-LVPECL (622.08 MHz) Note: All output clocks have nominal 50% duty cycle. Figure 14 - C19i Input to OC-CLKo Output Timing 16 Zarlink Semiconductor Inc. ZL30415 Data Sheet AC Electrical Characteristics† - REFin (19.44 MHz) Input to OC-CLKo Output Timing Characteristics Sym. Min. Typ.‡ Max. Units 1 REFin(19.44 MHz) to OC-CLKo(19) delay tC19-19D 2.4 4.3 6.2 ns 2 REFin(19.44 MHz) to OC-CLKo(38) delay tC19-38D 1.9 4.0 6.0 ns 3 REFin(19.44 MHz) to OC-CLKo(77) delay tC19-77D 1.7 3.7 5.6 ns 4 REFin(19.44 MHz) to OC-CLKo(155) delay tC19-155D 1.4 3.4 5.3 ns 5 REFin(19.44 MHz) to OC-CLKo(622) delay tC19-622D 0 0.8 1.6 ns Notes † Supply voltage and operating temperature are as per Recommended Operating Conditions. ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. VT-LVPECL REFin (19.44 MHz) tC19-19D OC-CLKo(19) VT-LVPECL (19.44 MHz) tC19-38D OC-CLKo(38) VT-LVPECL (38.88 MHz) tC19-77D OC-CLKo(77) VT-LVPECL (77.76 MHz) tC19-155D OC-CLKo(155) VT-LVPECL (155.52 MHz) tC19-622D OC-CLKo(622) VT-LVPECL (622.08 MHz) Note: All output clocks have nominal 50% duty cycle. Figure 15 - REFin (19.44 MHz) Input to OC-CLKo Output Timing 17 Zarlink Semiconductor Inc. ZL30415 Data Sheet AC Electrical Characteristics† - REFin (77.76 MHz) Input to OC-CLKo Output Timing Characteristics Sym. Min. Typ.‡ Max. Units 1 REFin(77.76 MHz) to OC-CLKo(19) delay tC77-19D 3.5 6.5 9.5 ns 2 REFin(77.76 MHz) to OC-CLKo(38) delay tC77-38D 3.2 6.2 9.2 ns 3 REFin(77.76 MHz) to OC-CLKo(77) delay tC77-77D 2.9 5.9 8.8 ns 4 REFin(77.76 MHz) to OC-CLKo(155) delay tC77-155D 2.6 5.6 8.6 ns 5 REFin(77.76 MHz) to OC-CLKo(622) delay tC77-622D 0 0.8 1.6 ns Notes † Supply voltage and operating temperature are as per Recommended Operating Conditions. ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. VT-LVPECL REFin (77.76 MHz) tC77-19D OC-CLKo(19) VT-LVPECL (19.44 MHz) tC77-38D OC-CLKo(38) VT-LVPECL (38.88 MHz) tC77-77D VT-LVPECL OC-CLKo(77) (77.76 MHz) tC77-155D OC-CLKo(155) VT-LVPECL (155.52 MHz) tC77-622D OC-CLKo(622) VT-LVPECL (622.08 MHz) Note: All output clocks have nominal 50% duty cycle. Figure 16 - REFin (77.76 MHz) Input to OC-CLKo Output Timing 18 Zarlink Semiconductor Inc. ZL30415 Data Sheet Performance Characteristics - Functional (VCC = 3.3 V ±10%; TA = Characteristics 1 Pull-in range 2 Lock Time Min. -40 to 85×C ) Typ. Max. ±1000 Units ppm 300 Notes At nominal input reference frequency C19i = 19.44 MHz ms Performance Characteristics: Output Jitter Generation (LVPECL: 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, and 622.08 MHz and CMOS: 19.44 MHz) - GR-253-CORE conformance - (VCC = 3.3 V ±10%; TA = - 40 to 85°C) GR-253-CORE Jitter Generation Requirements Interface (Category II) 1 2 OC-12 STS-12 OC-3 STS-3 Jitter Measurement Filter 12 kHz - 5 MHz 12 kHz - 1.3 MHz ZL30415 Jitter Generation Performance Equivalent limit in time domain Limit in UI 0.1 UIpp 161 0.01 UIRMS 16.1 0.1 UIpp 643 0.01 UIRMS 64.3 † Typical figures are for design aid only: not guaranteed and not subject to production testing. ‡ Loop Filter components: RF = 8.2 kΩ, CF = 470 nF. 19 Zarlink Semiconductor Inc. Typ.† 1.7 1.6 Max.‡ Units 35 psP-P 3.5 psRMS 33 psP-P 3.3 psRMS ZL30415 Data Sheet Performance Characteristics: Output Jitter Generation (LVPECL: 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, and 622.08 MHz and CMOS: 19.44 MHz) - ETSI EN 300 462-7-1 conformance - (VCC = 3.3 V ±10%; TA = -40 to 85°C) EN 300 462-7-1 Jitter Generation Requirements Interface 1 STM-4 Jitter Measurement Filter 250 kHz to 5 MHz ZL30415 Jitter Generation Performance Equivalent limit in time domain Limit in UI 0.1 UIpp 161 - - 0.5 UIpp 1 kHz to 5 MHz 2 STM-1 optical 65 kHz to 1.3 MHz - - 0.1 UIpp STM-1 electrical 65 kHz to 1.3 MHz - 0.5 UIpp 1.6 3215 - 0.075 UIpp 5 482 500 Hz to 1.3 MHz 4 643 3 1.5 804 500 Hz to 1.3 MHz Typ.† - 0.5 UIpp 1.6 3215 - - † Typical figures are for design aid only: not guaranteed and not subject to production testing. ‡ Loop Filter components: RF = 8.2 kΩ, CF = 470 nF. 20 Zarlink Semiconductor Inc. 5 Max.‡ Units 30 psP-P 3 psRMS 80 psP-P 8 psRMS 31 psP-P 3.1 psRMS 100 psP-P 10 psRMS 31 psP-P 3.1 psRMS 100 psP-P 10 psRMS ZL30415 Data Sheet Performance Characteristics: Output Jitter Generation (LVPECL: 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, and 622.08 MHz and CMOS: 19.44 MHz) - G.813 conformance (Option 1 and 2) - (VCC = 3.3 V ±10%; TA = -40 to 85°C) G.813 Jitter Generation Requirements Interface Jitter Measurement Filter ZL30415 Jitter Generation Performance Equivalent limit in time domain Limit in UI Typ.† Max.‡ Units Option 1 1 STM-4 250 kHz to 5 MHz 0.1 UIpp 161 1 kHz to 5 MHz - 0.5 UIpp 804 2 STM-1 65 kHz to 1.3 MHz - 0.1 UIpp 4 643 500 Hz to 1.3 MHz 1.5 - 0.5 UIpp 1.6 3215 - - 5 30 psP-P 3 psRMS 80 psP-P 8 psRMS 31 psP-P 3.1 psRMS 100 psP-P 10 psRMS 35 psP-P 3.5 psRMS 33 psP-P 3.3 psRMS Option 2 3 STM-4 12 kHz - 5 MHz 0.1 UIpp 161 4 STM-1 12 kHz - 1.3 MHz - 0.1 UIpp 1.7 643 - - † Typical figures are for design aid only: not guaranteed and not subject to production testing. ‡ Loop Filter components: RF = 8.2 kΩ, CF = 470 nF. 21 Zarlink Semiconductor Inc. 1.6 Package Code c Zarlink Semiconductor 2003 All rights reserved. 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