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ZL30416GGG

ZL30416GGG

  • 厂商:

    MICROSEMI(美高森美)

  • 封装:

    LFBGA64

  • 描述:

    IC PLL SONET/SDH CLK MULT 64CBGA

  • 数据手册
  • 价格&库存
ZL30416GGG 数据手册
ZL30416 SONET/SDH Clock Multiplier PLL Data Sheet Features • • June 2006 Low jitter clock outputs suitable for OC-192, OC48, OC-12, OC-3 and OC-1 SONET applications as defined in Telcordia GR-253-CORE Ordering Information ZL30416GGG ZL30416GGG2 Low jitter clock outputs suitable for STM-64, STM16, STM-4 and STM-1 applications as defined in ITU-T G.813 • Provides one differential LVPECL output clock selectable to 19.44, 38.88, 77.76, 155.52 or 622.08 MHz • Provides a single-ended CMOS output clock at 19.44 MHz • Accepts a single-ended CMOS reference at 19.44 MHz or a differential LVDS, LVPECL or CML reference at 19.44 or 77.76 MHz • Provides a LOCK indication • 8 mm x 8 mm CABGA package • 3.3 V supply *Pb Free Tin/Silver/Copper -40°C to +85°C Description The ZL30416 is an Analog Phase-Locked Loop (APLL) designed to provide jitter attenuation and rate conversion for SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The ZL30416 generates low jitter output clocks suitable for Telcordia GR-253CORE OC-192, OC-48, OC-12, OC-3, and OC-1 and ITU-T G.813 STM-64, STM-16, STM-4 and STM-1 applications. The ZL30416 accepts a CMOS compatible reference at 19.44 MHz or a differential LVDS, LVPECL or CML reference at 19.44 or 77.76 MHz and generates a differential LVPECL output clock selectable to 19.44, 38.88, 77.76, 155.52 or 622.08 MHz and a singleended CMOS clock at 19.44 MHz. The ZL30416 provides a lock indication. Applications • SONET/SDH line cards LPF REF_SEL C19i REFinP/N Reference Selection MUX Frequency & Phase Detector FS3 FS2 FS1 Loop Filter VCO 19.44 MHz and 77.76 MHz C19i or C77i CML, LVDS, LVPECL input REF_FREQ 64 Ball CABGA Trays, Bake & Drypack 64 Ball CABGA* Trays, Bake & Drypack State Machine Reference and Bias Circuit LOCK BIAS VCC GND Frequency Dividers and Clock Drivers VDD C19oEN Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved. C19o, C38o, C77o, C155o, C622o, LVPECL output OC-CLKoP/N C19o ZL30416 1 1 2 3 NC NC NC NC VCC1 GND VCC2 GND BIAS LPF LOCK NC 4 Data Sheet 5 6 7 8 NC NC A NC OC-CLKoP OC-CLKoN GND B NC GND GND VCC GND NC VDD GND GND VCC VCC GND GND FS2 VCC VDD NC REFinN C19i C19o GND REFinP VDD VDD GND GND GND C GND D NC E NC F NC NC REF_FREQ C19oEN GND VDD REF_SEL NC NC NC G FS3 GND GND FS1 VDD H 1 VDD - A1 corner is identified by metallized markings. 8 mm x 8 mm Ball Pitch 0.8mm Figure 2 - BGA 64 Ball Package (Top View) 1.0 Ball Description Ball Description Table Ball # Name Description A1, A2 A3 NC A4 A5 OC-CLKoP OC-CLKoN A6 GND A7, A8 B1, B2 NC B3 VCC1 Positive Analog Power Supply. +3.3 V +/-10% B4 GND Ground. 0 volt B5 NC B6, B7 GND No internal bonding Connection. Leave unconnected. SONET/SDH Clock (LVPECL Output). These outputs provide a selectable differential LVPECL clock at 19.44 Hz, 38.88 MHz, 77.76 MHz, 155.52 MHz, and 622.08 MHz. The output frequency is selected with FS3, FS2 and FS1 inputs. Ground. 0 volt No internal bonding Connection. Leave unconnected. No internal bonding Connection. Leave unconnected. Ground. 0 volt 2 Zarlink Semiconductor Inc. ZL30416 Data Sheet Ball Description Table (continued) Ball # Name B8 VCC Positive Analog Power Supply. +3.3 V ±10% C1 GND Ground. 0 volt C2 VCC2 Positive Analog Power Supply. +3.3 V ±10% C3, C4 C5 GND C6 NC C7 VDD Positive Digital Power Supply. +3.3 V ±10% C8 GND Ground. 0 volt D1 BIAS Bias Circuit. D2 LPF External Low-Pass Filter (Analog). Connect external RC network for the lowpass filter. D3 NC No internal bonding Connection. Leave unconnected. D4 GND Ground. 0 volt D5, D6 VCC Positive Analog Power Supply. +3.3 V ±10% D7, D8 GND Ground. 0 volt E1 LOCK Lock Indicator (CMOS Output). This output goes high when the PLL is frequency locked to the selected input reference. E2, E3 NC No internal bonding Connection. Leave unconnected. G4 E4 H5 FS3 FS2 FS1 Frequency Select 3-1 (CMOS Input). These inputs select the clock frequency on the OC-CLKo output. The possible output frequencies are: 19.44 MHz (000), 38.88 MHz (001), 77.76 MHz (010), 155.52 MHz (011), 622.08 (100) E5 VCC Positive Analog Power Supply. +3.3 V ±10% E6 VDD Positive Digital Power Supply. +3.3 V ±10% E7 NC E8 F8 REFinN REFinP F1, F2 NC F3 REF_FREQ F4 C19oEN F5 C19i Description Ground. 0 volt No internal bonding Connection. Leave unconnected. No internal bonding Connection. Leave unconnected. Differential Reference Clock Input (CML/LVDS/LVPECL Compatible Input). These inputs accept a differential clock at 77.76 MHz or 19.44 MHz as the reference for synchronization. These inputs do not have on-chip AC coupling capacitors. No internal bonding Connection. Leave unconnected. Reference Frequency (CMOS Input). This input selects the rate of the differential input clock (REFinP/N) to be either 77.76 MHz or 19.44 MHz. C19o Output Enable (CMOS Input). If tied high this control input enables the C19o output clock. Pulling this pin low forces the output driver into a high impedance state. C19 Reference Input (CMOS Input). This is a single-ended input reference source used for synchronization. This input accepts 19.44 MHz. 3 Zarlink Semiconductor Inc. ZL30416 Data Sheet Ball Description Table (continued) Ball # Name Description C19o Clock 19.44 MHz (CMOS Output). This output provides a single-ended CMOS clock at 19.44 MHz. F7, G1 GND Ground. 0 volt G2 VDD Positive Digital Power Supply. +3.3 V ±10% G3 REF_SEL G4 FS3 See E4 ball description. G5, G6 GND Ground. 0 volt G7, G8 VDD Positive Digital Power Supply. +3.3 V ±10% H1, H2 H3 NC H4 VDD Positive Digital Power Supply. +3.3 V ±10% H5 FS1 See E4 ball description. H6 VDD Positive Digital Power Supply. +3.3 V ±10% H7, H8 GND Ground. 0 volt. F6 2.0 Reference Select (CMOS Input). If tied low then the C19i single-ended reference is used as the input reference source. If tied high then the REFinP/N differential pair is used as the input reference source. No internal bonding Connection. Leave unconnected. Functional Description The ZL30416 is an analog phased-locked loop which provides rate conversion and jitter attenuation for SONET/SDH OC-192/STM-64, OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the ZL30416 is shown in Figure 1 and a brief description is presented in the following sections. 2.1 Reference Selection Multiplexer The ZL30416 accepts two types of input reference clocks: - differential: operating at 19.44 MHz or 77.76 MHz, compatible with LVDS/LVPECL/CML threshold levels - single-ended: operating at 19.44 MHz, compatible with CMOS switching levels The REF_SEL input determines whether the single-ended CMOS reference input (REFin) or the differential reference inputs (REFinP/N) are used as input reference clocks. The REF_FREQ input selects the rate of the differential input clock to be either 19.44 MHz or 77.76 MHz. See Table 1 for details. REF_SEL REF_FREQ Selected Input Reference Reference Frequency 0 x C19i 19.44 MHz (CMOS) 1 0 REFin 77.76 MHz (Differential) 1 1 REFin 19.44 MHz (Differential) Table 1 - Input Reference Selection 4 Zarlink Semiconductor Inc. ZL30416 2.2 Data Sheet Frequency/Phase Detector The Frequency/Phase Detector compares the frequency/phase of the input reference signal with the feedback signal from the Frequency Divider circuit and provides an error signal equal to the frequency/phase difference between the two. This error signal is passed to the Loop Filter circuit. 2.3 Lock Indicator The ZL30416 has a built-in LOCK detector that measures frequency difference between input reference clock C19i and the VCO frequency. When the VCO frequency is less than ±300 ppm apart from the input reference frequency then the LOCK output is set high. The LOCK output is pulled low if the frequency difference exceeds ±1000 ppm. 2.4 Loop Filter The Loop Filter is a low-pass filter. This low-pass filter eliminates high frequency spectral components from a phase error signal produced by the Phase Detector. This ensures low output jitter that meets network jitter requirements. The corner frequency of the Loop Filter is configurable with an external capacitor and resistor connected to the LPF ball and ground as shown in Figure 3. ZL30416 Frequency and Phase Detector LPF Loop Filter RF VCO CF RF=8.2 kΩ, CF=470 nF fTYP=14.4 kHz Figure 3 - Loop Filter Elements 2.5 VCO The voltage-controlled oscillator (VCO) receives the filtered error signal from the Loop Filter and based on the voltage of the error signal generates a primary frequency. The VCO output is connected to the "Frequency Dividers and Clock Drivers" block that divides VCO frequency and buffer generated clocks. 5 Zarlink Semiconductor Inc. ZL30416 2.6 Data Sheet Frequency Dividers and Clock Drivers The output of the VCO feeds the high frequency clock to the "Frequency Dividers and Clock Drivers" circuit to provide one differential LVPECL compatible clock with selectable frequency and one single-ended 19.44 MHz C19o output clock. The C19o clock can be enabled or disabled with the associated C19oEN Output Enable ball. Internally, this block provides a feedback clock that closes the PLL loop. The frequency of the OC-CLKo differential output clock is selected with FS3, FS2 and FS1 inputs as is shown in the following table. FS3 FS2 FS1 OC-CLKo Frequency 0 0 0 19.44 MHz 0 0 1 38.88 MHz 0 1 0 77.76 MHz 0 1 1 155.52 MHz 1 0 0 622.08 MHz 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Table 2 - OC-CLKo Clock Frequency Selection 6 Zarlink Semiconductor Inc. ZL30416 3.0 Data Sheet ZL30416 Performance The following are some of the ZL30416 performance indicators that complement results listed in the Characteristics section of this data sheet. 3.1 Input Jitter Tolerance Jitter tolerance is a measure of the PLL’s ability to operate properly (i.e., remain in lock and/or regain lock in the presence of large jitter magnitudes at various jitter frequencies) in the presence of jitter applied to its input reference. The input jitter tolerance of the ZL30416 is shown in Figure 4. On this graph, the single line at the top represents the input jitter tolerance and the three overlapping lines below represent the specification for minimum input jitter tolerance for OC-192, OC-48 and OC-12 network interfaces. The jitter tolerance is expressed in picoseconds (pk-pk) to accommodate requirements for interfaces operating at different rates. Figure 4 - Input Jitter Tolerance 3.2 Jitter Transfer Characteristic Jitter Transfer Characteristic represents a ratio of the jitter at the output of a PLL to the jitter applied to the input of a PLL. This ratio is expressed in dB and it characterizes the PLL’s ability to attenuate (filter) jitter. The ZL30416 jitter transfer characteristic complies with the maximum 0.1 dB jitter gain specified in Telcordia’s GR-253-CORE. 7 Zarlink Semiconductor Inc. ZL30416 Data Sheet 4.0 Applications 4.1 Generation of Low Jitter SONET/SDH Equipment Clocks The functionality and performance of the ZL30416 complements the entire family of the Zarlink’s advanced network synchronization PLL’s. Its jitter filtering characteristics exceed requirements of SONET/SDH optical interfaces operating up to OC-192/STM-64. The ZL30416 in combination with the MT90401 or the ZL30407 (SONET/SDH Network Element PLL’s) provides the core building blocks for high quality equipment clocks suitable for network synchronization (see Figure 5). 622.08 MHz OC-CLKoP/N LVPECL 155.52 MHz 77.76 MHz 38.88 MHz 19.44 MHz C19o CMOS 19.44 MHz REFinP/N ZL30416 C19i FS1 C19oEN RF FS2 CF FS3 LOCK REF_SEL REF_FREQ LPF PRI SEC Synchronization Reference Clocks RefSel RefAlign ZL30407 PRIOR SECOR D0 - D7 DS CS R/W A0 - A6 20 MHz OCXO C20i LOCK HOLDOVER RF = 1 kΩ CF = 470 nF C19o C155o C34o/C44o C16o C8o C6o C4o C2o C1.5o F16o F8o CMOS LVDS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS F0o CMOS Data Port uP Controller Port Note: Only main functional connections are shown Figure 5 - SONET/SDH Equipment Clock 8 Zarlink Semiconductor Inc. 19.44 MHz 155.52 MHz 34.368 MHz or 44.736 MHz 16.384 MHz 8.192 MHz 6.312 MHz 4.096 MHz 2.048 MHz 1.544 MHz 8 kHz 8 kHz 8 kHz ZL30416 4.2 Data Sheet Recommended Interface Circuit 4.2.1 4.2.1.1 Interfacing to REFin Receiver Interfacing REFin Receiver to LVPECL Driver The ZL30416 REFin differential receiver can be connected to LVPECL compatible driver with an interface circuit, as shown in Figure 7. The R1s and R2s terminating resistors should be placed close to the REFin input balls. ZL30416 VCC=+3.3V VDD/2 R1 R1 Cc Z=50 Ω Receiver REFinP LVPECL Driver REFinN Z=50 Ω R2 Cc R2 Typical resistor values: R1 = 127 Ω, R2 =82.5 Ω Typical capacitor values: Cc = 0.1 µF Figure 6 - Interfacing to LVPECL Driver 4.2.1.2 Interfacing REFin Receiver to LVDS or CML Drivers The ZL30416 REFin differential receiver can be connected to LVDS or CML driver with an interface circuit, as shown in Figure 7. The 100 Ω terminating resistors should be placed close to the REFin input balls. ZL30416 VDD/2 LVDS or CML Driver Receiver Cc Z=50 Ω REFinP 100Ω REFinN Z=50 Ω Cc Typical capacitor values: Cc = 0.1 µF Figure 7 - Interfacing to LVDS or CML Driver 9 Zarlink Semiconductor Inc. ZL30416 4.2.2 4.2.2.1 Data Sheet Interfacing to OC-CLKo Output LVPECL to LVPECL Interface The OC-CLKo outputs provide differential LVPECL clocks at 622.08 MHz, 155.52 MHz, 77.76 MHz, 38.88 MHz and 19.44 MHz selectable with FS3, FS2 and FS1 frequency select inputs. The LVPECL output drivers require a 50 Ω termination connected to the Vcc-2V source for each output terminal at the terminating end as shown below. The terminating resistors should be placed close to the LVPECL receiver. Typical resistor values: R1 = 127 Ω, R2 =82.5 Ω +3.3 V 0.1 uF ZL30416 VCC=+3.3 V VCC LVPECL Driver OC-CLKoP Z=50 Ω R1 R1 R2 R2 Z=50 Ω OC-CLKoN GND Figure 8 - LVPECL to LVPECL Interface 10 Zarlink Semiconductor Inc. LVPECL Receiver ZL30416 4.3 Data Sheet Power supply and BIAS Circuit Filtering Recommendations Figure 9 presents a complete filtering arrangement that is recommended for applications requiring maximum jitter performance. The level of required filtering is subject to further optimization and simplification. Please check Zarlink’s web site for updates. Ferrite Bead 0.1 uF 0.1 uF 10 uF 1 2 3 NC NC NC NC VCC1 GND VCC2 GND BIAS LPF LOCK NC 4 5 6 7 8 NC NC A 4.7 Ω NC OC-CLKoP OC-CLKoN GND B 33 uF 220 Ω 1 0.1 uF 0.1 uF 33 uF NC GND GND VCC GND NC VDD GND GND VCC VCC GND GND FS2 VCC VDD NC REFinN C19o GND REFinP VDD VDD GND GND GND C GND 0.1 uF 0.1 uF D 33 uF 0.1 uF NC E NC 0.1 uF 0.1 uF F +3.3 V Power Rail NC NC REF_FREQ C19oEN C19i GND VDD REF_SEL GND GND NC NC NC FS1 VDD G FS3 H VDD 0.1 uF 0.1 uF 0.1 uF 0.1 uF Notes: 1. All the ground pins (GND) are connected to the same ground plane. 2. Select Ferrite Bead with IDC > 400 mA and RDC in a range from 0.10 Ω to 0.15 Ω. Figure 9 - Power Supply and BIAS Circuit Filtering 11 Zarlink Semiconductor Inc. 0.1 uF 0.1 uF 0.1 uF ZL30416 5.0 Data Sheet Characteristics Absolute Maximum Ratings† Characteristics Sym. Min.‡ Max.‡ Units VDDR, VCCR TBD TBD V 1 Supply voltage 2 Voltage on any ball VBALL -0.5 VCC + 0.5 VDD + 0.5 V 3 Current on any ball IBALL -0.5 30 mA 4 ESD rating VESD 1250 V 5 Storage temperature TST 125 °C 6 Package power dissipation PPD 1.0 W -55 † Voltages are with respect to ground unless otherwise stated. ‡ Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions† Characteristics 1 Operating temperature 2 Positive supply Sym. Min. Typ.‡ Max. Units TOP -40 25 +85 °C VDD, VCC 3.0 3.3 3.6 V Notes † Voltages are with respect to ground unless otherwise stated. ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. DC Electrical Characteristics† Characteristics Sym. Min. IDD+ICC Typ.‡ Max. Units Notes mA Note 1 Note 2 1 Supply current 2 CMOS: High-level input voltage VIH 0.7 VDD VDD V 3 CMOS: Low-level input voltage VIL 0 0.3 VDD V 4 CMOS: Input leakage current IIL 1 5 uA VI = VDD or 0 V 5 CMOS: Input bias current for pulled-down inputs: FS1, FS2 and FS3 IB-PU 300 uA VI = VDD 6 CMOS: Input bias current for pulled-up inputs: C19oEN IB-PD 90 uA VI = 0 V 7 CMOS: High-level output voltage VOH V IOH = 8 mA 185 2.4 12 Zarlink Semiconductor Inc. ZL30416 Data Sheet DC Electrical Characteristics† (continued) Characteristics Sym. Min. Typ.‡ Max. Units Notes 0.4 V IOL = 4 mA 8 CMOS: Low-level output voltage VOL 9 CMOS: C19o output rise time TR 1.8 3.3 ns 18 pF load 10 CMOS: C19o output fall time TF 1.1 1.4 ns 18 pF load 11 LVPECL: Differential output voltage IVOD_LVPEC LI 1.30 V for 622 MHz Note 2 12 LVPECL: Offset voltage VOS_LVPECL V for 622 MHz Note 2 13 LVPECL: Output rise/fall times ps for 622 MHz Note 2 Vcc1.38 Vcc1.27 Vcc1.15 260 TRF † Voltages are with respect to ground unless otherwise stated. ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. Supply voltage and operating temperature are as per Recommended Operating Conditions. Note 1: The ILVPECL current is determined by the external termination network connected to LVPECL outputs. More than 25% of this current (10 mA) flows outside the chip and it does not contribute to the internal power dissipation. The Supply Current value listed in the table includes this current to reflect total current consumption of the ZL30416 and the attached LVPECL termination network. Note 2: LVPECL outputs terminated with ZT = 50 Ω resistors biased to VCC -2V (see Figure 8). AC Electrical Characteristics† - Output Timing Parameters Measurement Voltage Levels Characteristics Sym. CMOS LVPECL Units VT-CMOS VT-LVPECL 0.5 VDD 0.5 VOD_LVPECL V 1 Threshold voltage 2 Rise and fall threshold voltage high VHM 0.7 VDD 0.8 VOD_LVPECL V 3 Rise and fall threshold voltage low VLM 0.3 VDD 0.2 VOD_LVPECL V † Voltages are with respect to ground unless otherwise stated. Timing Reference Points VHM VT VLM All Signals tIF, tOF tIR, tOR Figure 10 - Output Timing Parameter Measurement Voltage Levels 13 Zarlink Semiconductor Inc. ZL30416 Data Sheet AC Electrical Characteristics† - C19i Input to C19o Output Timing Characteristics 1 C19i to C19o delay Sym. Min. Typ.‡ Max. Units tC19D 4.4 6.7 9.4 ns Notes † Supply voltage and operating temperature are as per Recommended Operating Conditions. ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. C19i V T-CMOS (19.44 MHz) tC19D C19o V T-CMOS (19.44 MHz) Note: All output clocks have nominal 50% duty cycle. Figure 11 - C19i Input to C19o Output Timing AC Electrical Characteristics† - REFin to C19o Output Timings Characteristics Sym. Min. Typ.‡ Max. Units 1 REFin (19.44 MHz) to C19o (19.44 MHz) delay tR19OC19D 1.4 7.8 10 ns 2 REFin (77.76 MHz) to C19o (19.44 MHz) delay tR77OC77D 7.9 9.9 13 ns Notes tR19OC19D REFin VT-LVPECL (19.44 MHz) tRW REFin tR77OC77D VT-LVPECL (77.76 MHz) VT-CMOS C19o (19.44 MHz) Figure 12 - REFin Input to C19o Output Timing 14 Zarlink Semiconductor Inc. ZL30416 Data Sheet AC Electrical Characteristics† - C19i Input to OC-CLKo Output Timing Characteristics Sym. Min. Typ.‡ Max. Units 1 C19i(CMOS) to C19o(LVPECL) delay tC19D 1.4 3.3 5.1 ns 2 C19i(CMOS) to OC-CLKo(38) delay tC38D 1.2 3.0 4.8 ns 3 C19i(CMOS) to OC-CLKo(77) delay tC77D 0.9 2.6 4.4 ns 4 C19i(CMOS) to OC-CLKo(155) delay tC155D 0.6 2.3 4.1 ns 5 C19i(CMOS) to OC-CLKo(622) delay tC622D 0 0.8 1.6 ns 6 All Output Clock duty cycle dC 48 50 52 % Notes † Supply voltage and operating temperature are as per Recommended Operating Conditions. ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. C19i VT-CMOS (19.44 MHz) tC19D OC-CLKo(19) VT-LVPECL (19.44 MHz) tC38D OC-CLKo(38) VT-LVPECL (38.88 MHz) tC77D VT-LVPECL OC-CLKo(77) (77.76 MHz) tC155D OC-CLKo(155) (155.52 MHz) VT-LVPECL tC622D OC-CLKo(622) (622.08 MHz) VT-LVPECL Note: All output clocks have nominal 50% duty cycle. Figure 13 - C19i Input to OC-CLKo Output Timing 15 Zarlink Semiconductor Inc. ZL30416 Data Sheet AC Electrical Characteristics† - REFin (19.44 MHz) Input to OC-CLKo Output Timing Characteristics Sym. Min. Typ.‡ Max. Units 1 REFin(19.44 MHz) to OC-CLKo(19) delay tC19-19D 2.4 4.3 6.2 ns 2 REFin(19.44 MHz) to OC-CLKo(38) delay tC19-38D 1.9 4.0 6.0 ns 3 REFin(19.44 MHz) to OC-CLKo(77) delay tC19-77D 1.7 3.7 5.6 ns 4 REFin(19.44 MHz) to OC-CLKo(155) delay tC19-155D 1.4 3.4 5.3 ns 5 REFin(19.44 MHz) to OC-CLKo(622) delay tC19-622D 0 0.8 1.6 ns Notes † Supply voltage and operating temperature are as per Recommended Operating Conditions. ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. VT-LVPECL REFin (19.44 MHz) tC19-19D OC-CLKo(19) VT-LVPECL (19.44 MHz) tC19-38D OC-CLKo(38) VT-LVPECL (38.88 MHz) tC19-77D OC-CLKo(77) VT-LVPECL (77.76 MHz) tC19-155D OC-CLKo(155) (155.52 MHz) VT-LVPECL tC19-622D OC-CLKo(622) (622.08 MHz) VT-LVPECL Note: All output clocks have nominal 50% duty cycle. Figure 14 - REFin (19.44 MHz) Input to OC-CLKo Output Timing 16 Zarlink Semiconductor Inc. ZL30416 Data Sheet AC Electrical Characteristics† - REFin (77.76 MHz) Input to OC-CLKo Output Timing Characteristics Sym. Min. Typ.‡ Max. Units 1 REFin(77.76 MHz) to OC-CLKo(19) delay tC77-19D 3.5 6.5 9.5 ns 2 REFin(77.76 MHz) to OC-CLKo(38) delay tC77-38D 3.2 6.2 9.2 ns 3 REFin(77.76 MHz) to OC-CLKo(77) delay tC77-77D 2.9 5.9 8.8 ns 4 REFin(77.76 MHz) to OC-CLKo(155) delay tC77-155D 2.6 5.6 8.6 ns 5 REFin(77.76 MHz) to OC-CLKo(622) delay tC77-622D 0 0.8 1.6 ns Notes † Supply voltage and operating temperature are as per Recommended Operating Conditions. ‡ Typical figures are for design aid only: not guaranteed and not subject to production testing. VT-LVPECL REFin (77.76 MHz) tC77-19D OC-CLKo(19) VT-LVPECL (19.44 MHz) tC77-38D OC-CLKo(38) VT-LVPECL (38.88 MHz) tC77-77D VT-LVPECL OC-CLKo(77) (77.76 MHz) tC77-155D OC-CLKo(155) (155.52 MHz) VT-LVPECL tC77-622D OC-CLKo(622) (622.08 MHz) VT-LVPECL Note: All output clocks have nominal 50% duty cycle. Figure 15 - REFin (77.76 MHz) Input to OC-CLKo Output Timing 17 Zarlink Semiconductor Inc. ZL30416 Data Sheet Performance Characteristics - Functional - (VCC = 3.3 V ±10%; TA = -40 to 85°C) Characteristics 1 Pull-in range 2 Lock Time Min. Typ. Max. ±1000 Units ppm 300 Notes At nominal input reference frequency C19i = 19.44 MHz ms Performance Characteristics: Output Jitter Generation - GR-253-CORE conformance (VCC = 3.3 V ±10%; TA = -40 to 85°C) ZL30416 Jitter Generation Performance GR-253-CORE Jitter Generation Requirements Interface (Category II) 1 OC-192 STS-192 Jitter Measurement Filter 4 MHz to 80 MHz 20 kHz to 80 MHz 2 3 OC-48 STS-48 12 kHz - 20 MHz OC-12 STS-12 12 kHz - 5 MHz Limit in UI 0.1 UIpp 0.3 UIpp Equivalent limit in time domain Typ.† Max.‡ 10.0 - 6.95 psP-P 0.49 0.89 psRMS - 11.5 psP-P 0.82 1.04 psRMS 30.1 Units 0.1 UIPP 40.2 - 7.32 psP-P 0.01 UIRMS 4.02 0.58 0.83 psRMS 0.1 UIPP 161 - 4.37 psP-P 0.01 UIRMS 16.1 0.34 0.60 psRMS † Typical figures are for design aid only: not guaranteed and not subject to production testing. ‡ Loop Filter components: RF=8.2 kΩ, CF=470 nF. 18 Zarlink Semiconductor Inc. ZL30416 Data Sheet Performance Characteristics: Output Jitter Generation - G.813 conformance (Option 1 and 2) (VCC = 3.3 V ±10%; TA = -40 to 85°C) ZL30416 Jitter Generation Performance G.813 Jitter Generation Requirements Interface Jitter Measurement Filter Limit in UI Equivalent limit in time domain Typ.† Max.‡ 10.0 - 6.95 psP-P 0.49 0.89 psRMS - 11.5 psP-P 0.82 1.04 psRMS - 6.40 psP-P 0.50 0.68 psRMS - 8.67 psP-P 0.68 1.06 psRMS - 3.33 psP-P 0.26 0.42 psRMS - 19.1 psP-P 1.51 2.88 psRMS - 6.95 psP-P 0.49 0.89 psRMS - 11.5 psP-P 0.82 1.04 psRMS - 7.32 psP-P 0.58 0.83 psRMS - 4.37 psP-P 0.34 0.60 psRMS Units Option 1 1 STM-64 4 MHz to 80 MHz 20 kHz to 80 MHz 2 STM-16 1 MHz to 20 MHz 5 kHz to 20 MHz 3 STM-4 250 kHz to 5 MHz 1 kHz to 5 MHz 0.1 UIpp 0.5 UIpp 50.2 0.1 UIpp 40.2 0.5 UIpp 201 0.1 UIpp 161 0.5 UIpp 804 Option 2 5 STM-64 4 MHz to 80 MHz 20 kHz to 80 MHz 6 7 STM-16 STM-4 12 kHz - 20 MHz 12 kHz - 5 MHz 0.1 UIpp 10.0 0.3 UIpp 30.1 0.1 UIpp 40.2 0.1 UIpp 161 † Typical figures are for design aid only: not guaranteed and not subject to production testing. ‡ Loop Filter components: RF=8.2 kΩ, CF=470 nF. 19 Zarlink Semiconductor Inc. ZL30416 Data Sheet Performance Characteristics: Output Jitter Generation - ETSI EN 300 462-7-1conformance (VCC = 3.3 V ±10%; TA = -40 to 85°C) ZL30416 Jitter Generation Performance EN 300 462-7-1 Jitter Generation Requirements Interface 1 STM-16 Jitter Measurement Filter 1 MHz to 20 MHz 5 kHz to 20 MHz 2 STM-4 250 kHz to 5 MHz 1 kHz to 5 MHz Limit in UI Equivalent limit in time domain Typ.† Max.‡ 40.2 - 6.40 psP-P 0.50 0.68 psRMS - 8.67 psP-P 0.68 1.06 psRMS - 3.33 psP-P 0.26 0.42 psRMS - 19.1 psP-P 1.51 2.88 psRMS 0.1 UIpp 0.5UIpp 201 0.1 UIpp 161 0.5 UIpp 804 † Typical figures are for design aid only: not guaranteed and not subject to production testing. ‡ Loop Filter components: RF=8.2 kΩ, CF=470 nF 20 Zarlink Semiconductor Inc. Units For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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