ZL38065
32 Channel Voice Echo Canceller
Data Sheet
Features
•
•
January 2006
Independent multiple channels of echo
cancellation; from 32 channels of 64 ms to 16
channels of 128 ms with the ability to mix
channels at 128 ms or 64 ms in any combination
Ordering Information
ZL38065QCG
ZL38065GDG
ZL38065QCG1
ZL38065GDG2
Fully compliant to ITU-T G.165, G.168 (2000) and
(2002) specifications
100
208
100
208
Pin LQFP
Ball LBGA
Pin LQFP*
Ball LBGA**
Trays,
Trays,
Trays,
Trays,
Bake
Bake
Bake
Bake
&
&
&
&
Drypack
Drypack
Drypack
Drypack
*Pb Free Matte Tin
**Pb Free Tin/Silver/Copper
-40°C to +85°C
•
Passed all AT&T voice quality tests for carrier
grade echo canceller systems.
•
Unparalleled in-system tunability
•
•
Sub 50 ms initial convergence times under many
typical network conditions
+9 dB to -12 dB level adjusters (3 dB steps) at all
signal ports
•
Offset nulling of all PCM channels
•
Fast reconvergence on echo path changes
•
•
Patented Advanced Non-Linear Processor with
high quality subjective performance
Independent Power Down mode for each group of
2 channels for power management
•
•
Superior noise matching algorithm
Compatible to ST-BUS and GCI interface at
2 Mbps serial PCM
•
PCM coding, µ/A-Law ITU-T G.711 or sign
magnitude
•
3.3 V pads and 1.8 V Logic core operation with
5 V tolerant inputs
•
Per channel Fax/Modem G.164 2100 Hz or G.165
2100 Hz phase reversal Tone Disable
•
IEEE-1149.1 (JTAG) Test Access Port
•
Per channel echo canceller parameters control
Applications
•
Transparent data transfer and mute
•
Voice over IP network gateways
•
Protection against narrow band signal divergence
and instability in high echo environments
•
Voice over ATM, Frame Relay
•
T1/E1/J1 multichannel echo cancellation
VDD1 (3.3V)
VDD2 (1.8 V)
VSS
ODE
Echo Canceller Pool
Rin
Sin
Serial
to
Parallel
MCLK
Fsel
PLL
C4i
F0i
Timing
Unit
Group 0
Group 1
Group 2
Group 3
ECA/ECB
ECA/ECB
ECA/ECB
ECA/ECB
Group 4
Group 5
Group 6
Group 7
ECA/ECB
ECA/ECB
ECA/ECB
ECA/ECB
Group 8
Group 9
Group 10
Group 11
ECA/ECB
ECA/ECB
ECA/ECB
ECA/ECB
Group 12
Group 13
Group 14
Group 15
ECA/ECB
ECA/ECB
ECA/ECB
ECA/ECB
Parallel
to
Serial
Note:
Refer to Figure 4
for Echo Canceller
block diagram
Rout
Sout
IC0
RESET
Microprocessor Interface
DS CS R/W A12-A0 DTA
Test Port
D7-D0
IRQ TMS TDI TDO TCK TRST
Figure 1 - ZL38065 Device Overview
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.
ZL38065
•
Wireless base stations
•
Echo Canceller pools
Data Sheet
Description
VSS
NC
NC
VDD1
NC
NC
NC
NC
VDD2
NC
fsel
NC
IC0
IC0
IC0
IC0
IC0
Mclk
NC
PLLVDD
76
PLLVSS2
77
PLLVSS1
78
VSS
79
NC
80
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
ZL38065QC
(100 pin LQFP)
VDD2 = 1.8 V
VDD1 = 3.3 V
NC
NC
VDD1
NC
NC
A9
NC
NC
A8
A12
VDD2
A10
A7
A11
VSS
A6
A5
A4
A3
A2
A1
49
50
A0
48
NC
47
VDD1
46
39
45
44
38
43
37
42
36
41
40
35
33
34
32
31
29
30
28
27
26
VSS
51
NC
81
NC
82
D7
83
D6
84
D5
85
D4
86
D3
87
VSS
88
D2
89
D1
90
D0
91
VDD2
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
DTA
8
R/W
7
CS
92
6
DS
93
5
TRSTB
IC0
94
4
VSS
RESETB
IRQB
95
3
TCK
96
2
TDO
97
1
TDI
98
100
TMS
99
VDD1
The ZL38065 Voice Echo Canceller implements a cost effective solution for telephony voice-band echo cancellation
conforming to ITU-T G.168 requirements. The ZL38065 architecture contains 16 groups of two echo cancellers
(ECA and ECB) which can be configured to provide two channels of 64 ms or one channel of 128 ms echo
cancellation. This provides 32 channels of 64 ms to 16 channels of 128 ms echo cancellation or any combination of
the two configurations. The ZL38065 supports ITU-T G.165 and G.164 tone disable requirements.
Figure 2 - 100 Pin LQFP
2
Zarlink Semiconductor Inc.
NC
NC
NC
IC0
IC0
IC0
VSS
IC0
IC0
IC0
IC0
VDD2
C4ib
Foib
Rin
Sin
Rout
Sout
ODE
VSS
NC
NC
NC
NC
NC
ZL38065
Data Sheet
Table of Contents
1.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1 Adaptive Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 Double-Talk Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3 Path Change Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4 Non-Linear Processor (NLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5 Disable Tone Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.6 Instability Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.7 Narrow Band Signal Detector (NBSD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.8 Offset Null Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.9 Adjustable Level Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.10 ITU-T G.168 Compliance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.0 Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 Normal Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 Back-to-Back Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 Extended Delay Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.0 Echo Canceller Functional States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Mute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 Disable Adaptation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Enable Adaptation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.0 ZL38065 Throughput Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.0 Serial PCM I/O channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 Serial Data Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.0 Memory Mapped Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Normal Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 Extended Delay Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3 Back-to-Back Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6 Call Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.0 JTAG Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3 Test Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3
Zarlink Semiconductor Inc.
ZL38065
Data Sheet
List of Figures
Figure 1 - ZL38065 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - 100 Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 3 - 208 Ball LBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5 - Sample G.168 Test 2A Convergence Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6 - Disable Tone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7 - Normal Device Configuration (64 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8 - Back-to-Back Device Configuration (64 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9 - Extended Delay Configuration (128 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10 - ST-BUS and GCI Interface Channel Assignment for 2 Mbps Data Streams . . . . . . . . . . . . . . . . . . . . 18
Figure 11 - Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12 - Power Up Sequence Flow Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13 - The MU Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 14 - ST-BUS Timing at 2.048 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 15 - GCI Interface Timing at 2.048 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 16 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 17 - Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 18 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4
Zarlink Semiconductor Inc.
ZL38065
Data Sheet
List of Tables
Table 1 - Quiet PCM Code Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2 - Memory Page Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3 - Group and Channel Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4 - Memory Mapping of Per Channel Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5
Zarlink Semiconductor Inc.
ZL38065
1
1
A
2
3
4
5
c4i
VDD1
6
Data Sheet
7
8
9
10
11
IC0
VSS
Sout
VDD1
IC0
VSS
VSS
IC0
VSS
B
IC0
VSS
IC0
VDD1
F0i
VSS
Rin
VSS
Rout
VDD1
Sin
C
IC0
IC0
VSS
VDD1
VSS
VDD2
VSS
VDD1
VSS
VDD1
D
NC
IC0
VDD1
VSS
VDD1
VDD2
VDD1
VSS
VDD1
VSS
E
NC
IC0
VSS
VSS
F
NC
NC
VDD1
VDD1
G
NC
MCLK
VSS
VSS
VSS
VSS
VSS
NC
Fsel
VDD1
VDD1
VSS
VSS
VDD2
VDD2
VSS
VSS
H
J
K
L
M
NC
IC0
NC
IC0 PLLVSS PLLVDD
1
14
15
16
VSS
NC
VSS
VSS
VSS
ODE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VSS
VDD1
VSS
VSS
VDD1
NC
A10
VDD1
VSS
A11
A9
VSS
VDD1
A12
A8
VSS
VDD2
VDD2
NC
A7
VSS
VSS
VSS
VSS
NC
A6
VSS
VSS
VSS
VDD1
VDD1
NC
A5
VSS
VSS
VSS
VSS
VSS
NC
A4
ZL38065GD
NC
VSS
VSS
VDD1
VDD1
NC
A3
TDI
TMS
VDD1
VDD1
VSS
VSS
VSS
A2
TDO
TRST
VSS
VSS
VSS
VDD1
VSS
VDD1
VSS
VDD1
VSS
VDD2
VSS
VDD1
VDD1
A1
TCK
VSS
VSS
VDD1
VSS
VDD1
VSS
VDD1
VSS
VDD1
VSS
VDD2
VSS
VSS
VDD1
A0
IC0
VSS
RESET
VDD1 R/W
VDD1
DTA
VDD1
IRQ
VDD1
DS
VDD1
CS
VSS
VSS
VSS
VSS
D0
VSS
D2
VSS
D3
D4
VSS
D5
VDD1
D6
VSS
D7
VSS
P
T
IC0
13
NC
N
R
12
D1
VDD1
- A1 corner is identified by metallized markings.
Figure 3 - 208 Ball LBGA
6
Zarlink Semiconductor Inc.
ZL38065
Data Sheet
Pin Description
Pin #
Pin
Name
208-Ball LBGA
Description
100 Pin
LQFP
VSS
A1, A3,A7,A11, A13,
5, 18, 32, Ground.
A15, A16, B2, B6, B8,
42, 56, 69,
B12, B14, B15, B16, C3, 81, 98
C5, C7, C9, C11, C12,
C13, C14, C16, D4, D8,
D10, D12, D13, E3, E4,
E14, F13, G3, G4, G7,
G8, G9, G10, H7, H8,
H9, H10, H13, H14, J7,
J8, J9, J10, K7, K8, K9,
K10, K13, K14, L3, L4,
M13, M14, M15, N3, N4,
N5, N7, N9, N11, N13,
P2, P3, P5, P7, P9.P11,
P13, P14, R2, R14,
R15, R16, T1, T3, T7,
T10, T14, T16
VDD1
A5, A9, B10, C4, C8,
27, 48, 77, Positive Power Supply. Nominally 3.3 V (I/O Voltage).
B4, C10, D3, D5, D7,
100
D9, D11, D14, E13, F3,
F4, F14, H3, H4, J13,
J14, L13, L14, M3, M4,
N6, N8, N10, N14, N15,
P4, P6, P8, P10, P15,
R4, R6, R8, R10, R12,
T5, T12
VDD2
C6, D6, J3, J4, N12,
P12, G13, G14
14, 37, 64, Positive Power Supply. Nominally 1.8 V (Core Voltage).
91
IC0
7, 65, 66, Internal Connection. These pins must be connected to VSS for
A12, A10, A6, A2, B1,
B3, C1, C2, D2, E2, J2, 67, 68, 70, normal operation.
71, 72, 86,
K2, R1
87, 88, 93,
94
NC
A14, C15, D1, D15, E1,
F1, G1, G15, H1, H15,
J1, J15, K1,
K15,L1,L15,F2,L2
24, 25, 26, No connection. These pins must be left open for normal
44, 45, 46, operation.
47, 49, 51,
52, 53, 54,
55, 73, 74,
75, 76, 78,
79, 80, 82,
83, 84, 85,
89, 99, 50
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Zarlink Semiconductor Inc.
ZL38065
Data Sheet
Pin Description (continued)
Pin #
Pin
Name
Description
100 Pin
LQFP
208-Ball LBGA
IRQ
R9
9
Interrupt Request (Open Drain Output). This output goes low
when an interrupt occurs in any channel. IRQ returns high when
all the interrupts have been read from the Interrupt FIFO
Register. A pull-up resistor (1 K typical) is required at this output.
DS
R11
10
Data Strobe (Input). This active low input works in conjunction
with CS to enable the read and write operations.
CS
R13
11
Chip Select (Input). This active low input is used by a
microprocessor to activate the microprocessor port.
R/W
R5
12
Read/Write (Input). This input controls the direction of the data
bus lines (D7-D0) during a microprocessor access.
DTA
R7
13
Data Transfer Acknowledgment (Open Drain Output). This
active low output indicates that a data bus transfer is completed.
A pull-up resistor (1 K typical) is required at this output.
D0..D7 T2,T4,T6,T8,T9,T11,
T13,T15
15, 16, 17, Data Bus D0 - D7 (Bidirectional). These pins form the 8 bit
19, 20, 21, bidirectional data bus of the microprocessor port.
22, 23
A0..A12 P16,N16,M16,L16,K16, 28, 29, 30, Address A0 to A12 (Input). These inputs provide the A12 - A0
J16,H16,G16,F16,E16, 31, 33, 34, address lines to the internal registers.
D16, E15, F15
35, 36, 38,
39, 40, 41,
43
ODE
B13
57
Output Drive Enable (Input). This input pin is logically AND’d
with the ODE bit-6 of the Main Control Register. When both ODE
bit and ODE input pin are high, the Rout and Sout ST-BUS
outputs are enabled.
When the ODE bit is low or the ODE input pin is low, the Rout
and Sout ST-BUS outputs are high impedance.
Sout
A8
58
Send PCM Signal Output (Output). Port 1 TDM data output
streams. Sout pin outputs serial TDM data streams at
2.048 Mbps with 32 channels per stream.
Rout
B9
59
Receive PCM Signal Output (Output). Port 2 TDM data output
streams. Rout pin outputs serial TDM data streams at
2.048 Mbps with 32 channels per stream.
Sin
B11
60
Send PCM Signal Input (Input). Port 2 TDM data input streams.
Sin pin receives serial TDM data streams at 2.048 Mbps with 32
channels per stream.
Rin
B7
61
Receive PCM Signal Input (Input). Port 1 TDM data input
streams. Rin pin receives serial TDM data streams at
2.048 Mbps with 32 channels per stream.
8
Zarlink Semiconductor Inc.
ZL38065
Data Sheet
Pin Description (continued)
Pin #
Pin
Name
Description
100 Pin
LQFP
208-Ball LBGA
F0i
B5
62
Frame Pulse (Input). This input accepts and automatically
identifies frame synchronization signals formatted according to
ST-BUS or GCI interface specifications.
C4i
A4
63
Serial Clock (Input). 4.096 MHz serial clock for shifting data
in/out on the serial streams (Rin, Sin, Rout, Sout).
MCLK
G2
90
Master Clock (Input). Nominal 10 MHz or 20 MHz Master Clock
input. May be connected to an asynchronous (relative to frame
signal) clock source.
Fsel
H2
92
Frequency select (Input). This input selects the Master Clock
frequency operation. When Fsel pin is low, nominal 19.2 MHz
Master Clock input must be applied. When Fsel pin is high,
nominal 9.6 MHz Master Clock input must be applied.
PLLVss1 K3
PLLVss2
97, 95
PLL Ground. Must be connected to VSS
PLLVDD K4
96
PLL Power Supply. Must be connected to VDD2 = 1.8 V
TMS
M2
1
Test Mode Select (3.3 V Input). JTAG signal that controls the
state transitions of the TAP controller. This pin is pulled high by
an internal pull-up when not driven.
TDI
M1
2
Test Serial Data In (3.3 V Input). JTAG serial test instructions
and data are shifted in on this pin. This pin is pulled high by an
internal pull-up when not driven.
TDO
N1
3
Test Serial Data Out (Output). JTAG serial data is output on this
pin on the falling edge of TCK. This pin is held in high impedance
state when JTAG scan is not enabled.
TCK
P1
4
Test Clock (3.3 V Input). Provides the clock to the JTAG test
logic.
TRST
N2
6
Test Reset (3.3 V Input). Asynchronously initializes the JTAG
TAP controller by putting it in the Test-Logic-Reset state. This pin
should be pulsed low on power-up or held low, to ensure that the
ZL38065 is in the normal functional mode. This pin is pulled by
an internal pull-down when not driven.
RESET R3
8
Device Reset (Schmitt Trigger Input). An active low resets the
device and puts the ZL38065 into a low-power stand-by mode.
When the RESET pin is returned to logic high and a clock is
applied to the MCLK pin, the device will automatically execute
initialization routines, which preset all the Main Control and
Status Registers to their default power-up values.
9
Zarlink Semiconductor Inc.
ZL38065
1.0
Data Sheet
Device Overview
The ZL38065 architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers,
Echo Canceller A and Echo Canceller B. Each group can be configured in Normal, Extended Delay or Back-toBack configurations. In Normal configuration, a group of echo cancellers provides two channels of 64 ms echo
cancellation, which run independently on different channels. In Extended Delay configuration, a group of echo
cancellers achieves 128 ms of echo cancellation by cascading the two echo cancellers (A & B). In Back-to-Back
configuration, the two echo cancellers from the same group are positioned to cancel echo coming from both
directions in a single channel, providing full-duplex 64 ms echo cancellation.
Each echo canceller contains the following main elements (see Figure 4).
•
Adaptive Filter for estimating the echo channel
•
Subtractor for cancelling the echo
•
Double-Talk detector for disabling the filter adaptation during periods of double-talk
•
Path Change detector for fast reconvergence on major echo path changes
•
Instability Detector to combat instability in very low ERL environments
•
Patented Advanced Non-Linear Processor for suppression of residual echo, with comfort noise injection
•
Disable Tone Detectors for detecting valid disable tones at send and receive path inputs
•
Narrow-Band Detector for preventing Adaptive Filter divergence from narrow-band signals
•
Offset Null filters for removing the DC component in PCM channels
•
+9 to -12 dB level adjusters at all signal ports
•
Parallel controller interface compatible with Motorola microcontrollers
•
PCM encoder/decoder compatible with µ/A-Law ITU-T G.711 or Sign-Magnitude coding
Each echo canceller in the ZL38065 has four functional states: Mute, Bypass, Disable Adaptation and Enable
Adaptation. These are explained in section 3.0, “Echo Canceller Functional States“.
µ/A-Law/
Linear
+9 to -12 dB
Level Adjust
Offset
Null
ST-BUS
PORT2
Adaptive
Filter
Disable Tone
Detector
Σ
Instability
Detector
Microprocessor
Interface
Double - Talk
Detector
Narrow-Band
Detector
Rout
(channel N)
Linear/
µ/A-Law
+9 to -12 dB
Level Adjust
Non-Linear
Processor
Control
Sin
(channel N)
MuteR
+9 to -12 dB
Level Adjust
+9 to -12 dB
Level Adjust
Path Change
Detector
ST-BUS
PORT1
Disable Tone
Detector
Offset
Null
Programmable Bypass
Figure 4 - Functional Block Diagram
Zarlink Semiconductor Inc.
Sout
(channel N)
MuteS
Echo Canceller (N), where 0 < N < 31
10
Linear/
µ/A-Law
µ/A-Law/
Linear
Rin
(channel N)
ZL38065
1.1
Data Sheet
Adaptive Filter
The adaptive filter adapts to the echo path and generates an estimate of the echo signal. This echo estimate is then
subtracted from Sin. For each group of echo cancellers, the adaptive filter is a 1024 tap FIR adaptive filter which is
divided into two sections. Each section contains 512 taps providing 64 ms of echo estimation. In Normal
configuration, the first section is dedicated to channel A and the second section to channel B. In Extended Delay
configuration, both sections are cascaded to provide 128 ms of echo estimation in channel A. In Back-to Back
configuration, the first section is used in the receive direction and the second section is used in the transmit
direction for the same channel.
The ZL38065 offers industry leading convergence speeds, both in initial convergence and reconvergence. A
sample test result from G.168-2002 Test 2A can be seen in Figure 5. This test result demonstrates one of the many
conditions where the Zarlink device offer sub 50 ms initial convergence times (G.168 Test 2A, Hybrid 5, 40 ms
delay, ERL=24dB, Lrin=0dBm0). Full G.168 test results across all hybrids and test conditions are available upon
request.
Figure 5 - Sample G.168 Test 2A Convergence Result
1.2
Double-Talk Detector
Double-Talk is defined as those periods of time when signal energy is present in both directions simultaneously.
When this happens, it is necessary to disable the filter adaptation to prevent divergence of the Adaptive Filter
coefficients. Note that when double-talk is detected, the adaptation process is halted but the echo canceller
continues to cancel echo using the previous converged echo profile. A double-talk condition exists whenever the
relative signal levels of Rin (Lrin) and Sin (Lsin) meet the following condition:
Lsin > Lrin + 20log10(DTDT)
where DTDT is the Double-Talk Detection Threshold. Lsin and Lrin are signal levels expressed in dBm0.
A different method is used when it is uncertain whether Sin consists of a low level double-talk signal or an echo
return. During these periods, the adaptation process is slowed down but it is not halted. The slow convergence
speed is set using the Slow sub-register in Control Register 4. During slow convergence, the adaptation speed is
11
Zarlink Semiconductor Inc.
ZL38065
Data Sheet
reduced by a factor of 2Slow relative to normal convergence for non-zero values of Slow. If Slow equals zero,
adaptation is halted completely.
In the G.168 standard, the echo return loss is expected to be at least 6 dB. This implies that the Double-Talk
Detector Threshold (DTDT) should be set to 0.5 (-6 dB). However, in order to achieve additional guardband, the
DTDT is set internally to 0.5625 (-5 dB).
In some applications the return loss can be higher or lower than 6 dB. The ZL38065 allows the user to change the
detection threshold to suit each application’s need. This threshold can be set by writing the desired threshold value
into the DTDT register.
The DTDT register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation:
DTDT(hex) = hex(DTDT(dec) * 32768)
where 0 < DTDT(dec) < 1
Example:For DTDT = 0.5625 (-5 dB), the
hexadecimal value becomes
hex(0.5625 * 32768) = 4800hex
1.3
Path Change Detector
Integrated into the ZL38065 is a Path Change Detector. This permits fast reconvergence when a major change
occurs in the echo channel. Subtle changes in the echo channel are also tracked automatically once convergence
is achieved, but at a much slower speed.
The Path Change Detector is activated by setting the PathDet bit in Control Register 3 to “1”. An optional path
clearing feature can be enabled by setting the PathClr bit in Control Register 3 to “1”. With path clearing turned on,
the existing echo channel estimate will also be cleared (i.e. the adaptive filter will be filled with zeroes) upon
detection of a major path change.
1.4
Non-Linear Processor (NLP)
After echo cancellation, there is always a small amount of residual echo which may still be audible. The ZL38065
uses Zarlink’s patented Advanced NLP to remove residual echo signals which have a level lower than the
Adaptive Suppression Threshold (TSUP in G.168). This threshold depends upon the level of the Rin (Lrin)
reference signal as well as the programmed value of the Non-Linear Processor Threshold register (NLPTHR).
TSUP can be calculated by the following equation:
TSUP = Lrin + 20log10(NLPTHR)
where NLPTHR is the Non-Linear Processor Threshold register value and Lrin is the relative power level expressed
in dBm0. The NLPTHR register is 16 bits wide. The register value in hexadecimal can be calculated with the
following equation:
NLPTHR(hex) = hex(NLPTHR(dec) * 32768)
where 0 < NLPTHR(dec) < 1
When the level of residual error signal falls below TSUP, the NLP is activated further attenuating the residual signal
by an additional 30 dB. To prevent a perceived decrease in background noise due to the activation of the NLP, a
spectrally-shaped comfort noise, equivalent in power level to the background noise, is injected. This keeps the
perceived noise level constant. Consequently, the user does not hear the activation and de-activation of the NLP.
The NLP processor can be disabled by setting the NLPDis bit to “1” in Control Register 2.
12
Zarlink Semiconductor Inc.
ZL38065
Data Sheet
The comfort noise injector can be disabled by setting the INJDis bit to “1” in Control Register 1. It should be noted
that the NLPTHR is valid and the comfort noise injection is active only when the NLP is enabled.
The Advanced NLP uses an exponential noise ramping scheme to quickly and more accurately estimate the
background noise level. A linear noise ramping method can also be used. The InjCtrl bit in Control Register 3
selects the ramping scheme.
The NLINC register is used to set the ramping speed. When InjCtrl = 1, a lower value will give faster ramping. The
Noise Scaling register can be used to adjust the relative volume of the comfort noise. Lowering this value will scale
the injected noise level down, conversely, raising the value will scale the comfort noise up.
IMPORTANT NOTE: The Noise Scaling register has been pre-programmed with G.168 compliant values. Changing
this value may result in undesirable comfort noise performance and G.168 test failures.
The Advanced NLP also contains safeguards to prevent double-talk and uncancelled echo from being mistaken for
background noise. These features can be disabled by setting the NLRun1 and NLRun2 bits in Control Register 3 to
“0”.
1.5
Disable Tone Detector
The G.165 recommendation defines the disable tone as having the following characteristics: 2100 Hz (±21 Hz) sine
wave, a power level between -6 to -31 dBm0, and a phase reversal of 180 degrees (±25 degrees) every
450 ms (±25 ms). If the disable tone is present for a minimum of one second with at least one phase reversal, the
Tone Detector will trigger.
The G.164 recommendation defines the disable tone as a 2100 Hz (+21 Hz) sine wave with a power level between
0 to -31 dBm0. If the disable tone is present for a minimum of 400 ms, with or without phase reversal, the Tone
Detector will trigger.
The ZL38065 has two Tone Detectors per channels (for a total of 64) in order to monitor the occurrence of a valid
disable tone on both Rin and Sin. Upon detection of a disable tone, TD bit of the Status Register will indicate logic
high and an interrupt is generated (i.e., IRQ pin low). Refer to Figure 6 and to the Interrupts section.
Rin
Tone
Detector
Sin
Tone
Detector
ECA
Status reg
TD bit
Echo Canceller A
Rin
Tone
Detector
Sin
Tone
Detector
ECB
Status reg
TD bit
Echo Canceller B
Figure 6 - Disable Tone Detection
Once a Tone Detector has been triggered, there is no longer a need for a valid disable tone (G.164 or G.165) to
maintain Tone Detector status (i.e., TD bit high). The Tone Detector status will only release (i.e., TD bit low) if the
signals Rin and Sin fall below -30 dBm0, in the frequency range of 390 Hz to 700 Hz, and below -34 dBm0, in the
frequency range of 700 Hz to 3400 Hz, for at least 400 ms. Whenever a Tone Detector releases, an interrupt is
generated (i.e., IRQ pin low).
The selection between G.165 and G.164 tone disable is controlled by the PHDis bit in Control Register 2 on a per
channel basis. When the PHDis bit is set to “1”, G.164 tone disable requirements are selected.
13
Zarlink Semiconductor Inc.
ZL38065
Data Sheet
In response to a valid disable tone, the echo canceller must be switched from the Enable Adaptation state to the
Bypass state. This can be done in two ways, automatically or externally. In automatic mode, the Tone Detectors
internally control the switching between Enable Adaptation and Bypass states. The automatic mode is activated by
setting the AutoTD bit in Control Register 2 to high. In external mode, an external controller is needed to service the
interrupts and poll the TD bits in the Status Registers. Following the detection of a disable tone (TD bit high) on a
given channel, the external controller must switch the echo canceller from Enable Adaptation to Bypass state.
1.6
Instability Detector
In systems with very low echo channel return loss (ERL), there may be enough feedback in the loop to cause
stability problems in the adaptive filter. This instability can result in variable pitched ringing or oscillation. Should this
ringing occur, the Instability Detector will activate and suppress the oscillations.
The Instability Detector is activated by setting the RingClr bit in Control Register 3 to “1”.
1.7
Narrow Band Signal Detector (NBSD)
Single or dual frequency tones (i.e., DTMF tones) present in the receive input (Rin) of the echo canceller for a
prolonged period of time may cause the Adaptive Filter to diverge. The Narrow Band Signal Detector (NBSD) is
designed to prevent this by detecting single or dual tones of arbitrary frequency, phase, and amplitude. When
narrow band signals are detected, adaptation is halted but the echo canceller continues to cancel echo.
The NBSD will be active regardless of the Echo Canceller functional state. However the NBSD can be disabled by
setting the NBDis bit to “1” in Control Register 2.
1.8
Offset Null Filter
Adaptive filters in general do not operate properly when a DC offset is present at any input. To remove the DC
component, the ZL38065 incorporates Offset Null filters in both Rin and Sin inputs.
The offset null filters can be disabled by setting the HPFDis bit to “1” in Control Register 2.
1.9
Adjustable Level Pads
The ZL38065 provides adjustable level pads at Rin, Rout, Sin and Sout. This setup allows signal strength to be
adjusted both inside and outside the echo path. Each signal level may be independently scaled with anywhere from
+9 dB to -12 dB level, in 3 dB steps. Level values are set using the Gains register.
CAUTION: Gain adjustment can help interface the ZL38065 to a particular system in order to provide optimum echo
cancellation, but it can also degrade performance if not done carefully. Excessive loss may cause low signal levels
and slow convergence. Exercise great care when adjusting these values. Also, due to internal signal routings in
Back to Back mode, it is not recommended that gain adjustments be used on Rin or Sout in this mode.
The -12 dB PAD bit in Control Register 1 is still supported as a legacy feature. Setting this bit will provide 12 dB of
attenuation at Rin, and override the values in the Gains register.
1.10
ITU-T G.168 Compliance
The ZL38065 has been certified G.168 (1997), (2000) and (2002) compliant in all 64 ms cancellation modes
(i.e., Normal and Back-to-Back configurations) by in-house testing with the DSPG ECT-1 echo canceller tester.
The ZL38065 has also been tested for G.168 compliance and all voice quality tests at AT&T Labs. The ZL38065
was classified as “carrier grade” echo canceller.
14
Zarlink Semiconductor Inc.
ZL38065
2.0
Data Sheet
Device Configuration
The ZL38065 architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers
which can be individually controlled (Echo Canceller A (ECA) and Echo Canceller B (ECB)). They can be set in
three distinct configurations: Normal, Back-to-Back, and Extended Delay. See Figures 7, 8 and 9.
2.1
Normal Configuration
In Normal configuration, the two echo cancellers (Echo Canceller A and B) are positioned in parallel, as shown in
Figure 7, providing 64 milliseconds of echo cancellation in two channels simultaneously.
Sin
channel A
Sout
+
-
echo
path A
Rout
Adaptive
Filter (64 ms)
channel A
Rin
PORT2
PORT1
ECA
channel B
+
-
echo
path B
Adaptive
Filter (64 ms)
channel B
ECB
Figure 7 - Normal Device Configuration (64 ms)
2.2
Back-to-Back Configuration
In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming
from both directions in a single channel providing full-duplex 64 ms echo cancellation. See Figure 8. This
configuration uses only one timeslot on PORT1 and PORT2 and the second timeslot normally associated with ECB
contains zero code. Back-to-Back configuration allows a no-glue interface for applications where bidirectional echo
cancellation is required.
Sout
+
Sin
echo
path
Adaptive
Filter (64 ms)
Adaptive
Filter (64 ms)
echo
path
Rout
PORT2
ECA
+
Rin
ECB
PORT1
Figure 8 - Back-to-Back Device Configuration (64 ms)
15
Zarlink Semiconductor Inc.
ZL38065
Data Sheet
Back-to-Back configuration is selected by writing a “1” into the BBM bit of Control Register 1 for both Echo
Canceller A and Echo Canceller B for a given group of echo canceller. Table 3 shows the 16 groups of 2 cancellers
that can be configured into Back-to-Back.
Examples of Back-to-Back configuration include positioning one group of echo cancellers between a codec and a
transmission device or between two codecs for echo control on analog trunks.
2.3
Extended Delay Configuration
In this configuration, the two echo cancellers from the same group are internally cascaded into one 128
milliseconds echo canceller. See Figure 9. This configuration uses only one timeslot on PORT1 and PORT2 and
the second timeslot normally associated with ECB contains quiet code.
Sin
channel A
+
Sout
echo
path A
Rout
PORT2
Adaptive Filter
(128 ms)
channel A
Rin
PORT1
ECA
Figure 9 - Extended Delay Configuration (128 ms)
Extended Delay configuration is selected by writing a “1” into the ExtDl bit in Echo Canceller A, Control Register 1.
For a given group, only Echo Canceller A, Control Register 1, has the ExtDl bit. For Echo Canceller B Control
Register 1, Bit 0 must always be set to zero.
Table 3 shows the 16 groups of 2 cancellers that can each be configured into 64 ms or 128 ms echo tail capacity.
3.0
Echo Canceller Functional States
Each echo canceller has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation.
3.1
Mute
In Normal and in Extended Delay configurations, writing a “1” into the MuteR bit replaces Rin with quiet code which
is applied to both the Adaptive Filter and Rout. Writing a “1” into the MuteS bit replaces the Sout PCM data with
quiet code.
LINEAR
SIGN/
16 bits
MAGNITUDE
2’s
µ-Law
complement
A-Law
+Zero
(quiet code)
0000hex
80hex
CCITT (G.711)
µ-Law
A-Law
FFhex
D5hex
Table 1 - Quiet PCM Code Assignment
In Back-to-Back configuration, writing a “1” into the MuteR bit of Echo Canceller A, Control Register 2, causes
quiet code to be transmitted on Rout. Writing a “1” into the MuteS bit of Echo Canceller A, Control Register 2,
causes quiet code to be transmitted on Sout.
16
Zarlink Semiconductor Inc.
ZL38065
Data Sheet
In Extended Delay and in Back-to-Back configurations, MuteR and MuteS bits of Echo Canceller B must always be
“0”. Refer to Figure 4 and to Control Register 2 for bit description.
3.2
Bypass
The Bypass state directly transfers PCM codes from Rin to Rout and from Sin to Sout. When Bypass state is
selected, the Adaptive Filter coefficients are reset to zero. Bypass state must be selected for at least one frame
(125 µs) in order to properly clear the filter.
3.3
Disable Adaptation
When the Disable Adaptation state is selected, the Adaptive Filter coefficients are frozen at their current value. The
adaptation process is halted, however, the echo canceller continues to cancel echo.
3.4
Enable Adaptation
In Enable Adaptation state, the Adaptive Filter coefficients are continually updated. This allows the echo canceller
to model the echo return path characteristics in order to cancel echo. This is the normal operating state.
The echo canceller functions are selected in Control Register 1 and Control Register 2 through four control bits:
MuteS, MuteR, Bypass and AdaptDis. Refer to the Registers Description for details.
4.0
ZL38065 Throughput Delay
The throughput delay of the ZL38065 varies according to the device configuration. For all device configurations, Rin
to Rout has a delay of two frames and Sin to Sout has a delay of three frames. In Bypass state, the Rin to Rout and
Sin to Sout paths have a delay of two frames.
5.0
Serial PCM I/O channels
There are two sets of TDM I/O streams, each with channels numbered from 0 to 31. One set of input streams is for
Receive (Rin) channels, and the other set of input streams is for Send (Sin) channels. Likewise, one set of output
streams is for Rout PCM channels, and the other set is for Sout channels. See Figure 10 for channel allocation.
The arrangement and connection of PCM channels to each echo canceller is a 2 port I/O configuration for each set
of PCM Send and Receive channels, as illustrated in Figure 4.
5.1
Serial Data Interface Timing
The ZL38065 provides ST-BUS and GCI interface timing. The Serial Interface clock frequency, C4i, is 4.096 MHz.
The input and output data rate of the ST-BUS and GCI bus is 2.048 Mbps.
The 8 KHz input frame pulse can be in either ST-BUS or GCI format. The ZL38065 automatically detects the
presence of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS format, every second falling
edge of the C4i clock marks a bit boundary, and the data is clocked in on the rising edge of C4i, three quarters of
the way into the bit cell (See Figure 14). In GCI format, every second rising edge of the C4i clock marks the bit
boundary, and data is clocked in on the second falling edge of C4i, half the way into the bit cell (see Figure 15).
17
Zarlink Semiconductor Inc.
ZL38065
Data Sheet
125 µsec
F0i
ST-BUS
F0i
GCI interface
Rin/Sin
Rout/Sout
Channel 0
Channel 1
Channel 30
Channel 31
Note: Refer to Figure 14 and Figure 15 for timing details.
Figure 10 - ST-BUS and GCI Interface Channel Assignment for 2 Mbps Data Streams
6.0
Memory Mapped Control and Status Registers
Internal memory and registers are memory mapped into the address space of the HOST interface. The internal dual
ported memory is mapped into segments on a “per channel” basis to monitor and control each individual echo
canceller and associated PCM channels. For example, in Normal configuration, echo canceller #5 makes use of
Echo Canceller B from group 2. It occupies the internal address space from 0A0hex to 0BFhex and interfaces to
PCM channel #5 on all serial PCM I/O streams.
Page
A12
A11
0
0
0
1
0
1
2
1
0
3
1
1
Table 2 - Memory Page Selection
As illustrated in Table 4, the “per channel” registers provide independent control and status bits for each echo
canceller. Figure 11 shows the memory map of the control/status register blocks for all echo cancellers.
Each internal echo canceller has four pages of registers. Page access control is done through address lines A11
and A12. The majority of registers are located on page 0 (A11=0, A12=0). Figure 11 shows which page each of the
relevant registers are mapped to respectively. Table 2 shows how the memory pages are related to address lines
A11 and A12.
When Extended Delay or Back-to-Back configuration is selected, Control Register 1 of ECA and ECB and Control
Register 2 of the selected group of echo cancellers require special care. Refer to the Register description section.
Table 3 is a list of the channels used for the 16 groups of echo cancellers when they are configured as Extended
Delay or Back-to-Back.
6.1
Normal Configuration
For a given group (group 0 to 15), 2 PCM I/O channels are used. For example, group 1 Echo Cancellers A and B,
channels 2 and 3 are active.
18
Zarlink Semiconductor Inc.
ZL38065
Data Sheet
Group
Channels
Group
Channels
0
0, 1
8
16, 17
1
2, 3
9
18, 19
2
4, 5
10
20, 21
3
6, 7
11
22, 23
4
8, 9
12
24, 25
5
10, 11
13
26, 27
6
12, 13
14
28, 29
7
14, 15
15
30, 31
Table 3 - Group and Channel Allocation
6.2
Extended Delay Configuration
For a given group (group 0 to 15), only one PCM I/O channel is active (Echo Canceller A) and the other channel
carries quiet code. For example, group 2, Echo Canceller A (Channel 4) will be active and Echo Canceller B
(Channel 5) will carry quiet code.
6.3
Back-to-Back Configuration
For a given group (group 0 to 15), only one PCM I/O channel is active (Echo Canceller A) and the other channel
carries quiet code. For example, group 5, Echo Canceller A (Channel 10) will be active and Echo Canceller B
(Channel 11) will carry quiet code.
Group 0
Echo
Cancellers
Registers
Channel 0, ECA Ctrl/Stat Registers
0000h --> 001Fh
Channel 1, ECB Ctrl/Stat Registers
0020h --> 003Fh
Group 1
Echo
Cancellers
Registers
Channel 2, ECA Ctrl/Stat Registers
0040h --> 005Fh
Channel 3, ECB Ctrl/Stat Registers
0060h --> 007Fh
Groups 2 --> 14
Echo Cancellers
Registers
Group 15
Echo
Cancellers
Registers
Channel 30, ECA Ctrl/Stat Registers
03C0h --> 03DFh
Channel 31, ECB Ctrl/Stat Registers
03E0h --> 03FFh
Main Control Registers
0400h --> 040Fh
Interrupt FIFO Register
0410h
Test Register
0411h
Reserved Test Register
0412h ---> FFFFh
Figure 11 - Memory Mapping
19
Zarlink Semiconductor Inc.
ZL38065
Base Address +
Echo Canceller A
Page
MS
Byte
LS
Byte
Register Name
0
-
00h
0
-
0
Data Sheet
Base Address +
Echo Canceller B
Page
MS
Byte
LS
Byte
Register Name
Control Reg 1
0
-
20h
Control Reg 1
01h
Control Reg 2
0
-
21h
Control Reg 2
-
02h
Status Reg
0
-
22h
Status Reg
0
-
04h
Flat Delay Reg
0
-
24h
Flat Delay Reg
0
-
06h
Decay Step Size Reg
0
-
26h
Decay Step Size Reg
0
-
07h
Decay Step Number
0
-
27h
Decay Step Number
0
-
08h
Control Reg 3
0
-
28h
Control Reg 3
0
-
09h
Control Reg 4
0
-
29h
Control Reg 4
0
0Dh
0Ch
Rin Peak Detect Reg
0
2Dh
2Ch
Rin Peak Detect Reg
0
0Fh
0Eh
Sin Peak Detect Reg
0
2Fh
2Eh
Sin Peak Detect Reg
0
11h
10h
Error Peak Detect Reg
0
31h
30h
Error Peak Detect Reg
0
-
12h
Path Change Timer
0
-
32h
Path Change Timer
0
-
13h
Path Change Sensitivity
0
-
33h
Path Change Sensitivity
0
15h
14h
DTDT/ERL
0
35h
34h
DTDT/ERL
0
17h
16h
ERLLOW
0
37h
36h
ERLLOW
0
19h
18h
NLP Threshold
0
39h
38h
NLP Threshold
0
1Bh
1Ah
Step Size, MU
0
3Bh
3Ah
Step Size, MU
0
1Dh
1Ch
Gain Pad Control
0
3Dh
3Ch
Gain Pad Control
0
-
1Eh
NLP Threshold 2
0
-
3Eh
NLP Threshold 2
0
-
1Fh
RIN Low Power Threshold
0
-
3Fh
RIN Low Power Threshold
1
05h
04h
Estimated Cancellation
1
25h
24h
Estimated Cancellation
1
07h
06h
Residual Error Signal
1
27h
26h
Residual Error Signal
2
11h
10h
NLINC
2
11h
10h
NLINC
2
19h
18h
Maximum Comfort Noise
2
39h
38h
Maximum Comfort Noise
2
1Bh
1Ah
NLP Ramp-out Speed
2
3Bh
3Ah
NLP Ramp-out Speed
2
1Dh
1Ch
NLP Ramp-in Speed
2
3Dh
3Ch
NLP Ramp-in Speed
3
03h
02h
Noise Level Estimate
3
23h
22h
Noise Level Estimate
3
05h
04h
NLP Gain Factor
3
25h
24h
NLP Gain Factor
3
0Dh
0Ch
Noise Level Scaling
Factor
3
2Dh
2Ch
Noise Level Scaling
Factor
Table 4 - Memory Mapping of Per Channel Control and Status Registers
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Zarlink Semiconductor Inc.
ZL38065
6.4
Data Sheet
Power Up Sequence
On power up, the RESET pin must be held low for 100 µs. Forcing the RESET pin low will put the ZL38065 in
power down state. In this state, all internal clocks are halted, D, Sout, Rout, DTA and IRQ pins are tristated.
The 16 Main Control Registers, the Interrupt FIFO Register and the Test Register are reset to zero.
When the RESET pin returns to logic high and a valid MCLK is applied, the user must wait 500 µs for the PLL to
lock. C4i and F0i can be active during this period. At this point, the echo canceller must have the internal registers
reset to an initial state. This is accomplished by one of two methods. The user can either issue a second hardware
reset or perform a software reset. A second hardware reset is performed by driving the RESET pin low for at least
500 ns and no more than 1500 ns before being released. A software reset is accomplished by programming a “1” to
each of the PWUP bits in the Main Control Registers, waiting 250 µs (2 frames) and then programming a “0” to
each of the PWUP bits.
The user must then wait 500 µs for the PLL to relock. Once the PLL has locked, the user can power up the 16
groups of echo cancellers individually by writing a “1” into the PWUP bit in Main Control Register of each echo
canceller group.
For each group of echo cancellers, when the PWUP bit toggles from zero to one, echo cancellers A and B execute
their initialization routine. The initialization routine sets their registers, Base Address+00hex to Base Address+3Fhex,
to the default Reset Value and clears the Adaptive Filter coefficients. Two frames are necessary for the initialization
routine to execute properly.
Once the initialization routine is executed, the user can set the per channel Control Registers, Base Address+00hex
to Base Address+3Fhex, for the specific application.
System Powerup
Reset Held Low
Delay 100 µs
Reset High
MCLK Active
Delay 500 µs
Hardware
Reg. Reset
Software
Reset Low
PWUP to “1”
Delay 1000 ns
Delay 250 µs
Reset High
PWUP to “0”
Delay 500 µs
ECAN Ready
Figure 12 - Power Up Sequence Flow Diagram
21
Zarlink Semiconductor Inc.
ZL38065
6.5
Data Sheet
Power Management
Each group of echo cancellers can be placed in Power Down mode by writing a “0” into the PWUP bit in their
respective Main Control Register. When a given group is in Power Down mode, the corresponding PCM data are
bypassed from Rin to Rout and from Sin to Sout with two frames delay. Refer to the Main Control Register section
on page 38 for description.
The typical power consumption can be calculated with the following equation:
PC = 9 * Nb_of_groups + 3.6, in mW
where 0 ≤ Nb_of_groups ≤ 16.
6.6
Call Initialization
To ensure fast initial convergence on a new call, it is important to clear the Adaptive Filter. This is done by putting
the echo canceller in bypass mode for at least one frame (125 µs) and then enabling adaptation.
Since the Narrow Band Detector is “ON” regardless of the functional state of Echo Canceller it is recommended that
the Echo cancellers are reset before any call progress tones are applied.
6.7
Interrupts
The ZL38065 provides an interrupt pin (IRQ) to indicate to the HOST processor when a G.164 or G.165 Tone
Disable is detected and released.
Although the ZL38065 may be configured to react automatically to tone disable status on any input PCM voice
channels, the user may want for the external HOST processor to respond to Tone Disable information in an
appropriate application-specific manner.
Each echo canceller will generate an interrupt when a Tone Disable occurs and will generate another interrupt
when a Tone Disable releases.
Upon receiving an IRQ, the HOST CPU should read the Interrupt FIFO Register. This register is a FIFO memory
containing the channel number of the echo canceller that has generated the interrupt.
All pending interrupts from any of the echo cancellers and their associated input channel number are stored in this
FIFO memory. The IRQ always returns high after a read access to the Interrupt FIFO Register. The IRQ pin will
toggle low for each pending interrupt.
After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel
Status Register can be read from internal memory to determine the cause of the interrupt (see Table 4 for address
mapping of Status register). The TD bit indicates the presence of a Tone Disable.
The MIRQ bit 5 in the Main Control Register 0 masks interrupts from the ZL38065. To provide more flexibility, the
MTDBI (bit-4) and MTDAI (bit-3) bits in the Main Control Register allow Tone Disable to be masked or
unmasked from generating an interrupt on a per channel basis. Refer to the Registers Description section on
page 38.
7.0
JTAG Support
The ZL38065 JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a
design-for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry is
controlled by an Test Access Port (TAP) controller. JTAG inputs are 3.3 V compliant only.
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Zarlink Semiconductor Inc.
ZL38065
7.1
Data Sheet
Test Access Port (TAP)
The TAP provides access to many test functions of the ZL38065. It consists of four input pins and one output pin.
The following pins are found on the TAP.
•
•
•
•
•
7.2
Test Clock Input (TCK)
The TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus
remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells
concurrent with the operation of the device and without interfering with the on-chip logic.
Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP Controller to control the test operations.
The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to VDD1 when it is
not driven from an external source.
Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register or into a test data register,
depending on the sequence previously applied to the TMS input. Both registers are described in a subsequent
section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to
VDD1 when it is not driven from an external source.
Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the contents of either the instruction register
or data register are serially shifted out towards the TDO. The data from the TDO is clocked on the falling edge
of the TCK pulses. When no data is shifted through the Boundary Scan cells, the TDO driver is set to a high
impedance state.
Test Reset (TRST)
This pin is used to reset the JTAG scan structure. This pin is internally pulled to VSS.
Instruction Register
In accordance with the IEEE 1149.1 standard, the ZL38065 uses public instructions. The JTAG Interface contains a
3-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP
Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to
select the test data register that will operate while the instruction is current, and to define the serial test data register
path, which is used to shift data between TDI and TDO during data register scanning.
7.3
Test Data Registers
As specified in IEEE 1149.1, the ZL38065 JTAG Interface contains three test data registers:
•
•
•
Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around
the boundary of the ZL38065 core logic.
Bypass Register
The Bypass register is a single stage shift register that provides a one-bit path from TDI to TDO.
Device Identification register
The Device Identification register provides access to the following encoded information:
device version number, part number and manufacturer's name.
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Zarlink Semiconductor Inc.
ZL38065
8.0
Data Sheet
Register Description
Page 0
Power-up
00hex
Bit 7
Reset
Reset
INJDis
ECA: Control Register 1
A12=0
A11=0
R/W Address:
00hex + Base Address
Bit 6
INJDis
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BBM
PAD
Bypass
AdpDis
0
ExtDis
Functional Description of Register Bits
When high, the power-up initialization is executed. This presets all register bits including this bit
and clears the Adaptive Filter coefficients.
When high, the noise injection process is disabled. When low noise injection is enabled.
BBM
When high, the Back to Back configuration is enabled. When low, the Normal configuration is
enabled. Note: Do not enable Extended-Delay and BBM configurations at the same time.
Always set both BBM bits of the two echo cancellers (Control Register 1) of the same group to
the same logic value to avoid conflict.
PAD
When high, 12 dB of attenuation is inserted into the Rin to Rout path. When low, the Gains
register controls the signal levels.
Bypass
AdpDis
0
ExtDl
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The Adaptive
Filter coefficients are set to zero and the filter adaptation is stopped. When low, output data on
both Sout and Rout is a function of the echo canceller algorithm.
When high, echo canceller adaptation is disabled. The Voice Processor cancels echo.
When low, the echo canceller dynamically adapts to the echo path characteristics.
Bits marked as “1” or “0” are reserved bits and should be written as indicated.
When high, Echo Cancellers A and B of the same group are internally cascaded into one
128 ms echo canceller. When low, Echo Cancellers A and B of the same group operate
independently.
Page 0
Power-up
02hex
Bit 7
Reset
Reset
INJDis
ECB: Control Register 1
A12=0
A11=0
R/W Address:
20hex + Base Address
Bit 6
INJDis
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BBM
PAD
Bypass
AdpDis
1
0
Functional Description of Register Bits
When high, the power-up initialization is executed which presets all register bits including this
bit and clears the Adaptive Filter coefficients.
When high, the noise injection process is disabled. When low, noise injection is enabled.
BBM
When high, the Back to Back configuration is enabled. When low, the Normal configuration is
enabled. Note: Do not enable Extended-Delay and BBM configurations at the same time.
Always set both BBM bits of the two echo cancellers (Control Register 1) of the same group to
the same logic value to avoid conflict.
PAD
When high, 12 dB of attenuation is inserted into the Rin to Rout path. When low, the Gains
register controls the signal levels.
Bypass
AdpDis
1
0
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The Adaptive
Filter coefficients are set to zero and the filter adaptation is stopped. When low, output data on
both Sout and Rout is a function of the echo canceller algorithm.
When high, echo canceller adaptation is disabled. The Voice Processor cancels echo.
When low, the echo canceller dynamically adapts to the echo path characteristics.
Bits marked as “1” or “0” are reserved bits and should be written as indicated.
Control Register 1 (Echo Canceller B) Bit 0 is a reserved bit and should be written “0”.
24
Zarlink Semiconductor Inc.
ZL38065
Power-up
00hex
Bit 7
TDis
TDis
PHDis
Data Sheet
ECA: Control Register 2
Page 0
R/W Address:
01hex + Base Address
ECB: Control Register 2
A12=0
A11=0
R/W Address:
21hex + Base Address
Bit 6
PHDis
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NLPDis
AutoTD
NBDis
HPFDis
MuteS
MuteR
Functional Description of Register Bits
When high, tone detection is disabled. When low, tone detection is enabled. When both Echo
Cancellers A and B TDis bits are high, Tone Disable processors are disabled entirely and are
put into Power Down mode.
When high, the tone detectors will trigger upon the presence of a 2100 Hz tone regardless of
the presence/absence of periodic phase reversals. When low, the tone detectors will trigger
only upon the presence of a 2100 Hz tone with periodic phase reversals.
NLPDis
When high, the non-linear processor is disabled. When low, the non-linear processors function
normally. Useful for G.165 conformance testing.
AutoTD
When high, the echo canceller puts itself in Bypass mode when the tone detectors detect the
presence of 2100 Hz tone. See PHDis for qualification of 2100 Hz tones.
When low, the echo canceller algorithm will remain operational regardless of the state of the
2100 Hz tone detectors.
NBDis
When high, the narrow-band detector is disabled. When low, the narrow-band detector is
enabled.
When high, the offset nulling high pass filters are bypassed in the Rin and Sin paths. When low,
the offset nulling filters are active and will remove DC offsets on PCM input signals.
When high, data on Sout is muted to quiet code. When low, Sout carries active code.
When high, data on Rout is muted to quiet code. When low, Rout carries active code.
HPFDis
MuteS
MuteR
Note: In order to correctly write to Control Register 1 and 2 of ECB, it is necessary to write the data twice to the register, one
immediately after another. The two writes must be separated by at least 350 ns and no more than 20 us.
Power-up
N/A
Bit 7
Reserved
Reserved
TD
DTDet
Bit 6
TD
ECA: Status Register
Page 0
Read Address:
02hex + Base Address
ECB: Status Register
A12=0
A11=0
Read Address:
22hex + Base Address
Bit 5
Bit 4
Bit 3
Bit 2
DTDet
Reserved
Reserved
ACTIVE
Functional Description of Register Bits
Bit 1
TDG
Bit 0
NB
Reserved bit.
Logic high indicates the presence of a 2100 Hz tone.
Logic high indicates the presence of a double-talk condition.
Reserved
Reserved bit.
Reserved
ACTIVE
TDG
Reserved bit.
Logic high indicates that the level on Rin has exceeded the LP threshold.
Tone detection status bit gated with the AutoTD bit. (Control Register 2)
Logic high indicates that AutoTD has been enabled and the tone detector has detected the
presence of a 2100 Hz tone.
Logic high indicates the presence of a narrow-band signal on Rin.
NB
25
Zarlink Semiconductor Inc.
ZL38065
Power-up
00hex
Bit 7
FD7
Bit 7
SS7
Page 0
R/W Address:
04hex + Base Address
ECB: Flat Delay Register (FD)
A12=0
A11=0
R/W Address:
24hex + Base Address
Bit 5
FD5
Bit 4
FD4
Bit 3
FD3
Bit 2
FD2
Bit 1
FD1
Bit 0
FD0
ECA: Decay Step Number Register (NS))
Page 0
R/W Address:
07hex + Base Address
ECB: Decay Step Number Register (NS)
A12=0
A11=0
R/W Address:
27hex + Base Address
Bit 6
SS6
Power-up
04hex
Bit 7
0
ECA: Flat Delay Register (FD)
Bit 6
FD6
Power-up
00hex
Data Sheet
Bit 5
SS5
Bit 4
SS4
Bit 3
SS3
Bit 2
SS2
Bit 1
SS1
Bit 0
SS0
ECA: Decay Step Size Control Register (SSC)
Page 0
R/W Address:
06hex + Base Address
ECB: Decay Step Size Control Register (SSC)
A12=0
A11=0
R/W Address:
26hex + Base Address
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
SSC2
Bit 1
SSC1
Bit 0
SSC0
Amplitude of MU
FIR Filter Length (512 or 1024 taps)
1.0
Step Size (SS)
Flat Delay (FD7-0)
2-16
Time
Number of Steps (NS7-0)
Figure 13 - The MU Profile
26
Zarlink Semiconductor Inc.
ZL38065
Data Sheet
Functional Description of Register Bits
The Exponential Decay registers (Decay Step Number and Decay Step Size) and Flat Delay register allow the LMS
adaptation step-size (MU) to be programmed over the length of the FIR filter. A programmable MU profile allows the
performance of the echo canceller to be optimized for specific applications. For example, if the characteristic of the
echo response is known to have a flat delay of several milliseconds and a roughly exponential decay of the echo
impulse response, then the MU profile can be programmed to approximate this expected impulse response thereby
improving the convergence characteristics of the Adaptive Filter. Note that in the following register descriptions, one
tap is equivalent to 125 µs (64 ms/512 taps).
FD7-0
Flat Delay: This register defines the flat delay of the MU profile, (i.e., where the MU value is 2-16). The
delay is defined as FD7-0 x 8 taps. For example; If FD7-0 = 5, then MU=2-16 for the first 40 taps of the
echo canceller FIR filter. The valid range of FD7-0 is: 0 ≤ FD7-0 ≤ 64 in normal mode and 0 ≤ FD7-0 ≤
128 in extended-delay mode. The default value of FD7-0 is zero.
SSC2-0 Decay Step Size Control: This register controls the step size (SS) to be used during the exponential decay
of MU. The decay rate is defined as a decrease of MU by a factor of 2 every SS taps of the FIR filter,
where SS = 4 x2SSC2-0. For example; If SSC2-0 = 4, then MU is reduced by a factor of 2 every 64 taps of
the FIR filter. The default value of SSC2-0 is 04hex.
NS7-0
Decay Step Number: This register defines the number of steps to be used for the decay of MU where each
step has a period of SS taps (see SSC2-0). The start of the exponential decay is defined as: Filter
Length (512 or 1024) - [Decay Step Number (NS7-0) x Step Size (SS)] where SS = 4 x2SSC2-0.
For example; If NS7-0=4 and SSC2-0=4, then the exponential decay start value is 512 - [NS7-0 x SS] =
512 - [4 x (4x24)] = 256 taps for a filter length of 512 taps.
Power-up
DBhex
Bit 7
NLRun2
Reserved
Reserved
NLRun1
Bit 6
InjCtrl
ECA: Control Register 3
Page 0
R/W Address:
08hex + Base Address
ECB: Control Register 3
A12=0
A11=0
R/W Address:
28hex + Base Address
Bit 5
Bit 4
Bit 3
Bit 2
NLRun1
RingClr
Reserve
PathClr
Functional Description of Register Bits
Bit 1
PathDet
Bit 0
NMatcj
Reserved bit.
Reserved bit.
When high, the comfort noise level estimator actively rejects uncancelled echo as being
background noise. When low, the noise level estimator makes no such distinction.
RingClr
When high, the instability detector is activated. When low, the instability detector is disabled.
Reserve
PathClr
Reserved bit. Must always be set to one for normal operation.
When high, the current echo channel estimate will be cleared and the echo canceller will enter
fast convergence mode upon detection of a path change. When low, the echo canceller will
keep the current path estimate but revert to fast convergence mode upon detection of a path
change. Note: this bit is ignored if PathDet is low.
When high, the path change detector is activated. When low, the path change detector is
disabled.
Reserved bit.
PathDet
Reserved
27
Zarlink Semiconductor Inc.
ZL38065
Power-up
54hex
Bit 7
0
0
SupDec
0
Slow
Page 0
R/W Address:
09hex + Base Address
ECB: Control Register 4
A12=0
A11=0
R/W Address:
29hex + Base Address
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SD1
SD0
0
Slow2
Slow1
Slow0
Functional Description of Register Bits
Must be set to zero.
These three bits (SD2,SD1,SD0) control how long the echo canceller remains in a fast
convergence state following a path change, Reset or Bypass operation. A value of zero will
keep the echo canceller in fast convergence indefinitely.
Must be set to zero.
Slow convergence mode speed adjustment.(Bits Slow2, Slow1,Slow0)
For Slow = 1, 2, ..., 7, slow convergence speed is reduced by a factor of 2Slow as compared to
normal adaptation.
For Slow = 0, no adaptation occurs during slow convergence.
Bit 6
RP14
Power-up
N/A
Bit 7
RP7
ECA: Control Register 4
Bit 6
SD2
Power-up
N/A
Bit 7
RP15
Data Sheet
ECA: Rin Peak Detect Register 2 (RP)
Page 0
Read Address:
0Dhex + Base Address
ECB: Rin Peak Detect Register 2 (RP)
A12=0
A11=0
Read Address:
2Dhex + Base Address
Bit 5
RP13
Bit 4
RP12
Bit 3
RP11
Bit 2
RP10
Bit 1
RP9
Bit 0
RP8
ECA: Rin Peak Detect Register 1 (RP)
Page 0
Read Address:
0Chex + Base Address
ECB: Rin Peak Detect Register 1 (RP)
A12=0
A11=0
Read Address:
2Chex + Base Address
Bit 6
RP6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RP5
RP4
RP3
RP2
RP1
RP0
Functional Description of Register Bits
These peak detector registers allow the user to monitor the receive in (Rin) peak signal level. The
information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo
canceller. The high byte is in Register 2 and the low byte is in Register 1.
28
Zarlink Semiconductor Inc.
ZL38065
Power-up
N/A
Bit 7
SP15
Bit 6
SP14
Bit 7
SP7
ECA: Sin Peak Detect Register 2 (SP)
Page 0
Read Address:
0Fhex + Base Address
ECB: Sin Peak Detect Register 2 (SP)
A12=0
A11=0
Read Address:
2Fhex + Base Address
Bit 5
SP13
Power-up
N/A
Data Sheet
Bit 4
SP12
Bit 3
SP11
Bit 2
SP10
Bit 1
SP9
Bit 0
SP8
ECA: Sin Peak Detect Register 1 (SP)
Page 0
R/W Address:
0Ehex + Base Address
ECB: Sin Peak Detect Register 1 (SP)
A12=0
A11=0
R/W Address:
2Ehex + Base Address
Bit 6
SP6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SP5
SP4
SP3
SP2
SP1
SP0
Functional Description of Register Bits
These peak detector registers allow the user to monitor the send in (Sin) peak signal level. The information
is in 16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The
high byte is in Register 2 and the low byte is in Register 1.
Power-up
N/A
Bit 7
EP15
Page 0
Read Address:
11hex + Base Address
ECB: Error Peak Detect Register 2 (EP))
A12=0
A11=0
Read Address:
21hex + Base Address
Bit 6
EP14
Power-up
N/A
Bit 7
EP7
ECA: Error Peak Detect Register 2 (EP)
Bit 5
EP13
Bit 4
EP12
Bit 3
EP11
Bit 2
EP10
Bit 1
EP9
Bit 0
EP8
ECA: Error Peak Detect Register 1 (EP)
Page 0
Read Address:
10hex + Base Address
ECB: Error Peak Detect Register 1 (EP)
A12=0
A11=0
Read Address:
30hex + Base Address
Bit 6
EP6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EP5
EP4
EP3
EP2
EP1
EP0
Functional Description of Register Bits
These peak detector registers allow the user to monitor the error signal peak level. The information is in 16
bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller.
Power-up
10hex
Bit 7
PTMR7
ECA: Path Change Timer (PATHTMR)
Page 0
R/W Address:
12hex + Base Address
ECB: Path Change Timer (PATHTMR)
A12=0
A11=0
R/W Address:
32hex + Base Address
Bit 6
PTMR6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PTMR5
PTMR4
PTMR3
PTMR2
PTMR1
PTMR0
Functional Description of Register Bits
Negative ERLE time required to declare a path change. Raising this value decreases the path change
sensitivity.
29
Zarlink Semiconductor Inc.
ZL38065
Power-up
41hex
Bit 7
PSENS7
Data Sheet
ECA: Path Change Sensitivity (PTHSENS)
Page 0
R/W Address:
13hex + Base Address
ECB: Path Change Sensitivity (PTHSENS)
A12=0
A11=0
R/W Address:
33hex + Base Address
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PSENS5
PSENS4
PSENS3
PSENS2
PSENS1
PSENS0
Functional Description of Register Bits
This register sets the negative ERLE sensitivity value. Raising this value decreases path change sensitivity.
Power-up
48hex
Bit 7
DTDT15
Power-up
00hex
Bit 7
DTDT7
Bit 6
PSENS6
ECA: Double-Talk Detection Threshold Register 2
(DTDT or ERL)
Page 0
R/W Address:
15hex + Base Address
ECB: Double-Talk Detection Threshold Register 2
(DTDT or ERL)
A12=0
A11=0
R/W Address:
35hex + Base Address
Bit 6
DTDT14
Bit 5
DTDT13
Bit 4
DTDT12
Bit 3
DTDT11
Bit 2
DTDT10
Bit 1
DTDT9
Bit 0
DTDT8
ECA: Double-Talk Detection Threshold Register 1
(DTDT or ERL)
Page 0
R/W Address:
14hex + Base Address
ECB: Double-Talk Detection Threshold Register 1
(DTDT or ERL)
A12=0
A11=0
R/W Address:
34hex + Base Address
Bit 6
DTDT6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DTDT5
DTDT4
DTDT3
DTDT2
DTDT1
DTDT0
Functional Description of Register Bits
This register should reflect the minimum return echo level (SIN) relative to ROUT expected in the system.
The default value of 4800hex= 0.5625 represents a path loss of -5 dB. This value sets the high-level doubletalk detection threshold (DTDT). The information is in 16 bit 2’s complement linear coded format presented
in two 8 bit registers for each echo canceller. The maximum value is 7FFFhex = 0.9999 or 0 dB.
Power-up
04hex
Bit 7
ERLW15
Bit 6
ERLW14
Power-up
00hex
Bit 7
ERLW7
ECA: SUP Lower Limit 2 (ERLLOW)
Page 0
R/W Address:
17hex + Base Address
ECB: SUP Lower Limit 2 (ERLLOW)
A12=0
A11=0
R/W Address:
37hex + Base Address
Bit 5
ERLW13
Bit 4
ERLW12
Bit 3
ERLW11
Bit 2
ERLW10
Bit 1
ERLW9
Bit 0
ERLW8
ECA: SUP Lower Limit 1 (ERLLOW)
Page 0
R/W Address:
16hex + Base Address
ECB: SUP Lower Limit 1 (ERLLOW)
A12=0
A11=0
R/W Address:
36hex + Base Address
Bit 6
ERLW6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ERLW5
ERLW4
ERLW3
ERLW2
ERLW1
ERLW0
Functional Description of Register Bits
This register sets the lower limit on SUP, which marks the region below which fast convergence always
occurs (provided a signal is present). If ERLLOW is set to the DTDT starting value (4800hex), the echo
canceller will remain in fast convergence mode and will not switch to slow convergence. The information is
in 16 bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller.
30
Zarlink Semiconductor Inc.
ZL38065
Power-up
0Chex
Bit 7
NLP15
Power-up
E0hex
Data Sheet
ECA: Non-Linear Processor Threshold Register 2
(NLPTHR)
Page 0
R/W Address:
19hex + Base Address
ECB: Non-Linear Processor Threshold Register 2
(NLPTHR)
A12=0
A11=0
R/W Address:
39hex + Base Address
Bit 6
NLP14
Bit 5
NLP13
Bit 4
NLP12
Bit 3
NLP11
ECA: Non-Linear Processor Threshold Register 1
(NLPTHR)
Bit 2
NLP10
Page 0
Bit 1
NLP9
Bit 0
NLP8
R/W Address:
18hex + Base Address
A12=0
R/W Address:
ECB: Non-Linear Processor Threshold Register 1
A11=0
38hex + Base Address
(NLPTHR)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NLP7
NLP6
NLP5
NLP4
NLP3
NLP2
NLP1
NLP0
Functional Description of Register Bits
This register allows the user to program the level of the Non-Linear Processor Threshold (NLPTHR). The 16
bit 2’s complement linear value defaults to 0CE0hex = 0.1 or -20.0 dB. The maximum value is 7FFFhex =
0.9999 or 0 dB.
Power-up
40hex
Bit 7
MU15
Power-up
00hex
Bit 7
MU7
ECA: Adaptation Step Size Register 2 (MU)
Page 0
R/W Address:
1Bhex + Base Address
ECB: Adaptation Step Size Register 2 (MU)
A12=0
A11=0
R/W Address:
3Bhex + Base Address
Bit 6
MU14
Bit 5
MU13
Bit 4
MU12
Bit 3
MU11
Bit 2
MU10
Bit 1
MU9
Bit 0
MU8
ECA: Adaptation Step Size Register 1 (MU)
Page 0
R/W Address:
1Ahex + Base Address
ECB: Adaptation Step Size Register 1 (MU)
A12=0
A11=0
R/W Address:
3Ahex + Base Address
Bit 6
MU6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MU5
MU4
MU3
MU2
MU1
MU0
Functional Description of Register Bits
This register allows the user to program the level of MU, which is the LMS filter step size. Increasing this
value can speed up convergence times, but can also potentially decrease VEC stability. MU is a 16 bit 2’s
complement value which defaults to 4000hex = 1.0 The maximum value is 7FFFhex or 1.9999 decimal. The
high byte is in Register 2 and the low byte is in Register 1.
31
Zarlink Semiconductor Inc.
ZL38065
Power-up
40hex
Bit 7
0
Bit 6
Rin2
Power-up
00hex
Bit 7
0
Data Sheet
ECA: Gains Register 2
Page 0
R/W Address:
1Dhex + Base Address
ECB: Gains Register 2
A12=0
A11=0
R/W Address:
3Dhex + Base Address
Bit 5
Rin1
Bit 4
Rin0
Bit 3
0
Bit 2
Rout2
Bit 1
Rout1
Bit 0
Rout0
ECA: Gains Register1
Page 0
R/W Address:
1Chex + Base Address
ECB: Gains Register 1
A12=0
A11=0
R/W Address:
3Chex + Base Address
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sin1
Sin0
0
Sout2
Sout1
Sout0
Functional Description of Register Bits
This register is used to select gain values on RIN, ROUT, SIN and SOUT.
Gains is split into four groups of four bits. Each group maps to a different signal port (as indicated above),
and has three gain bits. The following table indicates how these gain bits are used:
Bit2
1
1
1
1
0
0
0
0
Bit 6
Sin2
Bit1 Bit0
1 1
1 0
0 1
0 0
1 1
1 0
0 1
0 0
Gain Level
+9 dB
+6 dB)
+3 dB
0 dB (default)
-3 dB
-6 dB
-9 dB
-12 dB
Note that the -12 dB PAD bit in Control Register 1 provides 12 dB of attenuation in the Rin to Rout path, and
will override the settings in Gains.
Power-up
08hex
Bit 7
NLPTH7
ECA: NLP Threshold 2 (NLPTHR2)
Page 0
R/W Address:
1Ehex + Base Address
ECB: NLP Threshold 2 (NLPTHR2)
A12=0
A11=0
R/W Address:
3Ehex + Base Address
Bit 6
NLPTH6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NLPTH5
NLPTH4
NLPTH3
NLPTH2
NLPTH1
NLPTH0
Functional Description of Register Bits
This register is used to force the NLP off when very small signals exist on RIN. NLP is forced off if RIN is
below NLPTHR2
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