ZL40221
Precision 2:6 LVDS Fanout Buffer with Glitchfree Input Reference Switching
and On-Chip Input Termination
Data Sheet
November 2012
Features
Ordering Information
ZL40221LDG1
ZL40221LDF1
Inputs/Outputs
•
Accepts two differential or single-ended inputs
• LVPECL, LVDS, CML, HCSL, LVCMOS
•
•
32 Pin QFN
32 Pin QFN
Trays
Tape and Reel
Matte Tin
Package size: 5 x 5 mm
-40oC to +85oC
Glitch-free switching of references
On-chip input termination and biasing for AC
coupled inputs
Applications
•
Six precision LVDS outputs
•
General purpose clock distribution
•
Operating frequency up to 750 MHz
•
Low jitter clock trees
•
Logic translation
•
Clock and data signal restoration
•
Redundant clock distribution
•
Wired communications: OTN, SONET/SDH, GE,
10 GE, FC and 10G FC
•
Wireless communications
•
High performance micro-processor clock
distribution
Power
•
Option for 2.5 V or 3.3 V power supply
•
Current consumption of 97 mA
•
On-chip Low Drop Out (LDO) Regulator for superior
power supply rejection
Performance
Ultra low additive jitter of 165 fs RMS
ctrl0
vt0
out1_p
out1_n
clk0_p
clk0_n
clk1_p
clk1_n
ctrl1
vt1
out0_p
out0_n
Termination
and Bias
Control
•
out2_p
out2_n
Buffer
out3_p
out3_n
Termination
and Bias
out4_p
out4_n
out5_p
out5_n
sel
Figure 1 - Functional Block Diagram
1
Microsemi Corporation
Copyright 2012, Microsemi Corporation. All Rights Reserved.
ZL40221
Data Sheet
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.0 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.1 Clock Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.2 Clock Input Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Device Additive Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.1 Sensitivity to power supply noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.2 Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.3 PCB layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.0 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.0 Performance Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.0 Typical Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.0 Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.0 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2
Microsemi Corporation
ZL40221
Data Sheet
List of Figures
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3 - Simplified Diagram of input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4 - Output During Clock Switch - Both Clocks Running . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5 - Clock Input - LVPECL - DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6 - Clock Input - LVPECL - AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7 - Clock Input - LVDS - DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8 - Clock Input - LVDS - AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9 - Clock Input - CML- AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10 - Clock Input - HCSL- AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 11 - Clock Input - AC-coupled Single-Ended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12 - Clock Input - DC-coupled 3.3V CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 13 - Simplified LVDS Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 14 - LVDS DC Coupled Termination (Internal Receiver Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 15 - LVDS DC Coupled Termination (External Receiver Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 16 - LVDS AC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 17 - LVDS AC Output Termination for CML Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 18 - Additive Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 19 - Decoupling Connections for Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 20 - Differential Voltage Parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 21 - Input To Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3
Microsemi Corporation
ZL40221
1.0
Data Sheet
Package Description
24
22
20
gnd
vdd
out3_n
out3_p
out2_n
out2_p
vdd
gnd
The device is packaged in a 32 pin QFN
18
16
vdd
out1_n
out4_p
26
out1_p
out0_n
14
12
gnd (E-pad)
10
32
NC
gnd
clk1_n
8
ctrl1
vt1
clk1_p
6
clk0_n
4
ctrl0
vt0
2
clk0_p
out5_n
vdd
30
sel
gnd
out4_n
out5_p
28
out0_p
vdd
vdd
Figure 2 - Pin Connections
4
Microsemi Corporation
ZL40221
2.0
Data Sheet
Pin Description
Pin #
1, 4,
5, 8
Name
Description
clk0_p, clk0_n, Differential Input (Analog Input). Differential (or singled ended) input signals. For all
clk1_p, clk1_n input signal configuration see Section 3.1, “Clock Inputs“.
2, 6
vt0, vt1
On-Chip Input Termination Node (Analog). Center tap between internal 50 Ohm
termination resistors.
For a DC coupled LVPECL input connect this pin through a resistor to ground; 50 Ohms
for 3.3V LVPECL or 20 Ohms for 2.5V LVPECL.
For a DC coupled LVDS input or for an AC coupled differential input, leave this pin
unconnected.
3, 7
ctrl0, ctrl1
Digital Control for On-Chip Input Termination (Input). Selects differential input mode;
0: DC coupled LVPECL or LVDS modes
1: AC coupled differential modes
These pins are internally pulled down to GND.
29, 28,
27, 26,
22, 21,
20, 19,
15, 14,
13, 12
out0_p, out0_n Differential Output (Analog Output). Differential outputs.
out1_p, out1_n
out2_p, out2_n
out3_p, out3_n
out4_p, out4_n
out5_p, out5_n
11, 16,
18, 23,
25, 30
vdd
Positive Supply Voltage. 2.5VDC or 3.3 VDC nominal.
9, 17,
24, 32
gnd
Ground. 0 V.
31
sel
Input Select (Input). Selects the reference input that is buffered;
0: clk0
1: clk1
This pin is internally pulled down to GND.
10
NC
No Connection. Leave unconnected.
5
Microsemi Corporation
ZL40221
3.0
Data Sheet
Functional Description
he ZL40221 is an LVDS clock fanout buffer with six output clock drivers capable of operating at frequencies up to
750MHz.
The ZL40221 provides an internal input termination network for DC and AC coupled inputs; optional input biasing
for AC coupled inputs is also provided. The ZL40221 can accept DC or AC coupled LVPECL and LVDS input
signals, AC coupled CML or HCSL input signals, and single ended signals. A pin compatible device with external
termination is also available.
The ZL40221 is designed to fan out low-jitter reference clocks for wired or optical communications applications
while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors
minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its
operation is guaranteed over the industrial temperature range -40°C to +85°C.
The device block diagram is shown in Figure 1; its operation is described in the following sections.
3.1
Clock Inputs
The device has a differential input equipped with two on-chip 50 Ohm termination resistors arranged in series with a
center tap. The input can accept many differential and single-ended signals with AC or DC coupling as appropriate.
A control pin is available to enable internal biasing for AC coupled inputs. A block diagram of the input stage is in
Figure 3.
clk_p
50
Receiver
50
clk_n
Vt
Bias
ctrl
Figure 3 - Simplified Diagram of input stage
3.1.1
Clock Input Selection
The select line chooses which input clock is routed to the outputs.
Sel
Active Input
0
clk0
1
clk1
Table 1 - Input Selection
The following figure shows the expected clock switching performance. The output stops at the first falling edge of
the initial clock after the select pin changes state. During switching there will be a short time when the output clock
is not toggling. After this delay, the output will start toggling again with a rising edge of the newly selected clock.
This behavior is independent of the frequencies of the input clocks. For instance, the two clocks could be at
different frequencies and the behavior would still be consistent with this figure.
6
Microsemi Corporation
ZL40221
Data Sheet
clk0
clk1
sel 1
0
2 µs
outn
Figure 4 - Output During Clock Switch - Both Clocks Running
3.1.2
Clock Input Terminations
This following figures give the components values and configuration for the various circuits compatible with the
input stage and the use of the Vt and ctrl pins in each case.
In the following diagrams were the ctrl pin is ’1’ and the Vt pin is not connected, the Vt pin can be instead connected
to VDD with a capacitor. A capacitor can also help in Figure 5 between Vt and VDD. This capacitor will minimize the
noise at the point between the two internal termination resistors and improve the overall performance of the device.
VDD_driver
VDD
22 Ohms
Zo = 50 Ohms
clk_p
clk_p
LVPECL
Driver
clk_n
clk_n
Zo = 50 Ohms
Vt
Vt
22 Ohms
R
“0”
For 3.3 V: R= 50 Ohms
For 2.5 V: R= 22 Ohms
Figure 5 - Clock Input - LVPECL - DC Coupled
7
Microsemi Corporation
Ctrl
Ctrl
ZL40221
Data Sheet
VDD_driver
VDD
22 Ohms
LVPECL
Driver
Zo = 50 Ohms
clk_p
clk_n
22 Ohms
Zo = 50 Ohms
R
NC
R
“1”
Vt
Ctrl
For 3.3 V: R= 150 Ohms
For 2.5 V: R= 85 Ohms
Figure 6 - Clock Input - LVPECL - AC Coupled
VDD_driver
VDD
Zo = 50 Ohms
clk_p
LVDS
Driver
clk_n
Zo = 50 Ohms
NC
“0”
Figure 7 - Clock Input - LVDS - DC Coupled
8
Microsemi Corporation
Vt
Ctrl
ZL40221
Data Sheet
Note: This R is only needed to provide a DC
path for the LVDS driver. See driver data
sheet for more information.
VDD_driver
VDD
Zo = 50 Ohms
clk_p
LVDS
Driver
R
clk_n
Zo = 50 Ohms
NC
“1”
Vt
Ctrl
For VDD_driver = 3.3 V: R= 900 Ohms
For VDD_driver = 2.5 V: R = 680 Ohms
Figure 8 - Clock Input - LVDS - AC Coupled
VDD_driver
R
VDD
R
Zo = 50 Ohms
clk_p
CML
Driver
clk_n
Zo = 50 Ohms
NC
“1”
R= 50 Ohms
Figure 9 - Clock Input - CML- AC Coupled
9
Microsemi Corporation
Vt
Ctrl
ZL40221
Data Sheet
VDD_driver
VDD
Zo = 50 Ohms
clk_p
HCSL
Driver
clk_n
Zo = 50 Ohms
R
NC
R
“1”
Vt
Ctrl
R= 50 Ohms
Figure 10 - Clock Input - HCSL- AC Coupled
VDD_driver
VDD
CMOS
Driver
Zo = 50 Ohms
clk_p
clk_n
Vt
“1”
Figure 11 - Clock Input - AC-coupled Single-Ended
10
Microsemi Corporation
Ctrl
ZL40221
Data Sheet
VDD_driver
VDD
CMOS
Driver
Zo = 50 Ohms
clk_p
clk_n
NC
“1”
Figure 12 - Clock Input - DC-coupled 3.3V CMOS
11
Microsemi Corporation
Vt
Ctrl
ZL40221
3.2
Data Sheet
Clock Outputs
LVDS has lower signal swing than LVPECL which results in a low power consumption. A simplified diagram for the
LVDS output stage is shown in Figure 13.
VDD
3 mA
-
+
Output
+
-
Figure 13 - Simplified LVDS Output Driver
The methods to terminate the ZL40221 drivers are shown in the following figures.
VDD_Rx
VDD
ZL40221
clk_p
clk_n
Z o = 50 Ohms
LVDS
Receiver
Z o = 50 Ohms
Figure 14 - LVDS DC Coupled Termination (Internal Receiver Termination)
12
Microsemi Corporation
ZL40221
Data Sheet
VDD_Rx
VDD
ZL40221
clk_p
Zo = 50 Ohms
100 Ohms
clk_n
LVDS
Receiver
Zo = 50 Ohms
Figure 15 - LVDS DC Coupled Termination (External Receiver Termination)
VDD_Rx
VDD
R1
ZL40221
clk_p
R1
Zo = 50 Ohms
LVDS
Receiver
100 Ohms
clk_n
Zo = 50 Ohms
R2
R2
Note: R1 and R2 values and need for external termination
depend on the specification of the LVDS receiver
Figure 16 - LVDS AC Coupled Termination
13
Microsemi Corporation
VDD_Rx
ZL40221
Data Sheet
VDD_Rx
VDD
ZL40221
clk_p
clk_n
50 Ohms
Zo = 50 Ohms
50 Ohms
CML
Receiver
Zo = 50 Ohms
Figure 17 - LVDS AC Output Termination for CML Inputs
14
Microsemi Corporation
ZL40221
3.3
Data Sheet
Device Additive Jitter
The ZL40221 clock fanout buffer is not intended to filter clock jitter. The jitter performance of this type of device is
characterized by its additive jitter. Additive jitter is the jitter the device would add to a hypothetical jitter-free clock as
it passes through the device. The additive jitter of the ZL40221 is random and as such it is not correlated to the jitter
of the input clock signal.
The square of the resultant random RMS jitter at the output of the ZL40221 is equal to the sum of the squares of the
various random RMS jitter sources including: input clock jitter; additive jitter of the buffer; and additive jitter due to
power supply noise. There may be additional deterministic jitter sources, but they are not shown in Figure 18.
Jadd2
Jin2
Jps2
+
Jin
Jadd
Jps
Jout
+
= Random input clock jitter (RMS)
= Additive jitter due to the device (RMS)
= Additive jitter due to power supply noise (RMS)
= Resultant random output clock jitter (RMS)
Figure 18 - Additive Jitter
15
Microsemi Corporation
Jout2= Jin2+Jadd2+Jps2
ZL40221
3.4
Data Sheet
Power Supply
This device operates with either a 2.5V supply or 3.3V supply.
3.4.1
Sensitivity to power supply noise
Power supply noise from sources such as switching power supplies and high-power digital components such as
FPGAs can induce additive jitter on clock buffer outputs. The ZL40221 is equipped with an on-chip linear power
regulator and on-chip bulk capacitors to minimize additive jitter due to power supply noise. The on-chip measures in
combination with the simple recommended power supply filtering and PCB layout minimize additive jitter from
power supply noise.
3.4.2
Power supply filtering
For optimal jitter performance, the ZL40221 should be isolated from the power planes connected to its power
supply pins as shown in Figure 19.
•
•
•
10 µF capacitors should be size 0603 or size 0805 X5R or X7R ceramic, 6.3 V minimum rating
0.1 µF capacitors should be size 0402 X5R ceramic, 6.3 V minimum rating
Capacitors should be placed next to the connected device power pins
VDD
0.15 Ohms
10 µF
11
0.1 µF
16
0.1 µF
18
ZL40221
0.1 µF
23
0.1 µF
25
10 µF
30
Figure 19 - Decoupling Connections for Power Pins
3.4.3
PCB layout considerations
The power supply filtering shown in Figure 19 can be implemented either as a plane island, or as a routed power
topology with equal effect.
16
Microsemi Corporation
ZL40221
4.0
Data Sheet
AC and DC Electrical Characteristics
Absolute Maximum Ratings*
Parameter
Sym.
Min.
Max.
Units
VDD_R
-0.5
4.6
V
VPIN
-0.5
VDD
V
1
Supply voltage
2
Voltage on any digital pin
3
LVPECL output current
Iout
30
mA
4
Soldering temperature
T
260
°C
5
Storage temperature
TST
125
°C
6
Junction temperature
Tj
125
°C
7
Voltage on input pin
Vinput
VDD
V
8
Input capacitance each pin
Cp
500
fF
-55
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
* Voltages are with respect to ground (GND) unless otherwise stated
Recommended Operating Conditions*
Characteristics
Sym.
Min.
Typ.
Max.
Units
1
Supply voltage 2.5 V mode
VDD25
2.375
2.5
2.625
V
2
Supply voltage 3.3 V mode
VDD33
3.135
3.3
3.465
V
3
Operating temperature
TA
-40
25
85
°C
* Voltages are with respect to ground (GND) unless otherwise stated
DC Electrical Characteristics - Current Consumption
Characteristics
1
Supply current LVDS drivers
loaded (all outputs are active)
Sym.
-
Min.
Typ.
Idd_load
Max.
97
Units
Notes
mA
DC Electrical Characteristics - Inputs and outputs - for 2.5/3.3 V supply
Characteristics
Sym.
Min.
Typ.
Max.
1
CMOS control logic high-level input
VCIH
0.7*VDD
2
CMOS control logic low-level input
VCIL
3
CMOS control logic Input leakage
current
IIL
4
Differential input voltage difference
VID
0.25
1
V
5
Differential input common mode
VCM
1.1
1.6
V
for 2.5 V
6
Differential input common mode
VCM
1.1
2.0
V
for 3.3 V
7
Differential input resistance
VIR
80
120
ohm
1
Microsemi Corporation
Notes
V
0.3*VDD
17
Units
100
V
µA
VI = VDD or 0 V
ZL40221
Data Sheet
DC Electrical Characteristics - Inputs and outputs - for 2.5/3.3 V supply
Characteristics
Sym.
Min.
Typ.
Max.
Units
8
LVDS output differential voltage*
VOD
0.25
0.30
0.40
V
9
LVDS output common mode
VCM
1.1
1.25
1.375
V
Notes
* The VOD parameter was measured from 125 MHz to 750 MHz.
VOD
2*VOD
Figure 20 - Differential Voltage Parameter
AC Electrical Characteristics* - Inputs and Outputs (see Figure 21) - for 2.5/3.3 V supply.
Characteristics
Sym.
Min.
Typ.
Max.
Units
750
MHz
1
2
ns
1
Maximum Operating Frequency
1/tp
2
Input to output clock propagation delay
tpd
3
Output to output skew
tout2out
80
150
ps
4
Part to part output skew
tpart2part
120
300
ps
5
Output clock Duty Cycle degradation
0
5
Percent
6
LVDS Output slew rate
7
Reference transition time
0
tPWH/ tPWL
-5
rsl
0.55
tswitch
V/ns
2
* Supply voltage and operating temperature are as per Recommended Operating Conditions
tP
tREFW
tREFW
Input
tpd
Output
Figure 21 - Input To Output Timing
18
Microsemi Corporation
3
us
Notes
ZL40221
5.0
Data Sheet
Performance Characterization
Additive Jitter at 2.5 V*
Output Frequency (MHz)
Jitter
Measurement
Filter
Typical
RMS (fs)
1
125
12 kHz - 20 MHz
229
2
212.5
12 kHz - 20 MHz
217
3
311.04
12 kHz - 20 MHz
194
4
425
12 kHz - 20 MHz
186
5
500
12 kHz - 20 MHz
169
6
622.08
12 kHz - 20 MHz
165
7
750
12 kHz - 20 MHz
178
Notes
*The values in this table were taken with an approximate slew rate of 0.8 V/ns.
Additive Jitter at 3.3 V*
Output Frequency (MHz)
Jitter
Measurement
Filter
Typical
RMS (fs)
1
125
12 kHz - 20 MHz
231
2
212.5
12 kHz - 20 MHz
217
3
311.04
12 kHz - 20 MHz
196
4
425
12 kHz - 20 MHz
190
5
500
12 kHz - 20 MHz
173
6
622.08
12 kHz - 20 MHz
167
7
750
12 kHz - 20 MHz
181
Notes
*The values in this table were taken with an approximate slew rate of 0.8 V/ns.
Additive jitter from a power supply tone*
Carrier
frequency
Parameter
Typical
Units
125
25 mV
at 100 kHz
41
fs RMS
750
25 mV
at 100 kHz
43
fs RMS
Notes
* The values in this table are the additive periodic jitter caused by an interfering tone typically caused by a switching power supply. For this test,
measurements were taken over the full temperature and voltage range for VDD = 3.3 V. The magnitude of the interfering tone is measured at the
DUT.
19
Microsemi Corporation
ZL40221
6.0
Data Sheet
Typical Behavior
0.35
0.2
0.15
0.34
0.1
0.33
VOD
Voltage
0.05
0
0.32
-0.05
-0.1
0.31
-0.15
-0.2
0
5
10
15
0.3
20
0
Time (ns)
200
300
400
500
600
-50
125 MHz
-55
212.5 MHz
-65
-60
425 MHz
750 MHz
-65
PSRR (dBc)
-70
-75
-80
-70
-75
-80
125 MHz
-85
212.5 MHz
-90
-85
425 MHz
-95
750 MHz
-100
100
150
200
250
300
350
400
450
20
500
Power Supply Tone Frequency versus PSRR
0.85
0.8
0.75
0.7
0.65
-40
-20
0
20
40
40
50
60
70
80
Power Supply Tone Magnitude versus PSRR
0.9
0.6
30
Tone Magnitude (mV)
Tone Frequency (kHz)
Delay (ns)
800
VOD vs Frequency
-60
-90
700
Frequency (MHz)
Typical Waveform at 155.52 MHz
PSRR (dBc)
100
60
80
100
Temperature ( C)
Propogation Delay versus Temperature
Note: This is for a single device. For more details, see the
characterization section.
20
Microsemi Corporation
90
100
ZL40221
7.0
Data Sheet
Package Characteristics
Thermal Data
Parameter
Symbol
Test Condition
Value
Junction to Ambient Thermal Resistance
ΘJA
Still Air
1 m/s
2 m/s
37.4
33.1
31.5
o
Junction to Case Thermal Resistance
ΘJC
24.4
oC/W
Junction to Board Thermal Resistance
ΘJB
19.5
oC/W
Maximum Junction Temperature*
Tjmax
125
oC
Maximum Ambient Temperature
TA
85
oC
21
Microsemi Corporation
Unit
C/W
ZL40221
8.0
Mechanical Drawing
22
Microsemi Corporation
Data Sheet
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