ZL40222
Precision 2:8 LVDS Fanout Buffer with
Glitch-free Input Reference Switching
Data Sheet
November 2012
Features
Ordering Information
ZL40222LDG1
ZL40222LDF1
Inputs/Outputs
•
Accepts two differential or single-ended inputs
• LVPECL, LVDS, CML, HCSL, LVCMOS
•
Eight precision LVDS outputs
•
Operating frequency up to 750 MHz
Trays
Tape and Reel
Matte Tin
Package size: 5 x 5 mm
-40oC to +85oC
Glitch-free switching of references
•
32 Pin QFN
32 Pin QFN
Applications
•
General purpose clock distribution
Power
•
Low jitter clock trees
•
Option for 2.5 V or 3.3 V power supply
•
Logic translation
•
Current consumption of 110 mA
•
Clock and data signal restoration
•
On-chip Low Drop Out (LDO) Regulator for superior
power supply rejection
•
Redundant clock distribution
•
Wired communications: OTN, SONET/SDH, GE,
10 GE, FC and 10G FC
•
Wireless communications
•
High performance micro-processor clock
distribution
Performance
•
Ultra low additive jitter of 194 fs RMS
out0_p
out0_n
out1_p
out1_n
clk1_p
clk1_n
out2_p
out2_n
Control
clk0_p
clk0_n
Buffer
out3_p
out3_n
out4_p
out4_n
out5_p
out5_n
out6_p
out6_n
sel
out7_p
out7_n
Figure 1 - Functional Block Diagram
1
Microsemi Corporation
Copyright 2012, Microsemi Corporation, All Rights Reserved.
ZL40222
Data Sheet
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.0 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Clock Input Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Clock Input Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Device Additive Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.1 Sensitivity to power supply noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.2 Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.3 PCB layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.0 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.0 Performance Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.0 Typical Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.0 Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.0 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2
Microsemi Corporation
ZL40222
Data Sheet
List of Figures
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3 - Output During Clock Switch - Both Clocks Running . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4 - LVPECL Input DC Coupled Thevenin Equivalent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5 - LVPECL Input DC Coupled Parallel Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6 - LVPECL Input AC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7 - LVDS Input DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8 - LVDS Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9 - CML Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10 - HCSL Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 11 - CMOS Input DC Coupled Referenced to VDD/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12 - CMOS Input DC Coupled Referenced to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 13 - Simplified LVDS Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 14 - LVDS DC Coupled Termination (Internal Receiver Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 15 - LVDS DC Coupled Termination (External Receiver Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 16 - LVDS AC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 17 - LVDS AC Output Termination for CML Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 18 - Additive Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 19 - Decoupling Connections for Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 20 - Differential Voltage Parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 21 - Input To Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3
Microsemi Corporation
ZL40222
1.0
Data Sheet
Package Description
24
22
20
out4_n
18
out2_n
out2_p
out4_p
vdd
gnd
gnd
vdd
out3_n
out3_p
The device is packaged in a 32 pin QFN
16
out5_n
26
out1_n
out1_p
14
12
gnd (E-pad)
10
32
IC
vdd
clk1_n
8
NC
clk1_p
6
NC
NC
4
clk0_n
NC
2
clk0_p
out7_p
out7_n
30
sel
vdd
out6_p
out6_n
28
out0_n
out0_p
out5_p
Figure 2 - Pin Connections
4
Microsemi Corporation
ZL40222
2.0
Data Sheet
Pin Description
Pin #
1,3,
6, 8
30, 29,
28, 27,
26, 25,
24, 23,
18, 17,
16, 15,
14, 13,
12, 11
Name
Description
clk0_p, clk0_n, Differential Input (Analog Input). Differential (or singled ended) input signals. For all
clk1_p, clk1_n input signal configuration see Section 3.2, “Clock Input Termination“.
out0_p, out0_n Differential Output (Analog Output). Differential outputs.
out1_p, out1_n
out2_p, out2_n
out3_p, out3_n
out4_p, out4_n
out5_p, out5_n
out6_p, out6_n
out7_p, out7_n
9, 19,
22, 32
vdd
Positive Supply Voltage. 2.5VDC or 3.3 VDC nominal.
20, 21
gnd
Ground. 0 V.
31
sel
Input Select (Input). Selects the reference input that is buffered;
0: clk0
1: clk1
This pin is internally pulled down to GND.
2, 4,
5, 7, 10
NC
No Connection. Leave unconnected.
5
Microsemi Corporation
ZL40222
3.0
Data Sheet
Functional Description
The ZL40222 is an LVDS clock fanout buffer with eight identical output clock drivers capable of operating at
frequencies up to 750MHz.
The two Inputs to the ZL40222 are externally terminated to allow use of precision termination components and to
allow full flexibility of input termination. The ZL40222 can accept DC or AC coupled LVPECL, LVDS, CML or HCSL
input signals; single ended input signals can also be accepted. A pin compatible device with internal termination is
also available.
The ZL40222 is designed to fan out low-jitter reference clocks for wired or optical communications applications
while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors
minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its
operation is guaranteed over the industrial temperature range -40°C to +85°C.
The device block diagram is shown in Figure 1; its operation is described in the following sections.
3.1
Clock Input Selection
The select line chooses which input clock is routed to the outputs.
Sel
Active Input
0
clk0
1
clk1
Table 1 - Input Selection
The following figure shows the expected clock switching performance. The output stops at the first falling edge of
the initial clock after the select pin changes state. During switching there will be a short time when the output clock
is not toggling. After this delay, the output will start toggling again with a rising edge of the newly selected clock.
This behavior is independent of the frequencies of the input clocks. For instance, the two clocks could be at
different frequencies and the behavior would still be consistent with this figure.
clk0
clk1
sel 1
0
2 µs
outn
Figure 3 - Output During Clock Switch - Both Clocks Running
6
Microsemi Corporation
ZL40222
3.2
Data Sheet
Clock Input Termination
The ZL40222 is adaptable to support different types of differential and singled-ened input signals depending on the
passive components used in the input termination. The application diagrams in the following figures allow the
ZL40222 to accept LVPECL, LVDS, CML, HCSL and single-ended inputs.
VDD_driver
VDD
VDD_driver
R1
22 Ohms
ZL40222
R1
Z o = 50 Ohms
clk_p
LVPECL
Driver
clk_n
Z o = 50 Ohms
22 Ohms
R2
R2
VDD_driver=3.3V: R1=127 ohm, R2=82 ohm
VDD_driver=2.5V: R1=250 ohm, R2=62.5 ohm
Figure 4 - LVPECL Input DC Coupled Thevenin Equivalent
VDD
VDD_driver
ZL40222
22 Ohm s
LVPECL
Driver
Z o = 50 Ohm s
clk_p
Z o = 50 Ohm s
clk_n
22 Ohm s
50
Ohm s
50
Ohm s
R1
VDD_driver=3.3V: R1 = 50 ohm
VDD_driver=2.5V: R1 = 20 ohm
Figure 5 - LVPECL Input DC Coupled Parallel Termination
7
Microsemi Corporation
ZL40222
Data Sheet
VDD
VDD_driver=3.3V: R = 143 ohm
VDD_driver=2.5V: R = 82 ohm
2K
Ohm
VDD_driver
2K
Ohm
ZL40222
100 nF
Z o = 50 Ohm s
LVPECL
Driver
clk_p
100 nF
clk_n
Z o = 50 Ohm s
R
VDD
2K
Ohm
R
2K
Ohm
Figure 6 - LVPECL Input AC Coupled Termination
VDD
VDD_driver
ZL40222
Z o = 50 Ohm s
LVDS
Driver
Z o = 50 Ohm s
Figure 7 - LVDS Input DC Coupled
8
Microsemi Corporation
100
Ohm s
clk_p
clk_n
ZL40222
Data Sheet
VDD
VDD
2K
Ohm
2K
Ohm
100 nF
VDD_driver
Zo = 50 Ohms
LVDS
Driver
ZL40222
clk_p
100 Ohm
clk_n
Zo = 50 Ohms
100 nF
2K
Ohm
2K
Ohm
Figure 8 - LVDS Input AC Coupled
VDD_driver
50
Ohm
VDD
VDD
VDD_driver
50
Ohm
2K
Ohm
2K
Ohm
Zo = 50 Ohms
clk_p
100 nF
100 nF
CML
Driver
clk_n
Zo = 50 Ohms
2K
Ohm
Figure 9 - CML Input AC Coupled
9
Microsemi Corporation
ZL40222
2K
Ohm
ZL40222
Data Sheet
VDD
VDD
VDD_driver
100 nF
2K
Ohm
2K
Ohm
Zo = 50 Ohms
ZL40222
clk_p
HCSL
Driver
100 nF
clk_n
Zo = 50 Ohms
50
Ohm
50
Ohm
2K
Ohm
2K
Ohm
Figure 10 - HCSL Input AC Coupled
VDD_driver
VDD
VDD_driver
R
ZL40222
CM OS
Driver
clk_p
Vref = VDD_driver/2
R
C
R= 10 K ohm s, C = 100 nF
Figure 11 - CMOS Input DC Coupled Referenced to VDD/2
10
Microsemi Corporation
clk_n
ZL40222
Data Sheet
VDD
VDD
VDD_driver
ZL40222
R2
CMOS
Driver
clk_p
R1
RA
clk_n
R3
C
Figure 12 - CMOS Input DC Coupled Referenced to Ground
VDD_driver
R1 (kΩ)
R2 (kΩ)
R3 (kΩ)
RA (kΩ)
C (pF)
1.5
1.25
3.075
open
10
10
1.8
1
3.8
open
10
10
2.5
0.33
4.2
open
10
10
3.3
0.75
open
4.2
10
10
Table 2 - Component Values for Single Ended Input Reference to Ground
* For frequencies below 100 MHz, increase C to avoid signal integrity issues.
11
Microsemi Corporation
ZL40222
3.3
Data Sheet
Clock Outputs
LVDS has lower signal swing than LVPECL which results in a low power consumption. A simplified diagram for the
LVDS output stage is shown in Figure 13.
VDD
3 mA
-
+
Output
+
-
Figure 13 - Simplified LVDS Output Driver
The methods to terminate the ZL40222 drivers are shown in the following figures.
VDD_Rx
VDD
ZL40222
clk_p
clk_n
Zo = 50 Ohms
LVDS
Receiver
Zo = 50 Ohms
Figure 14 - LVDS DC Coupled Termination (Internal Receiver Termination)
12
Microsemi Corporation
ZL40222
Data Sheet
VDD_Rx
VDD
ZL40222
clk_p
Zo = 50 Ohms
100 Ohms
clk_n
LVDS
Receiver
Zo = 50 Ohms
Figure 15 - LVDS DC Coupled Termination (External Receiver Termination)
VDD
VDD_Rx
R1
ZL40222
clk_p
R1
Zo = 50 Ohms
LVDS
Receiver
100 Ohms
clk_n
Zo = 50 Ohms
R2
R2
Note: R1 and R2 values and need for external termination
depend on the specification of the LVDS receiver
Figure 16 - LVDS AC Coupled Termination
13
Microsemi Corporation
VDD_Rx
ZL40222
Data Sheet
VDD_Rx
VDD
ZL40222
clk_p
clk_n
50 Ohms
Zo = 50 Ohms
50 Ohms
CML
Receiver
Zo = 50 Ohms
Figure 17 - LVDS AC Output Termination for CML Inputs
14
Microsemi Corporation
ZL40222
3.4
Data Sheet
Device Additive Jitter
The ZL40222 clock fanout buffer is not intended to filter clock jitter. The jitter performance of this type of device is
characterized by its additive jitter. Additive jitter is the jitter the device would add to a hypothetical jitter-free clock as
it passes through the device. The additive jitter of the ZL40222 is random and as such it is not correlated to the jitter
of the input clock signal.
The square of the resultant random RMS jitter at the output of the ZL40222 is equal to the sum of the squares of the
various random RMS jitter sources including: input clock jitter; additive jitter of the buffer; and additive jitter due to
power supply noise. There may be additional deterministic jitter sources, but they are not shown in Figure 18.
Jadd2
Jin2
Jps2
+
Jin
Jadd
Jps
Jout
+
= Random input clock jitter (RMS)
= Additive jitter due to the device (RMS)
= Additive jitter due to power supply noise (RMS)
= Resultant random output clock jitter (RMS)
Figure 18 - Additive Jitter
15
Microsemi Corporation
Jout2= Jin2+Jadd2+Jps2
ZL40222
3.5
Data Sheet
Power Supply
This device operates with either a 2.5V supply or 3.3V supply.
3.5.1
Sensitivity to power supply noise
Power supply noise from sources such as switching power supplies and high-power digital components such as
FPGAs can induce additive jitter on clock buffer outputs. The ZL40222 is equipped with a low drop out (LDO)
power regulator and on-chip bulk capacitors to minimize additive jitter due to power supply noise. The on-chip
measures in combination with the simple recommended power supply filtering and PCB layout minimize additive
jitter from power supply noise.
3.5.2
Power supply filtering
For optimal jitter performance, the ZL40222 should be isolated from the power planes connected to its power
supply pins as shown in Figure 19.
•
•
•
10 µF capacitors should be size 0603 or size 0805 X5R or X7R ceramic, 6.3 V minimum rating
0.1 µF capacitors should be size 0402 X5R ceramic, 6.3 V minimum rating
Capacitors should be placed next to the connected device power pins
VDD
0.15 Ohm s
10 µF
9
0.1 µF
19
ZL40222
0.1 µF
22
10 µF
32
Figure 19 - Decoupling Connections for Power Pins
3.5.3
PCB layout considerations
The power supply filtering shown in Figure 19 can be implemented either as a plane island, or as a routed power
topology with equal performance.
16
Microsemi Corporation
ZL40222
4.0
Data Sheet
AC and DC Electrical Characteristics
Absolute Maximum Ratings*
Parameter
Sym.
Min.
Max.
Units
VDD_R
-0.5
4.6
V
VPIN
-0.5
VDD
V
260
°C
125
°C
1
Supply voltage
2
Voltage on any digital pin
3
Soldering temperature
4
Storage temperature
TST
5
Junction temperature
Tj
125
°C
6
Voltage on input pin
Vinput
VDD
V
7
Input capacitance each pin
Cp
500
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
* Voltages are with respect to ground (GND) unless otherwise stated
fF
T
-55
Recommended Operating Conditions*
Characteristics
Sym.
Min.
Typ.
Max.
Units
1
Supply voltage 2.5 V mode
VDD25
2.375
2.5
2.625
V
2
Supply voltage 3.3 V mode
VDD33
3.135
3.3
3.465
V
3
Operating temperature
TA
-40
25
85
°C
* Voltages are with respect to ground (GND) unless otherwise stated
DC Electrical Characteristics - Current Consumption
Characteristics
1
Supply current LVDS drivers
loaded (all outputs are active)
Sym.
-
Min.
Typ.
Idd_load
Max.
110
Units
Notes
mA
DC Electrical Characteristics - Inputs and outputs - for 2.5/3.3 V supply
Characteristics
Sym.
Min.
Typ.
Max.
1
CMOS control logic high-level input
VCIH
0.7*VDD
2
CMOS control logic low-level input
VCIL
3
CMOS control logic Input leakage
current
IIL
4
Differential input voltage difference
VID
0.25
1
V
5
Differential common mode voltage
VCM
1.1
1.6
V
for 2.5 V
6
Differential common mode voltage
VCM
1.1
2.0
V
for 3.3 V
7
LVDS output differential voltage*
VOD
0.25
0.30
0.40
V
8
LVDS output common mode
VCM
1.1
1.25
1.375
V
1
17
Microsemi Corporation
Notes
V
0.3*VDD
* The VOD parameter was measured from 125 MHz to 750 MHz.
Units
V
µA
VI = VDD or 0 V
ZL40222
Data Sheet
VOD
2*VOD
Figure 20 - Differential Voltage Parameter
AC Electrical Characteristics* - Inputs and Outputs (see Figure 21) - for 2.5/3.3 V supply.
Characteristics
Sym.
Min.
Typ.
Max.
Units
750
MHz
1
2
ns
1
Maximum Operating Frequency
1/tp
2
Input to output clock propagation delay
tpd
3
Output to output skew
tout2out
80
150
ps
4
Part to part output skew
tpart2part
120
300
ps
5
Output clock Duty Cycle degradation
0
5
Percent
6
LVDS Output slew rate
7
Reference transition time
0
tPWH/ tPWL
-5
rsl
0.55
tswitch
V/ns
2
* Supply voltage and operating temperature are as per Recommended Operating Conditions
tP
tREFW
tREFW
Input
tpd
Output
Figure 21 - Input To Output Timing
18
Microsemi Corporation
3
us
Notes
ZL40222
5.0
Data Sheet
Performance Characterization
Additive Jitter at 2.5 V*
Output Frequency (MHz)
Jitter
Measurement
Filter
Typical
RMS (fs)
1
125
12 kHz - 20 MHz
261
2
212.5
12 kHz - 20 MHz
249
3
311.04
12 kHz - 20 MHz
215
4
425
12 kHz - 20 MHz
189
5
500
12 kHz - 20 MHz
201
6
622.08
12 kHz - 20 MHz
194
7
750
12 kHz - 20 MHz
205
Notes
*The values in this table were taken with an approximate slew rate of 0.8 V/ns.
Additive Jitter at 3.3 V*
Output Frequency (MHz)
Jitter
Measurement
Filter
Typical
RMS (fs)
1
125
12 kHz - 20 MHz
268
2
212.5
12 kHz - 20 MHz
251
3
311.04
12 kHz - 20 MHz
229
4
425
12 kHz - 20 MHz
220
5
500
12 kHz - 20 MHz
197
6
622.08
12 kHz - 20 MHz
194
7
750
12 kHz - 20 MHz
203
Notes
*The values in this table were taken with an approximate slew rate of 0.8 V/ns.
Additive jitter from a power supply tone*
Carrier
frequency
Parameter
Typical
Units
125
25 mV
at 100 kHz
37
fs RMS
750
25 mV
at 100 kHz
40
fs RMS
Notes
* The values in this table are the additive periodic jitter caused by an interfering tone typically caused by a switching power supply. For this test,
measurements were taken over the full temperature and voltage range for VDD = 3.3 V. The magnitude of the interfering tone is measured at the
DUT.
19
Microsemi Corporation
ZL40222
6.0
Data Sheet
Typical Behavior
0.35
0.2
0.15
0.34
0.1
0.33
VOD
Voltage
0.05
0
0.32
-0.05
-0.1
0.31
-0.15
-0.2
0
5
10
15
0.3
20
0
Time (ns)
200
300
400
500
600
-50
125 MHz
-55
212.5 MHz
-65
-60
425 MHz
750 MHz
-65
PSRR (dBc)
-70
-75
-80
-70
-75
-80
125 MHz
-85
212.5 MHz
-90
-85
425 MHz
-95
750 MHz
-100
100
150
200
250
300
350
400
450
20
500
Power Supply Tone Frequency versus PSRR
0.85
0.8
0.75
0.7
0.65
-40
-20
0
20
40
40
50
60
70
80
Power Supply Tone Magnitude versus PSRR
0.9
0.6
30
Tone Magnitude (mV)
Tone Frequency (kHz)
Delay (ns)
800
VOD vs Frequency
-60
-90
700
Frequency (MHz)
Typical Waveform at 155.52 MHz
PSRR (dBc)
100
60
80
100
Temperature ( C)
Propogation Delay versus Temperature
Note: This is for a single device. For more details, see the
characterization section.
20
Microsemi Corporation
90
100
ZL40222
7.0
Data Sheet
Package Characteristics
Thermal Data
Parameter
Symbol
Test Condition
Value
Junction to Ambient Thermal Resistance
ΘJA
Still Air
1 m/s
2 m/s
37.4
33.1
31.5
o
Junction to Case Thermal Resistance
ΘJC
24.4
oC/W
Junction to Board Thermal Resistance
ΘJB
19.5
oC/W
Maximum Junction Temperature*
Tjmax
125
oC
Maximum Ambient Temperature
TA
85
oC
21
Microsemi Corporation
Unit
C/W
ZL40222
8.0
Mechanical Drawing
22
Microsemi Corporation
Data Sheet
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