2N3955

2N3955 MONOLITHIC DUAL N-CHANNEL JFET The 2N3955 is a Low Noise, Low Drift, Monolithic Dual N-Channel JFET The 2N3955 family are matched JFET pairs for differential amplifiers. The 2N3955 family of general purpose JFETs is characterized for low and medium frequency differential amplifiers requiring low offset voltage, drift, noise and capacitance The 2N3955 family exhibits low capacitance - 6pF max and a spot noise figure of - 0.5dB max. The part offers a superior tracking ability. The 8 Pin P-DIP and 8 Pin SOIC provide ease of manufacturing, and the symmetrical pinout prevents improper orientation. (See Packaging Information). FEATURES  LOW DRIFT  LOW LEAKAGE  LOW NOISE  ABSOLUTE MAXIMUM RATINGS   @ 25°C (unless otherwise noted)  |∆ VGS1‐2 /∆T|= 5µV/°C max. IG = 20pA TYP.  en = 10nV/√Hz TYP.  2N3955 Applications: Wideband Differential Amps High Input Impedance Amplifiers Maximum Temperatures  Storage Temperature  ‐65°C to +200°C  Operating Junction Temperature  +150°C  Maximum Voltage and Current for Each Transistor – Note 1  ‐VGSS  Gate Voltage to Drain or Source  60V  ‐VDSO  Drain to Source Voltage  60V  ‐IG(f)  Gate Forward Current  50mA  Maximum Power Dissipation  Device Dissipation @ Free Air – Total                 400mW @ 25°C    MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED SYMBOL  CHARACTERISTICS  VALUE  UNITS  CONDITIONS  | V GS1‐2 / T| max.  DRIFT VS.  25  µV/°C  VDG=20V, ID=200µA  TEMPERATURE  TA=‐55°C to +125°C  | V GS1‐2 | max.  OFFSET VOLTAGE  10  mV  VDG=20V, ID=200µA  MAX.  ‐‐  ‐‐    3000  1000  3    5  5    4.5  4    50  50  ‐‐  100    5  1  0.1    ‐‐  ‐‐    0.5  15    6  2  ‐‐  UNITS  V  V    µmho  µmho  %    mA  %    V  V    pA  nA  pA  pA    µmho  µmho  µmho    dB  dB    dB  nV/√Hz    pF  pF  pF  CONDITIONS  VDS = 0                  ID=1µA        I G= 1nA               ID= 0               IS= 0    VDG= 20V         VGS= 0V      f = 1kHz       VDG= 20V         ID= 200µA          VDG= 20V              VGS= 0V      VDS= 20V               ID= 1nA                VDS=20V                 ID=200µA    VDG= 20V          ID= 200µA  TA= +125°C   VDG= 10V         ID= 200µA  VDG= 20V              VDS= 0    VDG= 20V              VGS= 0V  VDG=  20V           ID= 200µA  ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted) SYMBOL  CHARACTERISTICS  MIN.  TYP.  BVGSS  Breakdown Voltage  60  ‐‐  BVGGO  Gate‐To‐Gate Breakdown  60  ‐‐    TRANSCONDUCTANCE      YfSS  Full Conduction  1000  2000  YfS  Typical Operation  500  700  |YFS1‐2 / Y FS|  Mismatch  ‐‐  0.6    DRAIN CURRENT      IDSS  Full Conduction  0.5  2  |IDSS1‐2 / IDSS|  Mismatch at Full Conduction  ‐‐  1  GATE VOLTAGE        VGS(off) or Vp  Pinchoff voltage  1  2  VGS(on)  Operating Range  0.5  ‐‐  GATE CURRENT        ‐IG  Operating  ‐‐  20  ‐IG  High Temperature  ‐‐  ‐‐  ‐IG  Reduced  VDG  ‐‐  5  ‐IGSS  At Full Conduction  ‐‐  ‐‐    OUTPUT CONDUCTANCE      YOSS  Full Conduction  ‐‐  ‐‐  YOS  Operating  ‐‐  0.1  |YOS1‐2|  Differential  ‐‐  0.01    COMMON MODE REJECTION      CMR  ‐20 log | VGS1‐2/ VDS|  ‐‐  100  CMR  ‐20 log | VGS1‐2/ VDS|  ‐‐  75    NOISE      NF  Figure  ‐‐  ‐‐  en  Voltage  ‐‐  ‐‐    CAPACITANCE      CISS  Input  ‐‐  ‐‐  CRSS  Reverse Transfer  ‐‐  ‐‐  CDD  Drain‐to‐Drain  ‐‐  0.1  Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired Click To Buy   ∆VDS = 10 to 20V        ID=200µA  ∆VDS = 5 to 10V        ID=200µA  VDS= 20V      VGS= 0V       RG= 10MΩ  f= 100Hz           NBW= 6Hz  VDS=20V   ID=200µA   f=10Hz  NBW=1Hz    VDS= 20V       VGS= 0V       f= 1MHz  VDG=  20V           ID= 200µA  PDIP / SOIC (Top View) Available Packages: 2N3955 in PDIP / SOIC 2N3955 available as bare die Please contact Micross for full package and die dimensions Micross Components Europe Tel: +44 1603 788967 Email: chipcomponents@micross.com Web: http://www.micross.com/distribution Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.