LS5907_SOIC

LS5907 LOW NOISE, LOW DRIFT MONOLITHIC DUAL N-CHANNEL JFET The LS5907 is a high-performance monolithic dual JFET featuring tight matching and low drift over temperature specifications, and is targeted for use in a wide range of precision instrumentation applications where tight tracking is required. The 8 Pin P-DIP and 8 Pin SOIC provide ease of manufacturing, and the symmetrical pinout prevents improper orientation. (See Packaging Information). FEATURES  LOW DRIFT  ULTRA LOW LEAKAGE  LOW PINCHOFF  ABSOLUTE MAXIMUM RATINGS   @ 25°C (unless otherwise noted)  | VGS1‐2 / T| = 5µV/°C TYP.  IG = 150fA TYP.  Vp = 2V TYP.  LS5907 Benefits: Tight Tracking Good matching Ultra Low Leakage Low Drift Maximum Temperatures  Storage Temperature  ‐65°C to +150°C  Operating Junction Temperature  +150°C  Maximum Voltage and Current for Each Transistor – Note 1  ‐VGSS  Gate Voltage to Drain or Source  40V  ‐VDSO  Drain to Source Voltage  40V  ‐IG(f)  Gate Forward Current  10mA  ‐IG  Gate Reverse Current  10µA  Maximum Power Dissipation  Device Dissipation @ Free Air – Total                 40mW @ +125°C  MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED SYMBOL  CHARACTERISTICS  VALUE  UNITS  CONDITIONS  | VGS1‐2 / T| max.  DRIFT VS.  10  µV/°C  VDG=10V, ID=30µA  TEMPERATURE  TA=‐55°C to +125°C  | V GS1‐2 | max.  OFFSET VOLTAGE  5  mV  VDG=10V, ID=30µA  TYP.  60  ‐‐    300  100  1    400  2    2  ‐‐    ‐‐  ‐‐  ‐‐  ‐‐  1    ‐‐  0.1  0.01    90  90    ‐‐  20    ‐‐  ‐‐  ‐‐  MAX.  ‐‐  ‐‐    500  200  5    1000  5    4.5  4    1  1  2  5  ‐‐    5  0.1  0.1    ‐‐  ‐‐    1  70    3  1.5  0.1  UNITS  V  V    µmho  µmho  %    µA  %    V  V    pA  nA  pA  nA  pA      µmho  CONDITIONS  VDS = 0                  ID=1nA        IG= 1nA               ID= 0               IS= 0    VDG= 10V         VGS= 0V      f = 1kHz       VDG= 10V         ID= 30µA      f = 1kHz      VDG= 10V              VGS= 0V      VDS= 10V               ID= 1nA                VDS=10V                 ID=30µA    VDG= 10V ID= 30µA  TA= +125°C   VDS =0V      VGS= 20V  TA= +125°C    VGG= 20V    VDG= 10V              VGS= 0V  VDG=  10V            ID=30µA    ∆VDS = 10 to 20V        ID=30µA  ∆VDS = 5 to 10V         ID=30µA  VDS= 10V      VGS= 0V       RG= 10MΩ  f= 100Hz           NBW= 6Hz  VDG=10V   ID=30µA   f=10Hz  NBW=1Hz    VDS= 10V       VGS= 0V       f= 1MHz  VDG = 20V    ID=30µA       ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted) SYMBOL  CHARACTERISTICS  MIN.  BVGSS  Breakdown Voltage  40  BVGGO  Gate‐To‐Gate Breakdown  40    TRANSCONDUCTANCE    YfSS  Full Conduction  70  YfS  Typical Operation  50  |YFS1‐2 / Y FS|  Mismatch  ‐‐    DRAIN CURRENT    IDSS  Full Conduction  60  |IDSS1‐2 / IDSS|  Mismatch at Full Conduction  ‐‐    GATE VOLTAGE    VGS(off) or Vp  Pinchoff voltage  0.6  VGS(on)  Operating Range  ‐‐  GATE CURRENT      ‐IGmax.  Operating  ‐‐  ‐IGmax.  High Temperature  ‐‐  ‐IGSSmax.  At Full Conduction  ‐‐  ‐IGSSmax.  High Temperature  ‐‐  IGGO  Gate‐to‐Gate Leakage  ‐‐  OUTPUT CONDUCTANCE      YOSS  Full Conduction  ‐‐  YOS  Operating  ‐‐  |YOS1‐2|  Differential  ‐‐    COMMON MODE REJECTION    CMR  ‐20 log |∆VGS1‐2/∆VDS|  ‐‐  CMR  ‐20 log |∆VGS1‐2/∆VDS|  ‐‐    NOISE    NF  Figure  ‐‐  en  Voltage  ‐‐    CAPACITANCE    CISS  Input  ‐‐  CRSS  Reverse Transfer  ‐‐  CDD  Drain‐to‐Drain  ‐‐  Click To Buy     dB      dB  nV/√Hz      pF    Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired SOIC / PDIP (Top View) Available Packages: LS5907 in PDIP / SOIC LS5907 available as bare die Please contact Micross for full package and die dimensions Micross Components Europe Tel: +44 1603 788967 Email: chipcomponents@micross.com Web: http://www.micross.com/distribution Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.