LS845_SOIC

LS845 MONOLITHIC DUAL N-CHANNEL JFET Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET The LS845 is a high-performance monolithic dual JFET featuring extremely low noise, tight offset voltage and low drift over temperature specifications, and is targeted for use in a wide range of precision instrumentation applications. The LS845 features a 15mV offset and 25-µV/°C drift. The 8 Pin P-DIP and 8 Pin SOIC provide ease of manufacturing, and the symmetrical pinout prevents improper orientation. (See Packaging Information). FEATURES  LOW DRIFT  | V GS1‐2 / T| ≤25µV/°C  LOW LEAKAGE  IG = 15pA TYP.  LOW NOISE  en = 3nV/√Hz TYP.  LOW OFFSET VOLTAGE  | V GS1‐2| ≤15mV  ABSOLUTE MAXIMUM RATINGS @ 25°C (unless otherwise noted)  Maximum Temperatures  Storage Temperature  ‐65°C to +150°C  Operating Junction Temperature  +150°C  Maximum Voltage and Current for Each Transistor – Note 1  ‐VGSS  Gate Voltage to Drain or Source  60V  ‐VDSO  Drain to Source Voltage  60V  ‐IG(f)  Gate Forward Current  50mA  Maximum Power Dissipation  Device Dissipation @ Free Air – Total                 400mW @ +125°C    MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED SYMBOL  CHARACTERISTICS  VALUE  UNITS  CONDITIONS  | V GS1‐2 / T| max.  DRIFT VS.  25  µV/°C  VDG=10V, ID=500µA  TEMPERATURE  TA=‐55°C to +125°C  | V GS1‐2 | max.  OFFSET VOLTAGE  15  mV  VDG=10V, ID=500µA  MAX.  ‐‐  ‐‐    ‐‐  ‐‐  3    15  5    3.5  3.5    50  50  30  100    20  2  0.2    ‐‐  ‐‐    0.5  7  11    8  3  ‐‐  UNITS  V  V    µmho  µmho  %    mA  %    V  V    pA  nA  pA  pA    µmho  µmho  µmho    dB  CONDITIONS  VDS = 0                  ID=1nA        I G= 1nA               ID= 0               IS= 0    VDG= 15V         VGS= 0V      f = 1kHz       VDG= 15V         ID= 500µA          VDG= 15V              VGS= 0V      VDS= 15V               ID= 1nA                VDS=15V                 ID=500µA    VDG= 15V ID= 500µA  TA= +125°C   VDG = 3V ID= 500µA  VDG= 15V , VDS =0    VDG= 15V              VGS= 0V  VDG=  15V            ID= 500µA  LS845 Applications: Wideband Differential Amps High-Speed,Temp-Compensated SingleEnded Input Amps High-Speed Comparators Impedance Converters and vibrations detectors. ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted) SYMBOL  CHARACTERISTICS  MIN.  TYP.  BVGSS  Breakdown Voltage  60  ‐‐  BVGGO  Gate‐To‐Gate Breakdown  60  ‐‐    TRANSCONDUCTANCE      YfSS  Full Conduction  1500  ‐‐  YfS  Typical Operation  1000  1500  |YFS1‐2 / Y FS|  Mismatch  ‐‐  0.6  DRAIN CURRENT        IDSS  Full Conduction  1.5  5  |IDSS1‐2 / IDSS|  Mismatch at Full Conduction  ‐‐  1  GATE VOLTAGE        VGS(off) or Vp  Pinchoff voltage  1  ‐‐  VGS(on)  Operating Range  0.5  ‐‐  GATE CURRENT        ‐IGmax.  Operating  ‐‐  15  ‐IGmax.  High Temperature  ‐‐  ‐‐  ‐IGmax.  Reduced VDG  ‐‐  5  ‐IGSSmax.  At Full Conduction  ‐‐  ‐‐  OUTPUT CONDUCTANCE        YOSS  Full Conduction  ‐‐  ‐‐  YOS  Operating  ‐‐  0.2  |YOS1‐2|  Differential  ‐‐  0.02    COMMON MODE REJECTION      CMR  ‐20 log | V GS1‐2/ V DS|  90  110  ‐20 log | V GS1‐2/ V DS|  ‐‐  85    NOISE      NF  Figure  ‐‐  ‐‐  en  Voltage  ‐‐  ‐‐  ‐‐  ‐‐    CAPACITANCE      CISS  Input  ‐‐  ‐‐  CRSS  Reverse Transfer  ‐‐  ‐‐  CDD  Drain‐to‐Drain  ‐‐  0.5  Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired Click To Buy   dB  nV/√Hz      pF      ∆VDS = 10 to 20V        ID=500µA  ∆VDS = 5 to 10V        ID=500µA  VDS= 15V      VGS= 0V       RG= 10MΩ  f= 100Hz           NBW= 6Hz  VDS=15V   ID=500µA  f=1KHz NBW=1Hz  VDS=15V   ID=500µA  f=10Hz NBW=1Hz    VDS= 15V,   ID=500µA      VDG= 15V,   ID=500µA    PDIP & SOIC (Top View) Available Packages: LS845 / LS845 in PDIP & SOIC LS845 / LS845 available as bare die Please contact Micross for full package and die dimensions Tel: +44 1603 788967 Email: chipcomponents@micross.com Web: http://www.micross.com/distribution Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.