LSU424_TO-71

LSU424 HIGH INPUT IMPEDANCE MONOLITHIC DUAL N-CHANNEL JFET Linear Systems replaces discontinued Siliconix U424 The LSU424 is a high input impedance Monolithic Dual N-Channel JFET The LSU424 monolithic dual n-channel JFET is designed to provide very high input impedance for differential amplification and impedance matching. Among its many unique features, this series offers operating gate current specified at -500 fA. The LSU424 is a direct replacement for discontinued Siliconix U424. The hermetically sealed TO-71 & TO-78 packages are well suited for military applications. The 8 Pin P-DIP and 8 Pin SOIC provide ease of manufacturing, and the symmetrical pinout prevents improper orientation. (See Packaging Information). FEATURES  HIGH INPUT IMPEDANCE  HIGH GAIN  LOW POWER OPERATION  ABSOLUTE MAXIMUM RATINGS   @ 25°C (unless otherwise noted)  IG = 0.25pA MAX  gfs = 120µmho MIN  VGS(OFF) = 2V MAX  LSU424 Applications: Ultra Low Input Current Differential Amps High-Speed Comparators Impedance Converters Maximum Temperatures  Storage Temperature  ‐65°C to +150°C  Operating Junction Temperature  +150°C  Maximum Voltage and Current for Each Transistor – Note 1  ‐VGSS  Gate Voltage to Drain or Source  40V  ‐VDSO  Drain to Source Voltage  40V  ‐IG(f)  Gate Forward Current  10mA  Maximum Power Dissipation  Device Dissipation @ Free Air – Total                 400mW @ +125°C  MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED SYMBOL  CHARACTERISTICS  VALUE  UNITS  CONDITIONS  |∆V GS1‐2 /∆T|max.  DRIFT VS.  10  µV/°C  VDG=10V, ID=30µA  TEMPERATURE  TA=‐55°C to +125°C  | V GS1‐2 | max.  OFFSET VOLTAGE  10  mV  VDG=10V, ID=30µA  TYP.  60  ‐‐    ‐‐  200    ‐‐    ‐‐  ‐‐    ‐‐  ‐‐  ‐‐  ‐‐    ‐‐  0.1    90  90    ‐‐  20  10    ‐‐  ‐‐  MAX.  ‐‐  ‐‐    1500  350    1000    2.0  1.8    .25  250  1.0  1.0    10  3.0    ‐‐  ‐‐    1  70  ‐‐    3.0  1.5  UNITS  V  V    µmho  µmho    µA    V  V    pA  pA  pA  nA    µmho  µmho    dB  dB    dB  nV/√Hz      pF  pF  CONDITIONS  VDS = 0                  IG =1nA        IG = 1µA               ID = 0               IS= 0    VDS = 10V         VGS = 0V      f = 1kHz       VDG = 10V          ID = 30µA    f = 1kHz    VDS = 10V              VGS = 0V    VDS = 10V               ID = 1nA              VDG = 10V                 ID = 30µA      VDG = 10V               ID = 30µA  TA = +125°C   VDS = 0V             VGS = 20V  TA = +125°C      VDS = 10V              VGS = 0V   VDG =  10V             ID = 30µA    ∆VDS = 10 to 20V        ID = 30µA  ∆VDS = 5 to 10V          ID = 30µA  VDG = 10V     ID = 30µA     RG = 10MΩ  f = 10Hz                 VDG = 10V     ID = 30µA      f = 10Hz        VDG  = 10V    ID = 30µA      f = 1KHz      VDS= 10V       VGS = 0     f = 1MHz    P-DIP / SOIC (Top View) ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted) SYMBOL  CHARACTERISTICS  MIN.  BVGSS  Breakdown Voltage  40  BVGGO  Gate‐To‐Gate Breakdown  40    TRANSCONDUCTANCE    YfSS  Full Conduction  300  YfS  Typical Operation  120  DRAIN CURRENT      IDSS  Full Conduction  60  GATE VOLTAGE      VGS(off)  Pinchoff voltage  ‐‐  VGS  Operating Range  ‐‐  GATE CURRENT      IGmax.  Operating  ‐‐  ‐IGmax.  High Temperature  ‐‐  IGSSmax.  At Full Conduction  ‐‐  ‐IGSSmax.  High Temperature  ‐‐      OUTPUT CONDUCTANCE  YOSS  Full Conduction  ‐‐  YOS  Operating  ‐‐    COMMON MODE REJECTION    CMR  ‐20 log | ∆V GS1‐2/ ∆VDS|  ‐‐    ‐20 log | ∆V GS1‐2/ ∆VDS|  ‐‐    NOISE    NF  Figure  ‐‐  en  Voltage  ‐‐      ‐‐  CAPACITANCE      CISS  Input  ‐‐  CRSS  Reverse Transfer  ‐‐  Click To Buy Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired TO-71 / TO-78 (Top View) Available Packages: LSU424 in TO-71 & TO-78 LSU424 in PDIP & SOIC LSU424 available as bare die Please contact Micross for full package and die dimensions Email: chipcomponents@micross.com Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.