ACE9050

ACE9050 System Controller and Data Modem Advance Information Supersedes January edition, DS4290 - 2.3 DS4290 - 3.0 December 1997 The ACE9050 provides the control and interface functions needed for AMPS or TACS analog cellular handsets. The device has been designed using Mitel Semiconductor submicron CMOS technology for low power and high performance. The ACE9050 contains an embedded microcontroller and peripheral functions. The controller is of the 6303 type with a Serial Communication Interface, Timer, ROM and RAM. The peripheral functions are: Data Modem, SAT Management, Serial Chip Interfaces, I 2C Interface, two Pulse Width Modulators, IFC Counter, Tone generator, I/O ports, Watchdog and Crystal Oscillator. Several power down modes are incorporated in the device as is a processor emulation mode for software and system development. An index to this data sheet is given on pages 49 and 50. FEATURES s Low Power, Low Voltage (3·6 to 5·0 V) Operation s 3·0V Memory Interface s Power Down and Emulation Modes s 6303R-type Microcontroller s AMPS or TACS Modem s Watchdog and Power Control Logic s SAT Detection, Generation and Loopback s 6K bytes RAM s Interface to FLASH and EEPROM Memories s 512 byte ROM Boot Block s I/O Ports for Keyboard Scanning s I2C Controller s Small Outline 100-pin package APPLICATIONS s AMPS and ETACS Cellular Telephones s Two-way Radio Systems RELATED PRODUCTS The ACE9050 is part of Mitel Semiconductor's ACE chipset, together with the following: ACE9020 Receiver and Transmitter interface ACE9030 Radio Interface and Twin Synthesiser ACE9040 Audio Processor OUTP2 [6] ICN LATCH1 OUTP2 [7] LATCH0 PWM2 DTFG EMUL IRQN POFFN VSS VSS VDD EXRESN C1008 MRN A15 A14 CPUCL R/W BAR DTMS PWM1 ECLK RXCD 75 76 LATC H3 SERV SYNTHCLK SYNTHDATA INRQ0 INRQ1 KPI [3] KPI [2] KPI [1] KPI [0] VDD VDD TXDATA TXSAT TXPOW AFC/RXDATA KPO [4] KPO [3] KPO [2] KPO [1] KPO [0] INP1[4] INP1[3] INP1[2] RXSAT 51 50 ACE9050 100 1 26 25 BA17 BA16 BA15 BA14 A13 A12 A11 A10 A9 A8 A7 A6 VDDM VSS VSS A5 A4 A3 A2 A1 A0 CSE2N CSEPN WEN OEN TESTN XIN XOUT DFMS AS BAUDCLK P1 [7] P1 [6] SCL/P1 [4] VSS VDD P1 [5] SDA/P1 [3] P1 [2] P1 [1] P1 [0] VSS D7 D6 D5 D4 D3 D2 D1 D0 FP100 Fig.1 Pin connections - top view. Pin 1 is identified by moulded spot and by coding orientation. See Table 1 for detailed pin descriptions. CLOCK & BAUD GENERATOR MEMORY INTERFACE WATCHDOG & POWER CONTROL INTERRUPT CONTROL I/O PORTS KEYPAD INTERFACE ACEBus INTERFACE 6303R MICROPROCESSOR UART (SCI) TIMER I/O PORTS 0·5K ROM 6K RAM I2C BUS INTERFACE 23PULSE WIDTH MODULATOR ORDERING INFORMATION Industrial temperature range. TQFP 100-lead 14314mm, 0·5mm pitch package (FP100) ACE9050D / IG / FP8N: trays and dry packed ACE9050D / IG / FP8Q: tape mounted and dry packed AMPS / TACS DATA MODEM IFC COUNTER SAT MANAGEMENT TONE GENERATOR ABSOLUTE MAXIMUM RATINGS Supply voltages VDD, VDDM Storage temperature Operating temperature Voltage on any pin 20·5V to 16V 255°C to 1150°C 240°C to 185°C VSS20·5V to VDD10·5V Fig.2 ACE9050 simplified block diagram ACE9050 SYNTHDATA SYNTHCLK DTFG LATCH0 LATCH1 LATCH3 72 73 82 80 78 75 SYNTHDATA SYNTHCLK DTFG LATCH0 ONRAD SINTSLEEP C1008 IRQSEND IRQREC PORT3[6] PORT4[7] PULSE WIDTH MODULATOR DAC1 DAC2 OUT2 [1] CONTROL PORT5 [0] } PORT5 [5:4] OUT2 [2] LATCH2 MUX #1 MUX CONTROL 98 ACE SERIAL INTERFACE }INTERRUPTS PWM #1 PWM #2 MRI IRW ID[7:0] OUTP2 [1]/ PWM1 OUTP2 [2]/ PWM2/ LATCH2 LSICOM0 LSICOM1 LATCH1 LSICOM2 LSICOM3 LATCH3 LSICOM4 LSICOM5 LATCH2 LSICOM6 MRI IRW ID[7:0] STR_WIDTH MUX #2 81 INTERNAL PORTS EXTERNAL PORTS OUT2 [7] 79 76 NOT BONDED TO MUX #2 TO MUX #1 TO CPUCL PIN POWERDET SERV 3 54, 53, 52 TO MUX #2 TO 6303 83 5 95 18-25 46-41 92,93 8 6 2 40,39,35-30 8 EMUL IP EMUL IP  REFER TO TEXT  FOR INDIVIDUAL  BIT FUNCTIONS   O/P IN EMULATION DATA INTERNAL ADDRESS PORT3 [7:0] PORT4 [7:0] PORT5 [7:0] PORT3 PORT4 PORT5 PORT3 PORT4 PORT5 O/P PORT2 OUT_PORT2 OUT2 [6] OUT2 [5:3] OUT2 [2] OUT2 [1] OUT2 [0] OUTP2 [7] OUTP2 [6] EMUL AS R/W D [7:0] A [7:0] A [13:8] A [15:14] BA [17:14] CSE2N CSEPN BUS INTERFACE EMUL ONLY EMUL IP EMUL DATA/AD IRW ID7:0 AD15:0 MRI IRW ID[7:0] LVN1 I/P PORT1 IN_PORT1 ID [7:0] INP1 [7] INP1 [6] INP1 [4:2] INP1 [1:0] INP1 [4:2] RAM 6016 BYTES (IRAM) AD [12:0] IRW IRAM IRQE EXT. INTERRUPTS IRQPRT4-RESET IRQPRT5-MASK IRQPRT6-READ 5 4 59-55 66-69 2 70, 71 INRQ [1:0] 50-47 29 28 4 MEMORY BANK SWITCHING EPROM BANK_SEL MRI IRW ID[4:0] AD[15:14] ROM 512 BYTES (IROM) BOOT BLOCK ID [7:0] AD [8:0] IRW IROM KEYPORT/CHIP ID KEYP R/W TO PORT KPOT O/P TRISTATE MRI IRW ID[7:0] ISDA ISCL KPO [4:0] KPI [3:0] IN_PORT1 OUT_PORT2 26 OEN IRQPRT4 DECODER WEN 27 IRQPRT5 IRAM EPROM IROM IROME    ACE9050  REGISTER  SELECTS    MEMORY  SELECTS  PORT4 [1] PORT3 [1] 6303 MICROPROCESSOR AND IRW READ/WRITE KERNEL AD15:O ID7:0 EMUL ICN COUNTER I/P RESET MRI CLOCK E PORT1 [7:0] PORT2 [4] PORT2 [3] BAUDCLK 8 7-9, 12-16 4 97 84 6 INTERRUPT IRQN 83BAUD P1 [7:0] DFMS/P2 [4] DTMS/P2 [3] IRQN BAUDCLK BAUD RATE CLOCK PORT5 [2] ENABLE RESET I2C I2C_ADDR I2C_DATA I2C_CNTR ISCL P1 [4] P1 [3] I2C_INTERRUPT IRQTX IRQWS IRQBISAT IRQRX IRQREQ IRQSEND 8·064MHz IRQTO BRG MRI IRW ID[7:0] IRQN I2C INTERRUPT IRQE (EXTERNAL INT.) IRQPRT0-RESET IRQPRT1-MASK IRQPRT2-READ MRI IRW AD[15:0] SLEEP BEEP ALARM RING GENERATOR (BAR) BAR 96 BAR BARENABLE BARHIGH BARLOW MRI ID[7:0] CLKBUS 126kHz I2C_STAT I2C_CCR I2C ISDA INT TESTN CLKBUS IRW ID[7:0]   INTERRUPT CONTROL    INTERRUPT SOURCE     MRI IRW ID[7:0] OUT2 [0] 94 90 99 2 3 1 TO WATCHDOG AND I2C 63 62 51 89 TO 6303 ICN (EMUL) AFC/RXDATA 77 60 ICN IFC COUNTER IFFREQ (2432/256) STIFCN (START/RESET) PORT3 [0] PORT3 [5]   INTERRUPTS   PORT4 [4] PORT3 [3] PORT3 [7] IRQRX IRQBISAT IRQWS IRQTX AFC/RXDATA NOMPLL MDMSLP ENMOD MODEM MODPRT0 MODPRT1 MODPRT2 ID [7:0] BARPORT TEST ACCESS ONLY TXDATA IRW MRI C1008 PORT5 [6] PORT4 [3] PORT3 [2] PORT5 P[1] CLOCK GENERATOR XOSC-PD TURBO ENSIS CLKENAB E (CPU CLOCK) CLKBUS C1008 LVN1 CPUCL 54kHz/450kHz VDD VDDM VSS 11, 64, 65, 68 38 10, 17, 36, 37, 86, 87 INP1 [6] 74 91 CPUCL/ OUTP2 [0] C1008 ECLK XIN XOUT TESTN WATCHDOG AND ATO REWD MASTER RESET WATCHDOG AND RESET LOGIC RESATO FILTER ATO LOGIC IRQTO MRI LVN1 SAT MANAGEMENT PORT4 [2] SELECT SAT GENERATOR SAT MUX SERV MRN TXDATA TXSAT RXSAT EXRESN RXCD TXPOW 100 61 85 POFFN CLKBUS IRW TESTN INP1 [7] POWDET PORT3 [4] UPOFFN Fig. 3 detailed block diagram of ACE9050 2 ACE9050 FUNCTIONAL OVERVIEW MICROPROCESSOR UNIT The processor unit is program compatible with the standard 6303R. It contains the following hardware: 8-bit CPU Serial Communication Interface: SCI (UART) 16-bit timer/counter 8-bit l/O port (P1) 2-bit l/O port (P2) The processor bus speed can be either 1·008 MHz or 2·016 MHz. An Emulation mode is provided whereby the internal 6303 is bypassed to allow software development on a standard 6303 In-Circuit Emulator (ICE). MEMORY The ACE9050 contains 512 bytes ofROM and 6144 bytes of RAM internally. The ROM code facilitates system initiation after a reset and the programming of FLASH memory via the 6303 SCI (UART). The Internal RAM area represents the total RAM requirement anticipated for a cellular phone. BUS INTERFACE and MEMORY BANK SWITCHING These blocks create the Data, Address and Control lines for the external memory. The external address bus is expanded from the standard 16 bits up to 18 bits by a banked addressing scheme. This increases the memory address space from 64K to 256K. Two programmable Chip Selects (CSEPN and CSE2N) are generated. The Memory Interface will operate down to 13V, allowing the use of low voltage memory parts. In Emulation mode the external processor controls the ACE9050 via the Bus Interface block. EXTERNAL PORTS The ACE9050 contains two Keypad Interface ports, two maskable external interrupts, and both Input and Output ports. These are in addition to the 6303 bidirectional Port1 and Port2. The Output port provides two high current outputs for driving LEDs. DECODER and INTERRUPT CONTROL The Decoder block memory maps ACE9050 register locations onto the processor’s address space. The Interrupt Control block handles both internal and external interrupt sources. These are fed into control logic allowing individual masking and reset by software. The Interrupt control logic output is internally connected to the 6303 IRQ and also drives an external pin. ACE SERIAL INTERFACE (SINT) and I2C Three serial interface protocols are supported: UART, I2C and ACEBus. The 6303 provides a UART interface via the SCI block. The ACE9050 I2C block provides an I2C interface with both Master and Slave capability. The ACEBus is designed for use with the ACE Chipset and has a data rate of just over 1MBits/sec. Three Latch pulse are available to target data at the relevant IC and control the ACE9030 Synthesiser. BEEP, ALARM and RING TONE GENERATOR (BAR) The BAR Generator is intended to drive an acoustic tone transducer. It has a programmable single digital pulse train output. MODEM and SAT MANAGEMENT The Modem provides two way data transfer and SAT management over the radio link between a base station and phone handset. AMPS and TACS data rates are supported . The Modem block contains: Digital Discriminator, Data Decoder and Word Synchronising hardware. Various modes can be selected by software. A squelch level is also set by software so that the quality of each data byte can be assessed. SAT detection and generation at the standard three frequencies 5970Hz, 6000Hz and 6030Hz is included. WATCHDOG and POWER CONTROL (ATO) The Watchdog function will provide an internal and external Reset if the processor does not make a write access to a defined address every 4 seconds. An Autonomous Time Out circuit (ATO) will drive the POFFN output low if Transmitter power is detected without Receiver power, independent of any processor operation. POFFN must be used in conjunction with external regulators to control power to the mobile handset. IF CONTROL COUNTER (IFC) The Intermediate Frequency Control (IFC) Counter is used as part of an AFC Loop. The IFC Counter provides a pulse after a set number of IF input pulses. The IFC Counter output is connected to the 6303 timer input and an external pin (ICN). TWIN PULSE WIDTH MODULATORS Two independently programmable Pulse Width Modulators (PWMs) are available. These provide digital output pulse trains, controllable by software. The output can be filtered externally to provide a DAC function. Typical applications are battery charging control and LCD contrast control. CLOCK GENERATOR The Clock Generator provides all the various internal and external clocks from a single 8·064 MHz source. The source can either be an external crystal or the ACE9030. 3 ACE9050 PIN DESCRIPTIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 Name TESTN XIN XOUT DFMS/P2 [4] AS BAUDCLK P1[7] P1[6] P1[4]/SCL VSS VDD P1[5] P1[3]/ SDA P1[2] P1[1] P1[0] VSS D7 D6 D5 D4 D3 D2 D1 D0 OEN WEN CSEPN CSE2N A0 A1 A2 A3 A4 A5 VSS VSS VDDM A6 A7 A8 A9 A10 A11 A12 A13 BA14 BA15 BA16 BA17 RXSAT INP1 [2] INP1 [3] INP1 [4] KPO [0] KPO [1] KPO [2] KPO [3] KPO [4] AFC/RXDATA TXPOW TXSAT TXDATA VDD VDD Type I I O I/O I O (I) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O Block CLK/WDATO CLK CLK CPU BINT BAUD CPU CPU CPU / I2C CPU CPU / I2C CPU CPU CPU BINT BINT BINT BINT BINT BINT BINT BINT DEC DEC MEMB MEMB BINT BINT BINT BINT BINT BINT Description Connect to VDD Crystal connection CMOS input: 8·064 MHz Crystal connection CPU Port2 bit 4 or Serial interface (SCI) output Address strobe (Latch Address during Emulation) Baud Rate Gen. output for Emulation (lnput in test mode) PORT 1 of CPU PORT 1 of CPU PORT 1 of CPU/I2C SCL Ground Digital Supply PORT 1 of CPU PORT 1 of CPU/I2C SDA PORT 1 of CPU PORT 1 of CPU PORT 1 of CPU Ground Data bus (and Emulation Address A7 Input) Data bus (and Emulation Address A6 Input) Data bus (and Emulation Address A5 Input) Data bus (and Emulation Address A4 Input) Data bus (and Emulation Address A3 Input) Data bus (and Emulation Address A2 Input) Data bus (and Emulation Address A1 Input) Data bus (and Emulation Address A0 Input) Output Enable Write Enable C/S External EPROM C/S External EEPROM Address bus Address bus Address bus Address bus Address bus Address bus Ground Ground Digital Supply for Memory Interface (pins18-35, 38-50) Address bus Address bus Address bus (Input during Emulation) Address bus (Input during Emulation) Address bus (Input during Emulation) Address bus (Input during Emulation) Address bus (Input during Emulation) Address bus (Input during Emulation) Address bus (Extended Address: From Bank Select Register) Address bus (Extended Address: From Bank Select Register) Address bus (Extended Address: From Bank Select Register) Address bus (Extended Address: From Bank Select Register) Received SAT input Bit 2 Input Port1 Bit 3 Input Port1 Bit 4 Input Port1 Keypad scan output/output port Keypad scan output/output port Keypad scan output/output pon Keypad scan output/output port Keypad scan output/output port 54/450kHz IF input fromACE9030 Power detect from transmitter SAT Output TACS / AMPS Modem Output Digital Supply Digital Supply Internal PU None None PU PU None None None None None None None None None None None None None None None None None None None None None None None None None None None None Cont… O O O (I) O (I) O (I) O (I) O (I) O (I) O O O O I I I I O O O O O I I O O BINT BINT BINT BINT BINT BINT BINT BINT MEMB MEMB MEMB MEMB MODEM EPORT EPORT EPORT EPORT EPORT EPORT EPORT EPORT IFC/MODEM WDATO MODEM MODEM Table 1 4 ACE9050 Pin 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name KPI [3] KPI [2] KPI [1] KPI [0] INRQ1 INRQ0 SYNTHDATA SYNTHCLK SERV LATCH3 OUTP2 [6] ICN LATCH1 OUTP2[7] LATCH0 OUTP2[2]/PWM2/ LATCH2 DTFG EMUL IRQN POFFN VSS VSS VDD EXRESN C1008 MRN A15 A14 CPUCL/OUTP2 [0] R/W BAR DTMS OUTP2 [1]/PWM 1 ECLK RXCD Type I I I I I I O O I O O O (I) O O O O I/O I O (I) O Block EPORT EPORT EPORT EPORT EPORT EPORT SINT SINT WDATO SINT EPORT IFC SINT EPORT SINT PWM SINT BINT/CPU CPU WDATO Description Keypad scan input/input port Keypad scan input/input port Keypad scan input/input port Keypad scan input/input port External Interrupt (also Bit1 Input Port1) External Interrupt (also Bit0 Input Port1) SynthBus Data Line SynthBus 126kHz Clock 1 = Service Mode Latch, programmable length. (To ACE9030, LATCHC pin) Output Port2 Bit 6: High Current Driver IF Counter Output for Emulation (input in Test mode) Latch O/P (To ACE9030 receiver Interface, LATCHB pin) Output Port2 Bit 7: High Current Driver Latch O/P (To ACE9040, LEN ) Output Port2 Bit 2/Pulse Width Modulator #2 Output/ SynthBus Latch O/P. Bidirectional serial inter-chip data, to/from the ACE9030 1 = CPU Emulation Mode CPU Interrupt for Emulation (input in Test mode) Power On/Off Ground Ground Digital Supply External reset output 1·008MHz Clock for ACEBus, ACE9030 and ACE9040 0 = Chip reset Address input for Emulation only Address input for Emulation only 8.064MHz clock/Out Port 2 bit 0 Read/Write (Input during Emulation) Beep, Alarm, Ring Tone Output CPU Port 2 bit 3 or Serial interface (SCI) input Output Port 2 Bit 1/Pulse Width Modulator #1 Output Processor Clock (Input during Emulation) Carrier detect from RX Internal PD PD PD PD PD PD None PU None PD None PU PU None None None None O O I I I O O (I) O I/O O O (I) I WDATO CLK WDATO BINT BINT CLK/EPORT BINT BAR CPU PWM CLK WDATO Table 1 (continued) ABBREVIATIONS BAR Beep, Alarm and Ring tone generator BAUD Baud Rate generator BINT Bus Interface MEMB Memory Bank switching CLK Clock generator CPU 6303 microprocessor unit DEC Decoder EPORT External Port I2C IFC MODEM PWM SINT WDATO PU PD I2C interface IF Control counter AMPS/TACS Modem Pulse Width Modulator and MUX Serial Inter-chip interface Watchdog/Autonomous Time Out Internal Pullup resistor present Internal Pulldown resistor present UNUSED INPUTS Input or bidirectional pins must have a suitable pullup or pulldown reststor if they are configured as inputs, with no external drive. Some inputs have an internal pullup or pulldown resistor of the order of 100kΩ; this value is suitable if the pin is not subject to excessive noise or residual current greater than 15µA. If the pins shown in Table 2 are not used in the system, an external resistor will be required. Pin 4 7 8 9 12 13 14 DFMS P1 [7] P1 [6] P1 [5] P1 [4] P1 [3] P1 [2] Name Pin 15 16 51 52 53 54 60 Name P1 [1] P1 [0] RXSAT INP1 [2] INP1 [3] INP1 [4] AFC_IN/RXDATA Pin 61 74 82 91 97 100 Name TXPOW SERV DTFG (Requires programming resistor) MRN DTMS RXCD NOTE: P1 [7:0], DFMS and DTMS are configured as inputs upon reset. Table 2 5 ACE9050 ELECTRICAL CHARACTERISTICS The Electrical Characteristics are guaranteed over the following range of operating conditions (unless otherwise stated): TAMB = 240°C to 185°C, VDD = 3·6V to 5·5V, VDDM = 3·0V to 5·5V (note 2) DC CHARACTERISTICS Value Characteristic Supply current (Normal clock) Supply current (Turbo clock) Supply current (Static) Input high voltage Input low voltage Output high voltage Output low voltage High current drive O/P source (pins 76 & 79) High current drive O/P sink (pins 76 & 79) Tristate leakage current Input leakage current Pullup/down resistance Symbol IDDNOR IDDTUR IDDSB VIH VIL VOH VOL IOHHI IOLHI IOZ IIN RIN Min. Typ. 3·5 6·0 150 0·7VDD 20·5 0·8VDD 0·2VDD 0·92VDD 0·2 0·4 10 6 10 9 1 1 150 Max. Units mA mA µA V V V V mA mA µA µA kΩ Conditions 1·008MHz ECLK, VDD = 5V 2·016MHz ECLK, VDD = 5V No clock & osc. powered down 35 IOH = 2mA, VDD > 3·6V IOL = 1mA, VDD < 3·6V IOH = 2mA, VDD > 3·6V IOL = 1·5mA, VDD < 3·6V VDD > 3·6V VDD = 3·6V VDD > 3·6V VDD = 3·6V No Pullup/down cell No Pullup/down cell VDD = 5·5V, TAMB = 25°C NOTES 1. The DC Characteristics Min. and Max figures are guaranteed by test. 2. The voltage on VDDM must be less than or equal to VDD. AC CHARACTERISTICS (CLOCKS and CRYSTAL) Value Characteristic Oscillator frequency Oscillator external I/P AC coupling capacitor External resistor External capacitors Crystal ESR Startup time Radio serial control bus Microprocessor clock Microprocessor clock Clock output Watchdog time out Autonomous time out Symbol fOSC fIP CCOUPLE R1 C1, C2 XTALESR tSU C1008 ECLK1 ECLK2 CPUCL WDTO ATOTO Min. Typ. 8·064 8·064 10 1000 22 120 5 1·008 1·008 2·016 8·064 4 30 Max. Units MHz MHz nF kΩ pF Ω ms MHz MHz MHz MHz s s Conditions External crystal CMOS/800mV sine I/P AC coupled Sine input Crystal oscillator Crystal oscillator (note 1) Crystal oscillator Crystal oscillator Normal clock Turbo clock Output enabled Normal Mode Normal Mode 470 NOTES 1. Refer to crystal manufacturer for exact deatils. 6 ACE9050 TIMING DIAGRAMS NORMAL MODE PROCESSOR INTERFACE Read Cycle tECLK ECLK ADDR tCSLCLL CS tCLLADI tCLLCSH tADVCSL tOELCLL OEN tCLLOEH tDAVCLL DATA tCLLDAI Fig.4 ACE9050 6303 Read cycle timing diagram Timing Cycle Conditions Input clock frequency, XIN = 8·064MHz. Worst case Timings: TAMB = 240°C to 185°C, VDD = 13·6V to 15·5V Typical timings: TAMB = 125°C, VDD = 13·75V Normal clock Description Symbol Min. Typ. 992 4 972 492 Max. Min. Turbo clock Typ. 496 4 480 245 Max. Units ns ns ns ns ns ns ns ns ns Cycle time Address valid to CS low Chip Select set-up time OEN set-up time Data set-up time Data hold time OEN hold time CS hold time Address hold time tECLK tADVCSL tCSLCLL tOELCLL tDAVCLL tCLLDAI tCLLOEH tCLLCSH tCLLADI 2 940 485 35 0 0 9 7 9 985 495 1 24 18 4 45 42 2 445 240 35 0 0 9 7 9 490 248 1 24 18 4 45 42 Table 3 ACE9050 6303 Read cycle timing 7 ACE9050 Write Cycle (Normal Mode) tECLK ECLK ADDR tADVWEH CS tWEHADI tADVCSL WEN tCSLWEH tWELWEH DATA tWEHCSH tADVDALZ tDAVWEH tWEHDAI Fig. 5 ACE9050 6303 Write cycle timing diagram Timing Cycle Conditions Input clock frequency, XIN = 8·064MHz. Worst case timings: TAMB = 240°C to 185°C, VDD = 13·6V to 15·5V Typical timings: TAMB = 125°C, VDD = 13·75V Normal clock Description Symbol Min. Typ. 992 853 140 840 364 368 473 5 140 Max. Min. Turbo clock Typ. 496 420 72 415 181 183 225 4 72 Max. Units ns ns ns ns ns ns ns ns ns ns Cycle time Address valid to end of Write Address hold time Chip enable set-up time WE pulse width Data valid set-up time Data hold time Address valid to data low Z Address valid to chip select WE high to CS high tECLK tADVWEH tWEHADI tCSLWEH tWELWEH tDAVWEH tWEHDAI tADVDALZ tADVCSL tWEHCSH 835 125 825 363 365 120 451 0 127 862 151 860 371 371 487 10 163 395 63 390 173 177 60 203 0 66 427 93 425 184 192 239 9 105 Table 4 ACE9050 6303 Write cycle timing 8 ACE9050 EMULATION MODE PROCESSOR INTERFACE Read and Write Cycles tCYC ECLK AS tECLRWV R/W INVALID STABLE INVALID tECLADV A[15:8] tECLADI tADVASL A[7:0]/D[7:0] AD[7:0] tASLADI tDAV DA[7:0] tDAI Fig.6 ACE9050 6303 Emulation mode Read/Write cycles timing diagram Emulation Mode Timing Cycle Conditions Input clock ECLK frequency = 1·008MHz (Normal clock), 2·016MHz (Turbo clock), TAMB = 125°C, VDD = 15V 610% Normal clock Description Symbol Min. Typ. 992 250 250 0 60 30 50 1 80 1 0 20 20 50 1 80 1 Max. Min. Turbo clock Typ. 496 160 160 Max. Units ns ns ns ns ns ns ns ns ns ns Cycle time Read/Write settling time Address delay time Address hold time Address to latch set-up time Address to latch hold time Data set-up time - WRITE Data hold time - WRITE Data set-up time - READ Data hold time - READ tCYC tECLRWV tECLADV tECLADI tADVASL tASLADI tDAV-W tDAI-W tDAV-R tDAI-R Table 5 6303 Emulation Mode Read/Write cycles timing 9 ACE9050 SERIAL INTERFACE BLOCK ACEBus Read and Write Timings C1008 DATA1 76 LATCH1 54 32 10 76 DATA2 54 32 10 76 DATA3 54 32 10 DTFG Fig.7 ACEBus Transmit Data flow C1008 12 DTFG DATA3 76 LATCH1 34 5 PREAMBLE 54 32 10 76 RESULT1 54 32 10 76 RESULT2 54 32 10 Fig.8 ACEBus Receive Data flow tCLH tCLL tDAVCLH C1008 tCLHDAI tCLLDAZ DTFG D1 [7] D1 [6] D3 [2] D3 [1] D3 [0] t CL H D A SYNTHDATA LATCH0/1/3 tCLHLAH tPW Fig.9 ACEBus Transmit timing diagram C1008 DTFG tDAVCLL tCLLDAI Fig.10 ACEBus Receive timing diagram 10 ACE9050 ACEBus Timing Cycle Conditions Input clock frequency, XIN = 8·064MHz. Worst case Timings: TAMB = 240°C to 1 85°C, VDD = 13·6V to 15·5V Typical timings: TAMB = 125°C, VDD = 13·75V Value Characteristic TRANSMIT Clock high to Data bus driven Data set-up time Data hold time Clock high to Latch high Latch width 0 and 1 Latch width 3 Clock low Clock high Clock high to data line tristate RECEIVE Data set-up time Data hold time Symbol Min. Typ. Max. Units Conditions tCLHDA tDAVCLH tCLHDAI tCLHLAH tPW01 tPW3 tCLL tCLH tCLHDAZ tDAVCLL tCLLDAI 491 488 491 491 491 0·099 496 12·59 496 496 0 14 14 5 ns ns ns ns ns ms ns ns ns ns ns Programmable width Table 6 ACEBus Read and Write timings SynthBus (Note: The SynthBus is not required when the ACE9050 is used as part of the ACE Chipset) tD17VCLH SYNTHCLK tCLH tCLL SYNTHDATA D1-7 D1-6 D3-1 D3-0 tDAVCLH DTFG tCLHDAI LATCH tCLHLAH tLAH Fig.11 SynthBus timing diagram SynthBus Timing Cycle Conditions Input clock frequency, XIN = 8·064MHz. Worst case Timings: TAMB = 240°C to 185°C, VDD = 13·6V to 15·5V Typical timings: TAMB = 125°C, VDD = 13·75V Value Characteristic Symbol Min. >0 3·9 4·0 4·97 952 3·99 3·93 Typ. Max. 7·84 Units µs µs µs µs ns µs µs Conditions First data bit set-up time Data bit set-up time (except first) Data hold time Clock high to latch high Latch width Clock low Clock high tD17VCLH tDAVCLH tCLHDAI tCLHLAH tLAH tCLL tCLH Table 7 SynthBus timing 11 ACE9050 INTERNAL REGISTERS AND RESET STATUS ACE9050 REGISTERS Name IN_PORT1 OUT_PORT2 PORT3 BARPORT IRQPRT2 IRQPRT6 MODPRT0 MODPRT1 MODPRT2 KEYP LSICOM4 LSICOM5 LSICOM6 PORT4 PORT5 BANK_SEL RESERVED BARHIGH BARLOW BARENABLE BRG I2C_ADDR I2C_DATA I2C_CNTR I2C_STAT I2C_CCR DAC1 DAC2 LSICOM0 LSICOM1 LSICOM2 LSICOM3 STR_WIDTH KPOT REWD RESAT0 IRQPRT0 IRQPRT1 IRQPRT4 IRQPRT5 R/W R R/W R/W R R R/W R/W R/W R/W R R R R/W R/W W W W W W R/W R/W R/W R W W W W W W W W W W W W W W W Address 22-23 24-25 26-27 28-29 2C-2D 2E-2F 30-31 32-33 34-35 36-37 3A-3B 3C-3D 3E-3F 40-41 42-43 44 45 50 51 52 53 54 55 56 57 57 5B 5C 60-61 62-63 64-65 66 67 68-69 6A-6B 6C-6D 70-71 72-73 74-75 76-77 Description External IP Port External OP Port Internal Port Test-Do Not Access Read Int Interrupts Read Ext Interrupts Modem Modem Modem Key Pad IP and Chip ID ACE Interface RX1 ACE Interface RX2 ACE Interface RX3 Internal Port Internal Port Bank Select Do Not Access BAR On BAR Off BAR OE UART Baud select I2C I2C I2C I2C I2C PWM 1 data PWM 2 Data ACE Interface TX1 ACE Interface TX2 ACE Interface TX3 ACE Interface Control Latch 3 Width O/P type for KPO Reset Watchdog Reset Time Out Reset Int Interrupts Mask Int Interrupts Reset Ext Interrupts Mask Ext Interrupts D7-0 reset condition EE0EEE00 Notes 1, 6 2 3, 7 00000000 00000000 111X111 XXXX1111 00000000 00000000 00000000 0010EEEE EEEEEEEE EEEEEEEE EEEEEEEE 6 4, 6 4, 6 4, 6 00000010 00000011 XXX00000 00000000 00000000 XXXXXX0 XXXXX000 00000000 00000000 00000000 11111000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 XXX11111 XXXXXXXX XXXXXXXX 7 7 5, 7 7 7 7 00000000 (Reset) 00000000 (Masked) XXXX0000 XXXX0000 7 7 Table 8 ACE9050 ports NOTES: 1. Bit 6 is set (1) in SERV mode. Bits 1 and 0 are set (1) if the corresponding interrupt is enabled (inverse of IRQPRT6). 2. Bit 4 (UPOFFN) is set (1) in SERV mode, but reset (0) in Normal mode. 3. Bit 4 is not used and should be treated as undetermined. 4. The LSICOM4, 5 and 6 ports values will depend on the DTFG input. 5. In SERV mode the Boot block will set up BRG to 00000100 (9600 Baud). 6. E = Depends on external input. 7. X = Not used or undetermined. 12 ACE9050 ACE9050 6303 REGISTERS Name DDR1 DDR2 PORT1 PORT2 TCSR FRC_HIGH FRC_LOW OCR_HIGH OCR_LOW ICR_HIGH ICR_LOW RMCR TRCSR RDR TDR RAMCR R/W W W R/W R/W R/W R/W R/W R/W R/W R R W R/W R W R Address 00 01 02 03 08 09 0A 0B 0C 0D 0E 10 11 12 13 14 Description Data Dir Register P1 Data Dir Register P2 Data Port 1 Data Port 2 Timer Control/Status Free Run Counter MSB Free Run Counter LSB O/P Compare Reg MSB O/P Compare Reg LSB I/P Capture Reg MSB I/P Capture Reg LSB Rate & Mode Control Tx/Rx Control and Status Rx Data Tx Data Not Used D7-0 reset condition 00000000 00000000 EEEEEEEE 010XXXXX Notes 1 1 2 3, 4 00000000 00000000 00000000 11111111 11111111 00000000 00000000 XXXX0000 00100000 00000000 00000000 00000000 4, 5 6 7 Table 9 6303 ports NOTES: 1. Both ports set to Input (0 = I/P, 1 = O/P) 2. E = external input 3. 6303 internally set to Multiplexed mode 4. X = Unused or undetermined 5. Set to 00001100 in SERV mode 6. Set to 00111010 in SERV mode 7. This register Read only in the ACE9050 MODES OF OPERATION The ACE9050 has three independent modes of operation: Normal, Emulation, Service. Mode Emulation Service Normal Pin EMUL SERV Enabled High High Default mode Pin D[7:0] A[13:8] A[15:14] ECLK R/W AS IRQN ICN Normal mode Function Type Data Address Not used 6303 Clk Not used Not used Not used Not used I/O O I O O I O O Emulation mode Function Data and A[7:0] I/P Address I/P A[13:8] Address I/P A[15:14] ACE9050 Clock I/P Read/Write strobe Address Latch strobe 6303 Interrupt 6303 Timer P2 [0] Type I/O I I I I I O O Table 10 Modes of operation 1, NORMAL MODE This is intended to be the mode of operation when the ACE9050 is fully commissioned in the application. The internal 6303 Microprocessor is used and the Boot block ensures the program counter goes to the beginning of the ROM code area after initialisation. In Normal mode various blocks can be powered down to save current, and the processor can be programmed to run at 1·008MHz or 2·016MHz. Table 11 Normal and Emulation mode functions 3. SERVICE MODE This mode is intended for system development and phone service, where reprogramming of a FLASH ROM device is required. The two areas that are affected by Service mode are: 1. The Watchdog and Autonomous Time Out (ATO) resets are inhibited. This is intended for software development work. The POFFN pin (85) is initially programmed to be a 1 by the ROM code in this mode. 2. The internal ROM code facilitates loading of a program into the RAM area from the SCI. This program would normally be a FLASH loading program. The SCI may then be used to load new object code into the FLASH memory of a system. 2. EMULATION MODE This mode is intended for system and software development work. In Emulation mode the Internal 6303 processor is made redundant and its function is replaced in the system by an external 6303 processor. This is to facilitate using a generic 6303 In-Circuit Emulator (ICE) for software development. Table 11 shows the functionality of external pins that change in this mode. This is to enable all of the internal functions of the ACE9050 to operate as they would in Normal mode. In Emulation mode the external processor or ICE must be set up to operate in Multiplexed mode. This mode is only intended for use at room temperature. 13 ACE9050 The ROM code has a time out function so that if a valid start code is not detected on the SCI normal code operation will begin. The ROM code is fully described in the Internal ROM Boot Block section. Name VDD VSS XTAL External E NMI IRQ RES Port2 [0] Port2 [1] Port2 [2] Port2 [3] Port2 [4] Port1 [7:0] Addr [15:8] D/A [7:0] R/W AS STBY I/O I I I I I I/O* I/O* I/O I/O I/O O I/O O O Description Internal power supply Internal Ground Not connected Not Used (System Clock Driven into E directly) System Clock IP Not used: Tied to VDD Connected to Interrupt Control block and IRQN pin Connected to Internal Reset MRI Internally connected to IFC Counter Not connected Internally connect to Baud Clk External Pin (SCI I/P or Port2) External Pin (SCI O/P or Port2) External Pin (Port1 I/0 Access) Connected to internal address Bus Internally connected to Buses Connected to internal logic and R/W pin Connected to internal logic Standby mode disabled = VDD 4. TEST MODE Test mode increases the efficiency of volume testing of the part. Pin 1, TESTN, should be hardwired to VDD. 5. POWER DOWN MODES To reduce overall power consumption, selective power down of various blocks is available under software control. In the power down state each block will go to a predetermined logic state. The following power reduction features are included: Bus Interface (CSEPN = 1 and Address = 3FFF) 8·064 MHz external Clock Off 1·008 MHz external Clock Off AMPS/TACS Modem power down ACE Serial Chip Interface Power down CPU Sleep Mode Crystal Oscillator Off 1MHz/2MHz Bus speed FUNCTIONAL DESCRIPTIONS 1. ACE9050 6303R DESCRIPTION General Description The embedded processor in the ACE9050 is functionally equivalent to a generic 6303R micro. This data sheet outlines the functionality of the embedded processor, detailing its operation with the internal peripheral circuitry. It is not intended as a programmers guide for a 6303. If further information is required the following publications are recommended: *Port2 bits 0 and 1 must be configured as inputs in the 6303 to use the IFC and Baud rate generator functions. clocks. Table 12 Generic 6303 I/O mapping HITACHI 8-bit single-Chip Microcomputer Data Book Sept.1989 Motorola Microprocessors Data Manual Macro Assemblers Reference Manual, Motorola Semiconductors MC68MASR(D). The 6303 is an 8-bit processing unit which has a completely compatible instruction set with the 6301. It has object code upwardly compatible with the HD6300, HD6801 and HD6802. The ACE9050 has 6016 bytes of internal RAM (the 6303R has 128 bytes). Other features are: a Serial communications interface (SCI or UART), a 16-bit timer, 8-bit I/O port and a 5-bit I/O port (only 2 are bonded out from the ACE9050). The bus speed can be configured to 1·008 in Normal mode or 2·016MHz in Turbo mode. The ACE9050 has an Emulation mode whereby its internal 6303 is bypassed and the peripheral functions may be driven externally by a standard 6303 ICE. Port 1 This is an eight bit I/O port with the direction of each bit being defined by the data direction register DDR1 as given in Table 13. The Port can be accessed for read and write via the Port1 register. The output buffers have tristate capability, being high impedance when used as inputs. When the processor is reset these are high impedance. Two pins (Bits 3 and 4) associated with this port are also used as I/0 from the I2C interface on the ACE9050. This is configured by Port 5 bit 2. The 6303 is internally configured to mimic Multiplexed mode of operation, so this port cannot be configured to output the lower address bits. The ACE9050 has dedicated pins for this purpose. Associated Registers Name DDR1 Bits [7: 0] Port 1 Bits [7:0] Description 1: Sets corresponding Port line to output 0: Sets corresponding Port line to input Read and Write access to Port 1 ACE9050 6303R Pin Description The ACE9050 6303 is embedded in a kernel which interfaces to the rest of the circuitry. Table 12 describes the internal connections to the ACE9050 6303. In Emulation mode, none of the output pins drive the internal buses. Clock The CPU Clock is provided from the Clock Generator Circuit in the ACE9050. This clock is either 1·008MHz or 2·016MHz. It is not further divided down in the 6303, so this clock frequency is the same as the processor bus speed. Refer to the Clock Generator section for details of how to configure the internal Table 13 Port 1 associated registers Port 2 This is a five-bit I/O port with the direction of each bit being defined by the data direction register DDR2. Only bit 3 and bit 4 are connected to external pins. This allows access to the I/O port and Serial Interface functions. Bit 0 and bit 2 are internally connected to the IFC and Baud clock. They must be configured as inputs to use these functions. Bit 0 and bit 2 are not externally accessible. 14 ACE9050 The ACE9050 has an additional Output Port 2, which is separate from the 6303 Port 2. Associated Registers Name DDR2* Bits [4:0] Port 2* Bits [4:3] Description 1: Sets corresponding Port line to output 0: Sets corresponding Port line to input Read and Write access to Port 2 Serial Communication Interface (SCI or UART) The processor contains a full-duplex asynchronous Serial Communications interface. It consists of a transmitter and receiver which operate independently but with the same data format and rate. Both parts communicate with the CPU via the data bus and to the outside world via Port 2. Interrupts generated can be individually masked. The receiver can be sent to ‘sleep’ by software. No receive interrupts are generated during a message in this state. The Baud rate can be generated within the ACE9050 6303 or the ACE9050 can provide a baud rate generator and selection register external to the processor block. This allows the following standard baud rates to be programmed: 600,1200. 2400, 4800 or 9600. The hardware consists of four registers: an 8-bit control/ status register, 4-bit mode select, an 8-bit receive data and an 8bit transmit data register. Bit R/W Name 7 6 5 4 3 R R R R/W R/W R/W R/W R/W Description *The TRCSR register overrules these registers. Table 14 Port 2 associated registers Programmable Timer The ACE9050 6303R contains a 16 bit programmable timer which may measure the period of an input waveform, as with a standard 6303R. This counter runs from the ECLK. The counter cannot generate an output waveform. The input to the timer is internally connected to the IFC counter for the AFC loop function. The timer hardware consists of an 8-bit status and control register, a 16-bit free running counter and a 16-bit input capture register. TCSR (Timer Control and Status Register) The Control and Status register has three flags: Input capture, Output Compare Match and Timer Overflow. Each flag has an associated interrupt enable. The other two bits in the register are for control of the output level and input edge select. The bits are described in Table 15. Bit R/W Name 7 R ICF Description Transition of appropriate type occurred on input (ICN). Cleared by read of Input Capture register Match between Free Running Counter and Output Compare Register* Timer overflow. Cleared by read of counter. Enable an ICF interrupt Enable an OCF interrupt* Enable Timer overflow interrupt 0 = Negative edge on ICN trigger ICR 1 = Positive edge on ICN trigger ICR Output level* Condition No Data Good Data RX Framing error Overrun error Bit 7 Bit 6 0 1 0 1 0 0 1 1 RDRF RX Data Register Full* ORFE Overrun/Framing Error* TDRE TX Data Register Empty RIE RE TIE TE WU RX Interrupt Enable: Enables an interrupt for both Bit 7 and Bit 6 RX Enable. This sets Port2 bit 3 to Input regardless of the DDR2 TX Interrupt enable: Bit 5 will generate an Interrupt TX Enable: This sets Port2 bit 4 to Output regardless of DDR2 Wake Up: Set by software and cleared by hardware.** 2 1 0 * ** 6 5 4 3 2 1 0 R R R/W OCF TOF EICI Overrun is where new data is placed in the Receive register before the old data has been read. Framing Error is where the bit counter is not synchronised with the boundary of the byte in the Received bit stream defined in Table 17. The Wake Up mode is intended for systems where more than one Processor is on the UART link, and is addressed by the first byte of data. If the address is incorrect the processor can disable the interrupts and effectively ignore the word. Table 16 TRCSR: Transmit/Receive Control Status Register bit descriptions R/W EOCI R/W ETOI R/W IEDG R/W OLVL *As the timer cannot generate an output these bits are considered nonfunctional in the ACE9050. Table 15 TCSR bit descriptions FRC: Free Running Counter The FRC is a 16-bit ReadWrite counter; Data can be read from or written to it. The register has extra hardware to load and save both bytes of the counter simultaneously when a double byte store instruction is used. The counter is incremented by the processor clock. Reading from the counter does not affect it. ICR: Input Capture Register The ICR is a16-bit Read register which holds the value of the Free Running Counter when a transition is detected on ICN, i.e. the IFC Counter Output. NOTE: Bits 7 and 6 are cleared by reading the Status register, followed by reading the Received Data register Table 17 RMCR Transfer Rate/Mode Control Register The mode select register controls the clock source and setup. This is a write-only register. The processor can use an internally divided down processor clock to give the Baud clock. The Baud rate division ratio can be set to a value from 16 to 4096. However, this could lead to non-standard Baud rates so the ACE9050 provides a separate Baud rate generator.The bit functions of this register are described in Table 18. 15 ACE9050 Bits Value Description Not used Clock Control mode SCI disabled Use processor Clk for Baud rate Not used Use ACE 9050 Baud rate generator Speed Select (Bits 3: 2 = 01) E416 E4128 E41024 E44096 mode is fully supported by the ACE9050 6303. This mode is entered by execution of the SLP instruction. Escape is via an interrupt or reset . [7: 4] XXXX [3: 2] 00 01 10 11 00 01 10 11 Address, Data and Memory Control The Address, Data and control lines from the ACE9050 6303 connect to a kernel which interfaces to the on chip bus structures. The Bus Interface block provides suitable buffering to drive required buses externally, and configure the I/0 for Emulation mode. [1: 0] Interrupt Processing The interrupt processing in the ACE9050 6303 is essentially the same as a generic 6303, the exception being NMI, which is not available. The IRQN is internally connected to the I2C interrupt, the External Interrupt and the Internal interrupt blocks. These blocks combine all the possible sources for interrupts into one line which is connected to IRQN. This is also connected to a pin for use in Emulation mode. The IRQN is maskable. The interrupt mask bit in the Condition Code Register must be zero for the CPU to respond to the Interrupt request, as with a generic 6303. The Interrupt Vector Memory map is shown in Table 20. Vector MSB LSB FFFE FFEE FFFA FFF8 FFF6 FFF4 FFF2 FFF0 FFFF FFEF FFFB FFF9 FFF7 FFF5 FFF3 FFF1 Table 18 RMCR Transfer Rate/Mode Control register Bits [7:0] (Data) Description RDR: Received Data Register Read received bits. First bit received is placed in bit 0, last in bit 7 TDR: Transmit Data Register Write register to store bits before serial transfer from Transmit shift register, bit 0 first [7:0] (Data) Priority 1 2 3 4 5 6 7 8 Interrupt RES TRAP Software Interrupt (SWI) IRQN ICF (Timer Input Capture) OCF (Timer OP Compare) TOF (Timer Overflow) SCI (UART) Table 19 Receive and Transmit Data registers In Normal Mode the SCI should be initialised before operation. This means writing to the mode select and the control/status register. In Service Mode the SCI is configured for 9600 baud, and the receive interrupt enabled. When the transmitter is first initialised it will send a ten-bit preamble of ‘1’s before being ready to transmit data. Once initialisation is complete data transmission enabled by writing to the transmit data register. TDRE is set to 0. A start bit is transmitted (0). Next the eight bit data starting at bit0 are transmitted followed by a single stop bit (1). The hardware sets the TDRE bit in the TRCSR register. If the CPU does not transfer another word the output goes high. The receiver is configured during initialisation. If enabled and a start bit is detected (0), the next nine bits will be sampled approximately at the centre of each bit. If the ninth bit is a 1 the data is transferred to the Receive data register. The RDFR bit is set in the TRCSR register. If the ninth bit is not a 1 or the receive data register is full then the ORFE bit is set to indicate an error. A read of the TRCSR register followed by a read of the Received data register (RDR) will clear these flags. RAM Control Register (RAMCR) This register is read only in the ACE9050. Bit 6 (RAME) is set to zero: this is because the RAM on the ACE9050 is external to the 6303 block. Bit 7 (STBY) is also set to zero by the ACE9050 because Standby mode is not supported. Table 20 Interrupt vector memory map Error Processing An interrupt is generated when an undefined op-code is fetched, or when an instruction is fetched from an impossible address. This is in the range 0000- 007F for the ACE9050 (0000001F for a standard 6303). 2. INTERNAL ROM BOOT BLOCK The ROM code provides a boot block for the ACE9050. Following a reset condition code execution will always start in the internal ROM. The internal ROM data flow depends on the condition of the SERV Input and thus the mode of operation of the ACE9050. The operation flow of the IROM is shown in Fig. 12 and described in the following sections: Normal Mode 1. Read serial data on ACEBus DTFG line 2. Configure ACE9030 Reference dividers via ACEBus. 3. Set the program counter to the beginning of external ROM (1800H). Operating Modes The Generic 6303R has two modes: Multiplexed and nonMultiplexed, where the mode is selected externally using P2[0], P2[1] and P2[2]. This is not required on the ACE9050, where the mode is set to mimic multiplexed internally when the reset (MRN) is released . The ACE9050 processor has two fundamental modes of operation: Emulation and Normal, which are described in the MODES OF OPERATION section. Low Power Consumption Modes The generic 6303 Standby mode is not supported by the ACE9050 6303. The STBY pin is not accessible. The Sleep Service Mode 1. 2. 3. 4. Read serial data on ACEBus DTFG line Configure ACE9030 Reference Dividers via ACEBus Configure the UART to RX Wait 2 seconds for special code on UART - if not found go to step 3 of Normal Mode 5. Load Data from UART into RAM 16 ACE9050 6. Pass control to Program loaded in RAM 7. Map Interrupt Vectors to RAM space. 8. The RAM program can then Program a FLASH memory via the UART. Steps 1and 2 - Both Modes The ACE Chipset offers the flexibility of using one of three different crystal frequencies: 12·8, 14·85 or 15·36 MHz. The chosen crystal can be used to generate all the system clocks and local oscillator frequencies required in a cellular phone application. The ACE9050 must detect what crystal is being used and set up the correct value for the OSC8 dividers in the ACE9030. This is handled in the Internal ROM. Upon Reset the ACE9030 sets the OSC8 for a 15·36 MHz Crystal, so the ACE9050 is not clocked faster than 8·064 MHz. The system designer must set up the DTFG input (the Radio Serial Interface, pin 82), using an external resistor of approximately 10kΩ. The crystal frequency determines where the resistor is terminated, as shown in Table 21. Upon reset the ACE9050 Internal ROM reads the DTFG input and programs the ACE9030 OSC8 accordingly. Crystal 12·8MHz 14·85MHz 15·36MHz Serial Data RXed 000000 0 < Data < FFFFFF FFFFFF Resistor from pin 82 to: VSS (Gnd) A1 (pin 31) VDD where: nn = Number of bytes ( xx1pp1dd1cc ) in record. pppp = Load address dd = data bytes, 1 to 16 xxxx = Name of proqram (ASCII coded) eeee = Program entry address cc = checksum calculated from [2552sum(pp)1sum (dd)1 sum (xx)1sum (ee)1nn)] MOD 256 When the ‘s9’ is read in from the End of File Record, the code will jump to the reset vector. This is mapped to 0FFE by the IROM. The RAM program will then begin execution as for a reset. The last 6 characters of the record file (nneeeecc) will be received while the program is running. (b) Binary dump file This format is for the binary representation of the code, not a proprietary binary format code. The start code for this format is ‘OB’ ASCII (ie 30H, 42H) . First two bytes are the start address pointer. The next two bytes are the end address pointer11. The next bytes are the data bytes. These are loaded consecutively from the start to the end address. When the last data byte is received the program counter will go to the loaded code start address pointer. Step7-Interrupt Vector table The Internal ROM will map the 6303 Interrupt vector table to an address space in RAM so the loaded program can deal with interrupts as shown in Table 22. In general only the SCI interrupt is required for a Flash Loading program. Vector address 0FFE 0FEE 0FFC 0FFA 0FF8 0FF6 0FF4 0FF2 0FF0 Interrupt Reset Trap Not Implemented SWI Software interrupt IRQN ICF Timer Input compare OCF Timer Output compare TOF Timer overflow SCI Table 21 Step 3 - Normal Mode Program code in the external EPROM at address 1800H is started. The Internal ROM resides at the top of the processor address space FE00H - FFFFH. Obviously the main program requires access to this space for Interrupt vectors. The Internal ROM is deselected by setting PORT4 [1] to zero. It is recommended that any external program does this quickly and always before enabling any Interrupt sources. Step 3 - Service Mode The Internal ROM will initialise the 6303 SCI (UART) and set up the Baud rate generator to 9600 Baud. The SCI is initialised to the following: Receiver On Transmitter ON Receive Interrupt enabled 9600 Baud rate from ACE9050 Baud Rate Generator The Receive interrupt will remain enabled after the IROM code execution. The UART is always configured for 8-bit data transfer, no parity and one stop bit. Steps 4, 5 and 6 - Service Mode When in service mode the ACE9050 can download a program from the SCI to RAM. To achieve this the first code (start code) must be sent down to the SCI within 2 seconds of releasing Reset. The boot block code will write the subsequent code into RAM. Two code formats are supported: (a) Motorola S- Record format (b) Binary dump (a) Motorola S-Record Format The start code for this format is ‘OA’ in ASCII ( i.e. 30H, 41H). s0nnppppxxxxxxxxxcc First Record in file s1nnppppdddddddddddddcc Data record with 16-bit address Table 22 RAM Area Reserved for IROM Operation The IROM code itself requires a small amount of RAM during its operation. This area must not be used for storage of the RAM program. RAM Reserved area: 080H to 100H Fig. 12 shows the data flow for the internal ROM. 3. DECODER The Decoder logic creates the memory map for system containing the ACE9050. Internally, it maps the ACE9050 registers, RAM and ROM onto the System Memory map. External ROM is also mapped onto the available address space by the Decoder, but the situation can be complicated by the Bank Address switching circuitry. Refer to Table 23 on the following page for details of memory mapping. Note that the ACE9050 contains Memory Banked Switching circuitry. Refer to the section 4 ‘BUS INTERFACE AND MEMORY BANKING’ below for details. The Decoder also creates suitably timed Output Enable and Write Enable signals (refer to Figs. 4 and 5) for parallel read and write cycles to external devices. · · s9nneeeecc End of file record (nn = 3) 17 ACE9050 Address (hex) 0000-001F 0020-007F 0080-17FF 1800-7FFF 8000-BFFF C000-FDFF FE00-FFFF Description 6303 Registers Internal ACE9050 Registers RAM Non Banked external ROM Banked external ROM Non-Banked external ROM Internal / External ROM External Pins OEN Output Enable, active low (pin 26) This signal is used when accessing external memory or other suitable devices. Driving the Output Enable input of external memory reduces the possibility of data bus contention conditions. WEN Write Enable, active low (pin 27) This output is used to latch data into external memory or other suitable devices. Table 23 Associated Registers IROM Port 4 bit 1 The ACE9050 internal ROM (IROM) is mapped to the top 512 bytes of the address space allowing it to provide interrupt handler routines. Upon reset the IROM select is enabled. It can and should be disabled by software before the interrupts are enabled. Bit 1 IROM Description Address range FE00H-FFFFH: 0 = External ROM 1 = Internal ROM (reset state) RESET RELEASED PC TO 6303 RESET VECTOR FFFE ACE9050 RESET IROM SELECTED (PORT4 [1]–1) START IROM CODE Table 24 000000 READ DATA FROM DTFG FFFFFF 0< DATA 6045 The buses can be used for data transfer between any ICs that have the appropriate interface logic; however, in a system using the ACE Chips the following words are valid on the ACEBus: ACE9030 Sleep Word Normal (ADC Values Read) Set-up Synth Word A Synth Word B Synth Word C Synth Word D Synth Dummy word (Low Noise Mode) ACE9040 Operating mode Initialising Mode 0 Initialising Mode 1 Handsfree For more information refer to the ACE9030 and ACE9040 data sheets. The ACEBus consists of a 1·008MHz clock, a bidirectional data line and 4 latch outputs. The clock and data lines are common, while the latch outputs are connected as follows: Latch 0: Control (ACE9040, LEN) Latch 1: Radio interface section (ACE9030, LATCHB) Latch 2: Internally connected to MUX #2 Latch 3: Synthesiser section (ACE9030, LATCHC) Valid data is transmitted in a stream of 24 continuous bits. At the end of the last bit the relevant latch is activated. This will latch the data into the target device. The data line will become tristate after the data transfer so that data may be received from a bus driver. The block contains eight ACE9050 registers. Three are for serial data transmit, three for receive and two are for bus control. The block also contains interrupt generating circuitry. The SynthBus contains a data line Synthdata, clock line Synthclk and associated Latch2, which is multiplexed with OUT2[2] and PWM2. The clock to ACE Serial Interface block can be disabled to reduce the overall power consumption of the ACE9050. Turning off this clock will disable the ACE Serial Interface but will not turn off the C1008 clock. Table 84 SAT Transmitter The ACE9050 has an on-chip SAT generator which can generate 5·97kHz, 6kHz, or 6·03 kHz signals. The selection is made via bits SCCTX [1:0] in MODPRT0. Alternatively the received SAT can be looped around and re-transmitted. The ACE9050 provides a multiplexer so either source can be selected under software control via the SATMUX bit in PORT4. The generator circuit consists of a series of preset counters running from the system clock. The ACE9050 makes no allowance for varying the phase of the regenerated SAT tone as this not a requirement for current AMPS or TACS protocols. When the Received SAT is looped around the ACE9050 only buffers the incoming SAT signal on RXSAT before feeding it to the TXSAT output pin. Associated Registers SCCTX[1:01 MODPRT0 [5:4] Write SCCTX [1:0] 00 01 10 11 Generated SAT tone (Hz) 5970 6000 6030 No SAT generated Table 85 SATMUX PORT 4[2] SATMUX 0 1 TX SAT source Internally generated SAT RX SAT External Pins C1008 (pin 90) Refer to Clock Generator Section. This clock is used for data transfer. In the ACE9030 and ACE9040 it is also used for clocking other functions so care must be exercised in turning this clock off. DTFG (pin 82) Bidirectional data line. The ACE9050 clocks out data loaded into the 3 registers. Data is clocked in and out of the ACE9050 on the falling edge of C1008. LATCH 0 (pin 80) Latch pulse used to target data transfer. In a system using the ACE chip set Latch0 is connected to the LEN input of the ACE9040. The latch is nominally a 500ns pulse. LATCH 1 (pin 78) Latch pulse used to target data transfer. In a system using the ACE chip set Latch1 is connected the ACE9030 Radio Interface (LATCHB). The latch is nominally a 500ns pulse. LATCH 3 (pin 75) Latch pulse used to target data transfer and optimise the performance of the synthesiser. In a system using the ACE chip Table 86 3. ACE SERIAL INTERFACE BLOCK General Description The ACE Serial Interface contains two serial interfaces: The ACEBus and the SynthBus. The ACEBus is used to distribute data to and from ICs in the ACE chipset. The SynthBus is redundant when using the ACE chipset. The ACE9050 contains the Master Transmitter/Receiver unit for the ACEBus. The ACE9040 and ACE9030 contain slave units. The bus is used for programming the devices into the required state. This will be required when the phone is powered up, and during phone operation. The ACE9030 can also transmit ADCs values to the ACE9050 on the ACEBus. 39 ACE9050 set Latch3 is connected to the LATCHC input of the ACE9030 Synthesiser. The lenqth of the latch can be varied and the latch can be set permanently high. Latch 3 can be used with the SynthBus, but is fixed at 500ns. SYNTHCL (pin 73) SynthBus clock line at nominally 126kHz. This is not a continuous clock. It is only activated when data transfer is required. SYNTHDAT (pin 72) SynthBus Data line. Contains valid data from the ACE9050, or is set to zero. LSICOM 3 (continued) Bit 3 2 1 0 Name Not used Not used Latch 1 Latch 0 Function Must be 0 Must be 0 Latch 1 enabled for data transfer Latch 0 enabled for data transfer Table 90 (continued) Bit 7 Name Go CL Function 0 = No data transfer 1 = Begin data transfer Must be 0 Transmitter Section The transmitter consists of five write registers, interrupt and latch generating logic, clock divider and timer, and three shift registers connected in series. These form the 24-bit message that is sent out on DTFG. The most significant bit of LSICOM 0 is transmitted first (refer to Fig. 7). Associated Registers Write Register LSICOM 0 LSICOM 1 LSICOM 2 SINTSLEEP Port 4 [7] Bit 7 Name Function Bits 7:0 7:0 7:0 Description First byte to transmit Second byte to transmit Third byte to transmit 6 5 4 3 2 1 0 Not used Must be 0 Not used Must be 0 Latch 3 Latch 2 Latch 3 enabled for data transfer Latch 2 enabled for data transfer Not used Must be 0 Not used Must be 0 Table 91 Valid bit fields for SynthBus Sending Data To begin the transmitting sequence the appropriate word has to be written to LSICOM 3. If a Latch 3 is required for the ACEBus a non-zero value must be written to STR_WIDTH prior to writing the control word in LSICOM 3. When LSICOM 3[7] (GO) is set, the clock to the serial shift registers is enabled. Data from LSICOM 0, 1 and 2 are clocked out on the falling edge of C1008. After the 24 data bits have been clocked out, the appropriate latch is generated on the next fallinq edge of C1008. At the same time as the latch the IRQ-SEND interrupt is generated internally. This is fed to the interrupt control block where it can be masked. The LSICOM 3 will then be reset, so as to be ready for the next data transfer. Table 87 SINTSLEEP 0 = ACE Serial Interface enabled 1 = ACE Serial Interface powered down Table 88 STR_WIDTH Write The pulse width of Latch 3 is programmable between 99·2µs and 12·6ms, with 99·2µs increments. This register only works with the ACEBus, not the Synthbus. Bits 6:0 Description Pulse duration in increments of 100 C1008 periods. This register is decremented when a pulse is generated. Writing a value of 0 in this register terminates the pulse. Receiver Section The receiver consists of three serial registers which can be read via LSICOM 4, 5 and 6. It also contains a counter, clocking and interrupt generating circuitry. Associated Registers Read Register LSICOM 4 LSICOM 5 LSICOM 6 Bits 7:0 7:0 7:0 Description First byte received (ACE9030 preamble) Second byte received (ACE9030 result 1) Third byte received (ACE9030 result 2) Table 89 LSICOM 3 Write This register is the control register. This is used to define the mode of the data transfer, select which latch to activate and also is used to initiate the transfer. Bit 7 6 5 4 Name Go CL ANS Function 0 = No data transfer 1 = Begin data transfer Must be 1 0 = No Answer request 1 = Answer request Table 92 Receiving Data In order to receive, LSICOM 3[5] (ANS) must be set. After the transmission sequence, data on the DTFG line is clocked into the receiver on the falling edge of C1008. This process begins on the fifth negative clock edge after the latch pulse, to allow a response time from the slave (Fig. 8). After 24 clock cycles the complete word will have been clocked into the ACE9050. The data in the shift registers is latched into the three read registers. At the same time the IRQREC interrupt is generated. The IRQ-SEND interrupt is generated in the receive sequence with the relevant latch in the same way as for a transmit only sequence. Not used Must be 0 Table 90 Valid bit fields for ACEBus data transfer 40 ACE9050 PROGRAMMING The Strobe width will be a minimum of 100µs, However data can be transmitted to the other slave units during the Latch3 high time. Alternatively the Latch3 may be terminated prematurely by writing 0 into the STR_WIDTH register. This may only be done after the IRQ-SEND interrupt, to ensure the latch is not terminated prematurely. The ONRAD bit (PORT 3 [6]) can be used to keep the Latch 3 line high. Care must be taken when enabling Latch3 in this way so that spurious data is not clocked into the synthesiser. By setting the STR_WIDTH register to a suitably large value and enabling ONRAD before the STR_WIDTH time expires, the Latch 3 line can be permanently asserted. The STR_WIDTH time begins when the data transfer has completed. SynthBus Transfers Latch 3 Data Transfer (1) Write Data to LSICOM 0 to 2 (2) Write LSICOM3 Control word: GO 1 CL 0 ANS 0 0 L3 1 L2 0 0 0 Programming Constraints The programming of the interface is relatively straightforward when used with the ACE Chipset. However, the following constraints apply: (a) To activate a Latch 3 transfer on the ACEBus, the STR_WIDTH register must be written to with a non-zero value prior to writing to LSICOM3 [7] (GO) set. (b) After writing to LSICOM3 with the GO bit set, registers LSICOM0 to 3 must not be written for 25µs or until an IRQSEND Interrupt has been generated. (c) After writing to LSICOM3 with the GO and ANS bits set, LSICOM0 to 3 must not be written to until 6 clock cycles after an IRQ-SEND. LSICOM3 cannot be written to with bit 7 (GO) set until 55µs or the IRQ-REC interrupt has been generated. This is because the DTFG will contain the slave data until this time. (d) A value greater than 0 must not be written to the STR_WIDTH register preceding a LATCH0, 1, 2 transfer or a Latch3 transfer with the SynthBus. (e) The ACEBus and the SynthBus cannot be used simultaneously. (3) Service IRQ-SEND interrupt if enabled Latch 2 Data Transfer (1) Write Data to LSICOM 0 to 2 (2) Write LSICOM 3 Control word: GO 1 CL 0 ANS 0 0 L3 0 L2 1 0 0 Programming Sequences ACEBus Transfers Latch 0 Data Transfer (1) Write Data to LSICOM0,1 and 2 (2) Write to LSICOM3 control word: GO 1 CL 1 ANS 0 0 0 0 L1 0 L0 1 (3) Service IRQ-SEND interrupt if enabled 4. IFC COUNTER The IFC counter is used as part of the Automatic Frequency Compensation loop, in conjunction with 6303 timer. The IFC counts a predetermined number of periods of the AFC_IN/ RXDATA signal. By timing this duration the frequency of the input can be determined. In a system using the ACE chipset this input frequency will be 54kHz. The Number of periods counted can be either 256 or 2432. This will give measurement times over a period of approximately 5ms or 45ms when using the ACE chipset. Other input frequencies are possible, but would give different time periods and thus accuracy could be affected. (3) Service IRQ-SEND interrupt if enabled Latch 1 Data Transfer (a) Without answer request (1) Write Data to LSICOM0, 1 and 2 (2) Write LSICOM3 Control word: GO 1 CL 1 ANS 0 0 0 0 L1 1 L0 0 (3) Service IRQ-SEND interrupt if enabled (b) With answer request (1) Write Data to LSICOM 0, 1 and 2 (2) Write LSICOM 3 Control word: GO 1 CL 1 ANS 1 0 0 0 L1 1 L0 0 External Signals AFC/RXDATA Input (pin 60) This signal also feeds to the AMPS/TACS modem. This pin can be directly connected to the AFCOUT pin of the ACE9030, when this device is being used. ICN Output (pin 77) This output is used in emulation mode only. It is output of the IFC counter, which should be connect to the Emulator 6303 PORT2 [0]. It is internally connected to the ACE9050 6303. Associated Registers Register STIFCN PORT 3 [5] IFFREQ P0RT 3 [0] Bit 0 1 0 1 Description Reset counter* Enable counter 2432 counts 256 counts (3) Service IRQ-SEND interrupt if enabled (4) Wait for IRQ-REC interrupt (5) Read data from LSICOM 4, 5 and 6 Latch 3 Data Transfer (ACEBus) (1) Write Data to LSICOM 0 to 2 (2) Write Strobe Width to STR_WIDTH(non-zero value) (3) Write LSICOM 3 Control word: GO 1 CL 1 ANS 0 0 0 0 L1 0 L0 0 *The counter must be reset before it can be enabled Table 93 (4) Service IRQ-SEND interrupt if enabled 41 ACE9050 TCSR 6303 Timer Control Status Register Register used to control and read the status of th 6303 Timer block. Refer to ‘6303 Processor Unit’ section of Hitachi or Motorola data book for full details . ICR 6303 Input Capture register 16 bit read only register used to hold the value of the free running counter captured when the proper transition of the ICN input occurred. Refer to ‘6303 Processor Unit’ section or Hitachi or Motorola data book for full details. Two Pulse Width Modulators are available in the ACE9050. These provide CMOS type outputs whose average high time can be set by software. External components can be used to filter the output and give a mean DC level. The values chosen for these components depend on the ripple and response time required in the application. Typical applications for such outputs are LCD contrast control and battery charging control. The PWM outputs are fed to output multiplexers; the corresponding external pin function is selected by software. The PWM circuits are designed to minimise the low frequency components of the output wave form. The PWM works on a 254µs cycle time, with 0·992µs pulse duration. The number of pulses is programmed using the appropriate register. The hardware ensures that the pulses are distributed as evenly as possible within a cycle. This is shown in Fig. 24 for some simple programming examples. With suitable external components the following formula can be used to obtain the mean DC level of a PWM output: VMEAN = (DAC[7:0]4256)3VDD Detailed Operation Once the IFC counter is set the next rising edge of the AFC/ RXDATA input pin will generate a negative transition on ICN. The IFC counter will then count the required number of transitions and create a positive edge on ICN at the end of the count period. The program has to control the 6303 timer in such a way that first the negative and then the positive transition of ICN is captured. The software can then calculate the difference between the two readings, which will give the elapsed time. Programming Example Initialise (a) Set IFFREQ to the determine the required Count (b) Reset STIFCN bit. This bit is reset by a hardware reset or by writing 0. It is not reset by the counter finishing execution. (c) Ensure the 6303 TCSR register is configured so as to capture a falling edge on ICN. Begin Count (a) Write 1 to STIFCN (b) Read the ICR after the negative transition on ICN (c) Set TCSR register so as to capture a rising edge on ICN (Within 5 or 45 ms) End of Count (a) When a capture has occurred the ICR register can be read. Calculate From the difference between the two ICR values captured, the elapsed time for the count period can be calculated. It is then possible to estimate the offset of the system crystal and cancel out this error using the ACE9030 DACs. If the crystal is off frequency it will have little effect on the timer accuracy. It will however affect the main synthesiser as the error is multiplied by the divider ratio set in the main synthesiser. The absolute error is then mixed down to appear on the 54kHz directly. External Pins OUT2[1]/PWM1 Output (pin 98) Selection for the source for this pin is made via the PWMlMUX bit in PORT5. This pin is also described in the External Ports and Multiplexer section. OUT[2]/PWM2/LATCH[2] Output (pin 81) Selection for the source for this pin is made via the OUT2.2_SEL bits in PORT5. This pin is also described in the External Ports and Multiplexer section. Associated Registers Write Register DAC1 PORT DAC2 PORT Bits 7:0 7:0 Description Number of output pulses in a cycle period Number of output pulses in a cycle period Table 94 5. PULSE WIDTH MODULATOR NUMBER LOADED 32 64 128 1·008 MHz CLOCK Fig. 24 Pulse Width Generator output 42 ACE9050 PORT5 Read/Write (Note 1) Bits Name Description DATA BUS KPOT 5 5:4 OUT2.2_SEL 00 = OUT_PORT2[2] (Note 2) 01 = PWM2 10 = Latch 2 11 = Not valid 0 PWM1MUX 0 = PWM1 1 = OUT_PORT2[1] (note 2) DATA BUS KEYP WRITE 5 5 59-55 KPO [4:0] NOTES 1. These register bits are also described in the External Ports and Multiplexer section. 2. Reset state. Table 95 KEYP READ 4 66-69 6. BEEP ALARM RING (BAR) TONE GENERATOR The ACE9050 provides a Beep Alarm and Ring Tone generator unit. This provides a digital output pulse train. The high and low time can be programmed with software. It is thus possible to vary the output tone frequency, period and volume. The pulse train can also be disabled whereupon the output will be set low. Within the system this output can be used to control a buzzer driver. [3:0] KPI INPUTS [7:4] IDENT KPI [3:0] 010 External Pin BAR Output (Pin 96) CMOS output which is determined by the state of the registers in the BAR block (BARHIGH, BARLOW and BARENABLE). Associated Registers Write Register BARHIGH BARLOW BARENABLE Bits 7:0 7:0 0 Description BAR ON time BAR OFF time 0 = BAR output low 1 = BAR output pulsing Fig. 25 Keyport configuration Output Port The output port has five individual outputs, which can be used as scanning outputs connected to a keyboard matrix, or can be used for other general purposes . External Pins KP0[4: 0] Outputs (Pins 59: 55) The state of these outputs are defined by the respective bits in the internal registers KEYP and KPOT. Associated Registers KEYP Write Keypad output port register Bits 4:0 Description Sets or clears associated bit in Output Port register Table 96 Programming The two programmable 8-bit registers determine the ON and OFF times in steps of approximately 8µs (7·9µs). The maximum ON and OFF times are approximately 2ms each (2·02ms). The following formula is used to calculate the actual times: BAR ON Time = (2562BARHIGH[7:0])37·93µs BAR OFF Time = (2562BARLOW[7:0])37·93µs Table 97 KPOT Write Output Port driver configuration Bits 4:0 Description 0 = Output driven to level set by relevant KEYP bit 1 = Output tristate 7. KEYPAD INTERFACE AND CHIP IDENTITY The Keyboard interface consists of a 5-bit output port, a 4-bit input port and associated registers to read, write and configure the ports (see Fig. 25). Alternatively these ports can be used for general I/O. The output port drive configuration can be set via software to provide the system designer with full flexibility. The port has tristate output buffers, controlled by the KPOT register. By programming KEYP and KPOT appropriately the outputs can be configured to drive in the following ways: High impedance Driving logic output (high or low) Open drain Open source. Table 98 Programming Examples The following bit patterns thus yield the following output configurations: KEYP Write 0 1 0 0 1 1 X KPOT 0 0 0 1 0 1 1 Output 0 1 0 Z 1 Z Z Description Logic drive Logic drive Open drain Open drain Open source Open source High impedance Table 99 43 ACE9050 Input Port The Keyboard interface has four inputs. These inputs can also be used as general inputs. The upper four bits of this port are hard wired and provide a means of identifying the present variant of the ACE9050. Level 0 1 Description Receive signal absent Receive signal present External Pins KPI[3:0] 4-bit Input port (pins 66 to 69) The state of this input port can be obtained by reading the respective bits in the internal register KEYP. Associated Registers KEYP [7:0] Read Keypad input port register Bits [7:4] [3:0] Description Chip Identity code (See Table 101) Reads the level of the associated input on KPI [3:0] Table 102 A typical source for the receive signal strength would be the RSSI output from the IF Strip. However this will need to be compared to a predefined level and the logical output fed to the ACE9050. The ACE9030 provides an ADC, programmable threshold register and comparator for this purpose via RXCD. TXPOW TX power level input (pin 61) Digital input to monitor the presence of a Transmitted signal, as shown in Table 103. Level 0 1 Description Transmit signal absent Transmit signal present Table 100 Identity code Bits 7 6 5 4 Read back 0 Read back 0 Read back1 Read back 0 Description Table 103 A typical source for the transmit signal presence would be a detector in the TX path. However this will need to be compared to a predefined level and the logical output fed to the ACE9050. The ACE9030 provides two Op Amps that may be used for this purpose. One may be used as a buffer/amp and the other as a comparator in conjunction with a DAC, which is also on the ACE9030. The level of TXPOW can be directly determined via IN Port1[7], POWDET. POFFN Power Off output (pin 85) This pin is intended to be used to control external power regulators for the phone. It is reset low by an MRN reset. The software and the ATO then control the state of POFFN: Table 101 8. AUTONOMOUS TIMEOUT (ATO) The Autonomous Time Out circuit (ATO) is provided to facilitate an automatic power down of the phone in the event of the phone entering an illegal transmitting state. The ATO block requires external functions to implement its intended operation. The ATO monitors the status of the RXCD and TXPOW inputs; in a typical system these will indicate the presence of received and transmitted signals, respectively. If a transmitted signal is detected, without the presence of a received signal the ATO circuitry can change the state of the output pin, POFFN. This should be used to remove power from the phone system via external power control circuitry. The main block in the ATO is a 30-second counter. It is reset by an accepted processor write to the RESATO register. The state of the external inputs RXCD and TXPOW determine whether the processor access is accepted. If the processor does not attempt to access the register, or access is blocked for a period of 30 seconds, the ATO Timer expires and an ATO reset occurs. The software can set the state of POFFN directly via Port 3[4]. The ATO reset can only drive POFFN output low. POFFN is not cleared by a Watchdog reset, so that this type of reset will not power down the phone. When in Service mode the ATO Reset is disabled and the IROM code sets POFFN to logic 1. Associated Registers RESATO Reset ATO: Write Bit Description Write access resets the 30s ATO timer. Table 104 UPOFFN Port 3 Bit 4 of this register sets the state of the POFFN output, as shown in Table 105. Bit 4 Name UPOFFN Description 0 = POFFN output set low 1 = POFFN output set high External Pins RXCD Receive Path Carrier Detect Input (pin 100) Digital input to indicate the presence of a carrier in the receiver part of the Radio as shown in Table 102. Table 105 44 ACE9050 Block Descriptions ATO Timer The ATO timer is a 30 second resetable counter. If the ATO counter reaches 30 seconds, an ATO Reset is generated. The counter is reset by the following actions: (a) External MRN Reset (b) Accepted Processor Write to the RESATO register The levels of the two external signals RXCD (pin 100) and TXPOW (pin 61) are used to determine whether a processor Write to RESATO is accepted or not, as shown in Table 106. RXCD 0 0 1 1 TXPOW 0 1 0 1 RESATO access Accepted Denied Accepted Accepted clean up before power is removed. The processor cannot prevent the ATO reset at this stage. The ACE9050 design assumes that the ATO Reset will remove power from the phone system. If the system is designed in such away that power is not removed from the ACE9050 the POFFN pin is only guaranteed to stay low for approximately 1 second. The state of the internal circuitry is not guaranteed after an ATO Reset. RXCD Filter The purpose of the filter is to smooth out short glitches in the RXCD input. The filter waits for 1 second of RXCD becoming high before the filter output is asserted. Once the output has been asserted for more than 1 second, if the RXCD goes low for more that 1 second the filter output will go low. The filter hardware consists of a 10-bit up-down counter clocked at 492Hz. If the RXCD input is high the counter increments. If it is low the counter decrements. Thus, assuming the counter begins at zero, with a fixed high on the RXCD the counter’s MSB will assert after 1 second and will overflow after approximately 2 seconds. When the counter overflows and RXCD is high it will continue to hold the maximum count value and conversely, when it reaches zero and RXCD is low, it will contain zero. The MSB of the counter is the filter output which is fed to the ATO. Programming Guide Although the processor only needs to access the ATO register once every 30 seconds to prevent the reset, the access should occur more frequently. This would ensure a spurious error condition unfortunately timed would not cause an ATO turnoff. Servicing the ATO with the Watchdog would be the sensible approach. NOTE: The CPU cannot tell whether a hardware access has been accepted or not. Table 106 The RXCD input is filtered prior to use in the ATO Timer logic by the RXCD Filter. The ATO timer is NOT reset by Watchdog reset. ATO Reset When the AT0 Times Out the ATO reset circuit is trigered and the following occurs: (a) A Time Out Interrupt is generated. (b) If the POFFN is high it will be driven low. The Time Out interrupt is generated at least 1 second before the POFFN is driven low. This is to give the processor time to 45 ACE9050 PROGRAMMER’S GUIDE TO CONTROL PORTS AND REGISTERS IN_PORT 1 External Inputs Read Bit 7 6 5 4 3 2 1 0 Name POWDET SERV 0 INP1 [4] INP1 [3] INP1 [2] INRQ [1] INRQ [0] Description Level of TXPOW pin Level of SERV pin Read back 0 Level of INP1 [4] pin Level of INP1 [3] pin Level of INP1 [2] pin Level of INRQ [1] pin (interrupt or INP1 [1]) Level of INRQ [0] pin (interrupt or INP1 [0]) PORT 4 ACE9050 Configuration Read/Write Bit 7 6 5 4 3 2 1 0 Name SINTSLEEP Not used Not used NOMPLL TURBO SATMUX IROM Not used Description 0 = ACE serial interface active* 1 = Sleep Read back 0 Read back 0 0 = Clock synchronised to data* 1 = Clock free running 0 = 1·008MHz processor bus* 1 = 2·016MHz processor bus 0 = TXSAT selected* 1 = RXSAT selected 0 = External ROM 1 = Internal ROM* - Table 107 OUT_PORT 2 External Outputs Read Bit 7 6 5 4 3 2 1 0 Name OUTP2 [7] OUTP2 [6] Reserved Reserved Reserved OUTP2 [2] OUTP2 [1] OUTP2 [0] Description Inverted drive to OUTP2 [7] pin Inverted drive to OUTP2 [6] pin Should be set to 0 Should be set to 0 Should be set to 0 Drive level of OUTP2 [2] pin when selec ted by Port 5 Drive level of OUTP2 [1] pin when selec ted by Port 5 Drive level to CPUCL pin when CPUCL is disabled in Port 3 * Reset state in Normal mode Table 110 PORT 5 ACE9050 Configuration Read/Write Bit 7 6 Name XOSC Description Logic state Not used Power down oscillator [5:4] OUT2.2_SEL Multiplex control 3 2 1 0 Table 108 PORT 3 ACE9050 Configuration Read/Write Bit 7 6 5 4 3 2 1 Name Description Logic state 0 = No action* 1 = Modem fully enabled 0 = Latch 3 pulse generated* 1 = Latch 3 set to 1 0 = IFC counter reset* 1 = Enable IFC counter 0 = POFFN set to 0* 1 = POFFN set to 1 0 = Active* 1 = Sleep 0 = OUT2 [0]* 1= 8·064MHz Clk 0 = CSEPN active for address FFFFH* 1 = CSEPN inactive for address FFFFH 0 = 256 period count* 1 = 2432 period count 0 = Active* 1 = Power down 00 = OUT2 [2]* 01 = PWM 2 10 = Latch 2* Not used SEL_I2C Select I2C 0 = I2C reset* 1 = I2C enabled CLKENAB CLK enable 0 = C1008 low 1 = C1008 enabled* PWM1MUX Multiplexer 0 = PWM 1 1= OUT_PORT 2 [1]* control ENMOD Modem on ONRAD ACE serial interface STIFC Start IFC count UPOFFN Power control MDMSLP Modem mode ENSIS CPUCL pin SLEEP Sleep * Reset state in Normal mode Read/Write Bit 7 6 Name MDRESN A_TN Table 111 MODPRT 0 Modem Control Function 0 = Reset Modem* 1 = Modem enabled 0 = TACS Modem* 1 = AMPS Modem Bits 5: 4 = SAT generator 00 = 5·97kHz* 01 = 6·00kHz 10 = 6·03kHz 11 = No SAT transmitted 0 = TX output disabled* 1 = TX output enabled Cont… [5:4] SCCTX 1 [0] 0 IFFREQ IFC counter 3 ENAMI * Reset state in Normal mode 46 * Reset state in Normal mode Table 112 Table 109 ACE9050 MODPRT 0 Modem Control (continued) Bit 2 1 0 Name SYNDET ENWS VC_CCN Function Bit 0 = Capture mode* 1 = Sync mode 0 = Word sync disabled* 1 = Receiver will resynchronise 0 = Control channel* 1 = Voice channel [7:5] 4 3 2 1 0 Name CS BA17 BA16 BA15 BA14 Description Not used Chip Select: 1 = CSE2N, 0 = CSEPN Banked address A17 Banked address A16 Banked address A15 Banked address A14 BANK_SEL Bank Select Register Write only * Reset state in Normal mode Table 112 (continued) Table 116 MODPRT 1 Modem Control Write Bit 7 6 5 4 Name MDMTST TXDINV RXDINV LF1_2 Function Must always be set to 0 0 = TX data not inverted* 1 = TX data inverted 0 = RX data not inverted* 1 = RX data inverted 0 = Discriminator enabled* 1 = Discriminator bypassed (Test) Set the squelch threshold level ACE9050 REGISTERS BY BLOCK 6303 Name DDR 1 DDR 2 PORT 1 PORT2 TCSR 1 FRC_HIGH FRC_LOW ICR_HIGH ICR_LOW RMCR TRCSR RDR TDR R/W Addr W W R/W R/W R/W R/W R/W R R W R/W R W 00 01 02 03 08 09 0A 0D 0E 10 11 12 13 Description Data Dir register P1 Data Dir register P2 Data Port 1 Data Port 2 Timer Control/Status Free run counter MSB Free run counter LSB IP Capture register MSB IP Capture register LSB Rate and mode control TX/RX Control and Status RX data TX data [3:0] SQLEV [3:0] * Reset state in Normal mode Table 113 MODPRT 1 Modem Status Read Bit 7 6 Name B_I Function Not used 0 = Busy/Idle bit = 0 1 = Busy/Idle bit = 1 Bits 5: 4 = SAT received 00 = 5·97kHz 01 = 6·00kHz 10 = 6·03kHz 11 = No SAT received Number of data bits in a word that have exceeded the preset Squelch threshold Table 117 ACE9050 Internal Ports Name PORT 3 PORT 4 PORT 5 R/W Addr R/W R/W R/W 26 40 42 Description ACE9050 configuration ACE9050 configuration ACE9050 configuration [5:4] SCCRX [1:0] [3:0] SQRX [3:0] Bus Interface Name BANK_SEL Table 118 R/W Addr W 44 Description Bank select Table 114 LSICOM 3 ACE Serial Interface Control Register Write Bit 7 6 5 4 3 2 1 0 Name GO CL ANS Not used Latch 3 Latch 2 Latch 1 Latch 0 Function Table 119 External Ports Name 0 = No data transfer 1 = Begin data transfer 0 = SynthBus (126kHz) 1 = ACEBus (1·008MHz) 0 = No answer request 1 = Answer request Must be 0 SynthBus: Latch 3 SynthBus: Latch 2 Latch 1 enabled for data transfer Latch 0 enabled for data transfer R/W Addr 22 24 36 68 Description External I/P Port External O/P Port Keypad I/P and chip ID O/P type for KPO IN_PORT 1 R OUY_PORT 2 R/W KEYP R/W KPOT W Table 120 Watchdog and ATO Name REWD RESATO R/W Addr W W 6A 6C Description Reset Watchdog Reset Time Out Table 115 Table 121 47 ACE9050 Interrupts Name IRQPRT0 IRQPRT1 IRQPRT2 IRQPRT4 IRQPRT5 IRQPRT6 R/W Addr W W R W W R 70 72 2C 74 76 2E Description Reset internal interrupts Mask internal interrupts Read internal interrupts Reset external interrupts Mask external interrupts Read exernal interrupts I2C Name I2C_ADDR I2C_DATA I2C_CNTR I2C_STAT I2C_CCR R/W Addr R/W R/W R/W R W 54 55 56 57 57 Description I2C Slave address I2C Data Tx/Rx I2C Control I2C Status I2C Clock Table 125 Table 122 Modem Name Description MODPRT0 MODPRT1 MODPRT2 R/W Addr R/W R/W R/W 30 32 34 Description Configuration Control/Status Data Tx/Rx ACE Serial Interface Name LSICOM0 LSICOM1 LSICOM2 LSICOM3 LSICOM4 LSICOM5 LSICOM6 STR_WIDTH R/W Addr W W W W R R R W 60 62 64 66 3A 3C 3E 67 ACE interface TX1 ACE interface TX2 ACE interface TX3 ACE interface Control ACE interface RX1 ACE interface RX2 ACE interface RX3 Latch 3 width BAR Name BARHIGH BARLOW BARENABLE Table 126 R/W Addr W W W 50 51 52 Description BAR on BAR off BAR Output Enable Table 123 PWM Name DAC1 DAC2 R/W Addr W W 5B 5C Description PWM 1 data PWM 2 data Table 127 Baud Rate Generator Name BRG R/W Addr W 53 Description UART Baud select Table 124 Table 128 48 ACE9050 INDEX FUNCTIONAL OVERVIEW PIN DESCRIPTIONS ELECTRICAL CHARACTERISTICS DC Characteristics AC Characteristics Page 3 4 6 6. EXTERNAL PORTS & MULTIPLEXER 7. CLOCK GENERATOR 23 24 24 24 25 26 26 27 28 28 28 28 28 28 28 29 29 30 30 30 30 31 31 31 31 31 31 31 5. INTERRUPTS Masking Interrupts Internal Interrupt Control Port External Interrupt Control Port Page 21 21 21 22 TIMING DIAGRAMS Normal Mode Processor Interface Read Cycle Write Cycle Emulation Mode Processor Interface Read and Write Cycles Serial Interface Block ACEBus Read and Write Timings SynthBus Timing 8. BAUD RATE GENERATOR 7 8 9 10,11 11 12 13 13 13 13 14 14 9. EXTERNAL RESET 10. I2C INTERFACE General SEL_I2C Register I2C_CNTR Register I2C_STAT Register I2C_CCR Register I2C_ADDR Register I2C_DATA Register Clock Synchronisation Bus Arbitration Bus and Internal Clock Speeds Modes Of Operation Master Transmit 1. Transmit Start Condition 2. Transmit Slave Address and Write 3. Transmit Data 4. Transmit Stop Master Receive 1. Transmit Start Condition 2. Transmit Slave Address and Read 3. Receive Data 4. Transmit Stop Slave Transmit 1. Entering Slave Transmit Mode 2. Sending Data 3. Completing transfer Slave Receive 1. Entering Slave Receive Mode 2. Receiving Data 3. Completing transfer INTERNAL REGISTERS AND RESET STATUS ACE9050 Registers 6303 Registers MODES OF OPERATION 1.Normal Mode 2.Emulation Mode 3.Service Mode 4.Test Mode 5.Power down Modes FUNCTIONAL DESCRIPTIONS 1. ACE9050 6303 General Description Pin Description Clock I/O Port 1 I/O Port 2 Programmable Timer Serial Communication Interface SCI (UART) RAM Control Register Operating Modes Low Power Consumption Modes Address Data & Memory Control Interrupt Processing Error Processing 2. INTERNAL ROM BOOT BLOCK Normal Mode Service Mode Steps 1 and 2 Step 3 Normal Mode Step 3 Service Mode Steps 4,5 and 6 Motorola S Format Binary Dump Step 7 Interrupt Vector table RAM Area Reserved for IROM Operation 3. DECODER 4. BUS INTERFACE AND MEMORY BANKING Memory Map and Banked Addressing Non-Banked Area (Root) Banked Area Banked Address System Memory Map 14 14 14 14 14 15 15 16 16 16 16 16 16 16 16 17 17 17 17 17 17 17 17 17,18 18 19 20 20 20 RADIO FUNCTIONS 1. INTERNAL CONFIGURATION REGISTERS 2. AMPS TACS MODEM AND SAT CONTROLLER General Description Interrupts Modem Block Descriptions Controller Discriminator Data Decoder Word Sync Detector Modes of Operation Control Channel Voice Channel Data Transmitter Data Transmission Sequence SAT Management SAT Detector SAT Transmitter 31 32 34 34 34 35 36 36 37 37 37 38 38 38 39 49 ACE9050 Page 3. ACE SERIAL INTERFACE BLOCK General Description Transmitter Section Sending Data Receiver Section Receiving Data Programming Programming Constraints Programming Sequences ACEBus Transfers SynthBus Transfers 4. IFC COUNTER Detailed Operation Programming Example 5.PULSE WIDTH MODULATOR 6. BEEP ALARM RING (BAR) TONE GENERATOR 7. KEYPAD INTERFACE AND CHIP IDENTITY Output Port Prograrnming Examples Input Port Identity Code 8. AUTONOMOUS TIMEOUT (ATO) Block Descriptions ATO Timer ATO Reset RXCD Filter 39 40 40 40 40 41 41 41 41 41 41 42 42 42 43 43 43 43 44 44 44 45 45 45 46 47 LIST OF ILLUSTRATIONS Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 6 Fig. 7 Fig. 8 Fig. 9 Fig. 10 Fig. 11 Fig. 12 Fig. 13 Fig. 14 Fig. 15 Fig. 16 Fig. 17 Fig. 18 Fig. 19 Fig. 20 Fig. 21 Fig. 22 Fig. 23 Fig. 24 Fig. 25 Pin connections ACE implified block diagram Detailed block diagram ACE9050 6303 Read cycle timing diagram ACE9050 6303 Write cycle timing diagram ACE9050 6303 Emulation Mode Read/Write cycle timing diagram ACEBus Transmit Data flow ACEBus Receive Data flow ACEBus Transmit timing diagram ACEBus Receive timing diagram SynthBus timing diagram Data flow for the internal ROM Data and Address Bus configuration Banked Addressing block diagram Memory Map and Banked Addressing ACE9050 Interrupt configuration External crystal components EXRESN Reset I2C Data transfer AMPS/TACS Modem and SAT controller Modem discriminator Modem Transmitter block diagram Modem Transmission sequence Pulse Width Generator output Keyport configuration Page 1 1 2 7 8 9 10 10 10 10 11 18 19 20 20 22 24 25 26 33 34 38 38 42 43 PROGRAMMER’S GUIDE TO CONTROL PORTS AND REGISTERS ACE9050 REGISTERS BY BLOCK 50 http://www.mitelsemi.com World Headquarters - Canada Tel: +1 (613) 592 2122 Fax: +1 (613) 592 6909 North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Asia/Pacific Tel: +65 333 6193 Fax: +65 333 6192 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. 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