MT8960

® ISO2-CMOS MT8960/61/62/63/64/65/66/67 Integrated PCM Filter Codec Features • • • • • • ST-BUS ™ c ompatible Transmit/Receive filters & PCM Codec in one I.C Meets AT&T D3/D4 and CCITT G711 and G712 µ -Law: MT8960/62/64/67 A-Law: MT8961/63/65/67 Low power consumption: Op.: 30 mW typ. Stby.: 2.5 mW typ. Digital Coding Options: MT8964/65/66/67 CCITT Code MT8960/61/62/63 Alternative Code Digitally controlled gain adjust of both filters Analog and digital loopback Filters and codec independently user accessible for testing Powerdown mode available 2.048 MHz master clock input Up to six uncommitted control outputs ±5V ±5% power supply ISSUE 10 May 1995 Ordering Information MT8964/65AC 18 Pin Ceramic DIP MT8960/61/64/65AE 18 Pin Plastic DIP MT8962/63AE 20 Pin Plastic DIP MT8962/63/66/67AS 20 Pin SOIC 0°C to+70°C Description Manufactured in ISO 2-CMOS, these integrated filter/ codecs are designed to meet the demanding performance needs of the digital telecommunications industry, e.g., PABX, Central Office, Digital telephones. • • • • • • • • ANUL VX Transmit Filter Analog to Digital PCM Encoder Output Register DSTo SD0 SD1 SD2 SD3 SD4 SD5 B-Register 8-Bits Output Register A Register 8-Bits CSTi CA Control Logic F1i C2i VR Receive Filter PCM Digital to Analog Decoder Input Register DSTi VRef GNDA GNDD VDD VEE Figure 1 - Functional Block Diagram 6-19 MT8960/61/62/63/64/65/66/67 ISO2-CMOS MT8960/61/64/65 CSTi DSTi C2i DSTo VDD F1i CA SD3 SD2 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 GNDD VRef GNDA VR ANUL VX VEE SD0 SD1 CSTi DSTi C2i DSTo VDD SD5 SD4 F1i CA SD3 MT8962/63/66/67 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GNDD VRef GNDA VR ANUL VX VEE SD0 SD1 SD2 18 PIN CERDIP/PDIP 20 PIN PDIP/SOIC Figure 2 - Pin Connections Pin Description Pin Name CSTi Description Control ST-BUS In is a TTL-compatible digital input used to control the function of the filter/codec. Three modes of operation may be effected by applying to this input a logic high (VDD), logic low (GNDD), or an 8-bit serial word, depending on the logic states of CA and F1i. Functions controlled are: powerdown, filter gain adjust, loopback, chip testing, SD outputs. Data ST-BUS In accepts the incoming 8-bit PCM word. Input is TTL-compatible. Clock Input is a TTL-compatible 2.048 MHz clock. Data ST-BUS Out is a three-state digital output driving the PCM bus with the outgoing 8-bit PCM word. Positive power Supply (+5V). Synchronization Input is an active low digital input enabling (in conjunction with CA) the PCM input, PCM output and digital control input. It is internally sampled on every positive edge of the clock, C2i, and provides frame and channel synchronization. Control Address is a three-level digital input which enables PCM input and output and determines into which control register (A or B) the serial data, presented to CSTi, is stored. System Drive Output is an open drain output of an N-channel transistor which has its source tied to GNDA. Inactive state is open circuit. System Drive Outputs are open drain outputs of N-channel transistors which have their source tied to GNDD. Inactive state is open circuit. System Drive Outputs are “Totempole“ CMOS outputs switching between GNDD and VDD. Inactive state is logic low. Negative power supply (-5V). Voice Transmit is the analog input to the transmit filter. Auto Null is used to integrate an internal auto-null signal. A 0.1µ F capacitor must be connected between this pin and GNDA. Voice Receive is the analog output of the receive filter. Analog ground (0V). Voltage Reference input to D to A converter. Digital ground (0V). DSTi C2i DSTo VDD F1i CA SD3 SD4-5 SD0-2 VEE VX ANUL VR GNDA VRef GNDD 6-20 ISO2-CMOS MT8960/61/62/63/64/65/66/67 MT8960/62 Digital Output 11111111 11110000 11100000 11010000 11000000 10110000 10100000 10010000 10000000 00000000 00010000 00100000 00110000 01000000 01010000 01100000 01110000 01111111 -2.415V Bit 7... MSB 0 LSB -1.207V 0V +1.207V +2.415V Analog Input Voltage (VIN) MT8964/66 Digital Output 10000000 10001111 10011111 10101111 10111111 11001111 11011111 11101111 11111111 01111111 01101111 01011111 01001111 00111111 00101111 00011111 00001111 00000000 Figure 3 - µ -Law Encoder Transfer Characteristic MT8961/63 Digital Output 11111111 11110000 11100000 11010000 11000000 10110000 10100000 10010000 10000000 00000000 00010000 00100000 00110000 01000000 01010000 01100000 01110000 01111111 -2.5V Bit 7... MSB 0 LSB -1.25V 0V +1.25V +2.5V Analog Input Voltage (VIN) MT8965/67 Digital Output 10101010 10100101 10110101 10000101 10010101 11100101 11110101 11000101 11010101 01010101 01000101 01110101 01100101 00010101 00000101 00110101 00100101 00101010 Figure 4 - A-Law Encoder Transfer Characteristic 6-21 MT8960/61/62/63/64/65/66/67 Functional Description Figure 1 shows the functional block diagram of the MT8960-67. These devices provide the conversion interface between the voiceband analog signals of a telephone subscriber loop and the digital signals required in a digital PCM (pulse code modulation) switching system. Analog (voiceband) signals in the transmit path enter the chip at VX, are sampled at 8kHz, and the samples quantized and assigned 8-bit digital values defined by logarithmic PCM encoding laws. Analog signals in the receive path leave the chip at V R after reconstruction from digital 8-bit words. Separate switched capacitor filter sections are used for bandlimiting prior to digital encoding in the transmit path and after digital decoding in the receive path. All filter clocks are derived from the 2.048 MHz master clock input, C2i. Chip size is minimized by the use of common circuitry performing the A to D and D to A conversion. A successive approximation technique is used with capacitor arrays to define the 16 steps and 8 chords in the signal conversion process. Eight-bit PCM encoded digital data enters and leaves the chip serially on DSTi and DSTo pins, respectively. ISO2-CMOS are 30 dB for 0-60 Hz and 35 dB for 4.6 kHz and above. The filter output signal is an 8 kHz staircase waveform which is fed into the codec capacitor array, or alternatively, into an external capacitive load of 250 pF when the chip is in the test mode. The digital encoder generates an eight-bit digital word representation of the 8 kHz sampled analog signal. The first bit of serial data stream is bit 7 (MSB) and represents the sign of the analog signal. Bits 4-6 represent the chord which contains the analog sample value. Bits 0-3 represent the step value of the analog sample within the selected chord. The MT8960-63 provide a sign plus magnitude PCM output code format. The MT8964/66 PCM output code conforms to the AT &T D3 specification, i.e., true sign bit and inverted magnitude bits. The MT8965/67 PCM output code conforms to the CCITT specifications with alternate digit inversion (even bits inverted). See Figs. 3 and 4 for the digital output code corresponding to the analog voltage, VIN, at VX input. The eight-bit digital word is output at DSTo at a nominal rate of 2.048 MHz, via the output buffer as the first 8-bits of the 125 µs sampling frame. Transmit Path Analog signals at the input (Vx) are firstly bandlimited to 508 kHz by an RC lowpass filter section. This performs the necessary anti-aliasing for the following first-order sampled data lowpass pre-filter which is clocked at 512 kHz. This further bandlimits the signal to 124 kHz before a fifth-order elliptic lowpass filter, clocked at 128 kHz, provides the 3.4 kHz bandwidth required by the encoder section. A 50/60 Hz third-order highpass notch filter clocked at 8 kHz completes the transmit filter path. Accumulated DC offset is cancelled in this last section by a switched-capacitor auto-zero loop which integrates the sign bit of the encoded PCM word, fed back from the codec and injects this voltage level into the non-inverting input of the comparator. An integrating capacitor (of value between 0.1 and 1 µF) must be externally connected from this point (ANUL) to the Analog Ground (GNDA). The absolute gain of the transmit filter (nominally 0 dB at 1 kHz) can be adjusted from 0 dB to 7 dB in 1 dB steps by means of three binary controlled gain pads. The resulting bandpass characteristics with the limits shown in Figure 10 meet the CCITT and AT&T recommended specifications. Typical atttenuations 6-22 Receive Path An eight-bit PCM encoded digital word is received on DSTi input once during the 125 µs period and is loaded into the input register. A charge proportional to the received PCM word appears on the capacitor array and an 8 kHz sample and hold circuit integrates this charge and holds it for the rest of the sampling period. The receive (D/A) filter provides interpolation filtering on the 8 kHz sample and hold signal from the codec. The filter consists of a 3.4 kHz lowpass fifth-order elliptic section clocked at 128 kHz and performs bandlimiting and smoothing of the 8 kHz "staircase" waveform. In addition, sinx/x gain correction is applied to the signal to compensate for the attenuation of higher frequencies caused by the capacitive sample and hold circuit. The absolute gain of the receive filter can be adjusted from 0 dB to -7 dB in 1 dB steps by means of three binary controlled gain pads. The resulting lowpass characteristics, with the limits shown in Figure 11, meet the CCITT and AT & T recommended specifications. Typical attenuation at 4.6 kHz and above is 30 dB. The filter is followed by a buffer amplifier which will drive 5V peak/peak into a 10k ohm load, suitable for driving electronic 2-4 wire circuits. ISO2-CMOS V Ref An external voltage must be supplied to the V Ref pin which provides the reference voltage for the digital encoding and decoding of the analog signal. For V Ref = 2.5V, the digital encode decision value for overload (maximum analog signal detect level) is equal to an analog input V IN = 2 .415V (µ-Law version) or 2.5V (A-Law version) and is equivalent to a signal level of 3.17 dBm0 or 3.14 dBm0 respectively, at the codec. The analog output voltage from the decoder at V R is defined as: µ-Law: V Ref MT8960/61/62/63/64/65/66/67 driving a large number of codecs due to the high Normal input impedance of the V Ref input. precautions should be taken in PCB layout design to minimize noise coupling to this pin. A 0.1 µF capacitor connected from V Ref t o ground and located as close as possible to the codec is recommended to minimize noise entering through V Ref. This capacitor should have good high frequency characteristics. Timing The codec operates in a synchronous manner (see Figure 9a). The codec is activated on the first positive edge of C2i after F1i has gone low. The digital output at DSTo (which is a three-state output driver) will then change from a high impedance state to the sign bit of the encoded PCM word to be output. This will remain valid until the next positive edge, when the next most significant bit will be output. On the first negative clock edge (after F1i signal has been internally synchronized and CA is at GNDD or VEE) the logic signal present at DSTi will be clocked into the input shift register as the sign bit of the incoming PCM word. The eight-bit word is thus input at DSTi on negative edges of C2i and output at DSTo on positive edges of C2i. F1i must return to a high level after the eighth clock pulse causing DSTo to enter high impedance and preventing further input data to DSTi. F1i will continue to be sampled on every positive edge of C2i. (Note: F1i may subsequently be taken low during the same sampling frame to enable entry of serial data into CSTi. This occurs usually mid-frame, in conjunction with CA=V DD, in order to enter an 8-bit control word into Register B. In this case, PCM input and output are inhibited by CA at VDD.) X [( -0.5 ) ( 1228 )(16.53+ S)] 128 3 + C ±V OFFSET A-Law: V Ref X [( )( 0.53+2 S )] 2 + [( 128 )(16.532 S )] C 2C+1 128 ±V OFFSETC=0 V Ref X ±V OFFSETC ≠0 where C = c hord number (0-7) S = s tep number (0-15) V Ref is a high impedance input with a varying capacitive load of up to 40 pF. The recommended reference voltage for the MT8960 series of codecs is 2.5V ±0.5%. The output voltage from the reference source should have a maximum temperature coefficient of 100 ppm/C°. This voltage should have a total regulation tolerance of ±0.5% both for changes in the input voltage and output loading of the voltage reference source. A voltage reference circuit capable of meeting these specifications is shown in Figure 5. Analog Devices ’AD1403A voltage reference circuit is capable of NC 8 NC 7 NC 6 NC 5 VRef 0.1 µ F MT8960-67 FILTER/CODEC AD1403A 1 2 3 4 NC +5V 2.5V Figure 5 - Typical Voltage Reference Circuit 6-23 MT8960/61/62/63/64/65/66/67 Internally the codec will then perform a decode cycle on the newly input PCM word. The sampled and held analog signal thus decoded will be updated 25 µs from the start of the cycle. After this the analog input from the filter is sampled for 18 µs, after which digital conversion takes place during the remaining 82 µs of the sampling cycle. Since a single clock frequency of 2.048 MHz is required, all digital data is input and output at this rate. DSTo, therefore, assumes a high impedance state for all but 3.9 µs of the 125 µs frame. Similarly, DSTi input data is valid for only 3.9 µs. ISO2-CMOS Mode 2 CA= -5V (VEE); CSTi receives an eight-bit control word CSTi accepts a serial data stream synchronously with DSTi (i.e., it accepts an eight-bit serial word in a 3.9 µs timeslot, updated every 125 µs, and is specified identically to DSTi for timing considerations). This eight-bit control word is entered into Control Register A and enables programming of the following functions: transmit and receive gain, powerdown, loopback. Register B is reset to zero and the SD outputs assume their inactive state. Test modes cannot be entered. Digital Control Functions CSTi is a digital input (levels GNDD to VDD) which is used to control the function of the filter/codec. It operates in three different modes depending on the logic levels applied to the Control Address input (CA) and chip enable input (F1i) (see Table 1). Mode 3 CA=0V (GNDD); CSTi receives an eight-bit control word As in Mode 2, the control word enters Register A and the aforementioned functions are controlled. In this mode, however, Register B is not reset, thus not affecting the states of the SD outputs. CA=+5V (VDD); CSTi receives an 8-bit control word In this case the control word is transferred into Register B. Register A is unaffected. The input and output of PCM data is inhibited. The contents of Register B controls the six uncommitted outputs SD0-SD5 (four outputs, SD0SD3, on MT8960/61/64/65 versions of chip) and also provide entry into one of the three test modes of the chip. FUNCTION Mode 1 CA=-5V (V EE); CSTi=0V (GNDD) The filter/codec is in normal operation with nominal transmit and receive gain of 0dB. The SD outputs are in their active states and the test modes cannot be entered. CA = -5V (VEE); CSTi = +5V (VDD) A state of powerdown is forced upon the chip whereby DSTo becomes high impedance, V R is connected to GNDA and all analog sections have power removed. MODE 1 (Note 1) 2 CA VEE VEE GNDD CSTi GNDD VDD Serial Data 3 (Note 2) Serial Data VDD Note 1: Note 2: Serial Data Normal chip operation. Powerdown. Eight-bit control word into Register A. Register B is reset. Eight-bit control word into register A. Register B is unaffected. Eight-bit control word into register A. Register B is unaffected. When operating in Mode 1, there should be only one frame pulse (F1i) per 125µ s frame When operating in Mode 3, PCM input and output is inhibited by CA=V DD. Table 1. Digital Control Modes 6-24 ISO2-CMOS Note: For Modes 1 and 2, F1i must be at logic low for one period of 3.9 µs, in each 125 µs cycle, when PCM data is being input and output, and the control word at CSTi enters Register A. For Mode 3, F1i must be at a logic low for two periods of 3.9 µs, in each 125 µs cycle. In the first period, CA must be at GNDD or VEE, and in the second period CA must be high (VDD). MT8960/61/62/63/64/65/66/67 BIT 2 0 0 0 0 1 BIT 1 0 0 1 1 0 0 1 1 BIT 4 0 0 1 1 0 0 1 1 BIT 6 0 1 0 1 BIT 0 0 1 0 1 0 1 0 1 BIT 3 0 1 0 1 0 1 0 1 TRANSMIT (A/D) FILTER GAIN (dB) 0 +1 +2 +3 +4 +5 +6 +7 RECEIVE (D/A) FILTER GAIN (dB) 0 -1 -2 -3 -4 -5 -6 -7 Control Registers A, B The contents of these registers control the filter/ codec functions as described in Tables 2 and 3. Bit 7 of the registers is the MSB and is defined as the first bit of the serial data stream input (corresponding to the sign bit of the PCM word). On initial power-up these registers are set to the powerdown condition for a maximum of 25 clock cycles. During this time it is impossible to change the data in these registers. 1 1 1 BIT 5 0 0 0 0 1 Chip Testing By enabling Register B with valid data (eight-bit control word input to CSTi when F1i=GNDD and CA= VCC) the chip testing mode can be entered. Bits 6 and 7 (most sign bits) define states for testing the transmit filter, receive filter and the codec function. The input in each case is V X input and the output in each case is VR output. (See Table 3 for details.) 1 1 1 BIT 7 0 FUNCTION CONTROL Normal operation Digital Loopback Analog Loopback Powerdown Loopback Loopback of the filter/codec is controlled by the control word entered into Register A. Bits 6 and 7 (most sign bits) provide either a digital or analog loopback condition. Digital loopback is defined as follows: • PCM input data at DSTi is latched into the PCM input register and the output of this register is connected to the input of the 3-state PCM output register. • The digital input to the PCM digital-to-analog decoder is disconnected, forced to zero (0). The output of the PCM encoder is disabled and thus the encoded data is lost. The PCM output at DSTo is determined by the PCM input data. 0 1 1 Table 2. Control States - Register A • Analog output buffer at V R has its input shorted to GNDA and disconnected from the receive filter output. Analog input at V X i s disconnected from the transmit filter input. The receive filter output is connected to the transmit filter input. Thus the decode signal is fed back through the receive path and encoded in the normal way. The analog output buffer at V R i s not tested by this configuration. DSTi is the input • • • Analog loopback is defined as follows: • PCM input data is latched, decoded and filtered as normal but not output at V R. In both cases of loopback, and DSTo is the output. 6-25 MT8960/61/62/63/64/65/66/67 Logic Control Outputs SD0-5 These outputs are directly controlled by the logic states of bits 0-5 in Register B. A logic low (GNDD) in Register B causes the SD outputs to assume an inactive state. A logic high (V DD) in Register B causes the SD outputs to assume an active state (see Table 3). SD0-2 switch between GNDD and VDD and may be used to control external logic or transistor circuitry, for example, that employed on the line card for performing such functions as relay drive for application of ringing to line, message waiting indication, etc. SD3-5 are used primarily to drive external analog circuitry. Examples may include the switching in or out of gain sections or filter sections (eg., ring trip filter) (Figure 7). MT8962/63/66/67 provides all six SD outputs. MT8960/61/64/65 each packaged in an 18-pin DIP provide only four control outputs, SD0-3. ISO2-CMOS Telephone Set 2 Wire Analog AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA AA AA PCM Highway AA AA AA AA AA AA Supervision AA AA Protection AA AA AA AA AA AA AA MT8960/61 AA AA Battery AA AA MT8962/63 AA AA Feed AA AA 2W/4W AA AA MT8964/65 AA AA Converter AA AA Ringing AA AA MT8966/67 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A Figure 6 - Typical Line Termination BITS 0-2 0 1 BIT 3 0 1 BITS 4,5 0 1 BIT 7 0 0 BIT 6 0 1 Normal operation. LOGIC CONTROL OUTPUTS SD0-SD2 Inactive state - logic low (GNDD). Active state - logic high (VDD). LOGIC CONTROL OUTPUT SD3 Inactive state - High Impedance. Active state - GNDA. LOGIC CONTROL OUTPUTS SD4, SD5 Inactive state - High Impedance. Active state - GNDD. CHIP TESTING CONTROLS Transmit filter testing, i.e.: Transmit filter input connected to VX input Receive filter and Buffer disconnected from VR Receive filter testing, i.e.: Receive filter input connected to VX input Receive filter input disconnected from codec Codec testing i.e.: Codec analog input connected to VX Codec analog input disconnected from transmit filter output Codec analog output connected to VR VR disconnected from receive filter output Table 3. Control States - Register B 1 0 1 1 6-26 ISO2-CMOS Powerdown Powerdown of the chip is achieved in several ways: Internal Control: 1) Initial Power-up. Initial application of VDD and VEE causes powerdown for a period of 25 clock cycles and during this period the chip will accept input only from C2i. The B-register is reset to zero forcing SD0-5 to be inactive. Bits 0-5 of Register A (gain adjust bits) are forced to zero and bits 6 and 7 of Register A become logic high thus reinforcing the powerdown. Loss of C2i. Powerdown is entered 10 to 40 µs after C2i has assumed a continuous logic high (V DD). In this condition the chip will be in the same state as in (1) above. Note: If C2i stops at a continuous logic low (GNDD), the digital data and status is indeterminate. MT8960/61/62/63/64/65/66/67 External Control: 1) Register A. Powerdown is controlled by bits 6 and 7 ( when both at logic high) of Register A which in turn receives its control word input via CSTi, when F1i is low and CA input is either at V EE o r GNDD. Power is removed from the filters and analog sections of the chip. The analog ouput buffer at V R w ill be connected to GNDA. DSTo becomes high impedance and the clocks to the majority of the logic are stopped. SD outputs are unaffected and may be updated as normal. CSTi Input. With CA at VEE and CSTi held at continuous logic high the chip assumes the same state as described in External Control (1) above. 2) 2) Message Waiting MT8960/61/64/65 From ST-BUS From ST-BUS Master Clock to ST-BUS 5V Alignment Register Select CSTi DSTi C2i DSTo VDD F1i CA SD3 SD2 GNDD VRef GNDA VR ANUL VX VEE SD0 SD1 -5V 0.1µF Ring Trip Filter (With Relay Drive) Gain Section 2/4 Wire Converter 2.5V (With Relay Drive) -100V DC Telephone Line Ring Feed (With Relay Drive) -48V DC -48V DC 90VRMS Figure 7 - Typical Use of the Special Drive Outputs 6-27 MT8960/61/62/63/64/65/66/67 ISO2-CMOS DSTi DSTo CDTi VX VR SD0 . . . SDn • • • Line Interface & Monitoring Circuitry Line 1 Speech Switch 8980 MT8960-67 8 8 • • • Repeated for Lines 2 to 255 • • • Repeated for Lines 2 to 255 Controlling MicroProcessor 8 8 Control & Signalling 8980 DSTi DSTo CDTi VX VR SD0 . . . SDn • • • Line Interface & Monitoring Circuitry Line 256 MT8960-67 Figure 8 - Example Architecture of a Simple Digital Switching System Using the MT8960-67 6-28 ISO2-CMOS Absolute Maximum Ratings* Parameter 1 DC Supply Voltages MT8960/61/62/63/64/65/66/67 Symbol VDD-GNDD VEE-GNDD VRef VX Except CA CA Min -0.3 -6.0 GNDA VEE GNDD-0.3 VEE-0.3 GNDD-0.3 VEE-0.3 VEE-0.3 -55 Max +6.0 +0.3 VDD VDD VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3 20 +125 500 Units V V V V V V V V V mA °C mW 2 3 4 Reference Voltage Analog Input Digital Inputs 5 Output Voltage SD0-2 SD3 SD 4-5 6 7 8 Current On Any Pin Storage Temperature Power Dissipation at 25°C (Derate 16 mW/°C above 75°C) II TS PDiss * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to GNDD unless otherwise stated Characteristics 1 Supply Voltage Sym VDD VEE VRef 2 Voltage On Digital Ground VGNDD Min 4.75 -5.25 Typ* 5.0 -5.0 2.5 Max 5.25 -4.75 Units V V V Comments See Note 1 Ref. to GNDA Ref. to GNDA 400ns max. duration in 125µs cycle -0.1 -0.4 0.0 0.0 +0.1 +0.4 +70 Vdc Vac °C mA mA µA 3 4 Operating Temperature Operating Current VDD VEE VRef VDD VEE TO IDD IEE IRef IDDO IEEO 0 3.0 3.0 2.0 0.25 0.25 4.0 4.0 All digital inputs at VDD or GNDD (or VEE for CA) Mean current All digital inputs at VDD or GNDD (or VEE for CA) 5 Standby Current 1.0 1.0 mA mA Note 1: Temperature coefficient of VRef s hould be better than 100 ppm/°C. DC Electrical Characteristics - Voltages are with respect to GNDD unless otherwise stated. TA=0 to 70°C, VDD=5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V,Clock Frequency =2.048MHz. Outputs unloaded unless otherwise specified. Characteristics 1 D I G I T A L Input Current Except CA CA 2 Input Low Voltage Except CA CA Sym II IIC VIL VILC VIH VIIC I0Z 0.0 VEE 2.4 0.0 ±0.1 10.0 Min Typ* Max 10.0 10.0 0.8 VEE+1.2 Units µA µA V V V V µA µA Test Conditions VIN = GNDD to VDD VIN = VEE to VDD 3 4 5 Input High Voltage All Inputs Input Intermediate CA Voltage Output Leakage Current (Tristate) DSTo SD3-5 5.0 0.8 Output High Impedance * Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing. 6-29 MT8960/61/62/63/64/65/66/67 DC Electrical Characteristics (cont’d) Characteristics 6 D I G I T A L Output Low Voltage Output High Voltage Output Resistance Output Capacitance Input Current A N A L O G Input Resistance Input Capacitance Input Offset Voltage Output Resistance DSTo SD0-2 DSTo SD0-2 SD3-5 DSTo VX VX VX VX VR Sym VOL VOL VOH VOH ROUT COUT IIN RIN CIN VOSIN ROUT VOSOUT ISO2-CMOS Min Typ* Max 0.4 1.0 Units V V V V KΩ pF Test Conditions IOUT =1.6 mA IOUT =1 mA IOUT =-100µA IOUT =-1mA VOUT =+1V Output High Impedance VEE ≤ VIN ≤ VCC 7 4.0 4.0 1.0 4.0 10.0 10.0 30.0 +1.0 100 100 2.0 8 9 10 11 12 13 14 15 µA MΩ pF mV Ω mV fIN = 0 - 4 kHz See Note 2 Output Offset Voltage VR Digital Input= +0 Note 2: V OSIN s pecifies the DC component of the digitally encoded PCM word. AC Electrical Characteristics - Voltages are with respect to GNDD unless otherwise stated. TA=0 to 70°C, VDD =5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency=2.048 MHz. Outputs unloaded unless otherwise specified. Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D I G I T A L Clock Frequency Clock Rise Time Clock Fall Time Clock Duty Cycle Chip Enable Rise Time Chip Enable Fall Time C2i C2i C2i C2i F1i F1i Sym fC tCR tCF Min 2.046 Typ* 2.048 Max 2.05 50 50 Units MHz ns ns % ns ns ns ns Test Conditions See Note 3 40 tER tEF tES tEH tOR tOF tPZL tPZH tPLH tPHL tIR tIF tISH tISL tIH 25 0 60 60 50 25 50 60 100 100 Chip Enable Setup Time F1i Chip Enable Hold Time Output Rise Time Output Fall Time F1i DSTo DSTo See Note 4 See Note 4 100 100 122 122 100 100 100 100 100 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns RL=10KΩ to VCC CL=100 pF Propagation Delay Clock DSTo to Output Enable Propagation Delay Clock to Output Input Rise Time Input Fall Time Input Setup Time Input Hold Time DSTo CSTi DSTi CSTi DSTi CSTi DSTi CSTi DSTi * Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing. 6-30 ISO2-CMOS AC Electrical Characteristics (cont’d) Characteristics 17 18 19 20 D I G I T A L Propagation Delay Clock to SD Output SD Output Fall Time SD Output Rise Time Digital Loopback Time DSTi to DSTo SD SD SD Sym tPCS tSF tSR tDL Min MT8960/61/62/63/64/65/66/67 Typ* Max 400 200 400 122 Units ns ns ns ns Test Conditions CL = 100 pF CL = 20 pF (See Figures 9a, 9b, 9c) Note 3: Note 4: The filter characteristics are totally dependent upon the accuracy of the clock frequency providing F1i is synchronized to C2i. The A/D and D/A functions are unaffected by changes in clock frequency. This gives a 75 ns period, 50 ns before and 25 ns after the 50% point of C2i rising edge, when change in F1i w ill give an undetermined state to to the internally synchronized enable signal. AC Electrical Characteristics - Transmit (A/D) Path - Voltages are with respect to GNDD unless otherwise stated. TA=0 to 70°C, VDD =5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency = 2.048MHz, Filter Gain Setting = 0dB. Outputs unloaded unless otherwise specified. Characteristics 1 Analog Input at VX equivalent to the overload decision level at the codec Absolute Gain (0dB setting) Absolute Gain (+1dB to +7dB settings) Gain Variation A N A L O G With Temp With Supplies Gain Tracking (See Figure 12) CCITT G712 (Method 1) Sym VIN Min Typ* 4.829 5.000 Max Units VPP VPP Test Conditions Level at codec: µ-Law: 3.17 dBm0 A-Law: 3.14 dBm0 See Note 6 0 dBm0 @ 1004 Hz from nominal, @ 1004 Hz TA=0°C to 70°C 2 3 4 GAX -0.25 -0.35 +0.25 +0.35 0.01 0.04 dB dB dB dB/V GAXT GAXS GTX1 -0.25 -0.25 -0.50 5 +0.25 +0.25 +0.50 +0.25 +0.50 +1.50 dB dB dB dB dB dB dB dB dB dB dB Sinusoidal Level: +3 to -20 dBm0 Noise Signal Level: -10 to -55 dBm0 -55 to -60 dBm0 Sinusoidal Level: +3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 Noise Signal Level: -3 dBm0 -6 to -27 dBm0 -34 dBm0 -40 dBm0 -55 dBm0 CCITT G712 (Method 2) AT&T 6 Quantization Distortion (See Figure 13) GTX2 -0.25 -0.50 -1.50 DQX1 28.00 35.60 33.90 29.30 14.20 CCITT G712 (Method 1) * Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing. 6-31 MT8960/61/62/63/64/65/66/67 Transmit (A/D) Path (cont’d) Characteristics Quantization Distortion (cont’d) (See Figure 13) 7 Idle Channel Noise 8 9 10 11 CCITT G712 (Method 2) AT&T C-message Psophometric Sym DQX2 ISO2-CMOS Min 35.30 29.30 24.30 Typ* Max Units dB dB dB Test Conditions Sinusoidal Input Level: 0 to -30 dBm0 -40 dBm0 -45 dBm0 NCX NPX NSFX 18 -67 -56 -46 dBrnC0 µ-Law Only dBm0p CCITT G712 dBm0 dB µs µs µs µs CCITT G712 Input Signal: 0 dBm0 @ 1.02 kHz @ 1004 Hz Input Signal: 400-3200 Hz Sinewave at 0 dBm0 50/60 Hz @ -23 dBm0 and any signal within 300-3400 Hz at -9 dBm0 740 Hz and 1255 Hz @ -4 to -21 dBm0. Equal Input Levels 2nd order products 3rd order products 0 dBm0 Input Signal Transmit Filter Response Single Frequency Noise Harmonic Distortion (2nd or 3rd Harmonic) Envelope Delay Envelope Delay Variation With Frequency Intermodulation Distortion 1000-2600 Hz 600-3000 Hz 400-3200 Hz CCITT G712 50/60 Hz CCITT G712 2 tone AT&T 4 tone Gain Relative to ≤50 Hz Gain @ 1004 Hz 60 Hz (See Figure 10) 200 Hz 300-3000 Hz 3200 Hz 3300 Hz 3400 Hz 4000 Hz ≥ 4600 Hz Crosstalk D/A to A/D Power Supply Rejection VDD VEE DAX DDX 60 150 250 270 12 A N A L O G IMDX1 -55 dB IMDX2 -41 dB IMDX3 IMDX4 GRX -1.8 -0.125 -0.275 -0.350 -0.80 -47 -49 -25 -30 0.00 0.125 0.125 0.030 -0.100 -14 -32 -70 33 35 dB dB dB dB dB dB dB dB dB dB dB dB dB dB 13 14 15 16 CTRT PSSR 1 PSSR2 0 dBm0 @ 1.02 kHz in D/A Input 50 mVRMS at 1.02 kHz Input frequency=1.02kHz Overload Distortion (See Fig.15) * Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing. Note 6: 0dBm0=1.185 V RMS f or the µ - Law codec. 0dBm0=1.231 V RMS f or the A-Law codec. 6-32 ISO2-CMOS MT8960/61/62/63/64/65/66/67 AC Electrical Characteristics - Receive (D/A) Path - Voltages are with respect to GNDD unless otherwise stated. TA=0 to 70°C, VDD =5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency = 2.048MHz, Filter Gain Setting = 0dB. Outputs unloaded unless otherwise specified. Characteristics 1 Analog output at VR equivalent to the overload decision level at codec Sym VOUT Min Typ* 4.829 5.000 Max Units Vpp Vpp Test Conditions Level at codec: µ-Law: 3.17 dBm0 A-Law: 3.14 dBm0 RL=10 KΩ See Note 7 0 dBm0 @ 1004Hz From nominal, @ 1004Hz 2 3 4 Absolute Gain (0dB setting) Absolute Attenuation (-1dB to -7dB settings) Gain Variation With Temp. With Supplies GAR -0.25 -0.35 +0.25 +0.35 0.01 0.04 dB dB dB dB/V GART GARS GTR1 -0.25 -0.25 -0.50 TA=0°C to 70°C 5 Gain Tracking (See Figure 12) CCITT G712 (Method 1) +0.25 +0.25 +0.50 +0.25 +0.50 +1.50 dB dB dB dB dB dB dB dB dB dB dB dB dB dB Sinusoidal Level: +3 to -10 dBm0 Noise Signal Level: -10 to -55 dBm0 -55 to -60 dBm0 Sinusoidal Level: +3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 Noise Signal Level: -3 dBm0 -6 to -27 dBm0 -34 dBm0 -40 dBm0 -55 dBm0 Sinusoidal Input Level: 0 to -30 dBm0 -40 dBm0 -45 dBm0 6 A N A L Quantization O Distortion G (See Fig. 13) CCITT G712 (Method 2) AT & T CCITT G712 (Method 1) GTR2 -0.25 -0.50 -1.50 DQR1 28.00 35.60 33.90 29.30 14.30 DQR2 36.40 30.40 25.40 NCR NPR NSFR 12 -75 -56 -46 IMDR2 IMDR3 IMDR4 -41 -47 -49 CCITT G712 (Method 2) AT & T 7 Idle Channel Noise 8 9 10 C-message Psophometric dBrnC0 µ-Law Only dBm0p CCITT G712 dBm0 dB dB dB dB 2nd order products 3rd order products CCITT G712 Input Signal 0 dBm0 at 1.02 kHz Single Frequency Noise Harmonic Distortion (2nd or 3rd Harmonic) Intermodulation Distortion CCITT G712 2 tone AT & T 4 tone * Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing. 6-33 MT8960/61/62/63/64/65/66/67 Receive (D/A) Path (cont’d) Characteristics 11 12 Envelope Delay Envelope Delay 1000-2600 Hz Variation with 600-3000 Hz Frequency 400-3200 Hz Sym DAR DDR Min ISO2-CMOS Typ* Max 210 Units µs µs µs µs Test Conditions @ 1004 Hz Input Signal: 400 - 3200 Hz digital sinewave at 0 dBm0 0 dBm0 Input Signal Receive Filter Response 90 170 265 -0.5 -0.125 -0.350 -0.80 0.125 0.125 0.125 0.030 -0.100 -14.0 -28.0 -70 33 35 Gain Relative to