SL3522NA1C

SL3522 500MHz 75dB Logarithmic/Limiting Amplifier Advance Information Supersedes edition in Professional Products IC Handbook May 1991 DS3534 - 2.0 April 1994 The SL3522 is a monolithic seven stage successive detection logarithmic amplifier integrated circuit for use in the 100MHz to 500MHz frequency range. It features an on–chip video amplifier with provision for external adjustment of log Slope and offset. It also features a balanced RF output. The SL3522 operates from supplies of ±5V. N/C N/C VEE GND VEE GND VEE RF O/P GND RF O/P– RF O/P+ RF O/P VEE VIDEO O/P VEE VIDEO O/P VIDEO O/P VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RF I/P+ RF I/P– VEE GND VEE GND VEE GND VIDEO VEE GAIN ADJUST TRIM REF OFFSET ADJ VIDEO GND VIDEO VCC FEATURES s 75dB Dynamic Range s Surface Mount SO Package s Adjustable Log Slope and Offset s 0dBm RF Limiting Output s 60dBm Limiting Range s 2V Video Output Range s Low Power (Typ. 1W) s Temperature Range (TCASE): -55°C to +125°C APPLICATIONS s Ultra Wideband Log Receivers s Channelised and Monpulse Radar s Instrumentation ABSOLUTE MAXIMUM RATINGS Supply Voltage Storage temperature Junction temperature Thermal resistance Die-to-case Die-to-ambient Applied DC voltage to RF input Applied RF power to RF input MC28 Fig.1 Pin connections - top view ORDERING INFORMATION SL3522 A MC (Miniature Ceramic package) SL3522 C MC (Miniature Ceramic package) SL3522 NA 1C (Probe-tested bare die) (Also available: SL3522 AA MC screened to Mitel HI-REL level A. Contact Mitel Semiconductor sales outlet for a separate datasheet.) ±6.0V -65°C to +175°C +175°C 15.5°C/W 76.5°C/W ±400mV +15dBm ESD PROTECTION To achieve the high frequency performance there are no ESD protection structures on the RF input pins (27, 28). These pins are highly static sensitive, typically measured as 250V using MIL-STD-883 method 3015. Therefore, ESD handling precautions are e ssential t o avoid degradation of performance or permanent damage to this device. RF O/P RF O/P– O/P+ VCC RF I/P – RF I/P + 27 9 10 14 O/P GND VIDEO OUT O/P VEE VIDEO VCC 28 16 13 12 VIDEO GAIN AND OFFSET ADJUST 15 19 3, 5, 7, 20, 22, 24, 26 VEE 4, 6, 8, 21, 23, 25 GND GAIN ADJ 18 RG 17 RT RO OFFSET ADJ Fig.2 Functional block diagram SL3522 ELECTRICAL CHARACTERISTICS The electrical characteristics are guaranteed over the following range of operating conditions, using test circuit in Fig. 3 (unless otherwise stated): Temperature range: Military: SL3522 A MC, SL3522 NA 1C Commercial: SL3522 C MC Supply voltage: VCC: +4.50V to +5.50V (all grades) VEE: -4.5V to -5.50V (all grades) Frequency =100MHz to 500MHz Rg, Ro, Rt =1.5KΩ Video output load =200Ω//20pF Test conditions (unless otherwise stated): Temperature: SL3522 A MC: +25°C, +125°C & -55°C (TCASE) SL3522 C MC: +25°C SL3522 NA 1C +25°C Supply voltage: VCC = +5.0V, VEE = -5.0V Parameter Positive supply current (quiescent) Negative supply current (quiescent) Dynamic range Linearity ALL VEE Pins 75 70 -1 -1 -1.25 Video output range Video slope Video slope variation Video slope adjust range Video offset Video offset variation Video offset adjust range Video trim reference voltage Video output impedance Video rise time Input VSWR RF bandwidth RF limiting range RF limited output level RF output impedance 13 13 13 13 13 13 13 17, 18, 19 13 13 27, 28 9, 10 9, 10 9, 10 9, 10 -3.0 10 16 1.5:1 450 60 -1.0 50 +1.0 MHz dB dBm Ω Ω ns See note 8 10% - 90% (60dB step) See note 7 Zs = 50Ω See note 7 TCASE = +25°C RFIN = -70dBm See notes 2, 7 See notes 2, 6, 7 R1 = 50Ω single ended See note 2 Single ended See notes 2, 8 ±0.5 -0.59 -0.54 -0.49 1.30 18 -5 ±20 -0.1 ±30 +0.25 -05 +0.5 1.75 21 +1 +1 +1.25 2.00 24 +5 150 180 175 210 mA mA dB dB dB dB dB V mV/dB % % V mV/°C V V TCASE = +25°C RO = 1kΩ to 2.2kΩ See note 5 RG = 1kΩ to 2.2kΩ VEE = -5.0V See note 1 VEE = -5.0V See note 2 100 to 400MHz See note 1, 3 See note 1, 4 TCASE = -55°C TCASE = +25°C TCASE = +125°C Pin Min. 14, 15 Value Typ. 28 Max. 35 mA VCC = +5.0V Units 55°C to +125°C (TCASE) 0°C to +70°C (TCASE) Conditions 2 SL3522 ELECTRICAL CHARACTERISTICS (cont.) Parameter Phase variation with RF Input level Phase tracking between units 3 Degrees Pin Min. Value Typ. 15 Max. Degrees Freq = 300MHz RFIN = -60 to +10dBm See notes 2, 7 TCASE = +25°C FREQ = 300MHz See notes 2, 7 Units Conditions Notes 1 RF output buffer OFF (pin 8 disconnected from 0V) 2 RF output buffer ON (pin 8 connected to 0V) 3 Minimum dynamic range under any single set of operating conditions 4 Log linearity guaranteed for pin = -64dBm to +6dBm for ALL supply, temperature and frequency conditions 5 Full range of supply, temperature and frequency conditions 6 Input limiting range typically -50dBm to +10dBm 7 Not tested, but guaranteed by characterisation 8 Not tested, but guaranteed by design The SL3522 CANNOT be GUARANTEED to operate below 100MHz and meet the electrical characteristics shown above. However, characterisation has shown that the device can still function adequately down to frequencies of 50MHz, with the following reservations:1)The video bandwidth is fixed to approx 40MHz a certain amount of carrier breakthrough on the video O/P (pin 13) will occur, with input signal frequencies below 100MHz. 2)There are 2 RF coupling capacitors (20pF) on-chip, which couple the output signal from stage 3 to the input of stage 4 (ref Fig. 24). These can introduce undesirable limiting phase performance for input signal frequencies below 100MHz. RF INPUT RT 1k5 L1 L2 GAIN ADJUST RG 2k2 10n OFFSET ADJUST R0 2k2 +5V VCC 123 ANZAC TP101 654 10n 10n 28 27 26 25 24 23 22 21 20 19 18 17 16 15 L3 SL3552 1 2 3 4 5 6 7 8 9 10 11 12 13 10n 14 10n SW1 10n 1n 1n L4 10n L5 470 200 18p VIDEO OUTPUT 100 +5V VEE NOTES 1. Inductors L1 to L5 = 3 TURNS 30SWG on Ferrite bead. 2. D.U.T. mounted in a test socket – ENPLAS OTS–28–1.27–04 3. Transmission line BALUNS used – not recommended in Application (see Para 3C) 654 ANZAC TP101 123 RF OUTPUT Fig.3 Test circuit 3 SL3522 PRODUCT DESCRIPTION The SL3522 is a complete monolithic successive detection Log/limiting amplifier which can operate over an input frequency range of 100MHz to 500MHz. Producing a log/lin characteristic for input signals between -64dBm and +6dBm, the log amplifier can provide an accuracy of better than ±1.00dB at case temperatures of -55°C and +25°C and an accuracy of better than ±1.25dB at +125°C. The dynamic range is better than 75dB over a frequency range of 100MHz to 400MHz. The graph in fig 4 shows how the dynamic range is guaranteed over frequency. The SL3522 consists of 6 Gain stages, 7 Detector stages, a limiting RF Output buffer and a Video Output amplifier. The power supply connections to each section are isolated from each other to aid stability. The SL3522 consumes 1.1W of power when ALL parts of the circuit are powered up from a ±5.0V power supply. As the circuit uses a differential architecture, the power consumption of the RF gain/detector stages and RF Output Buffer will be independent of RF input signal level. However, the Video Output (pin 13) is driven by a single ended emitter follower and so the power consumption of the Video amplifier will vary with RF input signal level between pins 27 and 28.(upto 10mA over 2V video output range with max video load of 200Ω //20pF) The SL3522 has a high RF gain (>50dB) across a wide bandwidth (>450MHz) when the limiting RF Output Buffer is enabled. The limiting RF Output Buffer provides a balanced Limited Output level of nominally –1.0dBm on each RF Output connection (pin 9 and 10), for RF input signal levels on pins 27 and 28 in excess of –50dBm. The limiting RF Output Buffer can be isolated from the other sections of the SL3522, by disconnecting the RF Output Buffer GND (pin 8) from 0V, and leave the pin floating. This feature aids stability in applications NOT requiring a Limited RF Output signal, and lowers the power consumption of the SL3522 to 0.95Watts, when the other sections are powered up from a ±5.0V power supply. Each of the Gain and Detector stages has approximately 12dB of gain, and a significant amount of on-chip RF decoupling (200pF per stage), also to aid stability. The Video amplifier provides a positive going output signal proportional to the log of the amplitude of an RF input applied between pins 27 and 28. The gain and the offset of the Video amplifier can be adjusted by 3 resistors; RG , RT , and RO which are connected to Gain adjust (pin 19),Trim reference (pin 18) and Offset adjust (pin 17). With RT set to 1.5kΩ , RG can be set to any value between 1kΩ and 2k2Ω and achieve a range in Video Slope of ±20%, centred on 21mV/dB. Similarly, RO can be set to any value between 1kΩ and 2.2KΩ and achieve an offset range of ±0.5V, which should allow the Video Offset to be trimmed to 0V if required. The RF input pins (27 and 28) have a 50Ω terminating resistor connected between them on–chip. These are capacitively coupled to the I/P gain stage with 20pF on-chip capacitors. (Refer to APPLICATION NOTES section for information on how to connect an RF input signal to the device). 100 90 80 70 60 Minimum guaranteed dynamic range (dB)” 50 40 30 20 10 0 100 200 300 400 500 600 700 800 –55°C +25°C +125°C Fig.4 Plot showing guaranteed dynamic range v. frequency (typical achievable dynamic range lines indicated across temperature) 4 SL3522 APPLICATION NOTES 1) VIDEO–AMPLIFIER 3) SL3522 AS A LOG/LIMITING AMPLIFIER - with RF Output-Buffer ENABLED (pin 8 connected to GND) If the SL3522 is to be used as a Limiting or Log/limiting amplifier with a requirement for a Limited RF Output signal,care is required in the layout of components and connections around the device to ensure stability. The following precautions should be observed (refer to Application circuit diagram in Fig. 6):a) The device should be mounted on a ground plane, ensuring that the impedance between the ground plane and ALL the GND pins is kept as low as possible. If a multilayer PCB is used where the ground plane is connected to the GND pins using through-plated holes (vias), it is essential to ensure that the vias have a very low impedance. ALL supply decoupling capacitors should be RF chip capacitors whose leads should be kept as short as possible. b) The RF VEE connections (pins 3,5,7,11,20,22,24,26) should be connected to a low impedance copper plane. A two layer PCB should help to achieve this. c) The RF input (pins 27 and 28) should be driven with a balanced source impedance. One way of achieving this is to use an isolating BALUN transformer (50Ω UNBALANCED → 50Ω BALANCED) connected between the signal source and the RF input pins. (e.g. Mini circuits TT1–6, TO –75). The device stability is VERY sensitive to an imbalance of the differential source impedance at pins 27 and 28. Use of a transmission line BALUN though, is NOT recommended. d) The RF Output connections (pins 9 and 10) should each be loaded with matched impedances ideally 50Ω transmission lines. The RF Output lines leading away from the device should be balanced. Driving highly reactive SWR loads is NOT recommended as these can encourage device instability, as can an imbalance of the differential load impedance at pins 9 and 10. e) The RF Output connections (pins 9 and 10) are DC coupled, and ideally the output pins should be capacitively coupled to their loads using 1nF capacitors. However the RF Outputs can drive a DC load to GND and a DC offset of approx. 400mV will exist on each RF Output pin. IT WILL NOT BE POSSIBLE TO DISABLE THE RF OUTPUT BUFFER UNDER THESE CONDITIONS. f) The RF output (pins 9 and 10) has a tendancy to limit on self noise, particularly at low ambient temperatures (-55°C), when the RF output buffer is enabled. NOTE that this will effect the liminting range as the gain of the RF output buffer will reduce as the amount of noise limiting increases. If required the limited RF Output can be attenuated using an attenuation network as shown in fig. 9. Under these conditions the effective RF Output currents will be reduced, allowing the device to operate with a greater margin of stability.It may be possible to run the device without a BALUN transformer on the RF input if the total output impedance on the RF Output >> 50Ω , and the attenuation components are mounted as close as possible to the RF Output connections (pins 9 and 10). The RF input connection could then be configured as in Fig 5. The SL3522 uses a single ended Video amplifier to produce a trimmable Video transfer characteristic. Both the gain (Slope) and Offset of the amplifier can be externally adjusted. a) Gain and Offset trimming (ref Applications circuits in figs 5 and 6) The Gain and Offset control is achieved by adjusting RG and RO respectively. The control is dependent upon their difference from the Trim reference resistor, RT. Adjustment of Gain has an effect on Offset, but adjustment of Offset does NOT affect the Gain. Therefore the Gain should be optimised first. The Offset should only be adjusted once the Gain has been set. Fig 7 shows the variation of Video Offset with value of RO, for a fixed value of RT and RG = 1k5Ω. Fig 8 shows the variation of Video Slope with value of RG, for a fixed value of RT and RO = 1k5Ω. The Video amplifier incorporates temperature compensation for Video gain (Slope). To ensure temperature stability for Video gain (Slope) over the operating temperature range, it is recommended that the resistors with identical temperature coefficients of resistance are used for RT and RG. The Video amplifier does NOT incorporate temperature compensation for Video Offset. Although it is recommended that a resistor with identical temperature coefficient of resistance to RT be used for RO, it may be necessary to use an additional external temperature compensating network. b) Video performance The Video–amplifier has a critically damped rise time of 16ns (10% - 90%).In order to achieve this transient performance, it is important to ensure that:i) the resistor connected to Trim reference (pin 18), has a nominal resistance of 1.5kΩ, with a parasitic capacitance LESS than 5pF. ii) the load applied to the Video Output (pin 13) does NOT exceed 200Ω resistance in parallel with 20pF. Also, the following decoupling should be incorporated:i) The Video Output VCC (pin 14) should be decoupled with a 10nF capacitor to the RETURN line from the video load, connected to Video GND (pin 16), avoiding any common impedance path. ii) The Video Output Vee (pin 12) should be decoupled with a 10nF capacitor DIRECTLY to Video-Output VCC (pin 14). 2) SL3522 AS A LOG AMPLIFIER with RF output buffer disabled (pin 8 floating) If the SL3522 is to be used as a Logarithmic successive detection amplifier only, with no requirement for a limited RF Output, the RF input (pins 27 and 28) can be driven EITHER differentially or single ended from a 50Ω source. If being used with a single ended input, the SIGNAL should be applied to pin 27 and the RETURN should be connected to pin 28, as shown in the Application circuit diagram in Fig 5. The SL3522 is VERY stable when used in this way. Although not a crucial requirement, it is recommended that the device should be mounted using a ground plane. 5 SL3522 GAIN ADJUST RG 2k2 RF INPUT 10n 10n RT 1k5 OFFSET ADJUST R0 2k2 10n +5V VCC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SL3522 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VIDEO OUTPUT VIDEO LOADING R 200 C 20p 10n 10n –5V VEE 10n Fig.5 Application circuit successive detection logarithmic function only RF INPUT GAIN ADJUST RG 2k2 10n 10n RT 1k5 OFFSET ADJUST R0 2k2 10n +5V VCC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SL3522 1 2 3 4 5 6 7 8 9 10n 10n 1n 1n 10n –5V VEE RF OUTPUT 10n 10 11 12 13 14 VIDEO OUTPUT VIDEO LOADING R 200 C 20p Fig.6 Application circuit - Log / Limiting function 6 SL3522 1.50 1.25 1.00 .75 Video offset (V) .50 .25 0.00 –.25 –.50 –.75 –1.00 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 Offset–adjust resistor (ohms) Fig.7 Video offset v. offset-adjust resistor (pin17 to gnd) across temperature 30 28 26 Video slope (mV/dB) 24 22 20 18 16 14 12 10 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 Gain–adjust resistor (ohms) Fig.8 Video slope v. gain-adjust resistor (pin19 to gnd) across temperature RF O/P– 9 RF O/P+ 10 1n 1n R1 R1 SL3522 RF O/P GND 8 50 50 Fig.9 Network for attenuating limited RF output 7 SL3522 A PRACTICAL APPLICATION FOR THE SL3522 AS A LOG/LIMITING AMPLIFIER The SL3522, with the RF Output-Buffer ENABLED, has a large limited RF Output level (0dBm on each of two RF Output pins (9 and10)) and a wide RF bandwidth (450MHz) in a small 28 pin Miniature Ceramic S.O package. As a result, there is a tendency for the device to become unstable unless care is used in the application. The PCB layout for a ”SL3522 DEMONSTRATION BOARD” in Fig. 11 has proved reliably stable. The PCB is a double layer Fibre epoxy board which uses SMDs where possible. A circuit diagram for the Demonstration PCB appears in Fig. 10. The following points should be noted when this application is realised practically:1) A wire needs to connect the two pads connected to pins 14 and 15 of the SL3522, to allow +5V to appear at both pins. 2) ALL the GND connections to the SL3522 are made through the PCB to a Ground plane on the bottom side. It is important to ensure that the impedance of each of these connections is kept to an absolute minimum to prevent instability. If these connections are achieved using through plated holes, it is recommended that they are filled with solder to lower their impedance. 3) The PCB is configured to accept SMA, SMB or SMC connectors for the RF input, RF Output and Video Output connections. These can be changed if necessary to an alternative type, but it is vital to ensure that the ground plane is solidly connected to the Guard Ring which surrounds the RF Output tracks. 4) The PCB is configured to accept a small surface mounting DC isolating BALUN transformer (e.g VANGUARD VE43666, available from Vanguard Electronics Company Inc, 1480 West 178th St. GARDENA, C.A. 90248, U.S.A. Tel:U.S.A. (213) 323 – 4100) to couple a signal into the RF input connections (pins 27 and 28). It is NOT recommended to attempt operating the SL3522 with the RF Output Buffer enabled, WITHOUT using an input BALUN, although it may be possible, provided the input source impedance to both pins 27 and 28 remains balanced. The centre tap of the secondary winding of the transformer should be soldered to the small ground plane on the upper side of the PCB. 5) The RF Output connection to the PCB is from pin 9 of the SL3522 only, with pin 10 being terminated on the PCB using a 51Ω resistor. It is important to ensure that both pin 9 and10 are terminated with equal impedances. 6) The RF Output Buffer can be enabled by soldering a link (LK) between pin 8 of the SL3522 and the adjacent guard track around the RF Output lines. Similarly, the buffer can be disabled by removing the same link. When the buffer is disabled, the following components can be omitted:1nF capacitors (C1, C2) 10nF capacitor (C8) 51Ω resistor (RFO ) 7) The Slope (gain) and Offset of the Video Output can be adjusted using two 1kΩ trimmers, provision for which is included in the PCB layout. The plots in Fig. 12 to fig. 23 are typical of the performance of SL3522 devices used with the PCB layout detailed in Fig.11. +5V VCC GAIN ADJUST VRG 1k C3 10n 28 27 26 25 24 23 22 21 C4 10n 20 19 18 17 OFFSET ADJUST VR0 1k C5 10n 16 15 RF INPUT RG 1k RT 1k5 RO 1k SL3522 1 2 3 C9 10n LK C1 1n C2 1n RFO 51 4 5 6 7 8 9 10 11 C8 10n 12 13 14 RVS 150 C7 10n C6 10n VIDEO OUTPUT –5V VEE VIDEO LOADING R 200 C 20p RF OUTPUT Fig.10 SL3522 demonstration board circuit diagram 8 SL3522 Fig.11 Demonstartion Circuit PCB showing components positions (2x full size) with top and bottom copper masks (full size) 9 SL3522 2 1.75 1.5 1.25 VIDEO O/P (V) 1 0.75 0.5 0.25 0 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 10 RF input power (dBm) Fig.12 Video O/P vs CW input level at 325MHz across temperature (VCC = +5.0V, VEE = -5.0V) 8 6 LOG – ERROR (dB) 4 2 0 –2 –4 –70 –60 –50 –40 –30 –20 –10 0 10 RF input power (dBm) Fig.13 Video O/P log-error, (referenced to single straight line measured at 325MHz, +25°C, 5.0V PSUs) across temperature 10 SL3522 7 6 5 4 4.5V 3 2 1 5.0V 0 –1 –2 –3 –70 –60 –50 –40 –30 –20 RF input power (dBm) –10 0 10 5.5V Fig.14 Video log error, (referenced to single straight line measured at 325MHz, 25°C, 5.0V PSUs), across supply voltage LOG – ERROR (dB) 6 5 500MHz 4 3 2 325MHz 1 0 –1 100MHz –2 –3 –4 –70 –60 –50 –40 –30 –20 RF input power (dBm) –10 0 10 LOG – ERROR (dB) Fig.15 Video log error, (referenced to single straight line measured at 325MHz, 25°C, 11 SL3522 70 60 50 40 GAIN (dB) 30 20 10 0 10 110 210 310 410 510 Frequency (MHz) 610 710 810 910 1010 Fig.16 Linear gain (-70dBm I/P) 0 –5 –10 RF output power (dBm) –15 –20 –25 –30 –35 –40 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 10 RF input power (dBm) Fig.17 RF input → output limiting transfer characteristic at Frequency = 100MHz 12 SL3522 0 –5 –10 RF output power (dBm) –15 –20 –25 –30 –35 –40 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 10 RF input power (dBm) Fig.18 RF input → output limiting transfer characteristic at Frequency = 325MHz 0 –5 –10 RF output power (dBm) –15 –20 –25 –30 –35 –40 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 10 RF input power (dBm) Fig.19 RF input → output limiting transfer characteristic at Frequency = 500MHz 13 SL3522 20 15 10 5 Phase error (degrees) 0 –5 –10 –15 –20 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 RF input power (dBm) Fig.20 Limiting phase (100MHz) normalised at -30dBm 20 15 10 5 Phase error (degrees) 0 –5 –10 –15 –20 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 RF input power (dBm) Fig.21 Limiting phase (300MHz) normalised at -30dBm 14 SL3522 20 15 10 5 Phase error (degrees) 0 –5 –10 –15 –20 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 RF input power (dBm) Fig.22 Limiting phase (500MHz) normalised at -30dBm +j1 +j0.5 +j2 +j0.2 +j5 0 0.2 0.5 600MHz 1 100MHz 2 5 –j0.2 –j5 –j0.5 –j2 –j1 Fig.23 Typical input impedance normalised to 50Ω - 20dBm I/P level 15 16 25 60 23 21 8 LIMITING RF OUTPUT BUFFER STAGE 2 STAGE 3 50R STAGE 4 STAGE 5 STAGES 6&7 50R 9 10 15 5 24 7 22 20 11 14 5kR RF I/P + RF I/P – GAIN V EE GND V EE GND OFFSET – + 13 –0.55V VIDEO O/P BUFFER 500R V EE GND VIDEO V EE GAIN ADJUST TRIM REF OFFSET ADJ VIDEO GND VIDEO V CC 19 VIDEO GAIN & OFFSET ADJUST 12 18 17 16 RG RT RO SL3522 40 27 STAGE 1 20pF 55R 28 25R 20pF 3 26 N/C N/C 1 2 28 27 V EE GND V EE GND 3 4 5 6 26 25 24 23 V EE RF O/P GND RF O/P – RF O/P + 7 8 9 10 22 21 20 19 RF O/P V EE VIDEO O/P V EE VIDEO O/P VIDEO O/P V CC 11 12 13 14 18 17 16 15 Fig.24 SL3522 Schematic diagram SL3522 1 2 46 45 44 43 42 41 40 39 38 37 36 35 34 47 33 32 31 30 29 28 27 26 25 24 23 3 48 49 50 4 51 52 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 5.480mm TO SCALE TERMINALS ((X) DENOTES MC PACKAGE PIN NUMBER) 1 2 3 4 5 6 7 8 9 10 11 12 13 Video O/P (13) Video O/P VCC (14) Gain VCC (15) Video GND (16) Offset ADJ (17) Trim REF (18) Gain ADJ (19) Gain VEE (20) Test point Test point VEE 6A (20) GND 6A (21) GND 5A (21) 14 15 16 17 18 19 20 21 22 23 24 25 26 VEE 5A (22) VEE 4A (22) GND 4B (23) GND 3A (23) VEE 3A (24) VEE 2A (24) GND 2A (25) GND 1A (25) VEE 1A (26) Test point RF I/P signal (27) Test point RF I/P return (28) 27 28 29 30 31 32 33 34 35 36 37 38 39 Test point VEE 1B (3) GND 1B (4) GND 2B (4) VEE 2A (5) VEE 3A (5) GND 3B (6) Test point Test point Test point Test point GND 4B (6) VEE 4B (7) 40 41 42 43 44 45 46 47 48 49 50 51 52 VEE 5B (7) RF BUF O/P GND (8) RF BUF O/P GND (8) RF O/P – (9) RF O/P + (10) RF BUF O/P VEE (11) Video O/P VEE (12) Test point Test point Test point Test point Test point Test point NOTES 1. All pads with square cross–section =120 m 120 m 100 m 2. All pads with octagonal cross–section =100 m 3. Chip is passivated with polyimide Fig.25 SL3522 pad map for bare IC dice 2.085mm 17 http://www.mitelsemi.com World Headquarters - Canada Tel: +1 (613) 592 2122 Fax: +1 (613) 592 6909 North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Asia/Pacific Tel: +65 333 6193 Fax: +65 333 6192 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. However, Mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. 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