VP306

VP305/6 Satellite Channel Decoder Preliminary Information DM5009-1.0 09/07/98 TECHNICAL MANUAL This is an unpublished work the copyright in which vests in Mitel. All rights reserved. The information contained herein is the property of Mitel and is supplied without liability for errors or omissions. No part may be reproduced or used except as authorised by contract or other written permission. The copyright and the foregoing restriction on reproduction and use extend to all media in which the media may be embodied. The VP305/6 is a decoder for digital satellite television transmissions to the European Broadcast Union ETS 300 421 specification (ref. 1). They receive digitised I and Q signals from the tuner, demodulate the QPSK data and provide a complete Forward Error Correction, (FEC) and descrambling function. The output is in the form of packetised MPEG2 transport stream data. The VP305/6 also provides automatic gain control and synchronising signals to the RF front end devices. The VP305 has only a parallel interface port to the control microprocessor. The VP306 has both a serial I²C port and a parallel interface port to the control microprocessor. MITEL CONFIDENTIAL INFORMATION VP305/6 CONTENTS. 1. DRAFT - PRELIMINARY DATA FUNCTIONAL DESCRIPTION. ..............................................................................................7 1.1. System overview. ..........................................................................................................7 1.2. The QPSK Demodulator block. .....................................................................................9 1.2.1. Input requirements. .............................................................................................10 1.2.3. Matched filters.....................................................................................................10 1.2.4. Decimation filters.................................................................................................10 1.2.5. Carrier frequency synchronisation ......................................................................11 1.2.6. Symbol synchronisation and tracking..................................................................12 1.3. The Viterbi Decoder block. ............................................................................................13 1.3.1. Viterbi error count measurement.........................................................................14 1.3.2. Viterbi error count coarse indication....................................................................15 1.4. The De-interleaver block. ..............................................................................................16 1.5. The Reed Solomon block. .............................................................................................18 1.6. The Energy Dispersal (descrambler) block. ..................................................................18 1.6.1. Output stage........................................................................................................19 1.7. Microprocessor interface. ..............................................................................................19 2. REGISTER DETAILS .............................................................................................................20 2.1. Parallel interface register map. .....................................................................................20 2.2. Serial interface register map. ........................................................................................23 2.3. BANK: Register bank address - Parallel mode only......................................................25 2.4. RADD: I²C Register address - Serial mode only. ..........................................................26 2.5. BANK 0: Monitor QPSK read registers..........................................................................27 2.5.1. ID: Identification register. ....................................................................................27 2.5.2. INT_QPSK: Interrupt for QPSK block, register....................................................27 2.5.3. INT_FEC: Interrupt FEC register.........................................................................28 2.5.4. STATUS: Status register. ....................................................................................29 2.5.5. AGC_LVL: AGC loop voltage meter register.......................................................30 2.5.6. CR_VCOF U & L: Measured VCO frequency registers. ......................................30 2.5.7. IE_QPSK: Interrupt enable QPSK register..........................................................31 2.6. BANK 1: Program QPSK registers. ...............................................................................32 2.6.1. SYM_CONFIG: Symbol configuration register. ...................................................32 2.6.2. SYM_RP: Symbol AFC reference period register. ..............................................33 2.6.3. SYM_NF U & L: Symbol input nominal frequency registers................................33 The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 2 DRAFT - PRELIMINARY DATA VP305/6 2.6.4. SYM_RATIO: Symbol input decimation factor register. ...................................... 34 2.6.5. AGC_REF: Reference AGC level registers. ....................................................... 34 2.6.6. AGC_BW: AGC estimation bandwidth register................................................... 35 2.7. BANK 2: Program QPSK registers................................................................................ 36 2.7.1. SCALE: IOUT and QOUT outputs, scale factor register. .................................... 36 2.7.2. SNR_THS: Signal to noise ratio estimator threshold register. ............................ 36 2.7.3. CR_OFFSET: Carrier loop DC offset register..................................................... 37 2.7.3.1. Acquisition Phase. ................................................................................. 38 2.7.3.2. Tracking Phase...................................................................................... 39 2.7.4. CR_RP: Carrier reference period register........................................................... 39 2.7.5. CR_KP: Carrier loop filter gain (P term) register................................................. 40 2.7.6. CR_KD: Carrier loop filter gain (D term) register. ............................................... 40 2.7.7. CR_THSL: Carrier lock detector threshold register. ........................................... 41 2.8. BANK 3: Program QPSK registers................................................................................ 42 2.8.1. CR_SWR: Carrier sweep rate register................................................................ 42 2.8.2. CR_USWL U & L: Carrier Upper sweep limit registers....................................... 43 2.8.3. CR_LSWL U & L: Carrier Lower sweep limit registers. ...................................... 44 2.8.4. CR_CONFIG: Carrier configuration register. ...................................................... 44 2.8.5. CONFIG: Configuration register.......................................................................... 45 2.9. BANK 4: Monitor FEC read registers. ........................................................................... 46 2.9.1. VIT_ERR_C H & L: Viterbi error count registers................................................. 46 2.9.2. RS_UBC: Reed Solomon uncorrected block count register. .............................. 46 2.10. BANK 5: Program FEC registers. ................................................................................. 47 2.10.1. VIT_MODE: Viterbi mode register..................................................................... 47 2.10.2. VIT_ERR H, M & L: Viterbi error period registers. ............................................ 48 2.10.3. VI_MAX_ERR: Viterbi maximum bit error count register. ................................. 48 2.10.4. VI_BER_PER: Viterbi bit error rate based synchronisation period register. ..... 49 2.10.5. VI_BER_LIM: Viterbi bit error rate based synchronisation limit register. .......... 49 2.11. BANK 6: Program FEC and general control registers.................................................. 50 2.11.1. VIT_CTRL1: Viterbi control synchronisation byte register 1 ............................. 50 2.11.2. VIT_CTRL2: Viterbi control synchronisation byte register 2 ............................. 51 2.11.3. IE_FEC: Interrupt FEC register......................................................................... 52 2.11.4. STAT_EN: Status enable register..................................................................... 53 2.11.5. GEN_CTRL: General control register. .............................................................. 54 The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 3 VP305/6 DRAFT - PRELIMINARY DATA 2.11.6. GPP_CTRL: General Purpose Port control register. .........................................54 2.11.7. RESET: Reset register. .....................................................................................55 2.12. BANK 7: Program test registers. ...................................................................................56 2.12.1. TEST1: Test 1 register - for diagnostic / qualification purposes only. ...............56 2.12.2. TEST2: Test 2 register - for diagnostic / qualification purposes only. ...............56 2.12.3. TEST3: Test 3 register - for diagnostic / qualification purposes only. ...............57 3. MICROPROCESSOR CONTROL. .........................................................................................58 3.1. I²C bus Interface............................................................................................................58 3.1.1. Examples of I²C bus messages: ........................................................................59 3.2. Parallel interface. ..........................................................................................................60 3.2.1. Examples of writing to and reading from the parallel interface. ..........................60 3.2.2. Parallel interface Write cycle description. ...........................................................60 3.2.3. Parallel interface Read cycle description. ...........................................................63 4. TIMING INFORMATION. ........................................................................................................65 4.1. I²C bus timing. ...............................................................................................................65 4.2. Parallel interface Write cycle timing. .............................................................................66 4.3. Parallel interface Read cycle timing. .............................................................................66 4.4. Data input timing. ..........................................................................................................67 5. MPEG PACKET DATA OUTPUT...........................................................................................68 5.1. Data output format.........................................................................................................68 5.2. Data output timing. ........................................................................................................70 6. VP305/6 OPERATING CONDITIONS. ...................................................................................71 6.1. Recommended operating conditions.............................................................................71 6.2. Electrical characteristics................................................................................................72 6.3. Crystal specification. ..................................................................................................... 73 6.4. Absolute maximum ratings. ...........................................................................................73 6.5. Pinout description..........................................................................................................74 6.6. Alphabetical listing of the pinout....................................................................................77 6.7. Numerical listing of the pinout. ......................................................................................78 7. 8. 9. REFERENCES. ......................................................................................................................80 APPENDIX 1: FEATURES .....................................................................................................81 APPENDIX 2: LOCK ACQUISITION ALGORITHM. ...............................................................82 9.1. Pre conditions. ..............................................................................................................82 9.2. Lock acquisition algorithm.............................................................................................82 The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 4 DRAFT - PRELIMINARY DATA LIST OF FIGURES. VP305/6 Figure 1. VP305/6 Block Diagram................................................................................................... 7 Figure 2. System Application Diagram ............................................................................................ 9 Figure 3. Carrier and Symbol synchronisation diagram.................................................................. 9 Figure 4. QPSK constellation.......................................................................................................... 10 Figure 5. Symbol filtering ................................................................................................................ 10 Figure 6. Frequency sweep generator ............................................................................................ 11 Figure 7. Viterbi block diagram showing error count generation..................................................... 14 Figure 8. Viterbi error count measurement ..................................................................................... 15 Figure 9. Viterbi error count coarse indication ................................................................................ 16 Figure 10. Conceptual diagram of the convolutional de-interleaver block ...................................... 17 Figure 11. Energy dispersal conceptual diagram............................................................................ 18 Figure 12. Eye diagram................................................................................................................... 34 Figure 13. SNR threshold vs Es / No ............................................................................................. 36 Figure 14. Carrier sweep rise and fall times vs. CR_OFFSET........................................................ 38 Figure 15. Carrier phase error detector gain...................................................................................40 Figure 16. Carrier sweep rate for a delta frequency of ±10MHz. .................................................... 43 Figure 17. Parallel interface write cycle action diagram.................................................................. 61 Figure 18. Parallel interface read cycle action diagram .................................................................. 63 Figure 19. I²C bus timing................................................................................................................. 65 Figure 20. Parallel interface write cycle timing diagram.................................................................. 66 Figure 21. Parallel interface read cycle timing diagram .................................................................. 66 Figure 22. VP305/6 data input timing diagram................................................................................ 67 Figure 23. VP305/6 Transport Packet Header bytes ...................................................................... 68 Figure 24. VP305/6 output data wave form diagram ...................................................................... 69 Figure 25. VP305/6 data output timing diagram ............................................................................. 70 Figure 26. Crystal oscillator circuit. ................................................................................................. 73 Figure 27. Pin connections - top view ............................................................................................. 79 The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 5 VP305/6 LIST OF TABLES. DRAFT - PRELIMINARY DATA Table 1. Decimation ratios...............................................................................................................11 Table 2. Viterbi decoder input format ..............................................................................................13 Table 3. Viterbi decoder code rate ..................................................................................................13 Table 4. De-interleaver data sequence ...........................................................................................17 Table 5a. BANK Register ................................................................................................................20 Table 5b. Register bank 0. BANK[5:3] = 0 ......................................................................................20 Table 5c. Register bank 1. BANK[5:3] = 8....................................................................................... 20 Table 5d. Register bank 2. BANK[5:3] = 16 ....................................................................................21 Table 5e. Register bank 3. BANK[5:3] = 24 ....................................................................................21 Table 5f. Register bank 4. BANK[5:3] = 32 .....................................................................................21 Table 5g. Register bank 5. BANK[5:3] = 40 ....................................................................................22 Table 5h. Register bank 6. BANK[5:3] = 48 ....................................................................................22 Table 5i. Register bank 7. BANK[5:3] = 56...................................................................................... 22 Table 6a. QPSK Register details.....................................................................................................23 Table 6b. FEC Register details .......................................................................................................24 Table 7. BANK address decodes for parallel mode ........................................................................25 Table 9. Viterbi bit error rate threshold............................................................................................49 Table 10. Number of correct bits in the sync byte. .........................................................................50 Table 11. Number of correct sync bytes to retain lock ....................................................................50 Table 12. Number of consecutive sync bytes to establish block lock..............................................51 Table 13. Number of incorrect sync bytes to lose lock....................................................................54 Table 14. Enable / disable circuit blocks .........................................................................................56 Table 15. I²C bus timing ..................................................................................................................65 Table 16. Parallel bus timing ...........................................................................................................67 Table 17. MPEG data output rates ..................................................................................................70 Table 18. Recommended operating conditions...............................................................................71 Table 19. DC Characteristics ..........................................................................................................72 Table 20. Pinout details...................................................................................................................76 Table 21. Alphabetical listing of the pinout......................................................................................77 Table 22. Numerical listing of the pinout .........................................................................................78 The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 6 DRAFT - PRELIMINARY DATA PLEASE NOTE: This manual has the following convention: VP305/6 All numerical values are shown as decimal numbers, unless otherwise defined. 1. FUNCTIONAL DESCRIPTION. CR_VCO SYM_VCO AGC_OUT 2 PSCAL SYS_CLK IIN5:0 QIN5:0 QPSK 3 3 8 Viterbi De-inter leaver 8 Reed Solomon 8 Energy Dispersal 4 2 2 SYMCLK Timing / sync MCLK VERR MOSTRT MDO7:0 MOVAL BKERR MDOEN INTVI INTQP Clock RES Microprocessor Interface SER GPP0 RESET A2:0 R/W AS CS Test XTCK XTO XTI GPP4:1 IRQ DTACK D7:0 SDA STATUS TEST1 TEST2 TEST3 Fig. 1. VP305/6 Block Diagram. 1.1. System overview. The VP305/6 decoder, together with the SL1710 I/Q down converter and the VP216/7 dual analog to digital converter (ADC) devices will provide a DVB compliant, satellite receiver system, see figure 2 on page 9. Before transmission, the data is processed using forward error correction techniques. Energy dispersal is added to even out 'ones' and 'zeros' for the power handling of the satellite output transmission devices. The VP305/6 device decodes the signal by reversing all these encoding techniques. The VP305/6 contains three phase lock loop systems for control of the voltage controlled oscillators in the SL1710, the VP216/7 and an internal numerically controlled oscillator (NCO) in the VP305/6. The NCO can be set to provide a triangular wave form frequency search to establish symbol lock. There are also two AGC systems in the VP305/6, one controlling the SL1710 gain and a second internal AGC control of the output power levels from the QPSK block to the Viterbi block. A crystal oscillator maintaining circuit is provided to sustain a stable frequency reference clock for the synthesiser loops. If a crystal is not used, the reference frequency signal may be input on the XTI pin. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 7 VP305/6 DRAFT - PRELIMINARY DATA A system clock (SYS_CLK) running at twice the symbol data rate is provided by the VCO on the VP216/7 ADC. The dual ADC circuit digitises the In phase (I) and Quadrature phase (Q) analog signals providing two, six bit binary offset, data channels. The code range is, from 000000 = least positive valid output, to 111111 = most positive valid output. These six bit data channels are input to the VP305/6 on the IIN and QIN pins to the QPSK demodulator block, see figure 2 on page 9. There the data is decimated and filtered to obtain the soft decision symbol data to pass to the Viterbi decoder. The QPSK block also generates a bit clock and resolves the π/2 demodulation phase ambiguity. The Viterbi decoder recovers the data by a process of de-puncturing, probability analysis and bit error correction, to obtain the eight bit wide, data bit stream. It also rearranges the bit stream into bytes, providing a byte clock and packet start signal for the subsequent stages. An indication of the bit error rate in the data, is provided in the Viterbi block, by comparing the delayed input data bit stream with the decoded output data bit stream. An actual bit error count may be read from registers and a coarse indication of the number of errors is provided to facilitate satellite receiver dish alignment. The data is then passed to the de-interleaver block where the data is reorganised in a series of FIFOs into the 204 byte blocks for the Reed Solomon decoder. The de-interleaver depth is 12. The Reed Solomon decoder is able to correct up to eight byte errors found in the byte data stream. If there are too many errors to be corrected, the packet will be flagged as uncorrectable. The 16 check bytes are removed and the 188 byte packet is passed to the next block. The final data processing block removes Energy Dispersion and inverts the inverted packet synchronisation byte which is used to mark every eighth 188 byte data packet. The data output from the VP305/6 is in the form of MPEG2 transport stream data packets on the MDO7:0 data bus, together with clock, data start, data valid and block error signals. The data rate is automatically varied, according to the puncture rate, to reduce the instantaneous data rate and the inter packet period. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 8 DRAFT - PRELIMINARY DATA FROM LNB LPF VP216/7 DUAL ADC LPF 479.5MHz VCO IIN QIN VP305/6 SAW SL1710 I/Q DOWN CONVERT VCO /32 VP305/6 SYS_CLK LOOP FILTER SYM_VCO PSCAL CR_VCO AGC_OUT SP5658 FREQ SYNTH. LOOP FILTER AGC LOOP FILTER 14.984375MHz MICROPROCESSOR Fig. 2. System Application Diagram. 1.2. The QPSK Demodulator block. The QPSK demodulator block performs the function of locking the receiver system to the incoming data stream. It controls the voltage controlled oscillators (VCO) in the SL1710 I/Q down converter and the VP216/7 dual analog to digital converter (ADC). The carrier frequency VCO is locked to maintain the intermediate frequency (IF) of 479.5MHz. The symbol frequency VCO synthesiser loop is locked to the twice the required symbol frequency (in the zero decimation case) and generates the system clock SYS_CLK which is running at the bit rate. IIN VP216/7 DUAL ADC VCO 479.5MHz SYS_CLK SYM_NF LOOP FILTER LOOP FILTER 14.984375MHz CONV SYM_VCO XTI CR_VCO PSCAL CR_RP CONV CR_U/LSWL AFC SYM_RP VCO SWEEP GEN SL1710 I/Q DOWN CONVERT /32 VCO LPF LPF VP305/6 QIN Fig. 3. Carrier and Symbol frequency synthesiser diagram. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 9 VP305/6 1.2.1. DRAFT - PRELIMINARY DATA Input requirements. The data input is digitised six bit I and Q channel data in the form of either binary format or offset 2's complement data. The QPSK phase constellation representation is shown below. Q I=1 Q=0 I=0 Q=0 I I=1 Q=1 I=0 Q=1 Fig. 4. QPSK constellation. 1.2.3. Matched filters The Decimation filter and matched filter together have a 0.35 roll-off square-root-raised-cosine frequency response as in reference 1. 1.2.4. Decimation filters In order to adjust to the wide range of symbol rates (5 to 30Msym/s), the I and Q data in may be decimated by varying degrees. The system also allows for the ADC sample clock to be adjusted to within the range 30 to 62MHz. The sample rate at the input to the matched filter is equal to twice the symbol rate, 2Rs. The SYM_DR bits in the SYM_CONFIG register can be programmed to allow for the following filtered symbol rates at the input to the VP305/6: 2Rs, 3Rs, 4Rs, where Rs = symbol rate. IIN QIN SYM_RATIO unfiltered Decimation SYM_RP filtered Decimation Matched Filter Fig. 5. Symbol filtering. The SYM_RATIO register allows the input symbol rate to be extended further to cover 6Rs, 8Rs, 12Rs, 16Rs, 24Rs, 32Rs, 48Rs and 64Rs unfiltered decimation rates. The number of samples / Symbol (M) can be calculated from the formula: M = (SYM_DR over sample rate) * (2SYM_RATIO) The range of values of M is shown in the table below. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 10 DRAFT - PRELIMINARY DATA VP305/6 SYM_RATIO SYM_DR 0 - (over sample 2) 1 - (over sample 4) 2 - (over sample 3) 0 1 2 3 4 M M M M M samples/Sym samples/Sym samples/Sym samples/Sym samples/Sym 2 4 3 4 8 6 8 16 12 16 32 24 32 64 48 Table 1. Decimation ratios. 1.2.5. Carrier frequency synchronisation The SL1710 local oscillator frequency of 479.5MHz is maintained by a frequency synthesis loop on the VP305/6. The SL1710 voltage controlled oscillator (VCO) frequency is divided internally by 32 to generate a push-pull feedback reference frequency signal. This is connected to the VP305/6 PSCAL PECL inputs and then to the CR_U/LSWL dividers. The output from the CR_U/LSWL dividers is compared with the crystal oscillator frequency divided by the CR_RP division ratio. A feedback signal (CR_VCO) is output to an active filter to complete the loop and control the SL1710 VCO, see Fig. 3 on page 9. The internal frequency sweep generator is controlled by the CR_SWR, CR_USWL,CR_LSWL, CR_RP registers and turned on and off by the CR_SW bit in the CONFIG register. The diagram in Fig. 3 on page 9 shows the registers which set up the dividers for both the carrier and symbol phase locked loops. t f Upper Sweep Limit Lower Sweep Limit Sweep Start Point Fig. 6. Frequency sweep generator. The carrier frequency reference period (CR_RP register) sets the count of the crystal clock cycles ( XTI pin). This sets the reference for the measurement of the I/Q down converter VCO frequency (PSCAL pins). The register value sets the 4 most significant bits of a 14 bit counter. The actual count is CR_RP[3:0] * 1024. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 11 VP305/6 DRAFT - PRELIMINARY DATA Fcrystal The comparison frequency, Fcomp = CR_RP * 1024 MHz. The upper and lower sweep boundaries are set by the CR_USWL and CR_LSWL respectively. These registers actually set the division ratios for dividing the I/Q down converter VCO frequency. The value programmed must take account of any fixed prescaler in the I/Q down converter, for the SL1710 this is divide by 32. Fvco The comparison frequency, Fcomp = 32 * CR_U/LSWL MHz. Therefore, Therefore, Therefore, Fvco Fcrystal CR_RP * 1024 = 32 * CR_U/LSWL Fcrystal * 32 * CR_U/LSWL = Fvco * CR_RP * 1024 Fvco 32 * CR_U/LSWL Fcrystal = CR_RP * 1024 The upper and lower sweep limits can be expressed in terms of the above equations together with two further terms including the delta variation in frequency. Let the delta variation in frequency = ± δF. Then the frequency limits are Fvco + δF and Fvco - δF. Therefore, CR_USWL = (Fvco + δF) * CR_RP * 1024 Fcrystal * 32 (Fvco - δF) * CR_RP * 1024 Fcrystal * 32 and CR_LSWL = When the AFC circuit achieves lock, as indicated by the CR_FLOCK bit in the STATUS register going high, the scaled carrier frequency can be read from the CR_VCOF U & L registers. The actual carrier frequency is found from the following formula: 32 * Fcrystal Fvco = CR_RP * 1024 * CR_VCOF MHz 1.2.6. Symbol synchronisation and tracking see page 30. The VP216/7 local oscillator frequency must be programmed to be at least twice the required symbol rate and is maintained by a Phase Locked Loop on the VP305/6. The ADC sample frequency should be adjusted by setting the SYM_NF and SYM_RP division ratios to match the decimation rate chosen. The VP216/7 voltage controlled oscillator (VCO) frequency is connected to the VP305/6 SYS_CLK input and then to the SYM_NF divider. The output from the SYM_NF divider is compared with the crystal oscillator frequency divided by the SYM_RP division ratio. A push-pull feedback signal (SYM_VCO) is output to an active filter to complete the loop and control the VP216/7 VCO, see Fig. 3 on page 9. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 12 DRAFT - PRELIMINARY DATA VP305/6 1.3. The Viterbi Decoder block. The Viterbi decoder input data format uses three bit, two's complement coding representation of the data in the following form, (binary numbers): I or Q value 011 010 001 000 111 110 101 100 Interpretation most likely one least likely one least likely zero most likely zero Table 2. Viterbi decoder input format. The first task for the Viterbi decoder is to 'de-puncture' the data. This is a process of restoring data bits which have been removed (punctured), prior to transmission, to improve the transmission efficiency. The de-puncture code rate must be programmed into the VIT MODE register. The following patterns are used: VITCR[2:0] 0 1 2 3 4 Code rate 1/2 2/3 3/4 5/6 7/8 Input bit stream I = X1 Q = Y1 I = X1Y2Y3 Q = Y1X3Y4 I = X1Y2 Q = Y1X3 I = X1Y2Y4 Q = Y1X3X5 I = X1Y2Y4Y6 Q = Y1Y3X5X7 Output bit stream X=1 Y=1 X = 1010 Y = 1111 X = 101 Y = 110 X = 10101 Y = 11010 X = 1000101 Y = 1111010 Table 3. Viterbi decoder code rate. The zeros in the above table represent unknown data bit values, effectively error bits. The decoder uses a trace back trellis technique to remove the uncertainty and recover the correct data. The trace back depth is 128. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 13 VP305/6 1.3.1. DRAFT - PRELIMINARY DATA Viterbi error count measurement. A measure of the effectiveness of the Viterbi decoder in removing bit errors is provided in the VP305/6. The incoming data bit stream is delayed and compared with the decoded bit stream to obtain a count of errors corrected by the decoder, see the Fig. 7 below. VITERBI DECODER DATA BIT STREAM VITERBI ENCODER DELAY COMP ERROR COUNT Fig. 7. Viterbi block diagram showing error count generation. The measurement system has a programmable register to determine the number of data bits (the error count period) over which the count is being recorded. A read register indicates the error count result and an interrupt can be generated to inform the host microprocessor that a new count is available. The VIT ERR H-M-L group of three registers is programmed with required number of data bits (the error count period) (VITEP[23:0]). The actual value is four times VITEP[23:0]. The count of errors found during this period is loaded by the VP305/6 into the VIT ERR C H-L pair of registers when the bit count VITEP[23:0] is reached. At the same time an interrupt is generated on the IRQ line. The actual error count value is four times VERRC[15:0]. If a value of 65535 is read out, the error count is too large for the VERRC[15:0] registers, so the error period in VITEP[23:0] should be reduced. The interrupt is enabled by setting the IE_FEC[2] bit in the IE_FEC register, see page 52. VERRC[15:0] is not cleared by reading the register, it is only loaded with the error count. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 14 DRAFT - PRELIMINARY DATA ERROR COUNT VP305/6 VERRC[15:0] 0 0 VITEP[23:0] DATA BITS IRQ Fig. 8. Viterbi error count measurement. Figure 8 above shows the bit errors rising until the maximum programmed value of VITEP[23:0] is reached, when an interrupt is generated on the IRQ line to advise the host microprocessor that a new value of bit error count has been loaded into the VERRC[15:0] register. The IRQ line will go high when the IE_FEC register is read by the host microprocessor. The error count may be expressed as a ratio: 1.3.2. VERRC[15:0] VITEP[23:0] . Viterbi error count coarse indication. To assist in the process of aligning the receiver dish aerial, a coarse indication of the number of bit errors being received can be provided by monitoring the VERR line with the following set up conditions. The frequency of the output wave form will be a function of the bit error count (triggering the maximum value programmed into the VI MAX ERR register (VMERR[7:0])) and the dish alignment on the satellite. This VERR mode is enabled by setting the INTVIS bit in the TEST2 register. Figure 9 below shows the bit errors rising to the maximum programmed value and triggering a change of state on the VERR line. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 15 VP305/6 V IT E R B I COAR S E B IT E R R OR COU N T DRAFT - PRELIMINARY DATA V M E R R [7 :0 ] 0 0 D AT A B I T S VE R R Fig. 9. Viterbi error count coarse indication. 1.4. The De-interleaver block. Before transmission, the data bytes are interleaved with each other in a cyclic pattern of twelve. This ensures the bytes are spaced out, so that successive message bytes are transmitted with a separation of at least 12 bytes. This system is used to avoid the possibility of a noise spike corrupting a group of consecutive message bytes. The diagram below shows conceptually how the convolutional de-interleaving system works. The synchronisation byte is always loaded into the First-In-First-Out (FIFO) memory in branch 0. The switch is operated at regular byte intervals to write successively received bytes into the next branch. After 12 bytes have been received, byte 13 is written next to the synchronisation byte in branch 0, etc. Only when the FIFOs are full, will the read out of the 204 byte message be enabled. On the VP305/6, this function is realised in random access memory (RAM) with some spare capacity to avoid messages being over written before they are read out. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 16 DRAFT - PRELIMINARY DATA 0 one byte per position 1 17x10 bytes 2 17x9 bytes 3 17x8 bytes 4 17x7 bytes 5 17x6 bytes 6 17x5 bytes 7 17x4 bytes 8 17x3 bytes 9 17x2 bytes 10 17x1 11 11 10 9 8 7 6 5 4 3 2 Sync word route 17x11 bytes 1 0 VP305/6 Fig. 10. Conceptual diagram of the convolutional de-interleaver block. The byte sequence for the first 204 byte block is shown below. Each row represents one branch FIFO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 109 121 133 145 157 169 181 193 110 122 134 146 158 170 182 194 111 123 135 147 159 171 183 195 100 112 124 136 148 160 172 184 196 101 113 125 137 149 161 173 185 197 102 114 126 138 150 162 174 186 198 103 115 127 139 151 163 175 187 199 104 116 128 140 152 164 176 188 200 105 117 129 141 153 165 177 189 201 106 118 130 142 154 166 178 190 202 107 119 131 143 155 167 179 191 203 108 120 132 144 156 168 180 192 204 Table 4. De-interleaver data sequence. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 17 VP305/6 1.5. DRAFT - PRELIMINARY DATA The Reed Solomon block. In the Transmission system, the MPEG2 message packet is encoded using the Reed Solomon RS(204,188, T=8) shortened code. This converts the 188 byte data packet into a Reed Solomon encoded block containing 204 bytes. The 16 check bytes allow the decoding system to search the packet for errors and correct up to eight bytes containing errors. If there are more than eight bytes containing errors, the packet is flagged as containing uncorrectable errors by pulling the BKERR pin low and setting the TEI bit in the second byte of the packet header, see figure 21 on page 68. The number of blocks containing uncorrectable errors may be read from the RS UBC register which is reset to zero each time it is read. The 16 check bytes are discarded before the data packet is passed on to the Energy Dispersal block. Sync byte 187 bytes Reed Solomon encoded block. Sync byte 187 bytes MPEG2 transport packet. 16 check bytes 1.6. The Energy Dispersal (descrambler) block. Before Reed Solomon encoding in the transmission system, the MPEG2 data stream is randomised using the configuration shown in figure 11 below. This is a Pseudo Random Binary Sequence (PRBS) generator, with the polynomial: 1 + X14 + X15 The PRBS registers are loaded with the initialisation sequence as shown, at the start of the first transport packet in a group of eight packets. This point is indicated by the inverted sync byte B8hex. The normal sync. byte is 47hex. The data starting with the first byte after the sync. byte is randomised. (The sync. bytes themselves are not randomised). In the decoder, the process of de-randomising or de scrambling the data is exactly the same as described above. Initialisation sequence 1 0 1 0 0 6 7 8 9 10 1 1 0 2 0 3 1 4 0 5 0 11 0 0 0 14 0 15 12 13 XOR Fig. 11. Energy dispersal conceptual diagram. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 18 DRAFT - PRELIMINARY DATA 1.6.1. Output stage. VP305/6 A complete transport stream data packet of 188 bytes is output on the MDO7:0 bus, clocked by the MCLK signal. The MDO7:0 bus is enabled by pulling the MDOEN low. The start sync byte is flagged by the MOSTRT signal going high and the MOVAL signal will also go high to indicate a valid packet. If the packet contains uncorrectable bytes, a BKERR signal will go low on the first error byte and remain low until the end of the packet. The TEI bit in the packet header can optionally be set automatically to indicate a packet with uncorrectable bytes. 1.7. Microprocessor interface. This interface can be either a serial I²C bus or a parallel interface port, see section 3 starting on page 58. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 19 VP305/6 2. DRAFT - PRELIMINARY DATA REGISTER DETAILS 2.1. Parallel interface register map. The default state of almost all of the registers is zero, except the ID register and unused registers. Reserved or unused bits should be set to zero when writing to a register. NAME BANK ADR 0 D7 D6 D5 AD5 D4 AD4 D3 AD3 D2 D1 Reserved D0 R/W W Reserved Table 5a. BANK Register 0. (Address byte = 0, Data byte = NEXT BANK) NAME ID INT_QPSK INT_FEC STATUS AGC_LVL CR_VCOF U CR_VCOF L IE_QPSK ADR 0 1 2 3 4 5 6 7 Reserved Reserved D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R/W ID[7:0] Chip identification INT_QPSK[7:0] Interrupt QPSK INT_FEC[7:0] Interrupt FEC STATUS[6:0] AGC_LVL[7:0] AGC loop voltage meter CR_VCOF[13:8] Measured VCO frequency (upper nibble) IE_QPSK[7:0] Interrupt enable QPSK CR_VCOF[7:0] Measured VCO frequency (lower byte) Table 5b. Register bank 0. BANK[5:3] = 0. Note: In Bank 0, the registers 1 to 6 are READ only. Writing to these addresses will have no effect. NAME ID SYM_CONFIG SYM_RP SYM_NF U SYM_NF L SYM_RATIO AGC_REF AGC_BW ADR 0 1 2 3 4 5 6 7 Reserved Reserved D7 D6 D5 D4 D3 D2 D1 D0 R/W R R/W R/W R/W R/W R/W R/W AGC_BW[2:0] R/W ID[7:0] Chip identification SYM_CONFIG[5:0] Symbol configuration SYM_RP[3:0] Symbol AFC reference period SYM_NF[15:8] Symbol input nominal frequency (upper byte) SYM_NF[7:0] Symbol input nominal frequency (lower byte) Reserved Reserved INT_DC SYM_RATIO[2:0] AGC_REF[7:0] Reference AGC level Table 5c. Register bank 1. BANK[5:3] = 8. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 20 DRAFT - PRELIMINARY DATA NAME ID SCALE SNR_THS CR_OFFSET CR_RP CR_KP CR_KD CR_THSL ADR 0 1 2 3 4 5 6 7 D7 D6 D5 D4 D3 D2 D1 VP305/6 D0 R/W R R/W R/W R/W R/W R/W R/W R/W ID[7:0] Chip identification SCALE[7:0] Scale factor for IOUT and QOUT outputs SNR_THS[7:0] SNR estimator threshold CR_OFFSET[7:0] Carrier loop DC offset compensation value Reserved CR_RP[3:0] Carrier reference period CR_KP[7:0] Carrier loop filter gain (P term) CR_KD[7:0] Carrier loop filter gain (D term) CR_THSL[7:0] Carrier lock detector threshold Table 5d Register bank 2. BANK[5:3] = 16. NAME ID CR_SWR CR_USWL U CR_USWL L CR_LSWL U CR_LSWL L CR_CONFIG CONFIG ADR 0 1 2 3 4 5 6 7 Reserved Reserved D7 D6 D5 D4 D3 D2 D1 D0 R/W R R/W R/W R/W R/W R/W R/W R/W ID[7:0] Chip identification CR_SWR[7:0] Carrier sweep rate CR_USWL[13:8] Carrier Upper sweep limit (upper nibble) CR_LSWL[13:8] Carrier Lower sweep limit (upper nibble) CR_CONFIG[7:0] Carrier configuration CONFIG[7:0] Configuration CR_USWL[7:0] Carrier Upper sweep limit (lower byte) CR_LSWL[7:0] Carrier Lower sweep limit (lower byte) Table 5e. Register bank 3. BANK[5:3] = 24. NAME ID VIT_ERR_C H VIT_ERR_C L RS_UBC Not used ADR 0 1 2 3 4-7 D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R/W ID[7:0] Chip identification VERRC[15:8] - Viterbi error count high byte VERRC[7:0] - Viterbi error count low byte RSUBC[7:0] - Reed Solomon uncorrected block count Writing to these addresses will have no effect. Reading will return 255 Table 5f. Register bank 4. BANK[5:3] = 32. Note: In Bank 4, the registers 1 to 3 are READ only and registers 4 to 7 are not used. Writing to these addresses will have no effect. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 21 VP305/6 DRAFT - PRELIMINARY DATA NAME ID VIT_MODE VIT_ERR H VIT_ERR M VIT_ERR L VI_MAX_ERR VI_BER_PER VI_BER_LIM ADR 0 1 2 3 4 5 6 7 D7 D6 D5 D4 Reserved D3 D2 D1 D0 R/W R R/W R/W R/W R/W R/W R/W R/W ID[7:0] Chip identification IQSWAP F_LOCK VITCR[2:0] - code rate VITEP[23:16] - Viterbi error period high byte VITEP[15:8] - Viterbi error period middle byte VITEP[7:0] - Viterbi error period low byte VMERR[7:0] - Viterbi max. bit error count VBPER[7:0] - Viterbi bit error rate based synchronisation period VBLIM[7:0] - Viterbi bit error rate based synchronisation limit Table 5g. Register bank 5. BANK[5:3] = 40. NAME ID VIT_CTRL1 VIT_CTRL2 IE_FEC STAT_EN GEN_CTRL GPP_CTRL RESET ADR 0 1 2 3 4 5 6 7 RES Reserved BS_MODE[1:0] Reserved IE_FEC[7:0] Interrupt enable FEC STAT_EN[7:0] Enable various outputs on STATUS pin. MCLKINV BSO PR_DS ENTEI PR_BS NSYNC[1:0] FR_QP GPP_CTRL[4:0] D7 D6 D5 D4 D3 D2 D1 D0 R/W R VBIT_MV[1:0] VS_LK[2:0] R/W R/W R/W R/W R/W R/W PR_QP R/W ID[7:0] Chip identification VS_UNLK[3:0] Table 5h. Register bank 6. BANK[5:3] = 48. NAME ID TEST1 TEST2 TEST3 Not used ADR 0 1 2 3 4-7 INTVIS Reserved Writing to these addresses will have no effect. Reading will return 255 D7 D6 D5 D4 D3 D2 D1 D0 R/W R R/W EN[3:0] R/W R/W R/W ID[7:0] Chip identification Reserved Table 5i. Register bank 7. BANK[5:3] = 56. Note: In Bank 7, the registers 4 - 7 are not used. Writing to these addresses will have no effect. Note: When writing to, or reading from registers which are part of a group, all registers in the group must be addressed for the data transfer to be sucessfully completed. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 22 DRAFT - PRELIMINARY DATA 2.2. Serial interface register map. Not available on VP305. The default state of all registers is reset to 0. Reserved or unused bits should be set to zero when writing to a register. All values are shown as decimal numbers, unless otherwise defined. NAME RADD ID INT_QPSK INT_FEC STATUS AGC_LVL CR_VCOF U CR_VCOF L Not used IE_QPSK ID SYM_CONFIG SYM_RP SYM_NF U SYM_NF L SYM_RATIO AGC_REF AGC_BW ID SCALE SNR_THS CR_OFFSET CR_RP CR_KP CR_KD CR_THSL ID CR_SWR CR_USWL U CR_USWL L CR_LSWL U CR_LSWL L CR_CONFIG CONFIG 00 01 02 03 04 05 06 01-06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reserved Reserved Reserved Reserved Reserved Reserved ADR D7 IAI D6 AD6 D5 AD5 D4 AD4 D3 AD3 D2 AD2 D1 AD1 VP305/6 D0 AD0 R/W W R R R R R R R W R/W R R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W ID[7:0] Chip identification. Writing to this address will have no effect. INT_QPSK[7:0] Interrupt QPSK INT_FEC[7:0] Interrupt FEC STATUS[6:0] AGC_LVL[7:0] AGC loop voltage meter CR_VCOF[13:8] Measured VCO frequency (upper nibble) Writing to these addresses will have no effect. IE_QPSK[7:0] Interrupt enable QPSK ID[7:0] Chip identification. Writing to this address will have no effect. SYM_CONFIG[5:0] Symbol configuration SYM_RP[3:0] Symbol AFC ref. period CR_VCOF[7:0] Measured VCO frequency (lower byte) SYM_NF[15:8] Symbol input nominal frequency (upper byte) SYM_NF[7:0] Symbol input nominal frequency (lower byte) Reserved Reserved INT_DC SYM_RATIO[2:0] AGC_BW[2:0] AGC_REF[7:0] Reference AGC level ID[7:0] Chip identification. Writing to this address will have no effect. SCALE[7:0] Scale factor for IOUT and QOUT outputs SNR_THS[7:0] SNR estimator threshold CR_OFFSET[7:0] Carrier loop DC offset compensation value Reserved CR_RP[3:0] Carrier reference period CR_KP[7:0] Carrier loop filter gain (P term) CR_KD[7:0] Carrier loop filter gain (D term) CR_THSL[7:0] Carrier lock detector threshold ID[7:0] Chip identification. Writing to this address will have no effect. CR_SWR[7:0] Carrier sweep rate CR_USWL[13:8] Carrier Upper sweep limit (upper nibble) CR_LSWL[13:8] Carrier Lower sweep limit (upper nibble) CR_CONFIG[7:0] Carrier configuration CONFIG[7:0] Configuration CR_USWL[7:0] Carrier Upper sweep limit (lower byte) CR_LSWL[7:0] Carrier Lower sweep limit (lower byte) Table 6a. QPSK Register details. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 23 VP305/6 NAME ID VIT_ERR_C H VIT_ERR_C L RS_UBC Not used Not used ID VIT_MODE VIT_ERR H VIT_ERR M VIT_ERR L VI_MAX_ERR VI_BER_PER VI_BER_LIM ID VIT_CTRL1 VIT_CTRL2 IE_FEC STAT_EN GEN_CTRL GPP_CTRL RESET ID TEST1 TEST2 TEST3 Not used ADR 32 33 34 35 33-35 36-39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60-63 INTVIS RES D7 DRAFT - PRELIMINARY DATA D6 D5 D4 D3 D2 D1 D0 R/W R R R R W R/W R R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W PR_QP R/W R R/W EN[3:0] R/W R/W R/W NSYNC[1:0] FR_QP ID[7:0] Chip identification. Writing to this address will have no effect. VERRC[15:8] - Viterbi error count high byte VERRC[7:0] - Viterbi error count low byte RSUBC[7:0] - Reed Solomon uncorrected block count Writing to these addresses will have no effect. Writing to these addresses will have no effect. Reading will return 255 ID[7:0] Chip identification. Writing to this address will have no effect. IQSWAP F_LOCK Reserved VITCR[2:0] - code rate VITEP[23:16] - Viterbi error period high byte VITEP[15:8] - Viterbi error period middle byte VITEP[7:0] - Viterbi error period low byte VMERR[7:0] - Viterbi max. bit error count VBPER[7:0] - Viterbi bit error rate based synchronisation period VBLIM[7:0] - Viterbi bit error rate based synchronisation limit ID[7:0] Chip identification. Writing to this address will have no effect. BS_MODE[1:0] Reserved IE_FEC[7:0] Interrupt enable FEC STAT_EN[7:0] Enable various outputs on STATUS pin. Reserved MCLKINV BSO PR_DS Reserved Reserved Writing to these addresses will have no effect. Reading will return 255 ENTEI PR_BS GPP_CTRL[4:0] VS_UNLK[3:0] VBIT_MV[1:0] VS_LK[2:0] ID[7:0] Chip identification. Writing to this address will have no effect. Table 6b. FEC Register details. Note: When writing to, or reading from registers which are part of a group, all registers in the group must be addressed for the data transfer to be sucessfully completed. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 24 DRAFT - PRELIMINARY DATA 2.3. BANK: Register bank address - Parallel mode only. VP305/6 Registers are directly addressed via the address bus in banks of seven. In the BANK register 0, the bits AD5, AD4 and AD3 are used to select the active register bank to be used until changed by writing to the BANK register. For examples of use, see page 60. Parallel mode Bank 0. Address 0. Type Write. Serial mode - see RADD / ID registers on pages 26 and 27. 7 Reserved AD[2:0] 6 5 AD5 4 AD4 3 AD3 2 1 Reserved 0 R/W W Reserved - not used. If these bits are written they are ignored by the VP305/6. This allows the microprocessor to write the BANK address with the serial mode register address. Bank address These are the active bits in the register. See table 7 below for details. AD5 0 0 0 0 1 1 1 1 AD4 AD3 Bank Function AD[5:3] BANK[5:0] decimal 0-7 8 - 15 16 - 23 24 - 31 32 - 39 40 - 47 48 - 55 56 - 59 0 0 0 Monitor interrupts and QPSK registers 0 1 1 Program QPSK registers 1 0 2 Program QPSK registers 1 1 3 Program QPSK registers 0 0 4 Monitor FEC registers 0 1 5 Program FEC registers 1 0 6 Program FEC and general registers 1 1 7 Program test registers Table 7. BANK address decodes for parallel mode. The register address in parallel mode may be calculated from the serial mode register address as follows: Parallel address = serial address (mod 8) Example where mod = modulus CR_CONFIG register: serial address =30, parallel = Bank 3 address 6 Bank address = 30 (serial address) Alternatively, the bit value is: BANK[5:3] = (30 - (30 mod 8)) = (30 - 6) = 24 This equates to Bank 3, see table 7 above. ) Parallel Address = 30 mod 8 = 6. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 25 VP305/6 DRAFT - PRELIMINARY DATA 2.4. RADD: I²C Register address - Serial mode only. Not available on VP305. RADD is the I²C register address. It is the first byte written after the VP306 I²C chip address when in write mode. To write to the chip, the microprocessor should send a START condition and the chip address with the write bit set, followed by the register address where subsequent data bytes are to be written. Finally, when all the 'message' has been sent, a STOP condition is sent to free the bus. To read from the chip from register address one, the microprocessor should send a START condition and the chip address with the read bit set, followed by the requisite number of SCL clocks to read the bytes out. Finally a STOP condition is sent to free the bus. RADD is not sent in this case. To read from the chip from an address other than one, the microprocessor should send the chip address with the write bit set, followed by the register address where subsequent data bytes are to be read from. Then the microprocessor should send a START condition and the chip address with the read bit set, followed by the requisite number of SCL clocks to read the bytes out. Finally a STOP condition is sent to free the bus. This case should also be used to read the chip identification number in register zero. A STOP condition shall reset the RADD value to 01. For examples of use, see page 59. Serial mode - Address none. 7 IAI AD[6:0] 6 AD6 5 AD5 Type Write. 4 AD4 3 AD3 2 AD2 1 AD1 0 AD0 R/W W I²C register address, numbers in the range 0 to 63 are allowed. AD6 should be set to zero. High = Inhibit auto increment. Low = Increment addresses. The IAI bit and function is only available via the I²C port. When the address is incremented to 63 it stops and the bus will continue to write to or read from 'register' 63 until a STOP condition is sent. Since 'register' 63 does not exist, data writen to it is lost or it will read back 255. IAI The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 26 DRAFT - PRELIMINARY DATA 2.5. BANK 0: Monitor QPSK read registers. 2.5.1. ID: Identification register. Parallel mode Bank 0-7. Address 0.Type Read. Serial mode - Addresses 00, 08, 16, 24, 32, 40, 48, 56. 7 6 5 4 3 ID[7:0] Chip identification 2 1 0 VP305/6 R/W R ID[7:0] Identification: 0 = VP305/6 version. 2.5.2. INT_QPSK: Interrupt for QPSK block, register. These bits indicate the QPSK block event causing the interrupt signalled by the IRQ line going low. The IRQ line is reset high and the register is reset to zero when the INT_QPSK register is read. The events can be masked from activating both the INT_QPSK register bit and the IRQ line by setting the appropriate event masking bit LOW in the IE_QPSK (interrupt enable) register, see page 31. All bits in the IE_QPSK register should be set high. Parallel mode Bank 0. Address 1. Type Read. Serial mode - Address 01. 7 6 5 4 3 INT_QPSK[7:0] 2 1 0 INT_QPSK[0] High = Symbol AFC lock is detected. This means that the number of clock VCO cycles measured during the reference period set by SYM_RP register is in the range SYM_NF (register) ±2 range. INT_QPSK[1] High = Symbol AFC lock is lost. INT_QPSK[2] High = Carrier Phase lock is detected. INT_QPSK[3] High = Carrier Phase lock is lost. INT_QPSK[4] High = Carrier Frequency lock is detected. INT_QPSK[5] High = Carrier Frequency lock is lost. INT_QPSK[6] High = Frequency sweep has reached its lower limit. INT_QPSK[7] High = Frequency sweep has reached its upper limit. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 27 VP305/6 DRAFT - PRELIMINARY DATA 2.5.3. INT_FEC: Interrupt FEC register. These bits indicate the FEC block event causing the interrupt signalled by the IRQ line going low. The IRQ line is reset high and the register is reset to zero when it is read. The events can be masked from activating the IRQ line by setting the appropriate event masking bit in the IE_FEC (interrupt enable) FEC register, see page 52. The masking of events does not affect the setting of the bits in the INT_FEC register. Parallel mode Bank 0. Address 2. Type Read. Serial mode - Address 02. 7 6 5 4 3 INT_FEC[7:0] 2 1 0 INT_FEC[0] INT_FEC[1] INT_FEC[2] INT_FEC[3] INT_FEC[4] INT_FEC[5] INT_FEC[6] INT_FEC[7] High = Descrambler lock established. High = Descrambler lock is lost. High = Viterbi error monitor period has reached the value programmed in the VMERR[7:0] register. Reserved. High = Viterbi bit lock established. High = Viterbi bit lock is lost. High = Frame alignment lock established. (A Frame is 8 blocks, each block is 204 bytes). High = Frame alignment lock is lost. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 28 DRAFT - PRELIMINARY DATA 2.5.4. STATUS: Status register. Parallel mode Bank 0. Addresses 3. Serial mode - Address 03. 7 Reserved 6 5 4 Type Read. VP305/6 3 STATUS[6:0] 2 1 0 The register is NOT reset to zero when it is read. Each of these indicators can be output on the STATUS pin by enabling the appropriate bit in the STAT_EN register, see page 53. STATUS[0] STATUS[1] STATUS[2] STATUS[3] STATUS[4] STATUS[5] STATUS[6] High = SYM_LCF, Symbol AFC within pull-in range. Low = SYM_LCF, Symbol AFC not within pull-in range. High = CR_LC, carrier loop in lock. Low = CR_LC, carrier loop out of lock. High = CR_LCF, carrier frequency detector in lock. Low = CR_LCF, carrier frequency detector out of lock. High = good SNR. Low = bad SNR. High = Descrambler lock detector in lock. Low = Descrambler lock detector out of lock. High = Viterbi bit lock detector in lock. Low = Viterbi bit lock detector out of lock. High = Frame align detector in lock. Low = Frame align detector out of lock. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 29 VP305/6 DRAFT - PRELIMINARY DATA 2.5.5. AGC_LVL: AGC loop voltage meter register. Parallel mode Bank 0. Address 4. Type Read. Serial mode - Address 04. 7 6 5 4 3 2 AGC_LVL[7:0] AGC loop voltage meter 1 0 AGC_LVL[7:0] AGC loop voltage meter. The register is NOT reset to zero when it is read. The relationship between the loop voltage Vagc and the AGC_LVL register is: Vagc = AGC_LVL * Vref / 256 The AGC_OUT pin has an open drain buffer allowing an external Vref of up to 5 volts to be used. 2.5.6. CR_VCOF U & L: Measured VCO frequency registers. Parallel mode Bank 0. Addresses 5, 6. Serial mode - Addresses 05, 06. 7 6 Type Read. 5 4 3 2 1 0 Reserved CR_VCOF[13:8] Measured VCO frequency (upper nibble) CR_VCOF[7:0] Measured VCO frequency (lower byte) These two bytes together form the 14 bit number: CR_VCOF[13:0] Measured carrier VCO frequency. The register is NOT reset to zero when it is read. The actual carrier frequency is found from the following formula: 32 * Fcrystal Fvco = CR_RP * 1024 * CR_VCOF The incremental carrier step frequency is found by putting the value of CR_VCOF = 1 in the equation: 32 * Fcrystal δFvco = CR_RP * 1024 * 1 See page 12 for further discussion. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 30 DRAFT - PRELIMINARY DATA 2.5.7. IE_QPSK: Interrupt enable QPSK register. VP305/6 When the bits of this register are set high, they enable an event to be signalled in the INT_QPSK register to generate an interrupt on the IRQ pin. All bits should be set high, see page 27. Parallel mode Bank 0. Address 7. Type Read / Write. Serial mode - Address 07. 7 6 5 4 3 2 IE_QPSK[7:0] Interrupt enable QPSK 1 0 IE_QPSK[7:0]Interrupt enable QPSK. When : IE_QPSK[i] =1 : enable INT_QPSK[i] IE_QPSK[i] =0 : disable INT_QPSK[i] where i = 0 to 7. IE_QPSK[0] High = Enable Symbol AFC lock detected indication in INT_QPSK register. IE_QPSK[1] High = Enable Symbol AFC lock lost indication in INT_QPSK register. IE_QPSK[2] High = Enable Carrier Phase lock detected indication in INT_QPSK register. IE_QPSK[3] High = Enable Carrier Phase lock lost indication in INT_QPSK register. IE_QPSK[4] High = Enable Carrier Frequency lock detected indication in INT_QPSK register. IE_QPSK[5] High = Enable Carrier Frequency lock lost indication in INT_QPSK register IE_QPSK[6] High = Enable Frequency sweep has reached its lower limit indication in INT_QPSK register. IE_QPSK[7] High = Enable Frequency sweep has reached its upper limit indication in INT_QPSK register. (default state) The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 31 VP305/6 DRAFT - PRELIMINARY DATA 2.6. BANK 1: Program QPSK registers. 2.6.1. SYM_CONFIG: Symbol configuration register. Parallel mode Bank 1. Address 1. Type Read / Write. Serial mode - Address 09. 7 Reserved 6 5 4 3 2 1 SYM_CONFIG[5:0] Symbol configuration 0 SYM_CONFIG[1:0] SYM_DR[1:0] Filtered decimation ratio select. 00 = no decimation (over sampling ratio = 2) 01 = decimation by 1/2 (over sampling ratio = 4) 10 = decimation by 2/3 (over sampling ratio = 3) See also SYM_RATIO: Input decimation factor register, page 34. SYM_CONFIG[2] SYM_VCO _SWAP High = swap U and D output polarity, pins 96 and 97. Low = normal SYM_CONFIG[3] SYM_LCF _SUPP High = suppress timing error detector. Low = normal SYM_CONFIG[4] SYM_VCO U/D High = tri-state D and U outputs. Low = active outputs. SYM_CONFIG[5] SYM_CONFIG[6] SYM_CONFIG[7] Reserved set low. Reserved set low. Reserved set low. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 32 DRAFT - PRELIMINARY DATA 2.6.2. SYM_RP: Symbol AFC reference period register. Parallel mode Bank 1. Address 2. Type Read / Write. Serial mode - Address 10. 7 6 Reserved 5 4 VP305/6 3 2 1 0 SYM_RP[3:0] Symbol AFC reference period SYM_RP[3:0] Symbol frequency reference period for the count of the crystal clock cycles ( XTI pin). This sets the reference for the measurement of the ADC VCO frequency (SYS_CLK pin). The register value sets the 4 most significant bits of a 14 bit counter. The actual count is SYM_RP[3:0] * 1024. 2.6.3. SYM_NF U & L: Symbol input nominal frequency registers. Parallel mode Bank 1. Addresses 3, 4. Serial mode - Addresses 11, 12. 7 Type Read / Write. 6 5 4 3 2 1 SYM_NF[15:8] Symbol input nominal frequency (upper byte) SYM_NF[7:0] Symbol input nominal frequency (lower byte) 0 These two bytes together form the 16 bit number: SYM_NF[15:0] Symbol input nominal frequency. This is the division ratio for the Symbol clock input from the ADC VCO. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 33 VP305/6 DRAFT - PRELIMINARY DATA 2.6.4. SYM_RATIO: Symbol input decimation factor register. Parallel mode Bank 1. Address 5. Type Read / Write. Serial mode - Address 13. 7 6 5 Reserved 4 3 2 1 0 SYM_RATIO[2:0] SYM_RATIO[2:0] SYM_RATIO[2:0] 0 1 2 3 4 5 to 7 Input decimation factor for IIN and QIN inputs, no filtering. Decimation factor no decimation input every second sample input every fourth sample input every eighth sample input every sixteenth sample reserved 2.6.5. AGC_REF: Reference AGC level registers. Parallel mode Bank 1. Address 6. Type Read / Write. Serial mode - Address 14. 7 6 5 4 3 2 AGC_REF[7:0] Reference AGC level 1 0 AGC_REF[7:0] Reference AGC level sets the ratio of the input signal range (S) to the ADC range (R). The objective is to maintain this a constant ratio (S : R = 1 : 1.7). Volts 0.5 0.3 0.0 -0.3 -0.5 -T/2 0 Fig. 12. Eye diagram. The AGC_REF value is found from the following formula: The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. S=0.6V input signal level R=1V ADC input range T/2 T = Symbol period 34 DRAFT - PRELIMINARY DATA S2 AGC_REF = 233.3 * L * R2 Where: or Therefore: for L = 1 0.62 AGC_REF = 233.3 * 1 * 12 = 84. 0.32 AGC_REF = 233.3 * 4 * 12 = 84. VP305/6 S = Signal peak-to-peak level at the ADC input R = Input range of the ADC. L = 1 for no filtered decimation, SYM_CONFIG[1:0] = 0 L = 4 for some filtered decimation, SYM_CONFIG[1:0] = 1 or 2, (this adds 6dB gain) for L = 4 2.6.6. AGC_BW: AGC estimation bandwidth register. Parallel mode Bank 1. Address 7. Type Read / Write. Serial mode - Address 15. 7 6 5 Reserved 4 3 2 INT_DC 1 0 AGC_BW[1:0] AGC_BW[1:0] AGC estimation bandwidth. AGC_BW[1:0] 0 1 2 3 Symbol rate Rs MSym/s >20 10 - 20 5 - 10 Reserved The AGC control signal drives the Sigma Delta modulated output AGC_OUT pin. This output can drive an external passive RC filter feeding the AGC stage. The RC time constant should be 30 for six bits of resolution. DDML BPS K 45 40 35 30 25 20 15 10 5 0 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB 16dB 18dB 20dB E s / No (dB ) DDML QPS K NDAML QPS K Fig. 15. Carrier phase error detector gain KD_CR vs. Es / No for AGC_REF = 84. 2.7.6. CR_KD: Carrier loop filter gain (D term) register. Parallel mode Bank 2. Address 6. Type Read / Write. Serial mode - Address 22. 7 6 5 4 3 2 CR_KD[7:0] Carrier loop filter gain (D term) Carrier loop filter gain (D term) 1 0 CR_KD[7:0] The loop damping factor is given by the following equation: ζ= where 2 * CR_KD * ωn Rs ωn = natural frequency in radians / second Rs = QPSK symbol rate. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 40 DRAFT - PRELIMINARY DATA ζ * Rs 2 * ωn VP305/6 therefore CR_KD = 2.7.7. CR_THSL: Carrier lock detector threshold register. Parallel mode Bank 2. Address 7. Type Read / Write. Serial mode - Address 23. 7 6 5 4 3 2 CR_THSL[7:0] Carrier lock detector threshold 1 0 CR_THSL[7:0] Carrier lock detector threshold. This should be set to correspond to the phase lock detector length set by bit 4 of the CONFIG register, see page 45. CONFIG[4] 0 1 CR_THSL 31 72 The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 41 VP305/6 DRAFT - PRELIMINARY DATA 2.8. BANK 3: Program QPSK registers. 2.8.1. CR_SWR: Carrier sweep rate register. Parallel mode Bank 3. Address 1. Type Read / Write. Serial mode - Address 25. 7 6 5 4 3 2 CR_SWR[7:0] Carrier sweep rate Carrier sweep rate. 1 0 CR_SWR[7:0] CR_SWP = 64 * KDCR * θ Where: KDCR is the carrier phase detector gain, typically 10 for low Eb / No of 4 dB. θ is the phase lock loop steady state error during acquisition. θ should be lower than 5° expressed in radians. During the tracking phase, the loop drives the residual steady state error to 0. Therefore, if KDCR = 10 and θ = 3° = 0.052rad. CR_SWP = 64 * 10 * 0.052 = 33 (rounded down). The frequency sweep rate is given by the following formula: f= For the SL1710 For VDD = 3.3V Therefore f= 5 * 33 * 11.56 * 106 * 3.3 3.13 * 106 = CR_KP * R 128 * π * CR_KP * RCR * CCR * 5 CR * CCR K VDD 5 * CR_SWP * VCOCR * Hz/s 128 * π *CR_KP RCR * CCR 5V KVCOCR = 11.56Mrad/s/V. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 42 DRAFT - PRELIMINARY DATA VP305/6 The sweep rate varies as a function of the value of CR_SWR register and the delta frequency, effectively selected by the CR_USWL and CR_LSWL registers. If the delta frequency is halved, the sweep rate doubles. If the receiver fails to lock, a higher value of CR_SWR should be tried. If the value of CR_SWR is too low, the frequency sweep may be stopped. The rise and fall times of the sweep can be adjusted to be equal by setting the value of CR_OFFSET, see page 37. This becomes more critical at very low values of CR_SWR where the sweep will stop unless the rise and fall times are equal. VP 305/6 carrier s weep function. 16 14 12 10 8 6 4 2 0 20 40 60 80 100 120 140 160 180 200 220 240 260 CR _S W R Fig. 16. Carrier sweep rate for a delta frequency of ±10MHz. 2.8.2. CR_USWL U & L: Carrier Upper sweep limit registers. Parallel mode Bank 3. Addresses 2, 3. Serial mode - Addresses 26, 27. 7 Reserved 6 Type Read / Write. 5 4 3 2 1 0 CR_USWL[13:8] Carrier Upper sweep limit (upper nibble) CR_USWL[7:0] Carrier Upper sweep limit (lower byte) These two bytes together form the 14 bit number: CR_USWL[13:0] Carrier Upper sweep limit. This is the division ratio (upper) for the prescaler input (PSCAL) from the SL1710. See page 12 for further discussion. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 43 VP305/6 DRAFT - PRELIMINARY DATA 2.8.3. CR_LSWL U & L: Carrier Lower sweep limit registers. Parallel mode Bank 3. Addresses 4, 5. Serial mode - Addresses 28, 28. 7 Reserved 6 Type Read / Write. 5 4 3 2 1 0 CR_LSWL[13:8] Carrier Lower sweep limit (upper nibble) CR_LSWL[7:0] Carrier Lower sweep limit (lower byte) These two bytes together form the 14 bit number: CR_LSWL[13:0] Carrier Lower sweep limit. This is the division ratio (lower) for the prescaler input (PSCAL) from the SL1710. 2.8.4. CR_CONFIG: Carrier configuration register. Parallel mode Bank 3. Address 6. Type Read / Write. Serial mode - Address 30. 7 6 5 4 3 2 CR_CONFIG[7:0] Carrier configuration 1 0 CR_CONFIG[0] CR_SW High = carrier loop sweep on. Low = carrier loop sweep off. CR_CONFIG[1] CR_OPEN High = carrier loop open. This is only used to get out of a false lock. Low = carrier loop closed. CR_CONFIG[2] CR_PED_SEL Carrier phase error detector select. High = NDAML Non-data aided maximum likelihood estimator (only available in QPSK mode). Low = DDML Decision directed maximum likelihood estimator. CR_CONFIG[3] Reserved set low. CR_CONFIG[4] CR_VCO1 D/U High = tri-state D and U outputs. Low = active outputs. CR_CONFIG[5] CR_VCO2 D/U High = tri-state D and U outputs. Low = active outputs. CR_CONFIG[6] CR_VCO_SWAP exchange polarity for both CR_VCO1 and CR_VCO2 D and U outputs. High = swapped (i.e. D and U inverted). Low = normal. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 44 DRAFT - PRELIMINARY DATA CR_CONFIG[7] CR_SWEEP_SWAP change carrier sweep direction. High = swapped. Low = normal. 2.8.5. CONFIG: Configuration register. Parallel mode Bank 3. Address 7. Type Read / Write. Serial mode - Address 31. 7 6 5 4 3 CONFIG[7:0] 2 1 0 VP305/6 CONFIG[0] IIN and QIN input format selector. High = 2's complement format. Low = Offset binary format. This is the normal format used with the VP216/7. Code for six bit input 00 01 • 31 32 33 • 62 63 Offset binary CONFIG[0] = 0 000000 000001 • 011111 100000 100001 • 111110 111111 Offset 2's Complement CONFIG[0] = 1 100000 100001 • 111111 000000 000001 • 011110 011111 CONFIG[1] Reserved set low. CONFIG[2] CONFIG[3] Reserved set high. AGC out. High = inverted. Low = normal. FP_LOCK_LEN : Frequency / Phase lock detector length. High = short. Low = normal - long. See also CR_THSL register on page 41. CONFIG[4] CONFIG[5] Reserved set low. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 45 VP305/6 CONFIG[6] DRAFT - PRELIMINARY DATA Constellation selector. High = BPSK. Low = QPSK.. SNR Estimator on/off. High = used. Low = off. CONFIG[7] 2.9. BANK 4: Monitor FEC read registers. 2.9.1. VIT_ERR_C H & L: Viterbi error count registers. Parallel mode Bank 4. Addresses 1, 2. Serial mode - Addresses 33, 34. 7 6 Type Read. 5 4 3 2 VERRC[15:8] - Viterbi error count high byte VERRC[7:0] - Viterbi error count low byte 1 0 These two bytes together form the 16 bit number: VERRC[15:0] Viterbi error count related to the period defined in the VIT_ERR H-M-L registers, see page 48. When the count increments to the maximum value, it freezes at 65535. The actual count = 4 x VERRC[15:0] data bits. The register is NOT reset to zero when it is read. See also figure 8 on page 15. 2.9.2. RS_UBC: Reed Solomon uncorrected block count register. Parallel mode Bank 4. Address 3. Type Read. Serial mode - Address 35. 7 6 5 4 3 2 1 RSUBC[7:0] - Reed Solomon uncorrected block count 0 RSUBC[7:0] Reed Solomon uncorrected block count. When the count increments to the maximum value, it freezes at 255. The register is reset to zero when it is read. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 46 DRAFT - PRELIMINARY DATA 2.10. BANK 5: Program FEC registers. 2.10.1. VIT_MODE: Viterbi mode register. Type Read / Write. VP305/6 Parallel mode Bank 5. Address 1 Serial mode - Address 41. 7 IQSWAP VITCR[2:0] 6 F_LOCK 5 4 Reserved 3 2 1 0 VITCR[2:0] - code rate Viterbi code rate VITCR[2:0] 0 1 2 3 4 5 6 7 code rate 1/2 2/3 3/4 5/6 7/8 1/2 1/2 1/2 F_LOCK False lock High = Exit false lock state. This is automatically set low after use. Low = normal. See section 2.10.5 on page 49 for an explanation on how to use this bit. I / Q Swap High = I lags Q. Low = I leads Q. IQSWAP The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 47 VP305/6 2.10.2. DRAFT - PRELIMINARY DATA VIT_ERR H, M & L: Viterbi error period registers. Type Read / Write. Parallel mode Bank 5. Addresses 2, 3, 4. Serial mode - Addresses 42, 43, 44. 7 6 5 4 3 2 VITEP[23:16] - Viterbi error period high byte VITEP[15:8] - Viterbi error period middle byte VITEP[7:0] - Viterbi error period low byte 1 0 These three bytes together form the 24 bit number: VITEP[23:0] Viterbi error period, effectively the number of valid data bits, during which an error count is accumulated. At the end of the defined period, the error count is frozen and that value stored in the VIT_ERR_C H-L registers, see page 46. Also at the end of the defined period, an interrupt is generated on the IRQ line to advise the microprocessor that a new error count is available to be read. The interrupt is enabled by setting the IE_FEC[2] bit in the IE_FEC register, see page 52. The actual period = 4 x VITEP[23:0] data bits. See also figure 8 on page 15. 2.10.3. VI_MAX_ERR: Viterbi maximum bit error count register. Parallel mode Bank 5. Address 5. Type Read / Write. Serial mode - Address 45. 7 6 5 4 3 2 VMERR[7:0] - Viterbi max. bit error count 1 0 VMERR[7:0] Viterbi maximum bit error count. When the coarse count reaches the number programmed in VMERR[7:0], the count is reset to zero and an interrupt is generated on the VERR line (provided the INTVIS bit is enabled in the TEST2 register, see page 56). This technique provides a visible indication of the frequency of bit errors in the signal. It may be used, via a suitable monitor device, to assist in receiver dish alignment. The actual count = 4 x VMERR[7:0] data bits. See also figure 9 on page 16. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 48 DRAFT - PRELIMINARY DATA 2.10.4. VP305/6 VI_BER_PER: Viterbi bit error rate based synchronisation period register. Parallel mode Bank 5. Address 6. Type Read / Write. Serial mode - Address 46. 7 6 5 4 3 2 1 VBPER[7:0] - Viterbi bit error rate based synchronisation period 0 VBPER[7:0] Viterbi bit error rate based synchronisation period. The actual period = 256 x VBPER[7:0] data bits. 2.10.5. VI_BER_LIM: Viterbi bit error rate based synchronisation limit register. Parallel mode Bank 5. Address 7. Type Read / Write. Serial mode - Address 47. 7 6 5 4 3 2 1 VBLIM[7:0] - Viterbi bit error rate based synchronisation limit Viterbi bit error rate based synchronisation limit. The actual limit = 128 x VBLIM[7:0] + 32 data bits. 0 VBLIM[7:0] The Viterbi bit error rate threshold is the ratio of the register values: Threshold = VI_BER_LIM / VI_BER_PER The following table shows recommended threshold values for the various Viterbi code rates. If the Viterbi bit error rate threshold is set too low, the Viterbi circuit will lock up on incorrect data. But conversely, if the threshold is set too high, the Viterbi circuit will have difficulty in llocking up. A false lock may be exited by toggling F_LOCK (bit 6 of VIT_MODE register, see page 47). Coding rate min. max. 0.120 0.070 0.050 0.035 0.025 1/2 0.090 2/3 0.055 3/4 0.035 5/6 0.020 7/8 0.010 Table 9. Viterbi bit error rate threshold. . The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 49 VP305/6 DRAFT - PRELIMINARY DATA 2.11. BANK 6: Program FEC and general control registers. 2.11.1. VIT_CTRL1: Viterbi control synchronisation byte register 1 Parallel mode Bank 6. Address 1. Type Read / Write. Serial mode - Address 49. 7 6 BS_MODE[1:0] 5 4 3 VS_UNLK[3:0] 2 1 0 VBIT_MV[1:0] VBIT_MV[1:0]Viterbi synchronisation majority voting selection for the number of correct bits in a byte to have the byte labelled as a synchronisation byte. VBIT_MV[1:0] 0 1 No. correct bits in sync 5 6 ← Recommended 2 7 3 8 Table 10. Number of correct bits in the sync byte. VS_UNLK[3:0] Viterbi sync majority voting selection for retaining sync lock. VS_UNLK[3:0] 0 1 2 3 4 No. syncs to keep lock 3 4 5 6 7 VIT_CTRL1 (weighted) 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 ← Recommended 5 8 6 9 7 10 8 11 9 12 10 13 11 14 12 15 13 16 14 17 15 18 Table 11. Number of correct sync bytes to retain lock. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 50 DRAFT - PRELIMINARY DATA BS_MODE[0] Byte sync mode bit 0 High = seeking lock Low = normal BS_MODE[1] Byte sync mode bit 1 High = remaining in lock Low = normal 2.11.2. VIT_CTRL2: Viterbi control synchronisation byte register 2 VP305/6 Parallel mode Bank 6. Address 2. Type Read / Write. Serial mode - Address 50. 7 6 5 4 VIT_CTRL2[7:3] - Reserved 3 2 1 VS_LK[2:0] 0 VS_LK[2:0] Viterbi synchronisation acquire. This defines the number of consecutive synchronisation bytes that need to be detected before block lock is established. VS_LK[2:0] 0 1 2 3 4 5 6 No. syncs for lock 2 3 4 5 6 7 Not valid ← Recommended 7 Not valid Table 12. Number of consecutive sync bytes to establish block lock . VIT_CTRL2[7:3] These bits are reserved for test applications. For normal operation, they must be set to zero. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 51 VP305/6 2.11.3. DRAFT - PRELIMINARY DATA IE_FEC: Interrupt FEC register. When the bits of this register are set high, they enable an event signalled in the INT_FEC register to generate an interrupt on the IRQ pin. They do not affect the setting of bits in the INT_FEC register, see page 28. Parallel mode Bank 6. Address 3. Type Read / Write. Serial mode - Address 51. 7 6 5 4 3 2 IE_FEC[7:0] Interrupt enable FEC 1 0 IE_FEC[7:0] Interrupt enable FEC When : IE_FEC[i] =1 : enable INT_FEC[i] IE_FEC[i] =0 : disable INT_FEC[i] (default state) where i = 0 to 7. IE_FEC[0] IE_FEC[1] IE_FEC[2] IE_FEC[3] IE_FEC[4] IE_FEC[5] IE_FEC[6] IE_FEC[7] High = Enable Descrambler lock established indication in INT_FEC register. High = Enable Descrambler lock lost indication in INT_FEC register. High = Enable Viterbi error period indication in INT_FEC register. Reserved set low. High = Enable Viterbi bit lock established indication in INT_FEC register. High = Enable Viterbi bit lock lost indication in INT_FEC register. High = Enable Frame alignment lock established indication in INT_FEC register. (A Frame is 8 blocks, each block is 204 bytes). High = Enable Frame alignment lock lost indication in INT_FEC register. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 52 DRAFT - PRELIMINARY DATA 2.11.4. STAT_EN: Status enable register. VP305/6 Parallel mode Bank 6. Address 4. Type Read / Write. Serial mode - Address 52. 7 6 5 4 3 2 1 STAT_EN[7:0] Enable various outputs on STATUS pin. 0 This register allows various indicator signals to be output on the STATUS pin. The signals are equivalent to the corresponding bits in the STATUS register, see page 29, or to events signalled in the INT_FEC register, see page 28. Note: only one bit should be programmed high at any one time, otherwise a meaningless output on the STATUS pin will result! STAT_EN[0] High = Enable Symbol AFC lock detect signal on the STATUS pin. STAT_EN[1] High = Enable Carrier Phase lock detect signal on the STATUS pin. STAT_EN[2] High = Enable Carrier Frequency lock detect signal on the STATUS pin. STAT_EN[3] High = Enable SNR quality signal on the STATUS pin. STAT_EN[4] High = Enable descrambler lock detect signal on the STATUS pin. STAT_EN[5] High = Enable Viterbi bit lock detect signal on the STATUS pin. STAT_EN[6] High = Enable Frame alignment lock detect signal on the STATUS pin. STAT_EN[7] High = Enable symbol clock signal on the STATUS pin. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 53 VP305/6 2.11.5. DRAFT - PRELIMINARY DATA GEN_CTRL: General control register. Parallel mode Bank 6. Address 5. Type Read / Write. Serial mode - Address 53. 7 6 5 4 MCLKINV 3 BSO 2 ENTEI 1 0 NSYNC[1:0] NSYNC[1:0] The number of successive incorrect synchronising bytes in N successive blocks before byte lock in the descrambler is lost. The value programmed is related to N as shown in the following truth table. NSYNC[1:0] 0 1 No. incorrect sync bytes 2 3 ← Recommended 2 4 3 5 Table 13. Number of incorrect sync bytes for descrambler to lose lock. ENTEI BSO MCLKINV High = Enable automatic setting of transport_error_indicator (TEI) bit in the MPEG packet header byte 2 when the block contains an uncorrectable byte error. High = Bit serial output of the MPEG data on MDO0 pin. High = MCLK clock output inverted. Low = MCLK clock output normal. GPP_CTRL: General Purpose Port control register. 2.11.6. Parallel mode Bank 6. Address 6. Type Read / Write. Serial mode - Address 54. 7 6 Reserved 5 4 3 2 1 GPP_CTRL[4:1] External outputs control. 0 GPP_CTRL[0] GPP_CTRL[i] bit drives the OUTPUT pin GPP[i] where i = 1, 2, 3 or 4. Note: GPP_CTRL[0] reads the logic level of the input pin GPP0. Writing to this bit has no effect. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 54 DRAFT - PRELIMINARY DATA 2.11.7. RESET: Reset register. VP305/6 Parallel mode Bank 6. Address 7. Type Read / Write. Serial mode - Address 55. 7 RES PR_QP FR_QP PR_BS PR_DS 6 5 4 3 PR_DS 2 PR_BS 1 FR_QP 0 PR_QP High = Partial reset of the QPSK block, except for the registers. Low = No reset. High = Full reset of the QPSK block, including the registers. Low = No reset. High = Partial reset of the byte synchronising mechanism. Low = No reset. High = Partial reset of the De scramble block with its synchronising function. Low = No reset. High = Reset the complete chip, except for the microprocessor interface, to its default state. Low = No reset. RES The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 55 VP305/6 DRAFT - PRELIMINARY DATA 2.12. BANK 7: Program test registers. 2.12.1. TEST1: Test 1 register - for diagnostic / qualification purposes only. Parallel mode Bank 7. Address 1. Type Read / Write. Serial mode - Address 57. 7 6 5 4 Reserved TEST1[7:0] 2.12.2. Set all bits low for normal operation. TEST2: Test 2 register - for diagnostic / qualification purposes only. 3 2 1 0 Parallel mode Bank 7. Address 2. Type Read / Write. Serial mode - Address 58. 7 INTVIS EN[3:0] 6 5 4 3 2 EN[3:0] 1 0 Enable / disable functions EN3,2,1,0 0 3 QPSK EN EN VITERBI DEINT EN EN EN DIS RS EN DIS DESCR EN DIS ← Default state ← Test viterbi output All other states reserved. Table 14. Enable / disable circuit blocks. In the mode 3, digitised I and Q data is input in the normal way to the QPSK decoder block. The output from the viterbi block is then connected directly to the MDO7:0 pins, bypassing the remaining blocks. INTVIS High = Enable the toggled VERR output when VMERR (viterbi max. error count) is reset. See also figure 9 on page 16. This is the mode to assist in aligning the satellite dish. Low = VERR pin held low. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 56 DRAFT - PRELIMINARY DATA 2.12.3. TEST3: Test 3 register - for diagnostic / qualification purposes only. VP305/6 Parallel mode Bank 7. Address 3. Type Read / Write. Serial mode - Address 59. 7 6 5 4 Reserved TEST3[7:0] Set all bits low for normal operation. 3 2 1 0 The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 57 VP305/6 3. DRAFT - PRELIMINARY DATA MICROPROCESSOR CONTROL. Selection of the microprocessor interface type is controlled by the SER pin. SER 0 1 interface type I²C bus interface Parallel interface 3.1. I²C bus Interface. Not available on VP305. The I²C bus serial interface (ref. 2.) uses pins: SDA Serial data, the most significant bit is sent first. SCL Serial clock (D0). The I²C bus Address is 0001 110 R/ W . The circuit works as a slave transmitter with the eighth bit set high or as a slave receiver with the eighth bit set low. In receive mode, the first data byte is written to RADD register, which forms the register sub-address. Bit 7 of the RADD register, IAI is an Increment Auto Inhibit function. When the IAI bit is set high, the automatic incrementing of register addresses is inhibited. IAI set low is the normal situation so that data bytes sent on the I²C bus after the RADD register data are loaded into successive registers. This automatic incrementing feature avoids the need to individually address each register. Following a valid chip address, the I²C bus STOP command resets the RADD register to 01. If the chip address is not recognised, the VP306 will ignore all activity until a valid chip address is received. The I²C bus START command does NOT reset the RADD register to 01. This allows a combined I²C bus message, to point to a particular read register with a write command, followed immediately with a read data command. If required, this could next be followed with a write command to continue from the latest address. RADD would not be sent in this case. Finally a STOP command should be sent to free the bus. When the I²C bus is addressed (after a recognised STOP command) with the read bit set, the first byte read out shall be the content of register 01. To access the chip identification in register 00, the microprocessor should send the chip address with the write bit set, followed by the register address 00, then a restart with the read bit set, followed by a data read. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 58 DRAFT - PRELIMINARY DATA 3.1.1. Examples of I²C bus messages: W R NA Write (= 0) Read (= 1) NOT Acknowledge VP305/6 KEY: S Start condition P Stop condition A Acknowledge VP305/6 output ITALICS Write operation - as a slave receiver. S DEVICE W A ADDRESS RADD (n) A DATA A DATA A P (reg n) (reg n+1) Read operation - VP305/6 as a slave transmitter. S DEVICE R A DATA A ADDRESS (reg 1) DATA (reg 2) A DATA NA P (reg 3) Write/read operation with repeated start - VP305/6 as a slave transmitter. S DEVICE W A ADDRESS RADD (n) AS DEVICE R A DATA A DATA NA P ADDRESS (reg n) (reg n+1) Write/read/write operation with repeated start and auto increment off with IAI set high - VP305/6 as a slave transmitter. This example uses the GPP_CTRL register which has a read bit 0 and write bits 1 to 4. Register address is 54 + 128 (IAI). S DEVICE W A RADD A S DEVICE R A DATA NA S DEVICE W A DATA A P ADDRESS (182) ADDRESS ADDRESS (reg 54) (reg 54) Note: The serial register map is NOT continuous. The increment function will address the nonused addresses, so when writing a sequence of data, dummy data will need to be inserted at the appropriate points for the non-used addresses. Similarly, when reading a sequence of data, the value 255 will be read out from the non-used addresses. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 59 VP305/6 3.2. Parallel interface. DRAFT - PRELIMINARY DATA The Parallel interface is selected by a logic '1' on the SER pin. This uses pins: D7-0 A2-0 CS AS DTAK R/ W data input/output bus address input bus chip select address select data acknowledge read / write control Registers are directly addressed via the address bus. There is no register incrementing feature as on the I²C bus interface. 3.2.1. Examples of writing to and reading from the parallel interface. To write the value 64 to the CONFIG register 7 in Bank 3, send the following sequence: Set R/ W to write Addr[0],Data[24] Addr[7],Data[64] this writes 24 (Bank 3) to the BANK register this writes 64 to register 7 (of Bank 3) (CONFIG) To read the value of the RS_UBC register 3 in Bank 4, send the following sequence: Set R/ W to write Addr[0],Data[32] Set R/ W to read Addr[3],Data[?]. this writes 32 (Bank 4) to the BANK register this reads register 3 (of Bank 4) (RS_UBC) It is not necessary to write the value of the BANK register if writing to / or reading from a group of registers in the same bank. For example, to read the registers 1 to 6 of Bank 0: Set R/ W to write Addr[0],Data[0] Set R/ W to read Addr[1],Data[?]. Addr[2],Data[?]. Addr[3],Data[?]. Addr[4],Data[?]. Addr[5],Data[?]. Addr[6],Data[?]. this writes 0 to the BANK register this reads register 1 (of Bank 0) (INT_QPSK) this reads register 2 (of Bank 0) (INT_FEC) this reads register 3 (of Bank 0) (STATUS) this reads register 4 (of Bank 0) (AGC_LVL) this reads register 5 (of Bank 0) (CR_VCOF U) this reads register 6 (of Bank 0) (CR_VCOF L) 3.2.2. Parallel interface Write cycle description. A write cycle starts with the master indicating its intent by setting R/ W to write and placing a valid address on A2:0 and asserting AS . The VP305/6 takes the assertion of AS as the start of a cycle and latches the address on A2:0 by the falling edge AS . This event also causes VP305/6 to respond to the request by the master to send data, WHEN IT CAN, by asserting DTACK . The The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 60 DRAFT - PRELIMINARY DATA VP305/6 master requests to send data by asserting CS , data may be placed on the data bus before or after asserting CS . Notice that there is no maximum time specified from the assertion of AS to the assertion of DTACK . It is assumed that the master will insert wait states/cycles until DTACK is recognised. When the master negates CS the VP305/6 will latch the data on D7:0 on the rising edge of CS . When the master negates CS the VP305/6 will then negate DTACK . A2:0 VAL ID R/W AS CS DTACK D7:0 V AL I D Fig. 17. Parallel interface write cycle action diagram. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 61 VP305/6 Write cycle flowchart. Bus master Address the VP305/6 Set R/W to Write Place address on A2:0 Assert Address Strobe Place data on D7:0 Assert Chip Select DRAFT - PRELIMINARY DATA VP305/6 Î Í Î Î Í Receive the address Latch/decode the address Assert Data Transfer Acknowledge Transfer the data De-Assert Chip Select Acquire the data Store data on D7:0 Terminate the cycle De-Assert Address Strobe Remove Data from D7:0 Set R/W to Read Terminate the cycle De-Assert Data Transfer Acknowledge Start next cycle The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 62 DRAFT - PRELIMINARY DATA 3.2.3. Parallel interface Read cycle description. VP305/6 A read cycle starts with the master indicating its intent by setting R/ W to read and placing a valid address on A2:0 and asserting AS . The VP305/6 takes the assertion of AS as the start of a cycle and latches the address on A2:0 by the falling edge AS . This event also causes VP305/6 to respond to the data request, WHEN IT CAN, by placing valid data on the data bus and asserting DTACK , informing the master that it may proceed. The master then requests data by asserting CS . Notice that there is no maximum time specified from the assertion of AS to the assertion of DTACK . It is assumed that the master will insert wait states/cycles until DTACK is recognised. The master will then read the data on D7:0 and negate CS and AS . The negation of CS causes the VP305/6 to remove the data from D7:0 and then negate DTACK . A2:0 VAL ID R/W AS CS DTACK D7:0 V AL I D Fig. 18. Parallel interface read cycle action diagram. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 63 VP305/6 Read cycle flowchart. Bus master Address the VP305/6 Set R/W to Read Place address on A2:0 Assert Address Strobe Assert Chip Select DRAFT - PRELIMINARY DATA VP305/6 Î Í Î Í Output the data Latch/decode the address Place data on D7:0 Assert Data Transfer Acknowledge Acquire the data Latch data De-Assert Chip Select De-Assert Address Strobe Terminate the cycle Remove Data from D7:0 De-Assert Data Transfer Acknowledge Start next cycle The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 64 DRAFT - PRELIMINARY DATA 4. TIMING INFORMATION. VP305/6 4.1. I²C bus timing. t BUFF SDA t LOW SCL P S Sr P tR tF t HD;STA t HD;DAT tHIGH tSU;DAT t SU;STA t SU;STO Where: Fig. 19. I²C bus timing. S = Start Sr = Restart, i.e. Start without stopping first. P = Stop. Symbol Value Min Max. 0 450 200 200 450 600 200 100 100 note 1 20 200 Unit kHz ns ns ns ns ns ns ns ns ns ns Parameter fSCL SCL clock frequency tBUFF Bus free time between a STOP and START condition. tHD;STA Hold time (repeated) START condition. tLOW LOW period of SCL clock. tHIGH HIGH period of SCL clock. tSU;STA Set-up time for a repeated START condition. tHD;DAT Data hold time (when input). tSU;DAT Data set-up time tR Rise time of both SCL and SDA signals. Rise time of both SCL and SDA signals, (100pF to ground). tF tSU;STO Set-up time for a STOP condition. Table 15. I²C bus timing. Note 1. The rise time depends on the external bus pull up resistor. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 65 VP305/6 DRAFT - PRELIMINARY DATA 4.2. Parallel interface Write cycle timing. A2:0 VAL ID t AVASL R/W t CSHAI t WVASL AS t ASHWI CS t CSHDTH DTACK t ASDTL D7:0 VAL I D t DVCSH t CSHDI Fig. 20. Parallel interface write cycle timing diagram. 4.3. Parallel interface Read cycle timing. A2:0 VAL ID t AVASL R/W t ASHDI t RVASL AS t ASHRI CS t CSHDTH DTACK t ASDTL D7:0 VAL I D t DVCSH t CSHDI Fig. 21. Parallel interface read cycle timing diagram. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 66 DRAFT - PRELIMINARY DATA VP305/6 Symbol tAVASL tRVASL tWVASL tASHDTH tASLDTL tDVCSH tCSHAI tASHRI tASHWI tCSHTDH tCSHDI Characteristic Address Valid to Address Strobe Low Read Valid to Address Strobe Low Write Valid to Address Strobe Low Address Strobe High to DTACK High Address Strobe Low to DTACK Low Data Valid to Chip Select High Chip Select High to Address Invalid Address Strobe High to Read Invalid Address Strobe High to Write Invalid Chip Select High to DTACK High Min. Max. Units ns ns ns ns ns ns ns ns ns ns ns Chip Select High to Data Invalid Table 16. Parallel bus timing. 4.4. Data input timing. S Y S _ CL K t ID IIN QIN Fig. 22. VP305/6 data input timing diagram. Parameter Data intput delay Symbol tID Min. 2.0 Typ. Max. 6.0 Units ns The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 67 VP305/6 5. 5.1. DRAFT - PRELIMINARY DATA MPEG PACKET DATA OUTPUT. Data output format. 188 byte packet output 184 Transport packet bytes Transport Packet Header 4 bytes 0 TEI 1 0 0 0 1 1 1 1st byte 2nd byte MDO[7] MDO[0] Fig. 23. VP305/6 Transport Packet Header bytes. After decoding, the 188 byte MPEG packet is output on the MDO pins in 188 consecutive clock cycles. Additionally, when the ENTEI bit in the GEN_CTRL register is set high, any decoded packets with uncorrectable bytes will automatically set the TEI bit in the MPEG header, see page 54. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 68 DRAFT - PRELIMINARY DATA 1st byte packet n 188th byte packet n VP305/6 1st byte packet n+1 MCLK MDO7:0 MOSTRT MOVAL BKERR Tp Ti Fig. 24. VP305/6 output data wave form diagram. MCLK will be a continuously running clock once symbol lock has been achieved in the QPSK block and is derived from the symbol clock. MCLK is the output interface byte rate clock, running at a rate given by the table on page 70. The maximum jitter in the packet synchronisation byte is limited to one output clock period. All output data and signals (MDO7:0, MOSTRT, MOVAL, BKERR ) change on the negative edge of MCLK to present stable data and signals on the positive edge of the clock. A complete packet of data is output on MDO7:0 on 188 consecutive clocks and the MDO7:0 pins will remain low during the inter packet gaps. MOSTRT goes high for the first byte clock of a packet. MOVAL will go high on the first byte of a packet and remain high until the 188th byte has been clocked out. BKERR will go low on the first byte of a packet where uncorrectable bytes are detected and remain low until the 188th byte has been clocked out. Tp is equivalent to 188 clock cycles irrespective of the code rate. Ti depends on the inner code rate (1/2, 2/3, 3/4, 5/6 or 7/8). The following table shows data output timing and an example of the data rate on MDO7:0 for a maximum input symbol rate (Rs) of 30Msym/sec. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 69 VP305/6 DRAFT - PRELIMINARY DATA Viterbi Code rate 1/2 2/3 3/4 5/6 7/8 tCLKP tCLKH tCLKL µs µs µs 16/2Rs 8/2Rs 8/2Rs 12/2Rs 6/2Rs 6/2Rs 11/2Rs 6.2Rs 5/2Rs 10/2Rs 5/2Rs 5/2Rs 9/2Rs 5/2Rs 4/2Rs Table 17. MPEG data output rates. e.g. MDO7:0 MByte/sec 3.7500 5.0000 5.4545 6.0000 6.6667 The Viterbi code rate is programmed in the VIT_MODE register, see page 47. 5.2. Data output timing. t CLKP MCL K t OD M OS T R T M OV A L MD O7 :0 BKERR t CLKL Fig. 25. VP305/6 data output timing diagram. Parameter Data output delay Symbol tOD Min. Typ. Max. ±20 Units ns The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 70 DRAFT - PRELIMINARY DATA 6. 6.1. VP305/6 VP305/6 OPERATING CONDITIONS. Recommended operating conditions. Symbol VDD IDD XTI Min. 2.97 9.99 Typ. 3.30 410 Max. 3.63 16.00 25.00 60.00 450 70 Units V mA MHz MHz MHz kHz °C Parameter Power supply voltage Power supply current Input clock frequency ¹ PSCAL input frequency PSCAL 15.00 Sytem clock input frequency SYS_CLK SCL clock frequency fSCL Ambient operating temperature 0 Table 18. Recommended operating conditions. Note 1. frequency range shown. When not using a crystal, XTI may be driven from an external source over the The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 71 VP305/6 6.2. DRAFT - PRELIMINARY DATA Electrical characteristics. Test conditions (unless otherwise stated): As specified in Recommended Operating Conditions. DC CHARACTERISTICS Parameter Digital Inputs CMOS compatible Input high voltage Input low voltage Digital Inputs TTL compatible Input high voltage Input low voltage Leakage current - All inputs except TEST1,2,3, XTI Input high Input low Leakage current - TEST1,2,3, XTI Input high Input low Digital Outputs CMOS compatible Output high voltage Output low voltage Digital Outputs Open drain Output high voltage Output low voltage PECL Inputs Common mode Input range Input voltage swing Conditions Symbol VIH VIL VIH VIL Min. 0.8VDD Typ. Max. 5.5 0.2VDD 5.5 0.8 Units V V V V 2.0 VIN = 5.5V VIN = VSS VIN = 3.63V VIN = VSS IOH = -1mA IOL = +1mA IIH IIL IIH IIL VOH VOL VOH VOL 0.8VDD 1 1 1 1 10 -10 10 -10 µA µA µA µA V V V V V mV 0.4 5.5 0.4 VDD-0.4 IOL = +6mA @ VDD VIR VDD-1.9 VIS 250 Table 19. DC Characteristics. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 72 DRAFT - PRELIMINARY DATA 6.3. Crystal specification. Parallel resonant fundamental frequency (preferred) Tolerance over operating temperature range Tolerance overall Nominal load capacitance Equivalent series resistance VP305/6 9.99 to 16.00MHz. ± 25ppm. ± 50ppm. 30pF. 5 Then A_FLAG = 1 GOTO EX_ACQ End If End If If LOOP_STAT = 0 Then TREND = 0 End If Next A_LOOP EX_ACQ: sucess If sucessful, the loop exits with A_FLAG = 1, otherwise, A_FLAG = 0. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 82 http://www.mitelsemi.com World Headquarters - Canada Tel: +1 (613) 592 2122 Fax: +1 (613) 592 6909 North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Asia/Pacific Tel: +65 333 6193 Fax: +65 333 6192 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. However, Mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. 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