M2V28S40ATP-7L

128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) PRELIMINARY Some of contents are described for general products and are subject to change without notice. DESCRIPTION M2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and M2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40ATP is organized as 4-bank x 2,097,152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK. M2V28S20ATP,M2V28S30ATP,M2V28S40ATP achieves very high speed data rates up to 133MHz, and is suitable for main memory or graphic memory in computer systems. FEATURES M2V28S20/30/40ATP ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time Row to Column Delay Access Time from CLK Ref/Active Command Period Operation Current (Max.) (Single Bank) (Max.) (Min.) (Min.) (Min.) (Max.) (CL=3) (Min.) V28S20 V28S30 V28S40 Icc6 Self Refresh Current -6 7.5ns 45ns 20ns 5.4ns 67.5ns 100mA 110mA 130mA 2mA -7 10ns 50ns 20ns 6ns 70ns 95mA 100mA 120mA 2mA -8 10ns 50ns 20ns 6ns 70ns 95mA 100mA 120mA 2mA Active to Precharge Command Period - Single 3.3V ±0.3V power supply - Max. Clock frequency -6:PC133 / -7:PC100 / -8:PC100 - Fully synchronous operation referenced to clock rising edge - 4-bank operation controlled by BA0,BA1(Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/FP (programmable) - Burst type- Sequential and interleave burst (programmable) - Byte Control- DQML and DQMU (M2V28S40ATP) - Random column access - Auto precharge / All bank precharge controlled by A10 - Auto and self refresh - 4096 refresh cycles /64ms - LVTTL Interface - Package M2V28S20ATP/30ATP/40ATP 400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch MITSUBISHI ELECTRIC 1 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L PIN CONFIGURATION (TOP VIEW) M2V28S20ATP M2V28S30ATP M2V28S40ATP SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) PIN CONFIGURATION (TOP VIEW) Vdd NC VddQ NC DQ0 VssQ NC NC VddQ NC DQ1 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10(AP) A0 A1 A2 A3 Vdd Vdd DQ0 VddQ NC DQ1 VssQ NC DQ2 VddQ NC DQ3 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10(AP) A0 A1 A2 A3 Vdd Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ DQ5 DQ6 VssQ DQ7 Vdd DQML /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10(AP) A0 A1 A2 A3 Vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 Vss NC DQMU CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss Vss DQ7 VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC Vss NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss Vss NC VssQ NC DQ3 VddQ NC NC VssQ NC DQ2 VddQ NC Vss NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss CLK CKE /CS /RAS /CAS /WE DQ0-15 : Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O DQM A0-11 BA0,1 Vdd VddQ Vss VssQ : Output Disable/ Write Mask : Address Input : Bank Address : Power Supply : Power Supply for Output : Ground : Ground for Output MITSUBISHI ELECTRIC 2 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L BLOCK DIAGRAM DQ0-7 SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) I/O Buffer Memory Array 4096 x1024 x8 Cell Array Memory Array 4096 x1024 x8 Cell Array Memory Array 4096 x1024 x8 Cell Array Memory Array 4096 x1024 x8 Cell Array Bank #0 Bank #1 Bank #2 Bank #3 Mode Register Control Circuitry Address Buffer Clock Buffer Control Signal Buffer A0-11 BA0,1 CLK CKE /CS /RAS /CAS /WE DQM Note : This figure shows the M2V28S30ATP. The M2V28S20ATP configration is 4096x2048x4 of cell array and DQ 0-3. The M2V28S40ATP configration is 4096x512x16 of cell array and DQ 0-15. Type Designation Code These rules are only applied to the Synchronous DRAM family. M2 V 28 S 3 0 A TP -8 Access Item -6 : 7.5ns (PC133/3-3-3), -7 : 10ns(PC100/2-2-2), -8 : 10ns(PC100/3-2-2) TP : TSOP(II) A : 2nd. gen. 0 : Random Column 2: x4, 3: x8, 4: x16 Package Type Process Generation Function Organization Synchronous DRAM Density Interface Mitsubishi DRAM 28 : 128Mbit V : LVTTL MITSUBISHI ELECTRIC 3 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) PIN FUNCTION CLK Input Master Clock: All other inputs are referenced to the rising edge of CLK. Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / selfrefresh. After self refresh mode is started, CKE becomes synchronous input. Self refresh is maintained as long as CKE is low. Chip Select: When /CS is high, any command means No Operation. Combination of /RAS, /CAS, /WE defines basic commands. A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-11. The Column Address is specified by A0-9,11 (x4) / A0-9 (x8) / A0-8 (x16). A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. Data In and Data out are referenced to the rising edge of CLK. Din Mask / Output Disable: When DQM is high in burst write, Din for the current cycle is masked. When DQM is high in burst read, Dout is disabled at the next but one cycle. Power Supply for the memory array and peripheral circuitry. VddQ and VssQ are supplied to the Output Buffers only. CKE Input /CS /RAS, /CAS, /WE Input Input A0-11 Input BA0,1 DQ0-7 Input Input / Output DQM Input Vdd, Vss VddQ, VssQ Power Supply Power Supply MITSUBISHI ELECTRIC 4 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) BASIC FUNCTIONS The M2V28S30ATP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table. CLK /CS /RAS /CAS /WE CKE A10 Chip Select : L=select, H=deselect Command Command Command Refresh Option @ refresh command Precharge Option @ precharge or read/write command define basic commands Activate (ACT) [/RAS =L, /CAS =/WE =H] ACT command activates a row in an idle bank indicated by BA. Read (READ) [/RAS =H, /CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-precharge, READA). Write (WRITE) [/RAS =H, /CAS =/WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA). Precharge (PRE) [/RAS =L, /CAS =H, /WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA ). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H] REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically. MITSUBISHI ELECTRIC 5 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) COMMAND TRUTH TABLE COMMAND Deselect No Operation Row Address Entry & Bank Activate Single Bank Precharge Precharge All Banks Column Address Entry & Write Column Address Entry & Write with Auto-Precharge Column Address Entry & Read Column Address Entry & Read with Auto-Precharge Auto-Refresh Self-Refresh Entry MNEMONIC DESEL NOP ACT PRE PREA WRITE WRITEA READ READA REFA REFS CKE CKE n-1 n H H H H H H H H H H H L Self-Refresh Exit REFSX L Mode Register Set MRS H H X L L H L H L H L X L X L X L X V*1 X X X X X X X X X H L H /CS /RAS /CAS /WE BA0,1 A11 H L L L L L L L L L L H X H L L L H H H H L L X X H H H H L L L L L L X X H H L L L L H H H H X X X V V X V V V V X X X X X V X X V V V V X X X A10 X X V L H L H L H X X X A0-9 X X V X X V V V V X X X H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. A7-A9 =0, A0-A6 =Mode Address MITSUBISHI ELECTRIC 6 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L FUNCTION TRUTH TABLE Current State IDLE /CS H L L L L L L L /RAS /CAS /WE Address X H H H L L L L X H H H H L L L L X H H L H H L L X H H L L H H L L X H L X H L H L X H L H L H L H L X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS Action NOP NOP SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) ILLEGAL*2 ILLEGAL*2 Bank Active, Latch RA NOP*4 Auto-Refresh*5 Mode Register Set*5 NOP NOP NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge Bank Active / ILLEGAL*2 Precharge / Precharge All ILLEGAL ILLEGAL ROW ACTIVE H L L L L L L L L MITSUBISHI ELECTRIC 7 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L FUNCTION TRUTH TABLE (continued) Current State READ /CS H L L L L L L L L WRITE H L L L L L L L L /RAS /CAS /WE Address X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command DESEL NOP TBST READ /READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS Action SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge*3 Terminate Burst, Latch CA, Begin Write, Determine Auto-Precharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, Begin Read, Determine Auto-Precharge*3 Terminate Burst, Latch CA,Begin Write, Determine Auto-Precharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL MITSUBISHI ELECTRIC 8 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L FUNCTION TRUTH TABLE (continued) Current State READ with AUTO PRECHARGE /CS H L L L L L L L L WRITE with AUTO PRECHARGE H L L L L L L L L /RAS /CAS /WE Address X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS Action SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL MITSUBISHI ELECTRIC 9 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L FUNCTION TRUTH TABLE (continued) Current State PRE CHARGING /CS H L L L L L L L ROW ACTIVATING H L L L L L L L /RAS /CAS /WE Address X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L X H L X H L H L X H L X H L H L X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS Action SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 NOP*4 (Idle after tRP) ILLEGAL ILLEGAL NOP (Row Active after tRCD) NOP (Row Active after tRCD) ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL MITSUBISHI ELECTRIC 10 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L FUNCTION TRUTH TABLE (continued) Current State /CS H L L L L L L L /RAS /CAS /WE Address X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L X H L X H L H L X H L X H L H L X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS Action NOP NOP SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) WRITE RECOVERING ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP (Idle after tRC) NOP (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL REFRESHING H L L L L L L L MITSUBISHI ELECTRIC 11 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L FUNCTION TRUTH TABLE (continued) Current State MODE REGISTER SETTING /CS H L L L L L L L /RAS /CAS /WE Address X H H H L L L L X H H L H H L L X H L X H L H L X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS Action SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) NOP (Idle after tRSC) NOP (Idle after tRSC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and/or data-integrity are not guaranteed. MITSUBISHI ELECTRIC 12 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L FUNCTION TRUTH TABLE for CKE Current State SELFREFRESH*1 CKE n-1 H L L L L L L POWER DOWN H L L ALL BANKS IDLE*2 H H H H H H H L ANY STATE other than listed above H H L L CKE n X H H H H H L X H L H L L L L L L X H L H L /CS X H L L L L X X X X X L H L L L L X X X X X /RAS /CAS X X H H H L X X X X X L X H H H L X X X X X X X H H L X X X X X X L X H H L X X X X X X /WE X X H L X X X X X X X H X H L X X X X X X X Add X X X X X X X X X X X X X X X X X X X X X X Action INVALID SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) Exit Self-Refresh (Idle after tRC) Exit Self-Refresh (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP (Maintain Power Down) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State =Power Down Refer to Function Truth Table Begin CLK Suspend at Next Cycle*3 Exit CLK Suspend at Next Cycle*3 Maintain CLK Suspend ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command. MITSUBISHI ELECTRIC 13 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SIMPLIFIED STATE DIAGRAM SELF REFRESH SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) REFS REFSX MODE REGISTER SET MRS IDLE REFA AUTO REFRESH CKEL CLK SUSPEND ACT CKEL CKEH CKEH POWER DOWN ROW ACTIVE WRITE WRITEA READA READ WRITE READ WRITE SUSPEND CKEL CKEL WRITE CKEH READ CKEH READ SUSPEND WRITEA WRITEA READA READA WRITEA SUSPEND CKEL CKEL WRITEA CKEH PRE PRE PRE READA CKEH READA SUSPEND POWER APPLIED POWER ON PRE PRE CHARGE Automatic Sequence Command Sequence MITSUBISHI ELECTRIC 14 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L POWER ON SEQUENCE SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs. 2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200µs. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation. MODE REGISTER Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when all banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command. CLK /CS /RAS /CAS /WE BA0,1 A11-A0 BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 V 0 0 0 0 0 0 0 LTMODE BT BL BL 000 001 010 011 100 101 110 111 BURST TYPE 0 1 BT= 0 1 2 4 8 R R R FP BT= 1 1 2 4 8 R R R R CL 000 001 LATENCY MODE 010 011 100 101 110 111 /CAS LATENCY R R 2 3 R R R R R: Reserved for Future Use BURST LENGTH SEQUENTIAL INTERLEAVED MITSUBISHI ELECTRIC 15 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) CLK Command Address DQ CL= 3 BL= 4 Read Y Q0 Q1 Q2 Q3 Write Y D0 D1 D2 D3 /CAS Latency Burst Length Burst Type Burst Length Initial Address A2 0 0 0 0 1 1 1 1 A1 A0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 BL Sequential 0 1 2 3 8 4 5 6 7 0 1 4 2 3 0 2 1 1 2 3 4 5 6 7 0 1 2 3 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 3 4 5 6 7 0 1 2 3 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 Column Addressing Interleaved 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 0 3 2 5 4 7 6 1 0 3 2 1 0 2 3 0 1 6 7 4 5 2 3 0 1 3 2 1 0 7 6 5 4 3 2 1 0 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 0 1 0 1 0 1 0 1 0 1 MITSUBISHI ELECTRIC 16 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) OPERATIONAL DESCRIPTION BANK ACTIVATE The SDRAM has four independent banks. Each bank is activated by the ACT command with the bank addresses (BA0,1). A row is indicated by the row addresses A0-11. The minimum activation interval between one bank and the other bank is tRRD. Maximum 2 ACT commands are allowed within tRC , although the number of banks which are active concurrently is not limited. PRECHARGE The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the precharge all command (PREA, PRE + A10=H) is available to deactivate them at the same time. After tRP from the precharge, an ACT command to the same bank can be issued. Bank Activation and Precharge All (BL=4, CL=3) CLK 2 ACT command / tRCmin tRCmin Command A0-9 A10 A11 BA0,1 DQ ACT tRRD Xa ACT READ tRAS Xb tRCD Xb Xb 01 00 Qa0 Y 0 PRE tRP ACT Xb Xa Xa 00 1 Xb Xb 01 Qa1 Qa2 Qa3 Precharge all READ After tRCD from the bank activation, a READ command can be issued. 1st output data is available after the /CAS Latency from the READ, followed by (BL -1) consecutive data when the Burst Length is BL. The start address is specified by A0-A9,A11(x4), A0-9(X8), A0-8(X16) , and the address sequence of burst data is defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous output data by interleaving the multiple banks. When A10 is high at a READ command, the auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at BL after READA. (Need to keep tRAS min.) The next ACT command can be issued after (BL + tRP) from the previous READA. MITSUBISHI ELECTRIC 17 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Multi Bank Interleaving READ (BL=4, CL=3) CLK Command A0-9 A10 A11 BA0,1 DQ /CAS latency ACT tRCD Xa Xa Xa 00 00 Y 0 Xb Xb Xb 10 Qa0 10 Qa1 00 Qa2 Y 0 0 READ ACT READ PRE SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) Qa3 Qb0 Qb1 Qb2 Burst Length READ with Auto-Precharge (BL=4, CL=3) CLK BL + tRP Command A0-9 A10 A11 BA0,1 DQ ACT tRCD Xa Xa Xa 00 READ BL Y 1 tRP ACT Xa Xa Xa 00 Qa0 Qa1 Qa2 Qa3 00 Internal precharge start READ Auto-Precharge Timing (BL=4) CLK Command CL=3 CL=2 DQ DQ Qa0 ACT READ BL Qa0 Qa1 Qa2 Qa3 Qa1 Qa2 Qa3 Internal Precharge Start Timing MITSUBISHI ELECTRIC 18 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) WRITE After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same cycle as the WRITE. Following (BL -1) data are written into the RAM, when the Burst Length is BL. The start address is specified by A0-A9,A11(x4), A0-9(X8), A0-8(X16) and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, the autoprecharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge begins at tWR after the last input data cycle. (Need to keep tRAS min.) The next ACT command can be issued after tRP from the internal precharge timing. Multi Bank Interleaving WRITE (BL=4) CLK Command A0-9 A10 A11 BA0,1 DQ ACT tRCD Xa Xa Xa Xa Xa 00 00 Da0 Y 0 Xb Xb Xb 10 Da1 Da2 Da3 10 Db0 Write ACT tRCD Y 0 0 0 00 Db1 Db2 Db3 0 0 10 Write PRE PRE WRITE with Auto-Precharge (BL=4) CLK Command A0-9 A10 A11 BA0,1 DQ ACT tRCD Xa Xa Xa 00 00 Da0 Da1 Da2 Da3 Internal precharge starts Y 1 Write tWR tRP Xa Xa Xa 00 ACT MITSUBISHI ELECTRIC 19 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) BURST INTERRUPTION [ Read Interrupted by Read ] Burst read operation can be interrupted by new read of any bank. Random column access is allowed READ to READ interval is minimum 1 CLK.. Read Interrupted by Read (BL=4, CL=3) CLK Command A0-9 A10 A11 BA0,1 DQ 00 00 10 Qai0 Qaj0 01 Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3 READ READ Yi 0 Yj 0 READ Yk 0 READ Yl 0 [ Read Interrupted by Write ] Burst read operation can be interrupted by write of any bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 1 cycle after WRITE assertion. Read Interrupted by Write (BL=4, CL=3) CLK Command A0-9 A10 A11 BA0,1 DQM Q D Qai0 Daj0 DQM control Daj1 Daj2 Daj3 00 00 READ Yi 0 Write Yj 0 Write control MITSUBISHI ELECTRIC 20 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) [ Read Interrupted by Precharge ] Burst read operation can be interrupted by precharge of the same bank . READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. As a result, READ to PRE interval determines valid data length to be output. The figure below shows examples of BL=4. Read Interrupted by Precharge (BL=4) CLK Command DQ Command READ PRE Q0 Q1 Q2 READ PRE Q0 Q1 CL=3 DQ Command DQ READ PRE Q0 Command DQ Command READ Q0 PRE Q1 Q2 READ PRE Q0 Q1 CL=2 DQ Command DQ READ PRE Q0 MITSUBISHI ELECTRIC 21 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L [ Write Interrupted by Write ] SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) Burst write operation can be interrupted by new write of any bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. Write Interrupted by Write (BL=4) CLK Command A0-9 A10 A11 BA0,1 DQ 00 Dai0 00 10 00 Dal1 Dal2 Dal3 Write Write Yi 0 Yj 0 Write Yk 0 Write Yl 0 Daj0 Daj1 Dbk0 Dbk1 Dbk2 Dal0 [ Write Interrupted by Read ] Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "don't care". Write Interrupted by Read (BL=4, CL=3) CLK Command A0-9 A10 A11 BA0,1 DQM DQ Dai0 Qaj0 Qaj1 Dbk0 Dbk1 Qal0 00 00 10 00 Write READ Yi 0 Yj 0 Write Yk 0 READ Yl 0 MITSUBISHI ELECTRIC 22 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) [ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank. Random column access is allowed. Write recovery time (tWR) is required from the last data to PRE command. Write Interrupted by Precharge (BL=4) CLK Command A0-9 A10 A11 BA0,1 DQM DQ Dai0 Dai1 Dai2 00 00 Write tWR Yi 0 0 PRE tRP Xb Xb Xb 00 ACT MITSUBISHI ELECTRIC 23 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L AUTO REFRESH SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H) command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 128Mbit memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto-refresh, all banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum tRC. Any command must not be supplied to the device before tRC from the REFA command. Auto-Refresh CLK /CS /RAS /CAS /WE CKE A0-11 BA0,1 minimum tRC NOP or DESELECT Auto Refresh on All Banks Auto Refresh on All Banks MITSUBISHI ELECTRIC 24 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SELF REFRESH SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enabled input ,all other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE (REFSX) for longer than tSRX. After tRC from REFSX all banks are in the idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then. Self-Refresh CLK Stable CLK /CS /RAS /CAS /WE CKE NOP tSRX new command X 00 A0-11 BA0,1 Self Refresh Entry Self Refresh Exit minimum tRC +1 CLOCK for recovery MITSUBISHI ELECTRIC 25 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) CLK SUSPEND CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored. ext.CLK CKE int.CLK Power Down by CKE CLK CKE Command PRE NOP NOP Standby Power Down NOP NOP NOP NOP NOP CKE Command ACT NOP NOP Active Power Down NOP NOP NOP NOP NOP DQ Suspend by CKE CLK CKE Command Write READ DQ D0 D1 D2 D3 Q0 Q1 Q2 Q3 MITSUBISHI ELECTRIC 26 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) DQM CONTROL DQM is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQM masks input data word by word. DQM to write mask latency is 0. During reads, DQM forces output to Hi-Z word by word. DQM to output Hi-Z latency is 2. DQM Function CLK Command DQM Write READ DQ D0 D2 D3 Q0 Q1 Q3 masked by DQM=H disabled by DQM=H MITSUBISHI ELECTRIC 27 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) ABSOLUTE MAXIMUM RATINGS Symbol Vdd VddQ VI VO IO Pd Topr Tstg Parameter Supply Voltage Supply Voltage for Output Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Ta = 25ºC Conditions with respect to Vss with respect to VssQ with respect to Vss with respect to VssQ Ratings -0.5 - 4.6 -0.5 - 4.6 -0.5 - 4.6 -0.5 - 4.6 50 1000 0 - 70 -65 - 150 Unit V V V V mA mW ºC ºC RECOMMENDED OPERATING CONDITIONS (Ta=0 – 70ºC, unless otherwise noted ) Limits Unit Min. Vdd Vss VddQ VssQ VIH*1 VIL*2 Supply Voltage Supply Voltage Supply Voltage for Output Supply Voltage for Output High-level Input Voltage all inputs Low-level Input Voltage all inputs 3.0 0 3.0 0 2.0 -0.3 Typ. 3.3 0 3.3 0 Max. 3.6 0 3.6 0 VddQ +0.3 0.8 V V V V V V Symbol Parameter NOTES) 1. VIH(max)=5.5V for pulse width less than 10ns. 2. VIL(min)=-1.0V for pulse width less than 10ns. CAPACITANCE (Ta=0 – 70ºC, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted ) Symbol CI(A) CI(C) CI(K) CI/O Parameter Input Capacitance, address pin Input Capacitance, contorl pin Input Capacitance, CLK pin Input Capacitance, I/O pin Test Condition Limits (min.) 2.5 @ 1MHz 1.4V bias 200mV swing Vcc=3.3V 2.5 2.5 4.0 Limits (max.) -6 (PC133) -7/-8(PC100) 3.8 3.8 3.5 6.5 5.0 5.0 4.0 6.5 Unit pF pF pF pF MITSUBISHI ELECTRIC 28 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L AVERAGE SUPPLY CURRENT from Vdd (Ta=0 – 70ºC, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted ) SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) ITEM operating current tRC=min, tCLK =min, BL=1 , CL=3 single bank operation Symbol Organization x4 Limits (max.) -6 100 110 130 25 -7 95 100 120 25 -8 95 100 120 25 Unit Note Icc1 x8 x16 mA *1 precharge standby current in Non Power down mode /CS > Vcc -0.2V tCLK = 15ns CKE = H VIH > Vcc - 0.2V VIL < 0.2V CLK = L & CKE = H VIH > Vcc - 0.2V VIL < 0.2V all input signals are fixed. Icc2N x4/x8/x16 mA *1 Icc2NS x4/x8/x16 15 15 15 mA *1 precharge standby current in Power down mode /CS > Vcc -0.2V tCLK = 15ns CKE = L CLK = L CKE = L CKE = H, tCLK=15ns Icc2P x4/x8/x16 2 2 2 mA *1 Icc2PS Icc3N Icc3NS x4/x8/x16 x4/x8/x16 x4/x8/x16 x4 1 30 20 140 150 160 160 2 1 30 20 110 120 130 160 2 0.8 1 30 mA *1 active standby current CKE = H, CLK=L mA 20 110 120 130 160 2 0.8 mA mA mA mA *1 burst current All Bank Active tCLK = min BL=4, CL=3 Icc4 x8 x16 *1 auto-refresh current self-refresh current tRC=min, tCLK=min Icc5 Icc6 x4/x8/x16 *1 *1 *1,2 CKE < 0.2V x4/x8/x16 0.8 NOTE) 1. Icc(max) is specified at the output open condition. 2. Low Power version. (-6L,-7L,-8L only) AC OPERATING CONDITIONS AND CHARACTERISTICS (Ta=0 – 70ºC, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted ) Symbol VOH (DC) VOL (DC) IOZ II Parameter High-Level Output Voltage (DC) Low-level Output Voltage (DC) Off-state Output Current Input Current Test Conditions Min. IOH=-2mA IOL= 2mA Q floating VO=0 -- VddQ VIH = 0 -- VddQ +0.3V -10 -10 2.4 0.4 10 10 Limits Max. V V µA µA unit MITSUBISHI ELECTRIC 29 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) AC TIMING REQUIREMENTS (Ta=0 – 70ºC, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted ) Input Pulse Levels: 0.8V – 2.0V Input Timing Measurement Level: 1.4V Limits Symbol Parameter Min. tCLK CLK cycle time CL=2 CL=3 tCH tCL tT tIS tIH tRC tRCD tRAS tRP tWR tRRD tRSC tSRX tPDE tREF CLK High pulse width CLK Low pulse width Transition time of CLK Input Setup time Input Hold time Row Cycle time Row to Column Delay Row Active time Row Precharge time Write Recovery time Act to Act Delay time Mode Register Set Cycle time Self-refresh Exit time Power Down Exit time -6 Max. Min. 10 10 3 3 10 1 2 1 70 20 100K 50 20 20 20 20 10 10 64 -7 Max. Min. 13 10 3 3 10 1 2 1 70 20 100K 50 20 20 20 20 10 10 64 -8 Max. Unit 10 7.5 2.5 2.5 1 1.5 0.8 67.5 20 45 20 15 15 15 7.5 7.5 ns ns ns ns 10 ns ns ns ns ns 100K ns ns ns ns ns ns ns 64 ms (all inputs) (all inputs) Refresh Interval time CLK 1.4V DQ 1.4V Any AC timing is referenced to the input signal passing through 1.4V. MITSUBISHI ELECTRIC 30 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) SWITCHING CHARACTERISTICS (Ta=0 – 70ºC, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted ) Limits Symbol Parameter Min. CL=2 tAC Access time from CLK CL=3 CL=2 CL=3 tOLZ tOHZ Delay time, output lowimpedance from CLK Delay time, output highimpedance from CLK 3 2.7 0 2.7 5.4 -6 Max. 6 5.4 3 3 0 3 6 Min. -7 Max. 6 6 3 3 0 3 6 Min. -8 Max. 7 6 ns ns ns ns ns ns *1 Unit Note tOH Output Hold time from CLK NOTE) 1. If clock rising time is longer than 1ns, (tr /2–0.5ns) should be added to the parameter. Output Load Condition VOUT 50pF CLK 1.4V DQ 1.4V Output Timing Measurement Reference Point CLK tOLZ DQ 1.4V 1.4V tAC tOH tOHZ MITSUBISHI ELECTRIC 31 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Burst Write (single bank) @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) 13 14 15 16 17 CLK tRC /CS tRAS tRP /RAS tRCD tRCD /CAS /WE tWR CKE DQM A0-8 A10 A9,11 BA0,1 DQ ACT#0 X Y X Y X X X X 0 0 0 0 0 D0 D0 D0 D0 D0 D0 D0 D0 WRITE#0 PRE#0 ACT#0 WRITE#0 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 32 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Burst Write (multi bank) @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) 13 14 15 16 17 CLK tRC /CS tRRD tRRD tRAS tRP /RAS tRCD tRCD /CAS /WE tWR tWR CKE DQM A0-8 A10 A9,11 BA0,1 DQ ACT#0 X X Y Y X X Y X X X X X X X X 0 1 0 1 0 0 1 2 0 D0 D0 D0 D0 D1 D1 D1 D1 D0 D0 D0 D0 WRITE#0 ACT#1 PRE#0 WRITE#1 ACT#0 ACT#2 WRITE#0 PRE#1 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 33 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Burst Read (single bank) @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) 13 14 15 16 17 CLK tRC /CS tRAS tRP /RAS tRCD tRCD /CAS /WE CKE DQM DQM read latency =2 A0-8 A10 A9,11 BA0,1 DQ X Y X Y X X X X 0 0 0 0 0 CL=3 Q0 Q0 Q0 Q0 Q0 Q0 ACT#0 READ#0 PRE#0 ACT#0 READ#0 READ to PRE ³BL allows full data out Italic parameter indicates minimum case MITSUBISHI ELECTRIC 34 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Burst Read (multiple bank) @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) 13 14 15 16 17 CLK tRC /CS tRRD tRAS tRP tRRD /RAS tRCD tRCD /CAS /WE CKE DQM DQM read latency =2 A0-8 A10 A9,11 BA0,1 DQ X X Y Y X X Y X X X X X X X X 0 1 0 1 0 0 1 2 0 CL=3 Q0 Q0 CL=3 Q0 Q0 Q1 Q1 Q1 Q1 Q0 ACT#0 READ#0 ACT#1 PRE#0 READ#1 ACT#0 PRE#1 READ#0 ACT#2 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 35 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) Burst Write (multi bank) with Auto-Precharge @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRRD tRRD /RAS tRCD tRCD BL-1+ tWR + tRP BL-1+ tWR + tRP tRCD /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ ACT#0 ACT#1 X X Y Y X Y X Y X X X X X X X X 0 1 0 1 0 0 1 1 D0 D0 D0 D0 D1 D1 D1 D1 D0 D0 D0 D0 D1 WRITE#0 with AutoPrecharge ACT#0 WRITE#1 with AutoPrecharge WRITE#0 ACT#1 WRITE#1 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 36 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRRD tRRD /RAS tRCD tRCD BL+tRP tRCD /CAS BL+tRP /WE CKE DQM DQM read latency =2 A0-8 A10 A9,11 BA0,1 DQ X X Y Y X Y X Y X X X X X X X X 0 1 0 1 0 0 1 1 CL=3 Q0 Q0 CL=3 Q0 Q0 Q1 Q1 Q1 Q1 CL=3 Q0 Q0 ACT#0 ACT#1 READ#0 with Auto-Precharge ACT#0 READ#1 with Auto-Precharge READ#0 ACT#1 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 37 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Page Mode Burst Write (multi bank) @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) 13 14 15 16 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ ACT#0 X X Y Y Y Y X X X X 0 1 0 0 1 0 D0 D0 D0 D0 D0 D0 D0 D0 D1 D1 D1 D1 D0 D0 D0 WRITE#0 ACT#1 WRITE#0 WRITE#1 WRITE#0 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 38 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) Page Mode Burst Read (multi bank) @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM DQM read latency=2 A0-8 A10 A9,11 BA0,1 DQ X X Y Y Y Y X X X X 0 1 0 0 1 0 CL=3 Q0 Q0 CL=3 Q0 Q0 Q0 Q0 CL=3 Q0 Q0 Q1 Q1 Q1 Q1 ACT#0 READ#0 ACT#1 READ#0 READ#1 READ#0 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 39 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Write Interrupted by Write / Read @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) 13 14 15 16 17 CLK /CS tRRD /RAS tRCD tCCD /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ ACT#0 X X Y Y Y Y Y X X X X 0 1 0 0 0 1 0 CL=3 D0 D0 D0 D0 D0 D0 D1 D1 Q0 Q0 Q0 Q0 WRITE#0 WRITE#0 WRITE#0 READ#0 ACT#1 WRITE#1 Burst Write can be interrupted by Write or Read of any active bank. Italic parameter indicates minimum case MITSUBISHI ELECTRIC 40 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) Read Interrupted by Read / Write @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM DQM read latency=2 A0-8 A10 A9,11 BA0,1 DQ X X Y Y Y Y Y Y X X X X 0 1 0 0 0 1 0 0 Q0 Q0 Q0 Q0 Q0 Q0 Q1 Q1 Q0 D0 D0 ACT#0 READ#0 READ#0 READ#0 READ#0 WRITE#0 ACT#1 READ#1 blank to prevent bus contention Burst Read can be interrupted by Read or Write of any active bank. Italic parameter indicates minimum case MITSUBISHI ELECTRIC 41 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Write Interrupted by Precharge @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) 13 14 15 16 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ ACT#0 X X Y Y X Y X X X X X X 0 1 0 1 0 1 1 1 D0 D0 D0 D0 D1 D1 D1 D1 D1 WRITE#0 ACT#1 PRE#0 WRITE#1 PRE#1 ACT#1 WRITE#1 Burst Write is not interrupted by Precharge of the other bank. Burst Write is interrupted by Precharge of the same bank. Italic parameter indicates minimum case MITSUBISHI ELECTRIC 42 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Read Interrupted by Precharge @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) 13 14 15 16 17 CLK /CS tRRD tRP /RAS tRCD tRCD /CAS /WE CKE DQM DQM read latency=2 A0-8 A10 A9,11 BA0,1 DQ X X Y Y X Y X X X X X X 0 1 0 1 0 1 1 1 Q0 Q0 Q0 Q0 Q1 Q1 ACT#0 READ#0 ACT#1 PRE#0 READ#1 PRE#1 ACT#1 READ#1 Burst Read is not interrupted by Precharge of the other bank. Burst Read is interrupted by Precharge of the same bank. Italic parameter indicates minimum case MITSUBISHI ELECTRIC 43 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Mode Register Setting 0 1 2 3 4 5 6 7 8 9 10 11 12 SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) 13 14 15 16 17 CLK /CS tRC tRSC /RAS tRCD /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ Auto-Ref (last of 8 cycles) Mode Register Setting ACT#0 0 M X Y X X 0 0 D0 D0 D0 D0 WRITE#0 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 44 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Auto-Refresh @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) 13 14 15 16 17 CLK /CS tRC /RAS tRCD /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ Auto-Refresh Before Auto-Refresh, all banks must be idle state. ACT#0 X Y X X 0 0 D0 D0 D0 D0 WRITE#0 After tRC from Auto-Refresh, all banks are idle state. Italic parameter indicates minimum case MITSUBISHI ELECTRIC 45 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Self-Refresh 0 1 2 3 4 5 6 7 8 9 10 11 12 SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) 13 14 15 16 17 CLK CLK can be stopped tRC /CS /RAS /CAS /WE tSRX CKE CKE must be low to maintain Self-Refresh DQM A0-8 A10 A9,11 BA0,1 DQ Self-Refresh Entry Before Self-Refresh Entry, all banks must be idle state. Self-Refresh Exit After tRC from Self-Refresh Exit, all banks are idle state. Italic parameter indicates minimum case ACT#0 X X X 0 MITSUBISHI ELECTRIC 46 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L DQM Write Mask @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ ACT#0 X Y Y Y X X 0 0 0 0 masked D0 D0 D0 D0 D0 D0 D0 masked WRITE#0 WRITE#0 WRITE#0 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 47 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L DQM Read Mask @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE DQM read latency=2 DQM A0-8 A10 A9,11 BA0,1 DQ ACT#0 READ#0 X Y Y Y X X 0 0 0 0 masked Q0 Q0 Q0 Q0 masked Q0 Q0 Q0 READ#0 READ#0 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 48 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Power Down 0 1 2 3 4 5 6 7 8 9 10 11 12 SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) 13 14 15 16 17 CLK /CS /RAS /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ Precharge All ACT#0 X Standby Power Down CKE latency=1 Active Power Down X X 0 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 49 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L CLK Suspend @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE CKE latency=1 CKE latency=1 DQM A0-8 A10 A9,11 BA0,1 DQ ACT#0 X Y Y X X 0 0 0 D0 D0 D0 D0 Q0 Q0 Q0 Q0 WRITE#0 CLK suspended READ#0 CLK suspended Italic parameter indicates minimum case MITSUBISHI ELECTRIC 50 128M Synchronous DRAM Nov. '99 M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SDRAM (Rev. 1.0E) (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. 2. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. 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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. MITSUBISHI ELECTRIC 51