M30240M5

MITSUBISHI ELECTRONICS AMERICA, INC. PRELIMINARY M30240 M30240 Group Specification Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Features...............................................................1-3 Applications......................................................... 1-3 Pin Configuration ................................................ 1-4 Block Diagram..................................................... 1-5 Performance outline............................................ 1-6 Pin Description.................................................... 1-8 Overview ........................................................... 1-10 Operation of Functional Blocks . . . . . . . . . 1-11 Central Processing Unit (CPU) ......................... 1-11 Processor Mode................................................ 1-14 Memory ............................................................. 1-15 SFR MAP .......................................................... 1-16 Reset................................................................. 1-22 Software Reset ................................................. 1-23 Clock-Generating Circuit................................... 1-23 Clock Control .................................................... 1-24 Stop Mode......................................................... 1-26 Wait Mode......................................................... 1-26 Status Transition Of the Internal Clock Φ ......... 1-26 Power Control ................................................... 1-27 Protection.......................................................... 1-28 Interrupts........................................................... 1-29 NMI Interrupt ..................................................... 1-35 Key-Input Interrupt ............................................ 1-36 Address Match Interrupt.................................... 1-38 Watchdog Timer................................................ 1-39 Frequency Synthesizer Circuit .......................... 1-41 Universal Serial Bus.......................................... 1-44 DMAC ............................................................... 1-63 Timers ............................................................... 1-68 Timer A ............................................................. 1-69 Timer B ............................................................. 1-80 UART0 through UART2 .................................... 1-83 A-D Converter ................................................. 1-106 CRC Calculation Circuit .................................. 1-116 Programmable I/O Ports ................................. 1-117 Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-124 Usage Precautions.......................................... 1-124 Specifications . . . . . . . . . . . . . . . . . . . . . . 1-128 Electrical ......................................................... 1-128 Timing ............................................................. 1-130 Timing Diagrams- Peripheral/interrupt ............ 1-133 Applications . . . . . . . . . . . . . . . . . . . . . . . 1-134 Frequency Synthesizer Interface and DC-DC Converter..................................... 1-134 Attach/Detach Function................................... 1-138 Low Pass Filter Network ................................. 1-139 USB Transceiver............................................. 1-140 Programming Notes ........................................ 1-141 MITSUBISHI ELECTRONICS AMERICA, INC. 1-2 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Features SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1.0 Description The M30240 group is a 16-bit microcomputer based on the M16C family core technology. They are single-chip USB peripheral microcontrollers based on the Universal Serial Bus (USB) Version 1.1 specification. They are packaged in an 80-pin, molded plastic QFP. These single-chip microcontrollers operate using sophisticated instructions featuring a high level of instruction efficiency, making them capable of executing instructions at high speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling office communications, industrial equipment, and other high-speed processing applications. 1.1 Features • • • • CPU .................................................... 16-bit (including a hardware multiplier) Number of instructions ........................ 91 Shortest instruction execution time ..... 83ns f(XIN)=12MHz USB Features:..................................... Five endpoint pairs (IN/OUT) FIFO Sizes (endpoints 0-4):32,128, 32, 32, 32 Conforms to USB V1.1 Specification USB Transceiver ................................. Conforms to USB V1.1 Specification-Internal Vref Frequency Synthesizer........................ PLL for 48MHz clock Memory capacity (mask device):......... ROM (40K, 48K) / RAM (3.0 K) Memory capacity (OTP device):.......... PROM (128K) / RAM (5K) Supply Voltage .................................... 4.1 to 5.25V f(XIN)=12MHz) Interrupts............................................. 21 internal and 4 external interrupt sources, 4 software interrupt sources; 7 levels (including key input interrupt X 16) Multifunction timer ............................... 5 X 16-bit, w/integrated 20mA (peak) PWM outputs General purpose timer ........................ 3 X 16-bit, internal interrupt only UART................................................... 3 X 7/8/9 bits; Configurable for synchronous or asynchronous mode DMAC.................................................. 2 channels (trigger: 18 sources) A-D Converter ..................................... 10 bits X 8 channels CRC calculation circuit ........................ 1 circuit (industry standard polynomial) Watchdog timer ................................... 1 line (15 bit) Programmable I/O............................... 63 lines High current and LED Drivers ............. 5 high current and 8 LED drivers Clock-generating circuit....................... 1 built-in circuit including feedback resistor Package: ............................................. 80P6N (0.8 mm pitch) • • • • • • • • • • • • • • • • • 1.2 Applications USB peripherals, such as telephones, audio systems, scanners, and digital cameras. 1-3 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Pin Configuration 1.3 Pin Configuration SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.1 shows the pin configuration (top view). P20/LED0 P21/LED1 P22/LED2 P23/LED3 P24/LED4 P25/LED5 P26/LED6 P27/LED7 P12/KI10 P13/KI11 P14/KI12 P15/KI13 P16/KI14 P17/KI15 P11/KI9 P04/KI4 P05/KI5 P06/KI6 P07/KI7 P10/KI8 Vcc P30 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P03/KI3 65 P02/KI2 66 P01/KI1 67 P00/KI0 68 40 39 38 37 36 35 34 P32 P33 P34 P35 P36 P37/CLKout P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TxD0 P64/CTS1/RTS1/CLKS1 P65/CLK1 P66/RxD1 P67/TxD1 P70/TxD2/TA0OUT P71/RxD2/TA0IN P107/AN7 69 P106/AN6 70 P105/AN5 71 P104/AN4 72 P103/AN3 73 P102/AN2 74 P101/AN1 75 P100/AN0 76 AVss 77 LPF 78 Vref 79 AVcc 80 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 M30240Mx/EC P31 33 32 31 30 29 28 27 26 25 1 2 3 P85/NMI 4 P84/INT1 5 P83/ATTACH 6 7 BYTE 8 CNVss 9 D+ Vss P73/CTS2/RTS2/TA1IN Figure 1.1: Pin Configuration (top view) 1-4 P72/CLK2/TA1OUT P80/TA4OUT P76/TA3OUT P74/TA2OUT P81/TA4IN P77/TA3IN P87/ADTRG P75/TA2IN EXTCAP P82/INT0 RESET P86/SOF Xout Xin Vcc Vss D- Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Block Diagram 1.4 Block Diagram SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.2 is a block diagram of the M30240 group. 8 8 8 8 8 8 7 8 I/O ports Port P0 Port P1 Port P2 Port P3 Port P6 Port P7 Port P8 0~84 Port P85 86, 8 7 Port P10 Internal peripheral functions Timer Memory ROM RAM Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer TA3 (16 bits) Timer TA4 (16 bits) Timer TB0 (16 bits) Timer TB1 (16 bits) Timer TB2 (16 bits) Watchdog timer (1 line) System clock generator XIN-XOUT A-D converter 10 bits X 8 channels M16C series16-bit CPU core Registers Program counter PC Vector table INTB Stack pointer ISP USP R0H R0L R0H R0L R1L R1H R2 R3 A0 A1 FB SB USB function Frequency Synthesizer UART/clock synchronous SI/O (8 bits X 3 channels) (Note 1) CRC arithmetic circuit (CCITT) (Polynomial : X 16+X12+X 5+1) DMAC (2 channels) Multiplier FLG Note 1: One of serial I/O can be used for SIM interface. Figure 1.2: Block diagram of M30240 group 1-5 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Performance outline 1.5 Performance outline SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.1 is a performance outline of the M30240 group. Table 1.1: Performance outline of M30240 group Item Number of basic instructions Shortest instruction execution time ROM Memory capacity RAM I/O port Input port Multifunction Timer General purpose Timer Serial I/O A-D converter DMAC CRC calculation circuit Watchdog timer Interrupt Clock-generating circuit Supply voltage (typical) Power consumption (typical) I/O withstand voltage I/O characteristics Average output current P0 to P3, P6,P7, P8 (except P85), P10 P85 TA0, TA1, TA2, TA3, TA4 TB0, TB1, TB2 UART0, UART1, UART2 8 bits x 7, 7 bits x 1 1 bit x 1 16 bits x 5 16 bits x 3 (UART or clock synchronous) x 3 10 bits x 8 channels 2 channels (trigger:18 sources) CRC-CCITT 15 bits x 1 (with prescaler) 21 internal and 4 external sources, 4 software sources, 7 levels Built-in clock generation circuit (built-in feedback resistor, and external ceramic or quartz oscillator) 4.1 to 5.25V, (f(XIN)=12MHz, without software wait) 250 mwatt, Vcc=5.0V, 12MHz 5V 5 mA available on ports P0, P1, P3,P6, P71, P73, P75, P77, P81~P84, P86, P87, P10 10 mA available on ports P2, P70, P72, P74, P76, P80 0 to 70oC CMOS high performance silicon gate 80-pin plastic molded QFP (See Figure 3: ROM capacity field) 91 instructions 83ns (f(XIN) =12MHz) Performance Operating temperature Device configuration Package 1-6 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Performance outline SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Mitsubishi plans to release the following products in the M30240 group: (1) Support for mask ROM version and one-time PROM version (2) ROM capacity (3) Package • 80P6N: Plastic molded QFP (mask ROM version and one-time PROM version) Figure 1.3 shows the type number, memory size and package for the M30240 group. Type No. M 3 0 24 0 M 5 – X X X F P Package type: FP : Package 80P6N ROM No. Omitted for blank one-time PROM version,and EPROM version ROM capacity: 1: 8K bytes 2: 16K bytes 3: 24K bytes 4: 32K bytes 5: 40K bytes 6: 48K bytes 7: 8: 9: A: C: 56K bytes 64K bytes 80K bytes 96K bytes 128K bytes Memory type: M : Mask ROM version E : EPROM or one-time PROM version S : External ROM version F : Flash memory version Part type: Specifies part variations with M30240 group M30240 Group M16C Family Figure 1.3: Type number, memory size, and package Table 1.2 shows the Package Number, type, ROM and RAM Capacity for M30240 Group. Table 1.2: Type M30240M5 M30240M6 M30240ECFP M30240 Group ROM Capacity 40K bytes 48K bytes 128K bytes RAM Capacity 3K bytes 3K bytes 5K bytes Package Type 80P6N 80P6N 80P6N Remarks Mask ROM Version Mask ROM Version One-time PROM version 1-7 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Pin Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1.6 Pin Description Table 1.3: Pin # 1 2 3 4,5 Figure Pin Description I/O I/O I/O I I/O Name P87 P86 P85/(NMI) P84 ~ P83 Description CMOS I/O port. This pin also functions as an external trigger for A-D conversion. CMOS I/O port. This pin also functions as the start of frame (SOF) pulse for the USB module. CMOS input port. This pin also functions as a non-maskable external interrupt. CMOS I/O port. These pins also functions as external interrupt 1 and are used to enable the stealth detach function for the USB transceiver. An external capacitor (Ext. Cap) pin. When the USB transceiver voltage converter is used, a 2.2 µF and a 0.1 µF capacitor should connect between this pin and Vss to ensure proper operation of the USB line driver. This option is enabled by setting bit 4 of the USB control register (000C16) to a “1”. Connect this pin to Vss Connect this pin to Vss USB D+ voltage line interface, a series resistor of 33 Ω is connected to this pin. USB D- voltage line interface, a series resistor of 33 Ω is connected to this pin. A “L” on this input resets the microcomputer. See Xin Ground: Vss = 0V Input and output signals to and from the internal clock generation circuit. Connect a ceramic resonator or quartz crystal between Xin and Xout pins to set the oscillation frequency. If an external clock is used, connect the clock source to the Xin pin and leave the Xout pin open. Power: Vcc = 4.1~ 5.25V CMOS I/O port. This pin also functions as external interrupt 0. CMOS I/O port. Pins in this port also function as TimerA4 input and output as selected by software. CMOS I/O port. Pins in this port also function as timer pins. P77 and P76 can function as TimerA3 input and output as selected by software. P75 and P74 can function as TimerA2 input and output as selected by software. CMOS I/O port. Pins in this port also function as UART2 CTS, RTS, CLK, RXD, and TXD as selected by software. P73 and P72 can function as TimerA1 input and output as selected by software. P71 and P70 can function as TimerA0 input and output as selected by software. CMOS I/O port. Pins in this port also function as UART1 CTS, RTS, CLK, Serial Clock, RXD, and TXD as selected by software. TXD(OE~) and RTS(SUSPEND) in addition to D+ and D- can be used to run the device in USB bypass mode. CMOS I/O port. Pins in this port also function as UART0 CTS, RTS, CLK, RXD, and TXD as selected by software. CMOS I/O port. CMOS I/O port. These pins are capable of driving up to 20mA (peak) for LEDs. 6 EXTCAP _ 7 8 9 10 11 12 13 BYTE CNVss USB D+ USB D - I I I/O I/O I O I RESET Xout Vss 14 Xin I 15 16 17-18 19-22 Vcc P82 P81 ~ P80 I I/O I/O P77 ~ P74 I/O 23-26 P73 ~ P70 I/O 27-30 P67 ~ P64 P63 ~ P60 P37 ~ P30 P27/LED7 ~ P20/LED0 I/O 31-34 35-42 43-50 I/O I/O I/O 1-8 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Pin Description Table 1.3: Pin # 51 52 53 54-60 61-68 69-76 77 78 79 80 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure Pin Description I/O I I/O I I/O I/O I/O I O I I Power: Vcc = 4.1~ 5.25V CMOS I/O port. This port can also function as the key-on wakeup interrupt KI15. Ground: Vss = 0V CMOS I/O port. This port can also function as the key-on wakeup interrupts (KI8 ~ KI14). CMOS I/O port. This port can also function as the key-on wakeup interrupts (KI0 ~ KI7). CMOS I/O port. These pins also function as Analog inputs 7-0 for A-D conversion This pin is a power supply input for the AD converter. (Connect to Vss) Loop filter for the frequency synthesizer. This pin is the reference voltage input for the A-D converter. This pin is a power supply input for the AD converter. (Connect to Vcc) Name Vcc P17/KI15 Vss P16/KI14 ~ P10/KI8 P07/KI7 ~ P00/KI0 P107 ~ P100 AVss LPF VREF AVcc Description 1-9 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Overview 1.7 Overview SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The M30240 group is a single chip PC peripheral microcontroller based on the Universal Serial Bus (USB) Version 1.1 specification. This device provides interface between a USBequipped host computer and PC peripherals such as telephones, audio systems, and digital cameras. The M30240 block diagram is shown in Figure 1.4. The USB function control unit of the M30240 group can support all four data transfer types listed in the USB specification: Isochronous, Interrupt, Bulk, and Control. Each transfer type is used for controlling a different set of PC peripherals. Isochronous transfers provide guaranteed bus access, a constant data rate, and error tolerance for devices such as computer-telephone integration (CTI) and audio systems. Interrupt transfers are designed to support human input devices (HID) that communicate small amounts of data infrequently. Bulk transfers are necessary for devices such as digital cameras and scanners that communicate large amounts of data to the PC as bus bandwidth becomes free. Finally, control transfers are supported and are useful for bursty, host-initiated type communication where bus management is the primary concern. 1 - 12MHz frequency 48 MHz synthesizer UART x 3 Φ RAM M16C CPU Watchdog Timer A-D Converter DMAC x 2 CRC Circuit Transceiver LED Drivers (X 8) Timers x 8 ROM USB Function Control Unit D+ D- FIFOs (Normal MCU or DMA Transfer) I/O Ports (P0~P3, P6 ~ P8, P10) Figure 1.4: M30240 block diagram 1-10 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Central Processing Unit (CPU) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.0 Operation of Functional Blocks The M30240 group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data, and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are peripheral units such as USB, timers, serial I/O, DMAC, CRC calculation circuit, A-D converter, and I/O ports. The following explains each unit. 2.1 Central Processing Unit (CPU) The CPU has a total of 13 registers shown in Figure 1.5. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks. b15 b8 b7 b0 R0(Note) H L b15 b8 b7 b0 b19 b0 R1(Note) H L Data registers PC Program counter b15 b0 b19 b0 R2(Note) INTB H L Interrupt table register b0 b15 b0 b15 R3(Note) USP User stack pointer b15 b0 b15 b0 A0(Note) Address registers ISP Interrupt stack pointer b15 b0 b15 b0 A1(Note) SB Static base register b15 b0 b15 b0 FB(Note) Frame base registers FLG Flag register IPL U I OBS Z DC Note: These registers consist of two register banks. Figure 1.5: Central processing unit register 2.1.1 Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3) Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. 1-11 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Central Processing Unit (CPU) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1, can be used as 32-bit data registers (R2R0/R3R1). 2.1.2 Address registers (A0 and A1) Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). 2.1.3 Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. 2.1.4 Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed. 2.1.5 Interrupt table register (INTB) Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table. INTB can be used as separate registers of four high-order bits and 16 low-order bits. 2.1.6 Stack pointer (USP/ISP) Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG). 2.1.7 Static base register (SB) Static base register (SB) is configured with 16 bits, and is used for SB relative addressing. 2.1.8 Flag register (FLG) Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.6 shows the flag register (FLG). The following explains the function of each flag: 2.1.8.1 Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.1.8.2 Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to “0” when the interrupt is acknowledged. 2.1.8.3 Bit 2: Zero flag (Z flag) This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”. 2.1.8.4 Bit 3: Sign flag (S flag) This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”. 2.1.8.5 Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is “0”; register bank 1 is selected when this flag is “1”. 2.1.8.6 Bit 5: Overflow flag (O flag) This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”. 1-12 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Central Processing Unit (CPU) 2.1.8.7 Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0” when the interrupt is acknowledged. 2.1.8.8 Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is “0”; user stack pointer (USP) is selected when this flag is “1”. This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software interrupts 0 to 31 is executed. 2.1.8.9 Bits 8 to 11: Reserved area 2.1.8.10 Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled. 2.1.8.11 Bit 15: Reserved area The C, Z, S, and O flags are changed when instructions are executed. See the M16C software manual for details. b15 b0 IPL U I OBSZDC Flag register (FLG) Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Figure 1.6: Flag register (FLG) 1-13 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Processor Mode 2.2 Processor Mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.7 shows the processor mode registers 0 and 1. Processor mode register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 00 0 Symbol PM0 Address 000416 When reset 0016 (Note) Bit symbol Reserved bit PM03 Bit name Function Must always be set to "0" RW Software reset bit The device is reset when this bit is set to “1”. The value of this bit is “0” when read. Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate. Note : Set bit 1 of the protect register (address 000A 16) to “1” when writing new values to this register. Processor mode register 1 (Note) b7 b6 b5 b4 b3 b2 b1 b0 0 00 Symbol PM1 Address 000516 When reset 00XXXXX0 2 Bit symbol Reserved bit Bit name Function Must always be set to “0” RW Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate. PM17 Wait bit 0 : No wait state 1 : Wait state inserted Note : Set bit 1 of the protect register (address 000A 16) to “1” when writing new values to this register. Figure 1.7: Processor mode registers 0 and 1 1-14 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Memory 2.3 Memory SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 0000016 00400 16 SFR RAM XXXXX16 unused yyyyy 16 ROM FFE0016 Special page vector table FFFDC 16 Undefined instruction Overflow Type M30240M5 M30240M6 M30240ECFP Address xxxxx 16 01000 16 01000 16 01800 16 Address yyyyy 16 F6000 16 F4000 16 E0000 16 FFFFF16 BRK instruction Address match Single step Watchdog timer DBC NMI Reset Figure 1.8: Memory Map Figure 1.8 is a memory map of the M30240 group. The address space extends the 1M bytes from address 0000016 to FFFFF16. Addresses above yyyyy16 are ROM. For example, in the M30240ECFP, there is 128K bytes of internal ROM from E000016 to FFFFF16. The special page vector table is mapped from FFE0016 to FFFDB16. If the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as two-byte instructions, reducing the number of program steps. The vector table for fixed interrupts such as the reset and NMI are mapped from FFFDC16 to FFFFF16. The starting addresses of the interrupt routines are stored here. The address of the vector table for software interrupts can be set as desired using the internal register (INTB). See Section 2.12 on interrupts for further details. Addresses below xxxxx16 are RAM. For example, in M30240ECFP, 5K bytes of internal RAM are mapped to the space from 0040016 to 017FF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated.The SFR area is mapped to 0000016 to 003FF16. This area accommodates control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers. Section 2.4 describes the SFR area for peripheral unit control registers. Any part of the SFR area that is unoccupied is reserved and cannot be used for other purposes. 1-15 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group SFR MAP 2.4 SFR MAP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The table below shows the peripheral control registers, their addresses, names, acronyms, and values after reset. Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Register name Acronym Value after reset Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 Address match interrupt enable register Protect register USB control register Watchdog timer start register Watchdog timer control register Address match interrupt register 0 PM0 PM1 CM0 CM1 AIER PRCR USBC WDTS WDC RMAD0 0016 00 4816 2016 00 000 0016 0 000????? 0016 0016 0000 0016 0016 0000 Address match interrupt register 1 RMAD1 Reserved USB attach / detach register USBAD SAR0 0016 DMA0 source pointer DMA0 destination pointer DAR0 DMA0 transfer counter TCR0 DMA0 control register DM0CON 00000?00 DMA1 source pointer SAR1 DMA1 destination pointer DAR1 DMA1 transfer counter TCR1 DMA1 control register DM1CON 00000?00 1-16 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group SFR MAP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Address 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C16 030D16 030E16 030F16 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 031C16 031D16 031E16 031F16 Register name Acronym Value after reset Suspend interrupt control register Resume interrupt control register USB SOF interrupt control register SUSPIC RSMIC SOFIC ?000 ?000 00?000 Bus collision detection interrupt control register DMA0 interrupt control register DMA1 interrupt control register Key input interrupt control register A-D conversion interrupt control register UART2 transmit interrupt control register UART2 receive interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register TIMER A0 interrupt control register TIMER A1 interrupt control register TIMER A2 interrupt control register TIMER A3 interrupt control register TIMER A4 interrupt control register TIMER B0 interrupt control register TIMER B1 interrupt control register Reset interrupt control register INT0 interrupt control register INT1 interrupt control register USB function interrupt control register --USB address register USB power management register USB interrupt status register 1 USB interrupt status register 2 USB interrupt enable register 1 USB interrupt enable register 2 USB frame number register low USB frame number register high USB ISO control register USB DMA0 source register USB DMA1 source register USB endpoint enable BCNIC DM0IC DM1IC KUPIC ADIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC RSTIC INT0IC INT1IC USBFIC USBA USBPM USBIS1 USBIS2 USBIE1 USBIE2 USBSOFL USBSOFH USBISOC USBSAR0 USBSAR1 USBEPEN ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 00? 00? ? 0016 0016 0016 0016 FF16 3316 0016 0016 0016 0016 0016 FF16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB reserved USB EP 0 control/status register USB reserved USB EP 0 max packet size register USB reserved USB EP 0 OUT write count USB reserved USB reserved USB reserved USB EP 1 IN control/status register USB EP 1 OUT control/status register USB EP 1 IN max packet size register USB EP 1 OUT max packet size register USB EP 1 OUT write count USB reserved USB reserved EP0CS EP0MP EP0WC 0016 0816 0016 EP1ICS EP1OCS EP1IMP EP1OMP EP1WC 0016 0016 0016 0016 0016 1-17 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group SFR MAP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Address 032016 032116 032216 032316 032416 032516 032616 032716 032816 032916 032A16 032B16 032C16 032D16 032E16 032F16 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 Register name USB reserved USB EP 2 IN control/status register USB EP 2 OUT control/status register USB EP 2 IN max packet size register USB EP 2 OUT max packet size register USB EP 2 OUT write count USB reserved USB reserved USB reserved USB EP 3 IN control/status register USB EP 3 OUT control/status register USB EP 3 IN max packet size register USB EP 3 OUT max packet size register USB EP 3 OUT write count USB reserved USB reserved USB reserved USB EP 4 IN control/status register USB EP 4 OUT control/status register USB EP 4 IN max packet size register USB EP 4 OUT max packet size register USB EP 4 OUT write count USB reserved USB reserved USB EP 0 FIFO USB EP 1 FIFO USB EP 2 FIFO USB EP 3 FIFO USB EP 4 FIFO reserved reserved reserved Acronym EP2ICS EP2OCS EP2IMP EP2OMP EP2WC Value after reset 0016 0016 0016 0016 0016 EP3ICS EP3OCS EP3IMP EP3OMP EP3WC 0016 0016 0016 0016 0016 0016 EP4ICS EP4OCS EP4IMP EP4OMP EP4WC 0016 0016 0016 0016 0016 EP0 EP1 EP2 EP3 EP4 1-18 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group SFR MAP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Address 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 Register name Acronym Value after reset Reserved UART2 transmit / receive mode register UART2 bit rate generator UART2 transmit buffer register UART2 transmit /receive control register 0 UART2 transmit / receive control register 1 UART2 receive buffer register Count start flag Reserved One-shot start flag Trigger select register Up-down flag U2MR U2BRG U2TB U2C0 U2C1 U2RB TABSR ONSF TRGSR UDF 00 0016 0816 0216 0016 00000 0016 0016 Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register TA0 TA1 TA2 TA3 TA4 TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR 0016 0016 0016 0016 0016 00? 0000 00? 0000 00? 0000 UART0 transmit / receive mode register UART0 bit rate generator UART0 transmit buffer register UART0 transmit / receive control register 0 UART0 transmit / receive control register 1 UART0 receive buffer register UART1 transmit / receive mode register UART1 bit rate generator UART1 transmit buffer register UART1 transmit / receive control register 0 UART1 transmit / receive control register 1 UART1 receive buffer register U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB 0016 0816 0216 0016 0816 0216 1-19 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group SFR MAP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Address 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 Register name UART transmit / receive control register 2 Acronym UCON Value after reset 0000000 DMA0 cause select register DMA1 cause select register DM0SL DM1SL 0016 0016 CRC data register CRC input register CRCD CRCIN A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A-D control register 2 A-D control register 0 A-D control register 1 ADCON2 ADCON0 ADCON1 0 00000??? 0016 Frequency synthesizer clock control Frequency synthesizer control Frequency synthesizer multiplier control Frequency synthesizer prescaler control Frequency synthesizer divider Port P0 Port P1 Port P0 direction register Port P1 direction register Port P2 Port P3 Port P2 direction register Port P3 direction register FSCCR FSC FSM FSP FSD P0 P1 PD0 PD1 P2 P3 PD2 PD3 0016 6016 FF16 FF16 FF16 0016 0016 0016 0016 Port P6 Port P7 Port P6 direction register Port P7 direction register P6 P7 PD6 PD7 0016 0016 1-20 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group SFR MAP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Address 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 Register name Port P8 Port P8 direction register Port P10 Port P10 direction register Acronym P8 PD8 P10 PD10 Value after reset 00 00000 0016 P2 drive capacity Timer A Output Drive Capacity Pull-up control register 0 Pull-up control register 1 P2DR TADR PUR0 PUR1 0016 0016 0016 0016 1-21 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Reset 2.5 Reset SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER There are two types of resets: hardware and software. In both cases, operation is the same after the reset. (See “Software Reset” for further details regarding software resets.) This section explains on hardware resets. When the supply voltage is within the range where operation is guaranteed, a reset is effected by holding the reset pin level “L” (0.2VCC max.) for at least 20 f(XIN) cycles. When the reset pin level is then returned to the “H” level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. Figure 1.9 shows an example of a reset circuit. Figure 1.10 shows the reset sequence. . 5V 4.0V VCC 0V 5V RESET 0.8V 0V Example when V CC = 5V . RESET VCC Figure 1.9: Reset circuit XIN At least 20 cycles are needed RESET Internal clock F Internal clock F 24 cycles FFFFC 16 Address FFFFE16 Content of reset vector Figure 1.10: Reset sequence 1-22 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Software Reset SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER When the RESET pin level = “L”, all ports change to input mode (floating.) Table 1.4 shows the status of the other pins while the RESET pin level is “L”. Table 1.4: Main clock-generating circuits Functions Use of clock Usable oscillator Pins to connect oscillator Oscillation stop/restart function Oscillator status immediately after reset Main clock-generating circuit • CPU’s operating clock source • Internal peripheral units’ operating clock source Ceramic or crystal oscillator Xin, Xout Available Oscillating 2.6 Software Reset Writing a “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the microcomputer. A software reset has almost the same effect as a hardware reset with the following exceptions: • The contents of internal RAM are preserved • All USB, DC-DC converter, and PLL SFR values are preserved. (See Section 2.4) 2.7 Clock-Generating Circuit The clock-generating circuit contains one oscillator circuit that supplies the operating clock sources to the CPU and internal peripheral units.Example of oscillator circuit Figure 1.11 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Circuit constants in Figure 1.11 vary with each oscillator used. Use circuit constant values recommended by the oscillator manufacturer. Microcomputer (Built-in feedback resistor) Microcomputer (Built-in feedback resistor) XIN XOUT (Note) Rd XIN XOUT Open Externally derived clock CIN COUT Vcc Vss Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Figure 1.11: Examples of clock source 1-23 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Clock Control 2.8 Clock Control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.12 shows the block diagram of the clock-generating circuit. XIN XOUT fusb (48MHz) Frequency Synthesizer Circuit fsyn fAD f1SIO2 f1 FSCCR0=1 FSCCR0=0 CM10 “1” Write signal RESET Software reset NMI Interrupt request level judgment output WAIT instruction CM02 SQ b R a c d Internal clock φφ Divider f8 f32 f8SIO2 f32SIO2 Main clock SQ R b a 1/2 1/2 1/2 1/2 1/2 c CM06=0 CM17,CM16=11 CM06=1 CM06=0 CM17,CM16=10 d CM06=0 CM17,CM16=01 CM06=0 CM17,CM16=00 CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 FSCCRi: Bit i at address 03DB16 Details of divider Figure 1.12: Clock-generating circuit The following paragraphs describe the clocks generated by the clock-generating circuit. 2.8.1 Main clock The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to the internal clock Φ. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the clock reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the f(Xout) pin can be reduced using the f(Xin)-f(Xout) drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the f(Xout) pin reduces the power dissipation. This bit defaults to “1” when shifting to stop mode and after a reset. 2.8.2 Internal clock Φ The internal clock Φ is the clock that drives the CPU, and is either the main clock or is derived by dividing the main clock by 2, 4, 8, or 16. The internal clock Φ is derived by dividing the main clock by 8 after a reset. When shifting to stop mode, the main clock division select bit (bit 6 at 000616) is set to “1”. 1-24 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Clock Control 2.8.3 Peripheral function clock 2.8.3.1 • f1, f8, f32 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction. 2.8.3.2 • fAD This clock has the same frequency as the main clock and is used for A-D conversion. 2.8.4 Clock Output In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8 or f32 to be output from the P37/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address 000616) is set to “1”, the output of f8 and f32 stops when a WAIT instruction is executed. Figure 1.13 shows the system clock control registers 0 and 1. System clock control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol CM0 Bit symbol CM00 CM01 CM02 Address 0006 16 Bit name Clock output function select bit When reset 48 16 Function b1 b0 RW WAIT peripheral function clock stop bit 0 0 : I/O port P3 7 0 1 : Invalid 1 0 : f 8 output 1 1 : f 32 output 0 : Do not stop f 1, f 8, f32 in wait mode 1 : Stop f 1, f8, f 32 in wait mode Reserved bit Reserved bit Reserved bit CM06 Main clock division select bit 0 (Note 2) Always set to "1" Always set to "0" Always set to "0" 0 : CM16 and CM17 valid 1 : Division by 8 mode Reserved bit Always set to "0" Note 1: Set bit 0 of the protect register (address 000A 16) to “1” before writing to this register. Note 2: Changes to “1” when shifting to stop mode. System clock control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 Symbol CM1 Bit symbol CM10 Address 0007 16 Bit name All clock stop control bit When reset 2016 Function 0 : Clock on 1 : All clocks off (stop mode) Always set to “0” Always set to “0” Always set to “0” Always set to “0” 0 : LOW 1 : HIGH 0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode b7 b6 RW Reserved bit Reserved bit Reserved bit Reserved bit CM15 CM16 CM17 XIN-XOUT drive capacity select bit (Note 2) Main clock division select bit 1 (Note 3) Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register. Note 2: Changes to “1” when shifting to stop mode. Note 3: Can be selected when bit 6 of system clock control register 0 (address 000616) is “0”. If “1”, division mode if fixed at 8. Figure 1.13: System clock control registers 0 and 1 1-25 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Stop Mode 2.9 Stop Mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Writing “1” to the all-clock stop control bit (bit 0 at address 0007 16) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V. Because the oscillation of internal clock Φ, f1 to f32, and fAD stops in stop mode, peripheral functions such as the A-D converter and watchdog timer do not function. However, timer A operates, provided that the event counter mode is set to an external pulse, and UARTi (i = 0 to 2) functions provided an external clock is selected. Table 1.5 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. The I flag must also be set prior to stopping for an interrupt to cancel it. After coming out of stop mode, it is recommended that five “NOP” instructions be executed to clear the instruction queue. When shifting to stop mode, the main clock division select bit 0 (bit 6 at 000616) is set to “1”. Table 1.5: Pin Port CLKOUT Port status during stop mode Single-chip mode Retains status before stop mode Retains status before stop mode 2.10 Wait Mode When a WAIT instruction is executed, the internal clock Φ stops and the microcomputer enters the wait mode. In this mode, oscillation continues but the internal clock Φ and watchdog timer stop. Writing “1” to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. Table 1.6 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the microcomputer restarts using as internal clock Φ the clock that had been selected when the WAIT instruction was executed Table 1.6: Pin Port CLKout Port status during wait mode Single-chip mode Retains status before stop mode Does not stop when the WAIT peripheral function clock stop bit is “0” When the WAIT peripheral function clock stop bit is “1”, the status immediately prior to entering wait mode is maintained. 2.11 Status Transition Of the Internal Clock Φ Power dissipation can be reduced and low-voltage operation achieved by changing the count source for internal clock Φ. Table 1.7 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. After a reset, operation defaults to division by 8 mode. When shifting to stop mode, the main clock division select bit 0 (bit 6 at address 000616) is set to “1”. The following shows the operational modes of internal clock 2.11.1 Division by 2 mode The main clock is divided by 2 to obtain the internal clock Φ. 1-26 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Power Control 2.11.2 Division by 4 mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The main clock is divided by 4 to obtain the internal clock Φ. 2.11.3 Division by 8 mode The main clock is divided by 8 to obtain the internal clock Φ. Note that oscillation of the main clock must have stabilized before transferring from this mode to another mode. 2.11.4 Division by 16 mode The main clock is divided by 16 to obtain the internal clock Φ. 2.11.5 No-division mode The main clock is used as internal clock. Table 1.7: CM17 0 1 Invalid 1 0 Operating modes dictated by settings of system clock control registers 0 and 1 CM16 1 0 Invalid 1 0 CM06 0 0 1 0 0 Operating mode of internal clock Division by 2 mode Division by 4 mode Division by 8 mode Division by 16 mode No-division mode 2.12 Power Control The following is a description of the three available power control modes: 2.12.0.1 Normal Operation Mode • High-speed mode Divide-by-1 frequency of the main clock become the internal clock Φ. The CPU operates with the internal clock selected. Each peripheral function operates according to its assigned clock. • Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the internal clock Φ. The CPU operates according to the internal clock selected. Each peripheral function operates according to its assigned clock. 2.12.0.2 Wait mode The CPU operation is stopped. The oscillators do not stop. 2.12.0.3 Stop Mode All oscillators stop. The CPU and all built-in peripheral functions stop. Of the three modes listed, this mode is the most effective in decreasing power consumption. 1-27 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Protection SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.13 Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.14 shows the protect register. The values in the processor mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716) and frequency synthesizer registers can only be changed when the respective bit in the protect register is set to “1”. The system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written to an address. The program must therefore be written to return these bits to “0”. Protect register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PRCR Bit symbol PRC0 Address 000A 16 Bit name When reset XXXXX000 2 Function 0 : Write-inhibited 1 : Write-enabled RW Enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 0007 16) and frequency synthesizer registers (addresses 03DB 16 to 03DF 16) PRC1 Enables writing to processor mode 0 : Write-inhibited registers 0 and 1 (addresses 0004 16 1 : Write-enabled and 0005 16) Must always be set to "0" Reserved bit Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate. Figure 1.14: Protect register 1-28 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Interrupts 2.14 Interrupts SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.8 and Table 1.9 show the interrupt sources and vector table addresses. When an interrupt is received, the program is executed from the address shown by the respective interrupt vector. The vector table addresses for the interrupts in Table 7 are fixed (interrupt vector addresses). These interrupts are not affected by the interrupt enable flag (I flag) (non-maskable interrupts). The vector table addresses for the interrupts in Table 8 are variable, being determined as relative to the fixed address in the interrupt table register (INTB). These interrupts can be enabled or disabled using the interrupt enable flag (I flag) (maskable interrupts). Sixty four vectors can be set in the interrupt table register (INTB). Any of software interrupts 0 to 63 can be assigned to each vector. By using the INT instruction to specify a software interrupt number, the program can be executed starting at the address indicated by the respective vector. The BRK instruction interrupt has interrupt vectors in both the fixed vector address and variable vector address. When the contents of FFFE416 through FFFE716 are all “FF16), the program is executed from the address shown in the BRK instruction interrupt vector in the variable vector address. Specify the starting address of the interrupt program in the interrupt vector. Figure 1.15 shows the format for specifying the address. Table 1.8: Interrupt vectors (fixed interrupt vector addresses) Vector table addresses Address(L) to Address(H) FFFDC16 to FFFDF16 FFFE016 to FFFE316 FFFE416 to FFFE716 FFFE816 to FFFEB16 FFFEC16 to FFFEF16 FFFF016 to FFF316 FFFF416 to FFFF716 FFFF816 to FFFFB16 FFFFC16 to FFFFF16 Do not use External interrupt by NMI pin Interrupt source Undefined instruction Overflow BRK instruction Address Match Single Step (Note) Watchdog timer DBC (Note) NMI Reset Remarks Interrupt on UND instruction Interrupt on INTO instruction If the vector is filled with FF16, program execution starts from the address shown by the vector in the variable vector table There is an address-matching interrupt enable bit Do not use Note: Interrupts used for debugging purposes only MSB LSB Low address Mid address 0000 0000 High address 0000 Vector address + 0 Vector address + 1 Vector address + 2 Vector address + 3 Figure 1.15: Format for specifying interrupt vector addresses 1-29 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Interrupts SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.9: Interrupt vectors (variable interrupt vector addresses) Vector table addresses Address(L) to Address(H) Software interrupt number Software interrupt number 0 Software interrupt number 4 Software interrupt number 6 Software interrupt number 7 Software interrupt number 10 Software interrupt number 11 Software interrupt number 12 Software interrupt number 13 Software interrupt number 14 Software interrupt number 15 Software interrupt number 16 Software interrupt number 17 Software interrupt number 18 Software interrupt number 19 Software interrupt number 20 Software interrupt number 21 Software interrupt number 22 Software interrupt number 23 Software interrupt number 24 Software interrupt number 25 Software interrupt number 26 Software interrupt number 27 Software interrupt number 28 Software interrupt number 29 Software interrupt number 30 Software interrupt number 31 Software interrupt number 32 to Software interrupt number 63 Interrupt source BRK instruction USB Suspend USB Resume USB Start of Frame Bus collision detection DMA0 DMA1 Key input interrupt A-D UART2 transmit UART2 receive UART0 transmit UART0 receive UART1 transmit UART1 receive Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 USB Reset INT0 INT1 USB Function Software interrupt Remarks Cannot be masked by I flag +0 to +3 (Note 1) +16 to +19 +24 to +27 +28 to +31 +40 to +43 +44 to +47 +48 to +51 +52 to +55 +56 to +59 +60 to +63 +64 to +67 +68 to +71 +72 to +75 +76 to +79 +80 to +83 +84 to +87 +88 to +91 +92 to +95 +96 to +99 +100 to +103 +104 to +107 +108 to +111 +112 to +115 +116 to +119 +120 to +123 +124 to +127 +252 to +255 Cannot be masked by I flag Note 1:Address relative to address in interrupt table base address register (INTB) 1-30 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Interrupts 2.14.1 Interrupt control registers SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Peripheral I/O interrupts have their own interrupt control registers. Table 1.10 shows the addresses of the interrupt control registers. Figure 1.16 shows the interrupt control registers. The interrupt request bit is set by hardware to “0” when an interrupt request is received. The interrupt request bit can also be set by software to “0”. (Do not set to “1”.) INT0 and INT1 are triggered by the edges of external inputs. The edge polarity is selected using the polarity select bit. (Other interrupts are described elsewhere.) An interrupt must first be enabled before it can be used to cancel stop mode. Table 1.10: Addresses in interrupt control register Symbol name SUSPIC RSMIC SOFIC BCNIC DM0IC DM1IC KUPIC ADIC S2TIC S2RIC S0TIC S0RIC S1TIC Address 004416 004616 004716 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 Interrupt control register UART1 receive Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 USB Reset INT0 INT1 USB Function Symbol name S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC RSTIC INT0IC INT1IC USBFIC Address 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 Interrupt control register USB Suspend Interrupt USB Resume interrupt USB Start Of Frame Bus collision detection DMA0 DMA1 Key input interrupt A-D UART2 transmit UART2 receive UART0 transmit UART0 receive UART1 transmit 1-31 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Interrupts SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol SUSPIC RSMIC BCNIC DMiIC(i=0, 1) KUPIC ADIC SiTIC(i=0 to 2) SiRIC(i=0 to 2) TAiIC(i=0 to 4) TBiIC(i=0 to 2) RSTIC USBFIC Address 0044 16 004616 004A16 004B16, 004C16 004D16 004E16 005116, 0053 16, 004F 16 005216, 0054 16, 0050 16 005516 to 0059 16 005A16 to 005B 16 005C16 005F16 When reset XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 XXXXX000 2 Bit symbol ILVL0 Bit name Interrupt priority level select bit b2 b1 b0 Function 000: 001: 010: 011: 100: 101: 110: 111: Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 R W ILVL1 ILVL2 IR Interrupt request bit 0 : Interrupt not requested 1 : Interrupt requested (Note) Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate. Note: This bit can only be reset (= 0), but cannot be set ( = 1). b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol INTiIC ( i= 0, 1) SOFIC Address 005D16, 005E16 004716 When reset XX00X000 2 XX00X000 2 Bit symbol ILVL0 Bit name Interrupt priority level select bit b2 b1 b0 Function 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Always set to “0” R W ILVL1 ILVL2 IR Interrupt request bit (Note 1) POL Polarity select bit (Note 2) Reserved bit Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate. Note 1: This bit can only be reset (=0), but cannot be set (=1). Note 2: For SOFIC (address 0047 1 6), a "0" should always be written. Figure 1.16: Interrupt control registers 1-32 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Interrupts 2.14.2 Interrupt priority SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The order of priority when two or more interrupts are generated simultaneously is determined by both hardware and software. The interrupt priority levels determined by hardware are reset > NMI > DBC > watchdog timer > peripheral I/O interrupts > single-step > address matching interrupt. The interrupt priority levels determined by software are set in the interrupt control registers. Figure 1.17 shows the circuit that judges the interrupt hardware priority level. When two or more interrupts are generated simultaneously, the interrupt with the higher software priority is selected. However, if the interrupts have the same software priority level, the interrupt is selected according to the hardware priority set in the circuit. The selected interrupt is accepted only when the priority level is higher than the processor interrupt priority level (IPL) in the flag register (FLG) and the interrupt enable flag (I flag) is “1”. Note that the reset, NMI, DBC, watchdog timer, single-step, address-match, BRK instruction, overflow, and undefined instruction interrupts are accepted regardless of the interrupt enable flag (I flag). 1-33 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Interrupts SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Priority level of each interrupt INT1 USB Reset Timer B0 Timer A3 Timer A1 USB Resume USB Suspend USB Function INT0 Timer B1 Timer A4 Timer A2 USB SOF UART1 reception UART0 reception UART2 reception A-D conversion DMA1 Bus collision detection Timer A0 UART1 transmission UART0 transmission UART2 transmission Key input interrupt DMA0 Processor interrupt priority level (IPL) Level 0 (initial value) High Priority of peripheral I/O interrupts (if priority levels are same) Low Interrupt enable flag (I flag) Address match Watchdog timer DBC NMI Reset Interrupt request accepted Figure 1.17: Interrupt resolution circuit 1-34 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group NMI Interrupt 2.14.3 Flag changes SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER When an interrupt request is received, the stack pointer select flag (U flag) changes to “0” and the flag register (FLG) and program counter (PC) are saved to the stack area indicated by the interrupt stack pointer (ISP). Thereafter, the interrupt enable flag (I flag) and debug flag (D flag) change to “0” and the processor interrupt priority level (IPL) at the flag register (FLG) is replaced by the priority level of the received interrupt. However, when interrupt requests are received for software interrupts 32 to 63, the flag register (FLG) and program counter (PC) are saved to the stack shown by the stack pointer select flag (U flag) at the time the interrupt was received. The stack pointer select flag (U flag) does not change. The value of the processor interrupt priority level (IPL) in the flag register (FLG) differs in the case of reset, NMI, DBC, watchdog timer, single-step, address-match, BRK instruction, overflow, and undefined instruction interrupts. Table 1.11 shows how the IPL changes when interrupt requests are received. Table 1.11: Change of IPL state when interrupt request are accepted Change of IPL Level 0 (“0002), is set Level 7 (“1112), is set Does not change Level 7 (“1112), is set Does not change Does not change Does not change Interrupt Reset NMI DBC Watchdog timer Single step Address match Software interrupt 2.13 NMI Interrupt An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI interrupt is a non-maskable external interrupt. The pin level can be checked in the Port P85 register (bit 5 at address 03F016). This pin cannot be used as a normal port input. 2.13.1 Notes: (1) (2) When not intending to use the NMI function, be sure to connect the NMI pin to VCC. Because the NMI interrupt is non-maskable, it cannot be disabled. When the NMI pin input is “L”, do not set the microcomputer in stop mode or wait mode. The NMI interrupt is triggered by the falling edge, so the “L” level does not need to be maintained longer than necessary. 1-35 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Key-Input Interrupt 2.14 Key-Input Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER If the direction register of any of pin of Port0 or Port1 is set for input and a falling edge is input to that port, a key-input interrupt is generated. A key-input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. Figure 1.18 shows the block diagram of the keyinput interrupt. Port P0i pull-up select bit Pull-up transistor i=0~7; j=0~7 Port P0i direction register Key input interrupt control register (address 004D16) P0i/KIj Pull-up transistor i=0~7; j=8~15 KIO0 Port PXi pull-up select bit Port P1i direction register Interrupt control circuit Key input interrupt request P1i/KIj KIO1 5 Figure 1.18: Block diagram of key input interrupt 2.14.1 Enabling/disabling the key-input interrupt The key-input interrupt can be enabled and disabled using the key-input interrupt register (004D16). The key-input interrupt is affected by the interrupt priority level (IPL) and the interrupt enable flag (I flag). 2.14.2 Occurrence timing of the key-input interrupt With key-input interrupt acceptance enabled, ports P0 and P1, which are set to input, become keyinput interrupt pins (KI0 through KI15). A key-input interrupt occurs when a falling edge is input to a key-input interrupt pin. At this moment, the level of other key-input interrupt pins must be “H”. No interrupt occurs when the level of any other key-input interrupt pins is “L”. 2.14.3 How to determine a key-input interrupt A key-input interrupt occurs when a falling edge is input to one of 16 pins, but each pin has the same vector address.Therefore, read the input level of ports P0 and P1 in the key-input interrupt routine to determine the interrupted pin. 1-36 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Key-Input Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.14.4 Registers related to the key-input interrupt Figure 1.19 shows the memory map of key-input interrupt-related registers Key-input interrupt control register (KUPIC) 04D16 Port 0 (P0) Port 1 (P1) 3E016 3E116 Port 0 direction register 3E216 Port 1 direction register 3E316 Pull-up control register 0 3FC16 Pull-up control register 1 3FD16 Figure 1.19: Memory Map of key input interrupt related registers 1-37 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Address Match Interrupt 2.15 Address Match Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). Figure 1.20 shows the address match interrupt-related registers. Address match interrupt enable register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Bit symbol Address 000916 Bit name Address match interrupt 0 enable bit Address match interrupt 1 enable bit When reset XXXXXX002 Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled RW AIER0 AIER1 Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate. Address match interrupt register i (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol RMAD0 RMAD1 Address 001216 to 001016 001616 to 001416 When reset X0000016 X0000016 Function Address setting register for address match interrupt Values that can be set R W 0000016 to FFFFF16 Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate. Figure 1.20: Address match interrupt-related registers 1-38 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Watchdog Timer 2.16 Watchdog Timer SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is 39a 15-bit counter that decrements using the clock derived by dividing the internal clock Φ using the prescaler. A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. Bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or 128). Table 1.12 shows the periodic table for the watchdog timer. Table 1.12: CM06 Watchdog timer periodic table (f(XIN)=10MHz) CM17 CM16 Internal clock Φ 10MHz 1 0 0 0 1 5MHz 1 0 0 1 0 2.5MHz 1 0 0 1 1 0.625MHz 1 0 1 Invalid Invalid 1.25MHz 1 Approx. 3.35s Approx. 6.71s Approx. 419.2ms Approx. 1.68s Approx. 838.8ms Approx. 838.8ms Approx. 209.7ms Approx. 419.2ms Approx. 104.9ms WDC7 0 Approx. 52.4ms Period 0 0 0 The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E16). Figure 1.21 shows the block diagram of the watchdog timer. Figure 1.22 shows the watchdog timerrelated registers. 1-39 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Watchdog Timer SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1/16 Internal clock Φ 1/128 WDC7 = 0 Watchdog timer WDC7 = 1 Write to the watchdog timer start register (address 000E16) Set to 7FFF16 RESET Watchdog timer interrupt request Figure 1.21: Block diagram of watchdog timer Watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol WDC Bit symbol Address 000F16 Bit name When reset 000XXXXX2 Function RW High-order bit of watchdog timer Reserved bit Reserved bit WDC7 Must always be set to 0 Must always be set to 0 Prescaler select bit 0 : Divided by 16 1 : Divided by 128 Watchdog timer start register b7 b0 Symbol WDTS Address 000E16 When reset Indeterminate RW Function The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to 7FFF16 regardless of whatever value is written. Figure 1.22: Watchdog timer control and start registers 1-40 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Frequency Synthesizer Circuit 2.17 Frequency Synthesizer Circuit SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The Frequency Synthesizer Circuit generates a 48MHz clock needed by the USB block and a clock fSYN that are both a multiple of the external input reference clock f(Xin). A block diagram of the circuit is shown in Figure 1.23. EN USBC5 fUSB f(Xin) Prescaler fPIN Frequency Multiplier fVCO Frequency Divider fSYN FSCCR0 8 Bit 8 Bit LS 8 Bit FSP 03DE FSM 03DD FSC 03DC FSD 03DF FSCCR 03DB Data Bus Figure 1.23: Frequency Synthesizer Circuit The frequency synthesizer consists of a prescaler, frequency multiplier macro, a frequency divider macro, and five registers, namely FSP, FSM, FSC, FSD, and FSCCR. Clock f(Xin) is prescaled down using FSP to generate fPIN. fPIN is multiplied using FSM to generate an fVCO clock which is then divided using FSD to produce the clock fSYN. The fVCO clock is optimized for 48 MHz operation and is buffered and sent out of the frequency synthesizer block as signal fUSB. This signal is used by the USB block. 2.17.1 Prescaler Clock fPIN is a divided down version of clock f(Xin) (see Figure 1.24). The relationship between fPIN and the clock input to the prescaler f(Xin) is as follows: • fPIN = f(Xin) / 2(n+1) where n is a decimal number between 0 and 254. Setting FSP to 255 disables the prescaler and fPIN = f(Xin). • Note: f(Xin) frequency below 1 MHz is not recommended. MSB 7 Bit 7 Bit 6 Bit 52 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSB 0 Address: 03DE16 Access: R/W Reset: FF16 fPIN 12 MHz 1 MHz 2 MHz 3 MHz 6 MHz FSP Dec(n) Hex(n) 255 FF 5 05 2 02 1 01 0 00 f(Xin)/2(n+1) = fPIN f(Xin) 12.00 MHz 12.00 MHz 12.00 MHz 12.00 MHz 12.00 MHz Figure 1.24: Frequency Synthesizer Prescaler Register (FSP) 1-41 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Frequency Synthesizer Circuit 2.17.2 Multiplier SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock fVCO is a multiplied up version of clock fPIN (See Figure 1.25). The relationship between fVCO and the clock input to the multiplier (fPIN) from the prescaler is as follows: • fVCO = fPIN x 2(n+1) where n is the decimal equivalent of the value loaded in FSM. Setting FSM to 255 disables the multiplier and fVCO = fPIN. Note 1: n must be chosen such that fVCO equals 48 MHz. Note 2: Minimum fPIN is 1 MHz. MSB 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 fPIN 1 MHz 2 MHz 4 MHz 6 MHz 12 MHz FSM Dec(n) 33 11 5 3 1 Address: 03DD16 LSB Access: R/W 0 Reset: FF16 Hex(n) 4A 0B 05 03 01 fVCO 48.00 MHz 48.00 MHz 48.00 MHz 48.00 MHz 48.00 MHz fPIN x 2(n+1) = fVCO Figure 1.25: Frequency Synthesizer Multiply Register (FSM) 2.17.3 Divider Clock fSYN is a divided down version of clock fVCO (See Figure 1.26). The relationship between fSYN and the clock input to the divider (fVCO) from the multiplier is as follows: • fSYN = fVCO / 2(m+1) where m is the decimal equivalent of the value loaded in FSD. Setting FSD to 255 disables the divider and fSYN = fVCO. MSB 7 LSB Address: 03DF16 0 Access: R/W Reset: FF16 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FSD Dec(m) 48.00 MHz 1 48.00 MHz 127 fVCO Hex(m) 01 7F fSYN 12.00 MHz 187.50 KHz fVCO/2(m+1) = fSYN Figure 1.26: Frequency Synthesizer Divide Register (FSD) 1-42 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Frequency Synthesizer Circuit SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The FSC0 bit in the FSC Control Register enables the frequency synthesizer block. When disabled (FSC0 = “0”), fVCO is held at either a high or low state. When the frequency synthesizer control bit is active (FSC0 = “1”), a lock status (LS = “1”) indicates that fSYN and fVCO are the correct frequency. The LS and FSCO control bits in the FSC Control register are shown in Figure 1.27. When using the frequency synthesizer, a low-pass filter must be connected to the LPF pin. Once the frequency synthesizer is enabled, a delay of 2-5ms is recommended before the output of the frequency synthesizer is used. This is done to allow the output to stabilize. It is also recommended that none of the registers be modified once the frequency synthesizer is enabled as it will cause the output to be temporarily (2-5ms) unstable. The MCU clock source is selected via the Frequency Synthesizer Clock Control register (FSCCR). See Figure 1.28. Note: None of the registers must be written to once the frequency synthesizer is enabled and used as the system clock source (FSCCR register, address 03DB16, bit ‘0’ set to ‘1’) because it will cause the output of the PLL to freeze. Switch system back to f(XIN) and disable before modifying PLL registers. Frequency Synthesizer Control Register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol FSC Bit symbol FSE VCO0 VCO Gain Control VCO1 Reserved bit Address 03DC 16 Bit name Frequency Synthesizer Enable 0 : Disable 1 : Enabled Bit 2 0 0 1 1 Bit 1 0: 1: 0: 1: When reset 6016 Function RW Lowest Gain (Note 1) Low Gain High Gain Highest Gain Must always be set to "0" Bit 6 0 0 1 1 Bit 5 0: 1: 0: 1: Disabled Low Current Intermediate Current (Note 1) High Current CHG0 LPF Current Control CHG1 LS Frequency Synthesizer Lock Status 0: 1: Unlocked Locked Note 1: Recommended Figure 1.27: Frequency Synthesizer Control Register (FSC) Frequency Synthesizer Clock Control Register b7 b6 b5 b4 b3 b2 b1 b0 00 00000 Symbol FSCCR Bit symbol FSCCR0 Reserved Address 03DB 16 Bit name Clock source selection When reset 0016 Function 0 : Xin 1 : fsyn Must always be set to "0" RW Figure 1.28: Frequency Synthesizer Clock Control Register (FSCCR) 1-43 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Universal Serial Bus 2.18 Universal Serial Bus SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The Universal Serial Bus (USB) has the following features: • Complete USB Specification (version 1.1) Compatibility • Error-handling capabilities • FIFOs: • Endpoint • Endpoint • Endpoint • Endpoint • Endpoint 0: 1: 2: 3: 4: IN/OUT 32-byte IN 128-byte OUT IN 32-byte OUT IN 32-byte OUT IN 32-byte OUT 128-byte 32-byte 32-byte 32-byte • Nine endpoints - control endpoint (Endpoint 0 - bi-directional) plus four IN and four OUT endpoints • Complete device configuration • Support of all device commands • Supports of full-speed functions • Support of all USB transfer types: • Isochronous • Bulk • Control • Interrupt • Suspend/Resume operation • On-chip USB transceiver with voltage converter • Start-of-frame interrupt and output pin 2.18.1 USB Function Control Unit (USB FCU) The implementation of the USB by this device is accomplished chiefly through the device’s USB Function Control Unit (See Figure 1.29). The Function Control Unit’s overall purpose is to handle the USB packet protocol layer. The Function Control Unit notifies the MCU that a valid token has been received. When this occurs, the data portion of the token is routed to the appropriate FIFO. The MCU transfers the data to, or from, the host by interacting with that endpoint’s FIFO and CSR register. The USB Function Control Unit is composed of five sections: • Serial Interface Engine (SIE) • Generic Function Interface (GFI) • Serial Engine Interface Unit (SIU) • Microcontroller Interface (MCI) • USB Transceiver 2.18.1.1 Serial Interface Engine The SIE interfaces to the USB serial data and handles deserialization/serialization of data, NRZI encoding decoding, clock extraction, CRC generation and checking, bit stuffing, and other items pertaining to the USB protocol such as handling inter-packet time-outs and packet ID (PID) decoding. 1-44 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Universal Serial Bus 2.18.1.2 Generic Function Interface SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The GFI handles all USB standard requests from the host through the control endpoint (endpoint zero), handles Bulk, Isochronous and Interrupt transfers through endpoints 1-4. The GFI handles read pointer reversal for re-transmission the current data set; write pointer reversal for reception of the last data set again and data toggle synchronization. 2.18.1.3 Serial Engine Interface Unit The SIU block decodes the Address and Endpoint fields from the USB host. 2.18.1.4 Microcontroller Interface The MCI block handles the Microcontroller interface and performs address decoding and synchronization of control signals. 2.18.1.5 USB Transceiver The USB transceiver, designed to interface with the physical layer of the USB, is compliant with the USB Specification (version 1.1) for full-speed devices. It consists of two 6-ohm drivers, a receiver, and Schmitt triggers for single-ended receive signals. The transceiver also includes a voltage converter. The voltage converter can supply 3.0 - 3.6V to the transmitter when the rest of the chip (CPU, USB FCU) operates at 4.15 - 5.25V. To enable the voltage converter, set bit 4 of the USB Control Register (USBC) to a “1”. To disable the voltage converter, set bit 4 of the USBC to a “0”. Refer to Section 5.4 “USB Transceiver” for more detailed information. SIU D+ CPU MCI SIE Transceiver D- GFI FIFOs Figure 1.29: USB Function Control Unit Block Diagram 2.18.2 USB Interrupts There are five USB interrupts in this device: • USB Function interrupt • USB Reset interrupt • USB Suspend interrupt • USB Resume interrupt • USB Start-of-Frame (SOF) interrupt. The first four interrupts are used to control the data flow and USB power. The SOF interrupt is used to monitor the transfer of isochronous (ISO) data. Each of the five USB interrupts is enabled by setting the corresponding bit in the Interrupt Control Register of the Interrupt Control Unit. Because the USB Function Interrupt has multiple interrupt sources, another level of enabling is within the USB Interrupt Registers 1 & 2. 1-45 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Universal Serial Bus 2.18.2.1 USB Function Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The USB Function Interrupt can be triggered by 10 sources; many of these may be cause by several different events. Interrupt status flags associated with each source are contained in USBIS1 and USBIS2. Endpoints 1-4 have two interrupt status flags associated with it to control data transfer or to report a STALL/ UNDER_RUN/OVER RUN condition. The USB Endpoint x Out Interrupt Status Flag is set when • USB FCU successfully receives a packet of data OR • USB FCU sets the FORCE_STALL bit or OVER_RUN bit of the Endpoint x OUT CSR. The USB Endpoint x In Interrupt Status is set when • USB FCU successfully sends a packet of data OR • USB FCU sets the UNDER_RUN bit of the Endpoint x IN CSR. The USB Endpoint 0 (control endpoint) has one interrupt status bit associated with it to control data transfer or report a STALL condition. The USB Endpoint 0 Interrupt Status Flag is set when • USB FCU successfully receives/sends a packet of data • Sets the SETUP_END bit or the FORCE_STALL bit, OR clears the DATA_END bit in the Endpoint 0 IN CSR. The Overrun/Underrun Interrupt Status Flag is set when (applicable to endpoints used for isochronous data transfer) • Overrun condition occurs in a endpoint (CPU is too slow to unload the data from the FIFO), OR • Underrun condition occurs in an endpoint (CPU is too slow to load the data to the FIFO). Each endpoint interrupt and overrun/underrun interrupt is enabled by setting the corresponding bit in the USB Interrupt Enable Register 1 and 2. 2.18.2.2 USB Reset Interrupt The USB Reset Interrupt Status Flag is set when the USB FCU sees a SE0 present on D+/D- for at least 2.5µs. When this bit is set, all USB internal registers except INTST13 (bit5 of USBIS2) are reset to their default values. INTST13, the USB reset Interrupt Status Flag, is set to a “1” when the USB Reset is detected. When the CPU recognizes a USB Reset Interrupt, it needs to re initialize the USB FCU so that the USB operation can behave properly. It must also clear INTST13 by writing a “1” to this bit to allow a USB Reset Interrupt request to occur the next time a USB Reset is detected. Register RSTIC contains the USB Reset Interrupt’s request bit and its interrupt priority select bits which are used to enable the interrupt and set its software priority level. 2.18.2.3 USB Suspend and Resume Interrupts The USB Suspend Interrupt is set when the USB FCU does not detect any bus activity on D+/D- (in J-state) for at least 3ms. The USB Suspend Signaling Interrupt Status Flag (INTST15, bit 7 of USBIS2) is set to a “1” when the USB Suspend is detected. The CPU must clear INTST15 by writing a “1” to this bit to allow a USB Suspend Interrupt request to occur the next time a USB Suspend is detected. The USB Resume Signaling Interrupt Status Flag is set when a USB FCU is in the suspend state and detects non-idle signaling on the D+/D-. Register SUSPIC contains the USB Suspend Interrupt’s request bit and its interrupt priority select bits which are used to enable the interrupt and set its software priority level. The USB Resume Interrupt request is set when the USB FCU is in the suspend state and detects non-idle signaling on D+/D-. The USB Signaling Interrupt Status Flag (INTST14, bit 6 of USBIS2) is set to a “1” when the USB Resume is detected. The CPU must clear INTST14 by writing a “1” to this bit to allow a USB Resume Interrupt request to occur the next time a USB Resume is detected. Register RSMIC contains the USB Resume Interrupt’s request bit and its interrupt priority select bits, which are used to enable the interrupt an set its software priority level. 1-46 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Universal Serial Bus 2.18.2.4 USB SOF Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The USB SOF (Start-Of-Frame) Interrupt is used to control the transfer of isochronous data. The USB FCU generates a USB SOF Interrupt request when a start-of-frame packet is received. Register SOFIC contains the USB SOF Interrupt’s request bit and its interrupt priority select bits, which are used to enable the interrupt and set its software priority level. 2.18.3 USB Endpoint FIFOs The USB FCU has an IN (transmit) FIFO and an OUT (receive) FIFO for each endpoint. Each endpoint (except endpoint 0) can be configured to support either single packet mode (in which only a single data packet is allowed to reside in the endpoint’s FIFO) or dual packet mode (in which up to two data packets are allowed to reside in the endpoint’s FIFO). Dual packet mode provides support for back-to-back transmission or backto-back reception. The mode is automatically determined by the MAXP value. When MAXP > 1/2 of the endpoint’s FIFO size, single packet mode is set. When MAXP 1/2 of the IN FIFO size: The CPU writes a “1” to the IN_PKT_RDY bit of the associated IN CSR after the CPU/DMAC finishes writing a packet of data to the IN FIFO. The USB FCU clears the IN_PKT_RDY bit after the packet has been successfully transmitted to the host (which is assumed for isochronous transfers and is concluded when an ACK is received from the host for non-isochronous transfers). MAXP 1/2 of the IN FIFO size: When the number of bytes of data equal to the MAXP (maximum packet size) has been written to the IN FIFO by the CPU/DMAC, the USB FCU sets the IN_PKT_RDY bit of the associated IN CSR to a “1” automatically. The USB FCU clears the IN_PKT_RDY bit after the packet has been successfully transmitted to the host (which is assumed for isochronous transfers and is concluded when an ACK is received from the host for non-isochronous transfers). MAXP 1/2 of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit of the associated IN CSR to a “1” after it has successfully received a packet of data from the host. The CPU writes a “0” to the OUT_PKT_RDY bit after the packet of data has been unloaded from the OUT FIFO by the CPU/DMAC. MAXP 1/2 of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit of the associated IN CSR to a “1” after it has successfully received a packet of data from the host. The USB FCU clears the OUT_PKT_RDY bit to a “0” automatically when the number of bytes of data equal to the MAXP (maximum packet size) has been unloaded from the OUT FIFO by the CPU/DMAC. MAXP 1/2 of the endpoint’s FIFO size; 2. Set INTPT bit of the IN CSR; 3. Flush the old data in the FIFO; 4. Load interrupt status information and set IN_PKT_RDY bit in the IN CSR; 5. Repeat steps 3 & 4 for all subsequent interrupt status updates. 2.18.4 USB Special Function Registers The MCU controls USB operation through the use of special function registers (SFR). This section describes each USB related SFR. Some USB special function registers have a mix of read/write, read only, and write only register bits. Additionally, the bits may be configured to allow the user to write only a “0” or a “1” to individual bits. • When accessing these registers, writing a “0” to a register that can only be set to a “1” by the CPU has no effect on that register bit. • Writing a “1” to a register that can only be set to a “0” by the CPU has not effect on that register bit. Each figure and description of the special function registers details this operation. All USB Special Function Registers, with the exception of USB Attach/Detach (001F16) and USB control (000C16) must use byte access. Work access is prohibited for USB internal registers (030016 033C16). The contents of all USB Special Functions Registers, including USB Attach/Detach and USB Control, are preserved on a software reset. 2.18.4.1 USB Attach/Detach Register The USB Attach / Detach Register is shown in Figure 1.30. The register is used to attach and detach the USB function from a USB host without physically disconnecting the USB cable. This functionality is enabled by setting P83_SECOND to a “1”. Doing this forces P83 to operate as a pull-up for D+ (through an external 1.5k ohm resistor). The port driver is tri-stated and a “1” is always read from the port bit in this mode. When the ATTACH/DETACH bit is a “1” (and P83_SECOND is a “1”), P83 is driven with the voltage on EXTCAP, causing D+ to be pulled up and the host to detect an attach. When the ATTACH/DETACH bit is a “0” (and P83_SECOND is a “1”), P83 is tri-stated, causing D+ to be pulled down (through the cable and 15k ohm resistor on the host/hub side) and a detach to be registered by the host. A 1.5k ohm pull-up resistor must be connected externally from P83 to D+ when this functionality is used. When it is not used, the 1.5k ohm resistor should be placed between EXTCAP and D+. USB Attach/Detach Register b7 b6 b5 b4 b3 b2 b1 b0 000000 Symbol USBAD Bit symbol P83_2nd Attach/ Detach Reserved Bit name Port 83-Second Address 001F16 When reset 0016 Function RW 0 : Normal mode for Port 8_3 1 : Forces Port 8_3 to operate as pull up for D+. 0 : Tri-states, P8_3 causing the host to detect a detach 1 : Drives P8_3 with voltage on EXTCAP, causing the host to detect an attach Must always be set to "0" Attach/Detach Figure 1.30: USB Attach/Detach Register 1-49 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Universal Serial Bus 2.18.4.2 USB Control Register SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The USB Control Register, shown in Figure 1.31, is used to control the USB FCU. This register is not reset by a USB reset signaling. After the USB is enabled (USBC7 set to “1”), a minimum delay of 250ns (three 12 MHz clock periods) is needed before performing any other USB register read/write operations. USB Control Register b7 b6 b5 b4 b3 b2 b1 b0 00 0 Symbol USBC Address 000C16 Bit name When reset 0016 Function Must always be set to "0" RW Bit symbol Reserved USBC3 USBC4 USBC5 Tranceiver voltage converter High/Low current mode selection USB tranceiver voltage converter enable bit USB clock enable bit USB SOF port select bit USB enable bit USBC6 USBC7 Note Note Note Note 1: 2: 3: 4: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: High current mode (Note 1) Low current mode (Note 2) Disabled Enabled Disabled Enabled Disabled (Note 3) Enabled Disabled (Note 4) Enabled For USB normal operation For USB suspend operation P8 6 is used as GPIO pin All USB internal registers are held at their default values. Figure 1.31: USB Control Register 2.18.4.3 USB Function Address Register The USB Function Address Register, shown in Figure 1.32, maintains the 7-bit USB address assigned by the host. The USB FCU uses this register value to decode USB token packet addresses. At reset, when the device is not yet configured, the value is 0016. For the procedures on how to update this register, refer to Application Notes USB Consecutive Set Address. Function Address Register b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol USBA Bit symbol FUNAD0-6 Reserved Address 030016 Bit name Function Address When reset 00 16 Function 7-bit programmable Function Address Must always be set to "0" RW Figure 1.32: USB Function Address Register 1-50 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Universal Serial Bus SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.18.4.4 The USB Power Management Register The USB Power Management Register, shown in Figure 1.33, is used for power management in the USB FCU. • SUSPEND Detection Flag: When the USB FCU does not detect any bus activity on D+/D- for at least 3ms (and D+/D- are in the J-state), it sets the Suspend Detection Flag and generates an interrupt. This bit is cleared when signaling from the host is detected on D+/D- (which sets the Resume Detection Flag and generates an interrupt), or the Remote Wake-up Bit is set and then cleared by the CPU. If the USB clock was disabled during the suspend state, the SUSPEND Detection Flag is not cleared until after the USB clock is re-enabled. • RESUME Detection Flag: When the USB FCU is in the suspend state and detects activity on D+/D- from the host, it sets the Resume Detection Flag and generates an interrupt. The CPU writes a “1” to INTST14 (bit 6 of USB Interrupt Status Register 2) to clear this flag. • WAKEUP Control Bit: The CPU writes a “1” to the WAKEUP Control Bit for remote wake-up. While this bit is set and the USB FCU is in suspend mode, resume signaling is sent to the host. The CPU must keep this bit set for a minimum of 10ms and a maximum of 15ms before writing a “0” to this bit. USB Power Management Register b7 b6 b5 b4 b3 b2 b1 b0 00000 Symbol USBPM Bit symbol SUSPEND RESUME WAKEUP Reserved Address 0301 16 Bit name Function When reset 00 16 RW Note 1 USB Suspend Detection Flag USB Resume Detection Flag USB Remote Wakeup Bit 0 : No USB suspend signal detected 1 : USB suspend signal detected 0 : No USB resume signal detected 1 : USB resume signal detected 0 : End remote resume signaling 1 : Remote resume signaling (Note 2) Must always be set to "0" Note 1 Note 1: Write "0" only or Read Note 2: If SUSPEND = "1" Figure 1.33: USB Power Management Register 1-51 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Universal Serial Bus SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.18.4.5 USB Interrupt Status Registers 1 and 2 USB Interrupt Status Registers 1 and 2, shown in Figure 1.34 and Figure 1.35, are used to indicate the condition that caused a USB function interrupt and USB Reset, Suspend and Resume Interrupts to the CPU. A “1” indicates the corresponding condition caused an interrupt. The USB Interrupt Status Register bits can be cleared by writing a “1” to the corresponding bit. INTST0 is set to a “1” by the USB FCU when (in Endpoint 0 CSR): •A packet of data is successfully received (EP0CSR0 - OUT_PKT_RDY is set by the USB FCU) •A packet of data is successfully sent (EP0CSR - IN_PKT_RDY is cleared by the USB FCU) •EP0CSR3 (DATA_END) bit is cleared by the USB FCU •EP0CSR4 (FORCE_STALL) bit is set by the USB FCU •EP0CSR5 (SETUP_END) bit is set by the USB FCU INTST2, INTST4, INTST6 or INTST8 is set to a “1” by the USB FCU when (in Endpoint x IN CSR): •A packet of data is successfully sent (INXCSR0 - IN_PKT_RDY is cleared by the USB FCU) •INXCSR1 (UNDER_RUN) bit is set by the USB FCU INTST3, INTST5, INTST7 or INTST9 is set to a “1” by the USB FCU when (in Endpoint xOUT CSR): •A packet of data is successfully received (OUTXCSR0 - OUT_PKT_RDY is set by the USB FCU) •OUTXCSR1 (OVER_RUN) bit is set by the USB FCU •OUTXCSR4 (FORCE_STALL) bit is set by the USB FCU INTST12 is set to a “1” by the USB FCU when an overrun or underrun condition occurs in any of the endpoints. INTST13 is set to a “1” by the USB FCU when a USB reset signaling from the host is received. All internal register bits except this bit are reset to their default values when the USB reset is received. INTST14 is set to a “1” by the USB FCU when the USB FCU is in the suspend state and non-idle signaling is received from D+/D-. INTST15 is set to a “1” by the USB FCU when D+/D- are in the idle state for more than 3ms. USB Interrupt Status Register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol USBIS1 Bit symbol INTST0 Reserved Address 030216 Bit name Function When reset 0016 RW USB Endpoint 0 Interrupt Status Flag 0 : No interrupt request issued 1 : Interrupt request issued Must always be set to "0" INTST2 INTST3 INTST4 INTST5 INTST6 INTST7 USB Endpoint 1 IN Interrupt Status Flag USB Endpoint 1 OUT Interrupt Status Flag USB Endpoint 2 IN Interrupt Status Flag USB Endpoint 2 OUT Interrupt Status Flag USB Endpoint 3 IN Interrupt Status Flag USB Endpoint 3 OUT Interrupt Status Flag 0 : No interrupt request issued 1 : Interrupt request issued 0 1 0 1 0 1 0 1 0 1 : : : : : : : : : : No interrupt request issued Interrupt request issued No interrupt request issued Interrupt request issued No interrupt request issued Interrupt request issued No interrupt request issued Interrupt request issued No interrupt request issued Interrupt request issued Figure 1.34: USB Interrupt Status Register 1 1-52 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Universal Serial Bus SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER USB Interrupt Status Register 2 b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol USBIS2 Bit symbol INTST8 INTST9 Reserved Address 030316 Bit name Function When reset 0016 RW USB Endpoint 4 IN Interrupt Status Flag USB Endpoint 4 OUT Interrupt Status Flag 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Must always be set to "0" INTST12 INTST13 INTST14 INTST15 USB Overrun/Underrun Interrupt Status Flag USB Reset Interrupt Status Flag USB Resume Signaling Interrupt Status Flag USB Suspend Signaling Interrupt Status Flag 0 1 0 1 0 1 : : : : : : No interrupt request issued Interrupt request issued No interrupt request issued Interrupt request issued No interrupt request issued Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Figure 1.35: USB Interrupt Status Register 2 2.18.4.6 Clearing of the USB Interrupt Status Registers The USB Interrupt Status Register 1 and 2 are used to indicate pending interrupts for a given source. The USB FCU sets the interrupt status bits. The CPU writes a “1” to each status bit to clear it. Because the USB Function Interrupt has multiple sources that can generate an interrupt, it is recommended that the user first read the two status registers and store them in variables then write back the same value for clearing all the existing interrupts that were pending when the status registers were read. This procedure prevents any interrupt that occurs after the status registers are read from being cleared by the ‘write-back’ operation. The CPU must read, then write both status registers, writing to status register 1 first and status register 2 second to guarantee proper operation. The upper three bits of the value written back to USBIS2 should always be “000” to prevent any of the USB Reset, Suspend and Resume Status Flags from being cleared. The USB Reset, Suspend and Resume Status Flags are contained in USBIS2 along with the USB Endpoint 4 In/Out Interrupt Status Flags and the USB Overrun/Underrun Interrupts Status Flag. Because the flags are not all sources for the same interrupt, use caution when clearing one or more of the flags to avoid inadvertently clearing other flags. The Reset, Suspend and Resume Status Flags should be cleared individually by writing a byte value with at “1” only at the position corresponding to the flag to be cleared. The USB Endpoint 4 In/ Out Interrupt status Flags and the USB Overrun/Underrun Interrupt Status Flag should be cleared as described in the preceding paragraph because they are sourced for the USB Function Interrupt. “Read-modify-write’ instructions, such as “BCLR’ and ‘BSET’, should not be used to clear any of the interrupt status bits in USBIS1 or USBIS2. Using these instructions could cause pending interrupts to be cleared without the firmware’s knowledge. 2.18.4.7 The USB Function Interrupt Enable Registers 1 and 2 The USB Function Interrupt Enable Registers 1 and 2, shown in Figure 1.36 and Figure 1.37, are used to enable the corresponding interrupt status conditions that can generate a USB Function Interrupt. When the bit to a corresponding interrupt condition is “0”, that condition does not generate a USB function interrupt. When the bit is a “1”, that condition can generate a USB function interrupt. At reset, all USB function interrupt status conditions are enabled. 1-53 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Universal Serial Bus SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER USB Interrupt Enable Register 1 b7 b6 b5 b4 b3 b2 b1 b0 1 Symbol USBIE1 Bit symbol INTEN0 Reserved Address 030416 Bit name Function 0 : Interrupt disabled 1 : Interrupt enabled Must always be set to "1" When reset FF16 RW USB Endpoint 0 Interrupt Enable Bit INTEN2 INTEN3 INTEN4 INTEN5 INTEN6 INTEN7 USB Endpoint 1 IN Interrupt Enable Bit USB Endpoint 1 OUT Interrupt Enable Bit USB Endpoint 2 IN Interrupt Enable Bit USB Endpoint 2 OUT Interrupt Enable Bit USB Endpoint 3 IN Interrupt Enable Bit USB Endpoint 3 OUT Interrupt Enable Bit 0 : Interrupt disabled 1 : Interrupt enabled 0 1 0 1 0 1 0 1 : : : : : : : : Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt disabled enabled disabled enabled disabled enabled disabled enabled 0 : Interrupt disabled 1 : Interrupt enabled Figure 1.36: USB Interrupt Enable Register 1 USB Interrupt Enable Register 2 b7 b6 b5 b4 b3 b2 b1 b0 001 0 0 Symbol USBIE2 Bit symbol INTEN8 INTEN9 Address 030516 Bit name Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Must always be set to "0" When reset 3316 RW USB Endpoint 4 IN Interrupt Enable Bit USB Endpoint 4 OUT Interrupt Enable Bit Reserved INTEN12 Reserved Reserved USB Overrun/Underrun Interrupt Enable Bit 0 : Interrupt disabled 1 : Interrupt enabled Must always be set to "1" Must always be set to "0" Figure 1.37: USB Interrupt Enable Register 2 1-54 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Universal Serial Bus 2.18.4.8 USB Frame Number Registers SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The USB Frame Number Low Register, shown in Figure 1.38, contains the lower 8 bits of the 11-bit frame number received from the host. The USB Frame Number High Register, shown in Figure 1.39 contains the upper 3 bits of the 11-bit frame number received from the host. USB Frame Number Low Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol USBSOFL Bit symbol FN0 to FN7 Address 0306 16 Bit name When reset 0016 Function RW Lower 8 bits of the 11-bit frame number issued with a SOF token X Figure 1.38: USB Frame Number Low Register USB Frame Number High Register b7 b6 b5 b4 b3 b2 b1 b0 0000 0 Symbol USBSOFH Bit symbol FN8 FN9 FN10 Address 0307 16 Bit name When reset 0016 Function RW Upper 3 bits of the 11-bit frame number issued with a SOF token Must always be set to "0" X Reserved X Figure 1.39: USB Frame Number High Register 2.18.4.9 USB ISO Control Register The USB ISO Control Register, shown in Figure 1.40, contains two global bits, ISO_UPD and AUTO_FL for controlling endpoints 1-4 isochronous data transfer. When ISO_UPD = “0”, a data packet in an endpoint’s IN FIFO is always ‘ready to transmit’ upon receiving the next IN_TOKEN from the host (with matched address and endpoint number) if the endpoint’s IN_PKT_RDY is set. When ISO_UPD = “1” and the ISO/TOGGLE_INIT bit of the corresponding endpoint’s IN CSR is set, the internal ‘ready to transmit’ signal to the transmit control logic is not activated when the endpoint’s IN_PKT_RDY is set. Instead, it is activated when the next SOF is received, this way, the data loaded in frame n is transmitted out in frame n+1. The ISO_UPD bit is a global bit for endpoints 1-4 and works with isochronous pipes only. When AUTO_FL = “1”, ISO_UPD = “1”, a particular IN endpoint’s ISO/TOGGLE_INIT bit is set, and the IN endpoint’s IN_PKT_RDY = “1”, the USB FCU detects a SOF packet and the USB FCU automatically flushes the oldest packet from the IN FIFO. In this case, IN_PKT_RDY = “1”, indicates that two data packets are in the IN FIFO. Because double buffering is a requirement for ISO transfer, MAXP must be set to less than or equal to 1/2 of the FIFO size. USB ISO Control Register b7 b6 b5 b4 b3 b2 b1 b0 00000 0 Symbol USBISOC Bit symbol Reserved Address 0308 16 Bit name 0: 1: 0: 1: When reset 0016 Function RW Must always be set to "0" AUTO_FL ISO_UPD AUTO_FLUSH Bit ISO_UPDATE Bit Hardware auto FIFO flush diabled Hardware auto FIFO flush enabled ISO_UPDATE disabled ISO_UPDATE enabled Figure 1.40: USB ISO Control Register 1-55 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Universal Serial Bus 2.18.4.10 USB DMAx Request Registers SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The USB DMAx Request Registers, shown in Figure 1.41 and Figure 1.42, are used to select which USB Endpoint x FIFO read/write requests are selected as the DMAC channel 0 or channel 1 request source. The USB DMA0 (DMA1) Request Register should have only one bit set at any given time. When multiple bits are set, no request is selected. USB DMA0 Request Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol USBSAR0 Bit symbol DMA0R0 DMA0R1 DMA0R2 DMA0R3 DMA0R4 DMA0R5 DMA0R6 DMA0R7 Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Address 0309 16 Bit name 1 IN FIFO write request selection bit 2 IN FIFO write request selection bit 3 IN FIFO write request selection bit 4 IN FIFO write request selection bit 1 OUT FIFO read request selection bit 2 OUT FIFO read request selection bit 3 OUT FIFO read request selection bit 4 OUT FIFO read request selection bit When reset 0016 Function 0 : Not selected 1 : Selected RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 1.41: USB DMA0 Request Register USB DMA1 Request Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol USBSAR1 Bit symbol DMA1R0 DMA1R1 DMA1R2 DMA1R3 DMA1R4 DMA1R5 DMA1R6 DMA1R7 Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Address 030A16 Bit name 1 IN FIFO write request selection bit 2 IN FIFO write request selection bit 3 IN FIFO write request selection bit 4 IN FIFO write request selection bit 1 OUT FIFO read request selection bit 2 OUT FIFO read request selection bit 3 OUT FIFO read request selection bit 4 OUT FIFO read request selection bit When reset 0016 Function 0 : Not selected 1 : Selected RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 1.42: USB DMA1 Request Register 2.18.4.11 USB Endpoint Enable Register The USB Endpoint Enable Register, shown in Figure 1.43, is used to enable/disable an individual endpoint. Endpoint 0 is always enabled and cannot be disabled by firmware. All endpoints are enabled after reset. USB Endpoint Enable Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol USBEPEN Bit symbol EP1_OUT EP1_IN EP2_OUT EP2_IN EP3_OUT EP3_IN EP4_OUT EP4_IN Address 030B 16 Bit name Endpoint 1OUT FIFO Enable bit Endpoint 1 IN FIFO Enable bit Endpoint 2OUT FIFO Enable bit Endpoint 2 IN FIFO Enable bit Endpoint 3 OUT FIFO Enable bit Endpoint 3 IN FIFO Enable bit Endpoint 4 OUT FIFO Enable bit Endpoint 4 IN FIFO Enable bit When reset FF16 Function 0 : Disabled 1 : Enabled RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 1.43: USB Endpoint Enable Register 1-56 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Universal Serial Bus SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.18.4.12 Endpoint 0 CSR (Control and Status Register) The Endpoint 0 CSR (Control and Status Register), shown in Figure 1.44 contains the control and status information of Endpoint 0. •EP0CSR0 (OUT_PKT_RDY): The USB FCU sets this bit to a “1” after it receives a valid SETUP/OUT token from the host. The CPU clears this bit after unloading the packet from the FIFO by writing a “1” to EP0CSR6. The CPU should not clear the OUT_PKT_RDY bit before it finishes decoding the host request. When EP0CSR2 (SEND_STALL) needs to be set (because the CPU decodes an invalid or unsupported request) a “1” should be written to EP0CSR6 and EP0CSR2 at the same time using the same instruction. • EP0CSR1 (IN_PKT_RDY): The CPU writes a “1” to this bit after it finishes writing a packet of data to the endpoint 0 FIFO. The USB FCU clears this bit after the packet is successfully transmitted to the host, or the EP0CSR5 (SETUP_END) bit is set. • EP0CSR2 (SEND_STALL): The CPU writes a “1” to this bit when it decodes an invalid or unsupported standard device request from the host. When the OUT-PKT_RDY bit is a “1” at the time the CPU wants to set the SEND_STALL bit to a “1”, the CPU must also set SERVICED_OUT_PKT_RDY to a “1” to clear the OUT-PKT_RDY at the same time as setting the SEND_STALL bit. The USB FCU returns a STALL handshake for all subsequent IN/OUT transactions (during control transfer data or status stages) while this bit is set. The CPU writes a “0” to clear it after it receives a new SETUP packet. It is up to the firmware to decide what SETUP packet should lead the clearing of the SEND_STALL bit. • EP0CSR3 (DATA_END): The CPU writes a “1” to this bit when it writes (IN data phase) or reads (OUT data phase) the last packet of data to or from the FIFO. The CPU sets this bit at the same time as it sets the last IN_PKT_RDY bit or sets the last SERVICED_OUT_PKT_RDY bit.This bit indicates to the USB FCU that the specific amount of data in the setup phase is transferred. The USB FCU advances to the status phase once this bit is set. When the status phase completes, the USB FCU clears this bit. When this bit is set to a “1”, and the host requests or sends more data, the USB FCU returns a STALL handshake and terminates the current control transfer. • EP0CSR4 (FORCE_STALL): The USB FCU sets this bit to a “1” to report an error status when one of the following occur: • Host sends an IN token in the absence of a SETUP stage • Host sends a bad data toggle in the STATUS stage, (i.e. DATA0 is used) • Host sends a bad data toggle in the SETUP stage, (i.e. DATA1 is used) • Host request more data than specified in the SETUP state, (i.e. IN token comes after DATA_END bit is set) • Host sends more data than specified in the SETUP state, (i.e. OUT token comes after DATA_END bit is set) • Host sends larger data packet than MAXP size All of the conditions stated (except bad data toggle in the SETUP stage) cause the device to send a STALL handshake for the current IN/OUT transaction. For the bad data toggle in the SETUP state, the device sends ACK for the SETUP stage and then sends STALL for the next IN/OUT transaction. A STALL handshake caused by the above listed conditions lasts for one transaction and terminates the ongoing control transfer. Any packet after the STALL handshake will be seen as the beginning of a new control transfer. The CPU writes a “0” to clear the FORCE_STALL status bit. • EP0CSR5 (SETUP_END): The USB FCU sets this bit to a “1” if a control transfer has ended before the specific length of data is transferred during the data phase (status phase starts before DATA_END bit is set) or a control transfer has ended before a new SETUP has arrived and before successfully completing the status phase. The CPU clears this bit by writing a “1” to IN0CSR7. Once the CPU detects the SETUP_END bit as set, it should stop accessing the FIFO to service the previous setup transaction. If the SETUP_END is caused by the reception of the SETUP packet prior to the end of the current control transfer, the OUT_PKT_RDY bit is set once the reception of the SETUP packet has completed (without errors). After the OUT_PKT_RDY bit is set, the new SETUP packet 1-57 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Universal Serial Bus SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER data will be in the FIFO. For this case, because the SETUP_END bit is set near the beginning of the packet when the SETUP PID is encountered and the OUT_PKT_RDY bit is set at the end of the packet, the value read from EP0IN_CSR in the USB functional interrupt routine may only show that the SETUP_END bit as “1” instead of both the SETUP_END and OUT_PKT_RDY bits. • EP0CSR6 and EP0CSR7: These bits are used to clear EP0CSR0 and EP0CSR5 respectively. Writing a “1” to these bits clears the corresponding register bit. USB Endpoint 0 Control and Status Register (Note 5) b7 b6 b5 b4 b3 b2 b1 b0 Symbol EP0CS Bit symbol EP0CSR0 EP0CSR1 EPOCSR2 EPOCSR3 EP0CSR4 EPOCSR5 Address 0311 16 Bit name OUT_PKT_RDY Flag IN_PKT_RDY Bit SEND_STALL Bit DATA_END Bit FORCE_STALL Flag SETUP_END Flag 0 1 0 1 0 1 0 1 0 1 0 1 : : : : : : : : : : : : When reset 0016 Function Not ready Ready Not ready Ready No action Stall Endpoint 0 by CPU No action Last packet transferred from/to FIFO No action Stall Endpoint 0 by USB FCU No action Control transfer ended before specific length of data transferred during data phase No change Clear the OUT_PKT_RDY bit (EPOCSR0) No change Clear the STUP-END bit (EP0CSR5) RW 00 Note 1 00 Note 2 00 00 00 00 Note 1 Note 2 Note 3 EP0CSR6 EPOCSR7 Note Note Note Note Note SERVICED_OUT_PKY_RDY Bit SERVICED_SETUP_END Bit 0: 1: 0: 1: 00 Note 4 00 Note 4 1: Read only 2: Write "1" only or Read 3: Write "0" only or Read 4: Write only - Read "0" 5: Refer to Section 5.5 "Programming Notes" for this register Figure 1.44: USB Endpoint 0 CSR 2.18.4.13 USB Endpoint 0 MAXP Register The USB Endpoint 0 MAXP Register, shown in Figure 1.45, indicates the maximum packet size (MAXP) of Endpoint 0 IN/OUT packet. The default value for Endpoint 0 MAXP is 8 bytes. USB Endpoint 0 MAXP Register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol EP0MP Bit symbol EP0MXP0 to EP0MXP5 Address 0313 16 Bit name Maximum packet size (MAXP) of Endpoint 0 IN/OUT packet When reset 0816 Function RW Reserved Must always be set to "0" Figure 1.45: USB Endpoint 0 MAXP 1-58 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Universal Serial Bus SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.18.4.14 USB Endpoint 0 OUT WRT CNT Register The USB Endpoint 0 OUT WRT CNT Register, shown in Figure 1.46, contains the number of bytes of the current data set in the OUT FIFO. The USB FCU sets the value in the Write Count Register after having successfully received a packet of data from the host. The CPU reads the register to determine the number of bytes to be read from the FIFO. USB Endpoint 0 OUT Write Count Register b7 b6 b5 b4 b3 b2 b1 b0 0 00 Symbol EP0WC Bit symbol W_CNT0 to W_CNT4 Address 031516 Bit name Receive byte count When reset 00 16 Function RW X Must always be set to "0" Reserved X Figure 1.46: USB Endpoint 0 OUT WRT CNT 2.18.4.15 USB Endpoint x IN CSR (Control & Status Register) The USB Endpoint x IN CSR (Control and Status Register), shown in Figure 1.47, contains control and status information of the respective IN endpoint 1-4. • INxCSR0 (IN_PKT_RDY) and INxCSR5 (TX_FIFO_NOT_EMPTY): These two bits are for IN FIFO status when in read operation (see “IN (Transmit) FIFO” operation for details). The CPU writes a “1” to the INxCSR0 bit to inform the USB FCU that a packet of data is written to the FIFO. The USB FCU updates the pointers up on this bit set. The USB FCU also updates the pointers upon a packet of data successfully sent to the host. When the pointer updates are completed, the IN FIFO status is shown on INxCSR0 and INxCSR5 bits for the CPU to read. The CPU must allow at least one wait state between writing and reading these bits for proper FIFO status. • INxCSR1 (UNDER_RUN): This bit is used in ISO mode only to indicate to the CPU that a FIFO underrun has occurred. The USB FCU sets this bit to a “1” at the beginning of an IN token if no data packet is in the FIFO. Setting this bit causes the INST12 bit of the Interrupt Status Register 2 to set. The CPU writes a “0” to clear this bit. • INxCSR2 (SEND_STALL): The CPU writes a “1” to this bit when the endpoint is stalled (transmitter halt). The USB FCU returns a STALL handshake while this bit is set. The CPU writes a “0” to clear this bit. • INxCSR3 (ISO/TOGGLE_INIT): When the endpoint is used for isochronous data transfer, the CPU sets this bit to a “1” for the entire duration of the isochronous transfer. With the ISO bit set to a “1”, the device uses DATA0 as the pid for all packets sent back to the host. When the endpoint is required to initialize the data toggle, this set/reset of the TOGGLE_INIT bit method assumes that there is no activity IN transaction to the respective endpoint on the bus at the time the initialization process is ongoing. Set/reset of the TOGGLE_INIT bit is performed only when an endpoint experiences a configuration event. • INxCSR4 (INTPT): The CPU writes a “1” to this bit to initialize this endpoint as a status change endpoint for IN transactions. This bit is set only when the corresponding endpoint is to be used to communicate rate feedback information (see Chapter. IN (Transmit) FIFOs for details). • INxCSR5 (TX_FIFO_NOT_EMPTY): The USB FCU sets this bit to a “1” when there is at least one data packet in the IN FIFO. This bit, in conjunction with IN_PKT_RDY bit, provides the transmit IN FIFO status information (see “IN (Transmit) FIFO” for details). • INxCSR6 (FLUSH): 1-59 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Universal Serial Bus SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The CPU writes a “1” to this bit to flush the IN FIFO. When there is one packet in the IN FIFO, a flush causes the IN FIFO to be empty. When there are two packets in the IN FIFO, a flush causes the older packet to be flushed out from the IN FIFO. Setting the INXCSR6 (FLUSH) bit during transmission could produce unpredictable results. •INxCSR7 (AUTO_SET): When the CPU sets this bit to a “1”, the IN_PKT_RDY bit is set automatically by the USB FCU after the number of bytes of data equal to the maximum packet size (MAXP) is written into the IN FIFO (see “IN (Transmit) FIFO” operation for details). USB Endpoint x IN Control and Status Register (Note 5) b7 b6 b5 b4 b3 b2 b1 b0 Symbol EPiICS (i= 1-4) Bit symbol INxCSR0 INxCSR1 INxCSR2 INxCSR3 INxCSR4 INxCSR5 INxCSR6 INxCSR7 Note Note Note Note Note Address 031916, 0321 16, 0329 16, 0331 16 Bit name 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 : : : : : : : : : : : : : : : : When reset 0016 Function RW 00 Note 1 IN_PKT_RDY Bit UNDER_RUN Flag SEND_STALL Bit ISO Bit INTPT TX_NOT_EPT Flag FLUSH Bit AUTO_SET Bit Not ready Ready No FIFO underrun FIFO underrun has occured No action Stall IN Endpoint x by CPU Select non-isochronous transfer Select isochronous transfer Select non-rate feedback interrupt transfer Select rate feedback interrupt transfer Transmit FIFO is empty Transmit FIFO is not empty No action Flush the FIFO AUTO-SET disabled AUTO-SET enabled 00 Note 2 00 00 00 00 Note 3 00 Note 4 00 1: Write "1" only or read 2: Write "0" only or read 3: Read only 4: Write only - Read "0" 5: Refer to section 5.5 "Programming Notes" for this register Figure 1.47: USB Endpoint x IN CSR 2.18.4.16 USB Endpoint x OUT Control and Status Register The USB Endpoint x OUT CSR (Control and Status Register), shown in Figure 1.48 contains control and status information of the respective OUT endpoint 1-4. • OUTxCSR0 (OUT_PKT_RDY): The OUTxCSR0 bit for the OUT FIFO status (see “OUT (Receive) FIFOs” for details). The USB FCU sets this bit to a “1” and updates the FIFO pointers after a data packet has been successfully received from the host. The CPU writes a “0” to this bit to inform the USB FCU that a data packet has been unloaded. The USB FCU updates the FIFO pointers when this occurs. The CPU must allow at least one clock cycle between writing and reading bit OUTxCSR0. • OUTXxCSR1 (OVER_RUN): This bit is used in ISO mode only to indicate to the CPU that a FIFO overrun has occurred. The USB FCU sets this bit to a “1” at the beginning of an OUT token when two data packets are already present in the FIFO. Setting this bit causes the INST12 bit of the Interrupt Status Register 2 to set. The CPU writes a “0” to clear OUTXCSR1. • OUTxCSR2 (SEND_STALL): The CPU writes a “1” to this bit when the endpoint is stalled. The USB FCU returns a STALL handshake while this bit is set. The CPU writes a “0” to clear this bit. • OUTxCSR3 (ISO/TOGGLE_INIT): When the endpoint is used for isochronous data transfer, the CPU sets this bit to a “1” for the entire duration of the isochronous transfer. With the ISO/TOGGLE_INIT bit set to a “1”, the device accepts either DATA0 or DATA1 for the PID sent by the host. 1-60 Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Mitsubishi microcomputers M30240 Group Universal Serial Bus SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER When endpoint is required to initialize the data toggle sequence bit (i.e. reset to DATA0 for the next data packet), the CPU sets this bit to a “1” and then resets it to a “0” to initialize the respective endpoint’s data toggle. Successful initialization of the data toggle sequence bit can only be guaranteed if no active OUT transaction to the respective endpoint is ongoing when the initialization process is taking place. Set/reset of the ISO/ TOGGLE_INIT bit should only be performed when an endpoint experiences a configuration event. • OUTxCSR4 (FORCE_STALL): The USB FCU sets this bit to a “1” when the host sends out a larger data packet than the MAXP size. The USB FCU returns a STALL handshake while this bit is set. The CPU writes a “0” to clear this bit. • OUTxCSR5 (DATA_ERR): The USB FCU sets this bit to a “1” to indicate that a CRC error or a bit stuffing error was received in an ISO packet. The CPU writes a “0” to clear this bit. • OUTxCSR6 (FLUSH): The CPU writes a “1” to this to flush the OUT FIFO. When there is one packet in the OUT FIFO, a flush causes the OUT FIFO to be empty. When there are two packets in the OUT FIFO, a flush causes the older packet to be flushed out from the OUT FIFO. Setting the OUTXCSR6 (FLUSH) bit during reception could produce unpredictable results. • OUTxCSR7 (AUTO_CLR): When the CPU sets this bit to a “1”, the OUT_PKT_RDY bit is cleared automatically by the USB FCU after the number of bytes of data equal to the maximum packet size (MAXP) is unloaded from the OUT FIFO (see “OUT (Receive) FIFO” for details). USB Endpoint x OUT Control and Status Register (Note 3) b7 b6 b5 b4 b3 b2 b1 b0 Symbol EPiOCS (i = 1-4) Bit symbol Address 031A 16, 0322 16, 032A 16, 033216 Bit name 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: When reset 0016 Function RW 00 Note 1 OUTxCSR0 OUT_PKT_RDY Flag OUTxCSR1 OVER_RUN Flag OUTxCSR2 SEND_STALL Bit OUTxCSR3 ISO Bit OUTxCSR4 FORCE-STALL Flag OUTxCSR5 DATA-ERR Flag OUTxCSR6 FLUSH Bit OUTxCSR7 AUTO_CLR Bit Not ready Ready No FIFO overrun FIFO overrun occured No action Stall OUT Endpoint x by CPU Select non-isochronous transfer Select isochronous transfer No action Stall Endpoint X by the USB FCU No error CRC or bit stuffing error received in ISO packet No action Flush the FIFO AUTO-CLR disabled AUTO-CLR enabled 00 Note 1 00 00 00 Note 1 00 Note 1 00 Note 2 00 Note 1: Write "0" only or read Note 2: Write only - Read "0" Note 3: Refer to section 5.5 "Programming Notes" for this register Figure 1.48: USB Endpoint x OUT CSR 2.18.4.17 USB Endpoint x IN MAXP Register The USB Endpoint x IN MAXP Register, shown in Figure 1.49, indicates the maximum packet size (MAXP) of an Endpoint x IN packet. The default values for Endpoints 1-4 are 0 bytes. The setting of this register also affects the configuration of single/dual packet operation. When MAXP > 1/2 of the FIFO size, single packet mode is set. When MAXP 1/2 of the FIFO size, single packet is set. When MAXP