M30612MCA-XXXGP

Mitsubishi microcomputers Description M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description The M16C/61 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communications, industrial equipment, and other high-speed processing applications. The M16C/61 group includes a wide range of products with different internal memory types and sizes and various package types. Features • Memory capacity ............................................ ROM (See Figure 1.1.4. ROM Expansion) RAM 4K to 10K bytes • Shortest instruction execution time ................ 100ns (f(XIN)=10MHZ) • Supply voltage ............................................... 4.0 to 5.5V (f(XIN)=10MHZ) 2.7 to 5.5V (f(XIN)=7MHZ with software one-wait) • Low power consumption ................................ 18mW ( f(XIN)=7MHZ, with software one-wait, VCC = 3V) • Interrupts ........................................................ 20 internal and 5 external interrupt sources, 4 software interrupt sources; 7 levels (including key input interrupt) • Multifunction 16-bit timer ................................ 5 output timers + 3 input timers • Serial I/O (UART or clock synchronous) ........ 3 channels • DMAC ............................................................ 2 channels (trigger: 16 sources) • A-D converter ................................................. 10 bits X 8 channels (Expandable up to 10 channels) • D-A converter ................................................. 8 bits X 2 channels • CRC calculation circuit ................................... 1 circuit • Watchdog timer .............................................. 1 line • Programmable I/O ......................................... 87 lines _______ • Input port ........................................................ 1 line (P85 shared with NMI pin) • Memory expansion ........................................ Available (to a maximum of 1M bytes) • Chip select output .......................................... 4 lines • Clock generating circuit ................................. 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) Applications Audio, cameras, office equipment, communications equipment, portable equipment ------Table of Contents-----Central Processing Unit (CPU) ..................... 11 Reset ............................................................. 14 Processor Mode ............................................ 19 Clock Generating Circuit ............................... 30 Protection ...................................................... 39 Interrupts ....................................................... 40 Watchdog Timer ............................................ 59 DMAC ........................................................... 61 Timer ............................................................. 70 Serial I/O ....................................................... 87 A-D Converter ............................................. 114 D-A Converter ............................................. 124 CRC Calculation Circuit .............................. 126 Programmable I/O Ports ............................. 128 Electrical Characteristics ............................. 142 1 Mitsubishi microcomputers Description M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Configuration Figures 1.1.1 and 1.1.2 show the pin configurations (top view). PIN CONFIGURATION (top view) P07/D7 P06/D6 P05/D5 P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P10/D8 P11/D9 P12/D10 P13/D11 P14/D12 P15/D13 P16/D14 P17/D15 P20/A0(/D0/-) P21/A1(/D1/D0) P22/A2(/D2/D1) P23/A3(/D3/D2) P24/A4(/D4/D3) P25/A5(/D5/D4) P26/A6(/D6/D5) P27/A7(/D7/D6) Vss P30/A8(/-/D7) Vcc P31/A9 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 P42/A18 P43/A19 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 M16C/61 Group 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P44/CS0 P45/CS1 P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE P52/RD P53/BCLK P54/HLDA P55/HOLD P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CTS0/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 P96/ANEX1 P95/ANEX0 P94/DA1 P93/DA0 P92/TB2IN P91/TB1IN P90/TB0IN BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN P80/TA4OUT P77/TA3IN P76/TA3OUT P75/TA2IN P74/TA2OUT P73/CTS2/RTS2/TA1IN P72/CLK2/TA1OUT P71/RxD2/TA0IN(Note) P70/TxD2/TA0OUT(Note) Package: 100P6S-A Note: P70 and P71 are N channel open-drain output pin. Figure 1.1.1. Pin configuration (top view) 2 Mitsubishi microcomputers Description M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (top view) P13/D11 P14/D12 P15/D13 P16/D14 P17/D15 P20/A0(/D0/-) P21/A1(/D1/D0) P22 /A2(/D2/D1) P23/A3(/D3/D2) P24/A4(/D4/D3) P25/A5(/D5/D4) P26/A6 (/D6/D5) P27/A7(/D7/D6) Vss P30/A8(/-/D7) Vcc P31/A9 P32/A10 P33 /A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 P12/D10 P11/D9 P10/D8 P07/D7 P06/D6 P05/D5 P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG P96/ANEX1 P95/ANEX0 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 M16C/61 Group 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P42/A18 P43/A19 P44/CS0 P45/CS1 P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE P52/RD P53/BCLK P54/HLDA P55/HOLD P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TX D0 P64/CTS 1/RTS 1/CTS 0/CLKS 1 P65/CLK1 P66/RxD1 P67/TX D1 P70/TxD2/TA0OUT (Note) P71/RxD2/TA0IN (Note) P72/CLK2/TA1OUT P94 /DA1 P93/DA0 P92/TB2IN P91/TB1IN P90/TB0IN BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83 /INT1 P82/INT0 P81 /TA4IN P80/TA4OUT P77/TA3IN P76/TA3OUT P75/TA2IN P74/TA2OUT P73/CTS2/RTS2/TA1IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Package: 100P6Q-A Note: P70 and P71 are N channel open-drain output pin. Figure 1.1.2. Pin configuration (top view) 3 Mitsubishi microcomputers Description M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Block Diagram Figure 1.1.3 is a block diagram of the M16C/61 group. Block diagram of the M16C/61 group 8 8 8 8 8 8 8 I/O ports Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7 Internal peripheral functions Timer A-D converter (10 bits X 8 channels Expandable up to 10 channels) System clock generator XIN-XOUT XCIN-XCOUT 8 Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer TA3 (16 bits) Timer TA4 (16 bits) Timer TB0 (16 bits) Timer TB1 (16 bits) Timer TB2 (16 bits) Port P8 UART/clock synchronous SI/O (8 bits X 3channels) (Note 3) CRC arithmetic circuit (CCITT ) (Polynomial : X16+X12+X5+1) 7 Port P85 M16C/60 series16-bit CPU core Registers Program counter PC Vector table INTB Stack pointer ISP USP FLG R0H R0L R0H R0L R1H R1L R1H R1L R2 R2 R3 R3 A0 A0 A1 A1 FB FB SB Memory ROM (Note 1) RAM (Note 2) Watchdog timer (15 bits) Port P9 8 DMAC (2 channels) D-A converter (8 bits X 2 channels) Port P10 Multiplier 8 Note 1: ROM size depends on MCU type. Note 2: RAM size depends on MCU type. Note 3: One of serial I/O can use for SIM interface. Figure 1.1.3. Block diagram of M16C/61 group 4 Mitsubishi microcomputers Description M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Performance Outline Table 1.1.1 is a performance outline of M16C/61 group. Table 1.1.1. Performance outline of M16C/61 group Item Number of basic instructions Shortest instruction execution time Memory ROM capacity RAM I/O port P0 to P10 (except P85) Input port P85 Multifunction TA0, TA1, TA2, TA3, TA4 timer TB0, TB1, TB2 Serial I/O UART0, UART1, UART2 A-D converter D-A converter DMAC CRC calculation circuit Watchdog timer Interrupt Clock generating circuit Supply voltage Power consumption I/O I/O withstand voltage characteristics Output current Memory expansion Device configuration Package Performance 91 instructions 100ns(f(XIN)=10MHZ) (See the Figure 4. ROM Expansion) 4K to 10K bytes 8 bits x 10, 7 bits x 1 1 bit x 1 16 bits x 5 16 bits x 3 (UART or clock synchronous) x 3 10 bits x (8 + 2) channels 8 bits x 2 2 channels (trigger: 16 sources) CRC - CCITT 15 bits x 1 (with prescaler) 20 internal and 5 external sources, 4 software sources, 7 levels 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) 4.0 to 5.5V (f(XIN ) = 10MHZ) 2.7 to 5.5V(f(XIN)=7MHZ with software one-wait) 18mW (f(XIN) = 7MHZ with software one-wait,VCC = 3V) 5V 5mA Available (to a maximum of 1M bytes) CMOS silicon gate 100-pin plastic mold QFP 5 Mitsubishi microcomputers Description M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Mitsubishi plans to release the following products in the M16C/61 group: (1) Support for mask ROM version, external ROM version, one-time PROM version, and EPROM version (2) ROM capacity (3) Package 100P6S-A : Plastic molded QFP (mask ROM version and one-time PROM version) 100P6Q-A : Plastic molded QFP (mask ROM version and one-time PROM version) 100D0 : Ceramic LCC (EPROM version) ROM Size(Byte) External ROM 128 K 96 K 64 K 32 K M30610MCA-XXXFP/GP M30612MCA-XXXFP/GP M30610MAA-XXXFP/GP M30612MAA-XXXFP/GP M30610M8A-XXXFP/GP M30612M8A-XXXFP/GP M30612M4A-XXXFP/GP M30612SAFP/GP M30610SAFP/GP M30610ECFP/GP M30610ECFS M30612E4FP/GP Mask ROM version One-time PROM version EPROM version External ROM version Figure 1.1.4. ROM expansion The M16C/61 group products currently supported are listed in Table 2. Table 1.1.2. M16C/61 group Type No M30612M4A-XXXFP M30612M4A-XXXGP M30610M8A-XXXFP M30610M8A-XXXGP M30612M8A-XXXFP M30612M8A-XXXGP M30610MAA-XXXFP M30610MAA-XXXGP M30612MAA-XXXFP M30612MAA-XXXGP M30610MCA-XXXFP M30610MCA-XXXGP M30612MCA-XXXFP M30612MCA-XXXGP M30612E4FP M30612E4GP M30610ECFP M30610ECGP M30610ECFS M30610SAFP M30610SAGP M30612SAFP M30612SAGP 32K byte 128K byte 128K byte 4K byte 10K byte 10K byte 10K byte 4K byte 128K byte 5K byte 96K byte 4K byte 10K byte 64K byte 4K byte 10K byte ROM capacity 32K byte RAM capacity 4K byte 10K byte Package type 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100D0 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A External ROM version EPROM version (Note) One-time PROM version Mask ROM version Apr. 1999 Remarks Note: Do not use the EPROM version for mass production, because it is a tool for program development (for evaluation). 6 Mitsubishi microcomputers Description M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Type No. M30612 M 4 – XXX FP Package type: FP : Package GP : FS : 100P6S-A 100P6Q-A 100D0 ROM No. Omitted for blank one-time PROM version and EPROM version ROM capacity: 4 : 32K bytes 8 : 64K bytes A : 96K bytes C : 128K bytes Memory type: M : Mask ROM version E : EPROM or one-time PROM version S : External ROM version Shows RAM capacity, pin count, etc (The value itself has no specific meaning) M16C/61 Group M16C Family Figure 1.1.5. Type No., memory size, and package 7 Mitsubishi microcomputers M16C / 61 Group Pin Description Pin Description Pin name VCC, VSS CNVSS Signal name Power supply input CNVSS Input I/O type Function Supply 2.7 to 5.5 V to the VCC pin. Supply 0 V to the VSS pin. This pin switches between processor modes. Connect it to the VSS pin when operating in single-chip or memory expansion mode. Connect it to the VCC pin when in microprocessor mode. A “L” on this input resets the microcomputer. These pins are provided for the main clock generating circuit.Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. This pin selects the width of an external data bus. A 16-bit width is selected when this input is “L”; an 8-bit width is selected when this input is “H”. This input must be fixed to either “H” or “L”. When operating in single-chip mode,connect this pin to VSS. This pin is a power supply input for the A-D converter. Connect this pin to VCC. This pin is a power supply input for the A-D converter. Connect this pin to VSS. Input Input/output This pin is a reference voltage input for the A-D converter. This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When used for input in single-chip mode, the port can be set to have or not have a pull-up resistor in units of four bits by software. In memory expansion and microprocessor modes, selection of the internal pull-resistor is not available. When set as a separate bus, these pins input and output data (D0–D7). This is an 8-bit I/O port equivalent to P0. When set as a separate bus, these pins input and output data (D8–D15). This is an 8-bit I/O port equivalent to P0. These pins output 8 low-order address bits (A0–A7). If the external bus is set as an 8-bit wide multiplexed bus, these pins input and output data (D0–D7) and output 8 low-order address bits (A0–A7) separated in time by multiplexing. If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D0–D6) and output address (A1–A7) separated in time by multiplexing. They also output address (A0). This is an 8-bit I/O port equivalent to P0. These pins output 8 middle-order address bits (A8–A15). If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D7) and output address (A8) separated in time by multiplexing. They also output address (A9–A15). This is an 8-bit I/O port equivalent to P0. These pins output CS0–CS3 signals and A16–A19. CS0–CS3 are chip select signals used to specify an access space. A16–A19 are 4 highorder address bits. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER RESET XIN XOUT Reset input Clock input Clock output Input Input Output BYTE External data bus width select input Analog power supply input Analog power supply input Reference voltage input I/O port P0 Input AVCC AVSS VREF P00 to P07 D0 to D7 P10 to P17 D8 to D15 P20 to P27 A0 to A7 A0/D0 to A7/D7 A0, A1/D0 to A7/D6 P30 to P37 A8 to A15 A8/D7, A9 to A15 P40 to P47 CS0 to CS3, A16 to A19 I/O port P4 I/O port P3 I/O port P2 I/O port P1 Input/output Input/output Input/output Input/output Output Input/output Output Input/output Input/output Output Input/output Output Input/output Output Output 8 Mitsubishi microcomputers M16C / 61 Group Pin Description Pin Description Pin name P50 to P57 Signal name I/O port P5 I/O type Input/output Function This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of the same frequency as XCIN as selected by software. Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE signals. WRL and WRH, and BHE and WR can be switched using software control. WRL, WRH, and RD selected With a 16-bit external data bus, data is written to even addresses when the WRL signal is “L” and to the odd addresses when the WRH signal is “L”. Data is read when RD is “L”. WR, BHE, and RD selected Data is written when WR is “L”. Data is read when RD is “L”. Odd addresses are accessed when BHE is “L”. Use this mode when using an 8-bit external data bus. While the input level at the HOLD pin is “L”, the microcomputer is placed in the hold state. While in the hold state, HLDA outputs a “L” level. ALE is used to latch the address. While the input level of the RDY pin is “L”, the microcomputer is in the ready state. This is an 8-bit I/O port equivalent to P0. When used for input in singlechip, memory expansion, and microprocessor modes, the port can be set to have or not have a pull-up resistor in units of four bits by software. Pins in this port also function as UART0 and UART1 I/O pins as selected by software. This is an 8-bit I/O port equivalent to P6 (P70 and P71 are N channel open-drain output). Pins in this port also function as timer A0–A3 or UART2 I/O pins as selected by software. P80 to P84, P86, and P87 are I/O ports with the same functions as P6. Using software, they can be made to function as the I/O pins for timer A4 and the input pins for external interrupts. P86 and P87 can be set using software to function as the I/O pins for a sub clock generation circuit. In this case, connect a quartz oscillator between P86 (XCOUT pin) and P87 (XCIN pin). P85 is an input-only port that also functions for NMI. The NMI interrupt is generated when the input at this pin changes from “H” to “L”. The NMI function cannot be cancelled using software. The pull-up cannot be set for this pin. This is an 8-bit I/O port equivalent to P6. Pins in this port also function as Timer B0–B2 input pins, D-A converter output pins, A-D converter extended input pins, or A-D trigger input pins as selected by software. This is an 8-bit I/O port equivalent to P6. Pins in this port also function as A-D converter input pins. Furthermore, P104–P107 also function as input pins for the key input interrupt function. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER WRL / WR, WRH / BHE, RD, BCLK, HLDA, HOLD, ALE, RDY Output Output Output Output Output Input Output Input P60 to P67 I/O port P6 Input/output P70 to P77 I/O port P7 Input/output P80 to P84, P86, P87, P85 I/O port P8 Input/output Input/output Input/output I/O port P85 Input P90 to P97 I/O port P9 Input/output P100 to P107 I/O port P10 Input/output 9 Mitsubishi microcomputers M16C / 61 Group Memory SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Operation of Functional Blocks The M16C/61 group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC calculation circuit, A-D converter, and I/O ports. The following explains each unit. Memory Figure 1.4.1 is a memory map of the M16C/61 group. The address space extends the 1M bytes from address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30612M4A-XXXFP, there is 32K bytes of internal ROM from F800016 to FFFFF16. The vector table for fixed interrupts such as _______ the reset and NMI are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details. From 0040016 up is RAM. For example, in the M30612M4A-XXXFP, 4K bytes of internal RAM is mapped to the space from 0040016 to 013FF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated. The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes. The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps. In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be used. For example, in the M30612M4A-XXXFP, the following spaces cannot be used. • The space between 0140016 and 03FFF16 • The space between D000016 and F7FFF16 (When external area do not expand in memory expansion mode) Do not expand the external area in single chip mode. A part of internal memory cannot be used depending on MCU. 0000016 SFR area For details, see Figure 1.7.1 and Figure 1.7.2 FFE0016 0040016 Internal RAM area XXXXX16 Internal reserved area (Note 1) Special page vector table 0400016 External area Type No. M30610M8A M30610MAA M30610MCA/EC M30612M4A/E4 M30612M8A M30612MAA M30612MCA Address XXXXX16 Address YYYYY16 02BFF16 02BFF16 02BFF16 013FF16 013FF16 013FF16 017FF16 F000016 E800016 E000016 F800016 F000016 E800016 E000016 FFFDC16 Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer DBC NMI Reset D000016 YYYYY16 Internal reserved area (Note 2) Internal ROM area FFFFF16 FFFFF16 Note 1: During memory expansion and microprocessor modes, can not be used. Note 2: When external area do not expand in memory expansion mode. Figure 1.4.1. Memory map 10 Mitsubishi microcomputers M16C / 61 Group CPU SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Central Processing Unit (CPU) The CPU has a total of 13 registers shown in Figure 1.5.1. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks. b15 b8 b7 b0 R0(Note) H L b15 b8 b7 b0 b19 b0 R1(Note) H L Data registers PC Program counter b15 b0 b19 b0 R2(Note) INTB H L Interrupt table register b0 b15 b0 b15 R3(Note) USP User stack pointer b15 b0 b15 b0 A0(Note) Address registers ISP Interrupt stack pointer b15 b0 b15 b0 A1(Note) SB Static base register b15 b0 b15 b0 FB(Note) Frame base registers FLG Flag register IPL U I OBS Z DC Note: These registers consist of two register banks. Figure 1.5.1. Central processing unit register (1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3) Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0/R3R1). (2) Address registers (A0 and A1) Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). 11 Mitsubishi microcomputers M16C / 61 Group CPU (3) Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (4) Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed. (5) Interrupt table register (INTB) Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) Stack pointer (USP/ISP) Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG). (7) Static base register (SB) Static base register (SB) is configured with 16 bits, and is used for SB relative addressing. (8) Flag register (FLG) Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.5.2 shows the flag register (FLG). The following explains the function of each flag: • Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. • Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to “0” when the interrupt is acknowledged. • Bit 2: Zero flag (Z flag) This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”. • Bit 3: Sign flag (S flag) This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”. • Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”. • Bit 5: Overflow flag (O flag) This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”. • Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0” when the interrupt is acknowledged. 12 Mitsubishi microcomputers M16C / 61 Group CPU SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER • Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this flag is “1”. This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed. • Bits 8 to 11: Reserved area • Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled. • Bit 15: Reserved area The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details. b15 b0 IPL U I OBSZDC Flag register (FLG) Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Figure 1.5.2. Flag register (FLG) 13 Mitsubishi microcomputers M16C / 61 Group Reset Reset There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See “Software Reset” for details of software resets.) This section explains on hardware resets. When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H” level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. Figure 1.6.1 shows the example reset circuit. Figure 1.6.2 shows the reset sequence. 5V 4.0V VCC 0V 5V RESET 0.8V 0V Example when VCC = 5V. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER RESET VCC Figure 1.6.1. Example reset circuit XIN More than 20 cycles are needed Microprocessor mode BYTE = “H” RESET BCLK 24cycles BCLK Content of reset vector Address FFFFC16 FFFFD16 FFFFE16 RD WR CS0 Microprocessor mode BYTE = “L” Address FFFFC16 FFFFE16 Content of reset vector RD WR CS0 Single chip mode Address FFFFC16 FFFFE16 Content of reset vector Figure 1.6.2. Reset sequence 14 Mitsubishi microcomputers M16C / 61 Group Reset ____________ SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.6.1 shows the statuses of the other pins while the RESET pin level is “L”. Figure 1.6.3 shows the internal status of the microcomputer immediately after the reset is cancelled. ____________ Table 1.6.1. Pin status when RESET pin level is “L” Status Pin name P0 P1 P2, P3, P40 to P43 P44 P45 to P47 P50 P51 P52 P53 P54 CNVSS = VCC CNVSS = VSS BYTE = VSS Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Data input (floating) Data input (floating) Address output (undefined) CS0 output (“H” level is output) Input port (floating) WR output (“H” level is output) BHE output (undefined) RD output (“H” level is output) BCLK output BYTE = VCC Data input (floating) Input port (floating) Address output (undefined) CS0 output (“H” level is output) Input port (floating) WR output (“H” level is output) BHE output (undefined) RD output (“H” level is output) BCLK output HLDA output (The output value HLDA output (The output value depends on the input to the depends on the input to the HOLD pin) HOLD pin) HOLD input (floating) ALE output (“L” level is output) RDY input (floating) Input port (floating) HOLD input (floating) ALE output (“L” level is output) RDY input (floating) Input port (floating) P55 P56 P57 Input port (floating) Input port (floating) Input port (floating) P6, P7, P80 to P84, P86, P87, P9, P10 Input port (floating) 15 Mitsubishi microcomputers M16C / 61 Group Reset SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Processor mode register 0 (Note) (2) Processor mode register 1 (3) System clock control register 0 (4) System clock control register 1 (5) Chip select control register (6) Address match interrupt enable register (7) Protect register (8) Watchdog timer control register (9) Address match interrupt register 0 (000416)··· (000516)··· (000616)··· (000716)··· (000816)··· (000916)··· (000A16)··· (000F16)··· (001016)··· (001116)··· (001216)··· 00 0016 0 (43) Timer A0 mode register (44) Timer A1 mode register (45) Timer A2 mode register (46) Timer A3 mode register (47) Timer A4 mode register (48) Timer B0 mode register (49) Timer B1 mode register (50) Timer B2 mode register (51) UART0 transmit/receive mode register (039616)··· (039716)··· (039816)··· (039916)··· (039A16)··· (039B16)··· (039C16)··· (039D16)··· (03A016)··· 00? 00? 00? 0016 0016 0016 0016 0016 0000 0000 0000 0016 00001000 00000010 0016 00001000 00000010 0000000 0016 0016 0000 0 01001000 00100000 00000001 00 000 000????? 0016 0016 0000 0016 0016 0000 00000?00 00000?00 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 00?000 00?000 00?000 0016 00001000 00000010 0016 0 00 00000 0016 0016 (52) UART0 transmit/receive control register 0 (03A416)··· (53) UART0 transmit/receive control register 1 (03A516)··· (54) UART1 transmit/receive mode register (03A816)··· (10) Address match interrupt register 1 (001416)··· (001516)··· (001616)··· (55) UART1 transmit/receive control register 0 (03AC16)··· (56) UART1 transmit/receive control register 1 (03AD16)··· (57) UART transmit/receive control register 2 (58) DMA0 cause select register (59) DMA1 cause select register (60) A-D control register 2 (61) A-D control register 0 (62) A-D control register 1 (63) D-A control register (64) Port P0 direction register (65) Port P1 direction register (66) Port P2 direction register (67) Port P3 direction register (68) Port P4 direction register (69) Port P5 direction register (70) Port P6 direction register (71) Port P7 direction register (72) Port P8 direction register (73) Port P9 direction register (74) Port P10 direction register (75) Pull-up control register 0 (76) Pull-up control register 1 (77) Pull-up control register 2 (78) Data registers (R0/R1/R2/R3) (79) Address registers (A0/A1) (80) Frame base register (FB) (81) Interrupt table register (INTB) (82) User stack pointer (USP) (83) Interrupt stack pointer (ISP) (84) Static base register (SB) (85) Flag register (FLG) x : Nothing is mapped to this bit ? : Undefined (03B016)··· (03B816)··· (03BA16)··· (03D416)··· (03D616)··· (03D716)··· (03DC16)··· (03E216)··· (03E316)··· (03E616)··· (03E716)··· (03EA16)··· (03EB16)··· (03EE16)··· (03EF16)··· (03F216)··· (03F316)··· (03F616)··· (03FC16)··· (03FD16)··· (03FE16)··· (11)DMA0 control register (12) DMA1 control register (13) Bus collision detection interrupt control register (002C16)··· (003C16)··· (004A16)··· (004B16)··· (004C16)··· (004D16)··· (004E16)··· (004F16)··· (005016)··· (005116)··· (005216)··· (005316)··· (005416)··· (005516)··· (005616)··· (005716)··· (005816)··· (005916)··· (005A16)··· (005B16)··· (005C16)··· (005D16)··· (005E16)··· (005F16)··· (037816)··· (037C16)··· (037D16)··· (038016)··· (038116)··· (038216)··· (038316)··· (038416)··· (14) DMA0 interrupt control register (15) DMA1 interrupt control register (16) Key input interrupt control register (17) A-D conversion interrupt control register (18) UART2 transmit interrupt control register (19)UART2 receive interrupt control register (20) UART0 transmit interrupt control register (21)UART0 receive interrupt control register (22) UART1 transmit interrupt control register (23)UART1 receive interrupt control register (24) Timer A0 interrupt control register (25) Timer A1 interrupt control register (26) Timer A2 interrupt control register (27) Timer A3 interrupt control register (28) Timer A4 interrupt control register (29) Timer B0 interrupt control register (30) Timer B1 interrupt control register (31) Timer B2 interrupt control register (32) INT0 interrupt control register (33) INT1 interrupt control register (34) INT2 interrupt control register (35) UART2 transmit/receive mode register (36) UART2 transmit/receive control register 0 (37) UART2 transmit/receive control register 1 (38) Count start flag (39) Clock prescaler reset flag (40) One-shot start flag (41) Trigger select flag (42) Up-down flag 00000??? 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 00 00000 0016 0016 0016 0016 0016 000016 000016 000016 0000016 000016 000016 000016 000016 The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. Note: When the VCC level is applied to the CNVSS pin, it is 0316 at a reset. Figure 1.6.3. Device's internal status after a reset is cleared 16 Mitsubishi microcomputers SFR M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 004016 004116 004216 004316 Processor mode register 0 (PM0) Processor mode register 1(PM1) System clock control register 0 (CM0) System clock control register 1 (CM1) Chip select control register (CSR) Address match interrupt enable register (AIER) Protect register (PRCR) 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 Bus collision detection interrupt control register (BCNIC) Watchdog timer start register (WDTS) Watchdog timer control register (WDC) Address match interrupt register 0 (RMAD0) 004E16 004F16 005016 005116 005216 005316 005416 DMA0 interrupt control register (DM0IC) DMA1 interrupt control register (DM1IC) Key input interrupt control register (KUPIC) A-D conversion interrupt control register (ADIC) UART2 UART2 UART0 UART0 UART1 UART1 transmit interrupt control register (S2TIC) receive interrupt control register (S2RIC) transmit interrupt control register (S0TIC) receive interrupt control register (S0RIC) transmit interrupt control register (S1TIC) receive interrupt control register (S1RIC) Address match interrupt register 1 (RMAD1) 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 Timer A0 interrupt control register (TA0IC) Timer A1 interrupt control register (TA1IC) Timer A2 interrupt control register (TA2IC) Timer A3 interrupt control register (TA3IC) Timer A4 interrupt control register (TA4IC) Timer B0 interrupt control register (TB0IC) Timer B1 interrupt control register (TB1IC) Timer B2 interrupt control register (TB2IC) INT0 interrupt control register (INT0IC) INT1 interrupt control register (INT1IC) INT2 interrupt control register (INT2IC) DMA0 source pointer (SAR0) 036316 036416 DMA0 destination pointer (DAR0) 036516 036616 036716 036816 036916 036A16 036B16 DMA0 transfer counter (TCR0) DMA0 control register (DM0CON) 036C16 036D16 036E16 036F16 037016 DMA1 source pointer (SAR1) 037116 037216 037316 037416 DMA1 destination pointer (DAR1) 037516 037616 037716 037816 037916 037A16 037B16 DMA1 transfer counter (TCR1) UART2 transmit/receive mode register (U2MR) UART2 bit rate generator (U2BRG) UART2 transmit buffer register (U2TB) UART2 transmit/receive control register 0 (U2C0) UART2 transmit/receive control register 1 (U2C1) UART2 receive buffer register (U2RB) DMA1 control register (DM1CON) 037C16 037D16 037E16 037F16 Figure 1.7.1. Location of peripheral unit control registers 17 Mitsubishi microcomputers M16C / 61 Group SFR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 Count start flag (TABSR) Clock prescaler reset flag (CPSRF) One-shot start flag (ONSF) Trigger select register (TRGSR) Up-down flag (UDF) Timer A0 (TA0) Timer A1 (TA1) Timer A2 (TA2) Timer A3 (TA3) Timer A4 (TA4) Timer B0 (TB0) Timer B1 (TB1) Timer B2 (TB2) Timer A0 mode register (TA0MR) Timer A1 mode register (TA1MR) Timer A2 mode register (TA2MR) Timer A3 mode register (TA3MR) Timer A4 mode register (TA4MR) Timer B0 mode register (TB0MR) Timer B1 mode register (TB1MR) Timer B2 mode register (TB2MR) 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 A-D register 0 (AD0) A-D register 1 (AD1) A-D register 2 (AD2) A-D register 3 (AD3) A-D register 4 (AD4) A-D register 5 (AD5) A-D register 6 (AD6) A-D register 7 (AD7) A-D control register 2 (ADCON2) A-D control register 0 (ADCON0) A-D control register 1 (ADCON1) D-A register 0 (DA0) D-A register 1 (DA1) D-A control register (DACON) UART0 transmit/receive mode register (U0MR) 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 UART0 bit rate generator (U0BRG) UART0 transmit buffer register (U0TB) UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1) UART0 receive buffer register (U0RB) UART1 transmit/receive mode register (U1MR) UART1 bit rate generator (U1BRG) UART1 transmit buffer register (U1TB) UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1) UART1 receive buffer register (U1RB) UART transmit/receive control register 2 (UCON) Port P0 (P0) Port P1 (P1) Port P0 direction register (PD0) Port P1 direction register (PD1) Port P2 (P2) Port P3 (P3) Port P2 direction register (PD2) Port P3 direction register (PD3) Port P4 (P4) Port P5 (P5) Port P4 direction register (PD4) Port P5 direction register (PD5) Port P6 (P6) Port P7 (P7) Port P6 direction register (PD6) Port P7 direction register (PD7) Port P8 (P8) Port P9 (P9) Port P8 direction register (PD8) Port P9 direction register (PD9) Port P10 (P10) Port P10 direction register (PD10) DMA0 cause select register (DM0SL) DMA1 cause select register (DM1SL) CRC data register (CRCD) CRC input register (CRCIN) 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Pull-up control register 2 (PUR2) Figure 1.7.2. Location of peripheral unit control registers 18 Mitsubishi microcomputers M16C / 61 Group Software Reset Software Reset Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal RAM are preserved. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Processor Mode (1) Types of Processor Mode One of three processor modes can be selected: single-chip mode, memory expansion mode, and microprocessor mode. The functions of some pins, the memory map, and the access space differ according to the selected processor mode. • Single-chip mode In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be accessed. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal peripheral functions. • Memory expansion mode In memory expansion mode, external memory can be accessed in addition to the internal memory space (SFR, internal RAM, and internal ROM). In this mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus and register settings. (See “Bus Settings” for details.) • Microprocessor mode In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The internal ROM area cannot be accessed. In this mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus and register settings. (See “Bus Settings” for details.) (2) Setting Processor Modes The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address 000416). Do not set the processor mode bits to “102”. Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore, never change the processor mode bits when changing the contents of other bits. Also do not attempt to shift to or from the microprocessor mode within the program stored in the internal ROM area. • Applying VSS to CNVSS pin The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode is selected by writing “012” to the processor mode is selected bits. • Applying VCC to CNVSS pin The microcomputer starts to operate in microprocessor mode after being reset. Figure 1.8.1 shows the processor mode register 0 and 1. Figure 1.9.1 shows the memory maps applicable for each of the modes. 19 Mitsubishi microcomputers M16C / 61 Group Processor Mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Processor mode register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PM0 Address 000416 When reset 0016 (Note 2) Bit symbol PM00 PM01 PM02 PM03 Bit name Processor mode bit b1 b0 Function 0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Inhibited 1 1: Microprocessor mode 0 : RD,BHE,WR 1 : RD,WRH,WRL The device is reset when this bit is set to “1”. The value of this bit is “0” when read. b5 b4 RW R/W mode select bit Software reset bit PM04 PM05 PM06 Multiplexed bus space select bit 0 0 : Multiplexed bus is not used 0 1 : Allocated to CS2 space 1 0 : Allocated to CS1 space 1 1 : Allocated to entire space (Note4) Port P40 to P43 function select bit (Note 3) BCLK output disable bit 0 : Address output 1 : Port function (Address is not output) 0 : BCLK is output 1 : BCLK is not output (Pin is left floating) PM07 Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register. Note 2: If the VCC voltage is applied to the CNVSS, the value of this register when reset is 0316. (PM00 and PM01 both are set to “1”.) Note 3: Valid in microprocessor and memory expansion modes. Note 4: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width.The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. Processor mode register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 00 0 0 Symbol PM1 Address 000516 When reset 00XXXXX02 Bit symbol Reserved bit Bit name Function Must always be set to “0” RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Reserved bit PM16 Must always be set to “0” External memory area expansion bit (Note 2) Wait bit 0 : Do not expand 1 : Expand 0 : No wait state 1 : Wait state inserted PM17 Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register. Note 2: When this bit is set to “1” in memory expansion mode, M30612M4A/E4 provides the means of using part of internal reserved area as an external area. Set this bit to “0” except M30612M4A/E4. Set this bit to “0” in single chip mode. Figure 1.8.1. Processor mode register 0 and 1 20 Mitsubishi microcomputers M16C / 61 Group Processor Mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Single-chip mode 0000016 Memory expansion mode SFR area Internal RAM area Internally reserved area Microprocessor mode SFR area Internal RAM area Internally reserved area SFR area 0040016 Internal RAM area XXXXX16 0400016 Inhibited D000016 YYYYY16 External area Internally reserved area (Note 1) External area Internal ROM area (Note 2) FFFFF16 Internal ROM area Type No. M30610M8A M30610MAA M30610MCA/EC M30612M4A/E4 M30612M8A M30612MAA M30612MCA Address XXXXX16 02BFF16 02BFF16 02BFF16 013FF16 013FF16 013FF16 017FF16 Address YYYYY16 F000016 E800016 E000016 F800016 F000016 E800016 E000016 External area : Accessing this area allows the user to access a device connected externally to the microcomputer. Note 1: This area becomes external area when PM16 (external memory area expansion bit ) = “1” in M30612M4A/E4. Set “0” except M30612M4A/E4. Note 2: Set “0” to PM16 (external memory area expansion bit) in single chip mode. Figure 1.9.1. Memory maps in each processor mode 21 Mitsubishi microcomputers M16C / 61 Group Bus Settings Bus Settings The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 000416) are used to change the bus settings. Table 1.10.1 shows the factors used to change the bus settings. Table 1.10.1. Factors for switching bus settings Bus setting Switching factor Switching external address bus width Bit 6 of processor mode register 0 Switching external data bus width BYTE pin Switching between separate and multiplex bus Bits 4 and 5 of processor mode register 0 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Selecting external address bus width The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K bytes address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register 0 is set to “1”, the external address bus width is set to 16 bits, and P2 and P3 become part of the address bus. P40 to P43 can be used as programmable I/O ports. When bit 6 of processor mode register 0 is set to “0”, the external address bus width is set to 20 bits, and P2, P3, and P40 to P43 become part of the address bus. (2) Selecting external data bus width The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can be set.) When the BYTE pin is “L”, the bus width is set to 16 bits; when “H”, it is set to 8 bits. (The internal bus width is permanently set to 16 bits.) While operating, fix the BYTE pin either to “H” or to “L”. (3) Selecting separate/multiplex bus The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0. • Separate bus In this mode, the data and address are input and output separately. The data bus can be set using the BYTE pin to be 8 or 16 bits. When the BYTE pin is “H”, the data bus is set to 8 bits and P0 functions as the data bus and P1 as a programmable I/O port. When the BYTE pin is “L”, the data bus is set to 16 bits and P0 and P1 are both used for the data bus. When the separate bus is used for access, a software wait can be selected. • Multiplex bus In this mode, data and address I/O are time multiplexed. With an 8-bit data bus selected (BYTE pin = “H”), the 8 bits from D0 to D7 are multiplexed with A0 to A7. With a 16-bit data bus selected (BYTE pin = “L”), the 8 bits from D0 to D7 are multiplexed with A1 to A8. D8 to D15 are not multiplexed. In this case, the external devices connected to the multiplexed bus are mapped to the microcomputer’s even addresses (every 2nd address). To access these external devices, access the even addresses as bytes. The ALE signal latches the address. It is output from P56. Before using the multiplex bus for access, be sure to insert a software wait. If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width. The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. 22 Mitsubishi microcomputers M16C / 61 Group Bus Settings Table 1.10.2. Pin functions for each processor mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Processor mode Single-chip mode Memory expansion mode/microprocessor modes “01”, “10” “00” (separate bus) 8 bits “H” Data bus I/O port Address bus Address bus Address bus Address bus /O port 16 bits “L” Data bus Data bus Address bus Address bus Address bus Address bus I/O port Memory expansion mode Multiplexed bus space select bit Either CS1 or CS2 is for multiplexed bus and others are for separate bus 8 bits “H” I/O port I/O port I/O port I/O port I/O port I/O port I/O port Data bus I/O port 16 bits “L” Data bus Data bus “11” (Note 1) multiplexed bus for the entire space 8 bit “H” I/O port I/O port Address bus /data bus Address bus /data bus A8/D7 I/O port I/O port Data bus width BYTE pin level P00 to P07 P10 to P17 P20 P21 to P27 P30 P31 to P37 P40 to P43 Port P40 to P43 function select bit = 1 P40 to P43 Port P40 to P43 function select bit = 0 P44 to P47 P50 to P53 P54 P55 P56 P57 Address bus Address bus /data bus(Note 2) Address bus /data bus(Note 2) Address bus /data bus(Note 2) Address bus Address bus /data bus(Note 2) Address bus I/O port Address bus I/O port I/O port Address bus Address bus Address bus Address bus I/O port I/O port I/O port I/O port I/O port I/O port I/O port CS (chip select) or programmable I/O port (For details, refer to “Bus control”) Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK (For details, refer to “Bus control”) HLDA HOLD ALE RDY HLDA HOLD ALE RDY HLDA HOLD ALE RDY HLDA HOLD ALE RDY HLDA HOLD ALE RDY Note 1: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width. The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. Note 2: Address bus when in separate bus mode. 23 Mitsubishi microcomputers M16C / 61 Group Bus Control Bus Control The following explains the signals required for accessing external devices and software waits. The signals required for accessing the external devices are valid when the processor mode is set to memory expansion mode and microprocessor mode. The software waits are valid in all processor modes. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Address bus/data bus The address bus consists of the 20 pins A0 to A19 for accessing the 1M bytes of address space. The data bus consists of the pins for data I/O. When the BYTE pin is “H”, the 8 ports D0 to D7 function as the data bus. When BYTE is “L”, the 16 ports D0 to D15 function as the data bus. Both the address and data bus retain their previous states when internal ROM or RAM is accessed. Also, when a change is made from single-chip mode to memory expansion mode, the value of the address bus is undefined until external memory is accessed. (2) Chip select signal The chip select signal is output using the same pins as P44 to P47. Bits 0 to 3 of the chip select control register (address 000816) set each pin to function as a port or to output the chip select signal. The chip select control register is valid in memory expansion mode and microprocessor mode. In single-chip mode, P44 to P47 function as programmable I/O ports regardless of the value in the chip select control register. _______ In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been cancelled. _______ _______ _______ _______ CS1 to CS3 function as input ports. Therefore, when using CS1 to CS3, external pull-up resistors are required. Figure 1.11.1 shows the chip select control register. The chip select signal can be used to split the external area into as many as four blocks. Table 1.11.1 shows the external memory areas specified using the chip select signal. Table 1.11.1. External areas specified by the chip select signals Chip select CS0 CS1 CS2 CS3 Specified address range Memory expansion mode Microprocessor mode 3000016 to CFFFF16 (640K) 3000016 to FFFFF16 (832K) 3000016 to F7FFF16 (800K) (Note) 2800016 to 2FFFF16 (32K) 2800016 to 2FFFF16 (32K) 0800016 to 27FFF16 (128K) 0800016 to 27FFF16 (128K) (16K) 0400016 to 07FFF16 0400016 to 07FFF16 (16K) Note: When PM16 (External memory area expansion bit) = “1”. (Only M30612M4A/E4 is valid.) Chip select control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol CSR Address 000816 When reset 0116 Bit symbol CS0 CS1 CS2 CS3 CS0W CS1W CS2W CS3W Bit name CS0 output enable bit CS1 output enable bit CS2 output enable bit CS3 output enable bit CS0 wait bit CS1 wait bit CS2 wait bit CS3 wait bit Function 0 : Chip select output disabled (Normal port pin) 1 : Chip select output enabled RW 0 : Wait state inserted 1 : No wait state Figure 1.11.1. Chip select control register 24 Mitsubishi microcomputers M16C / 61 Group Bus Control (3) Read/write signals With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select the _____ ________ ______ _____ ________ _________ combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE _____ ______ _______ pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0 (address 000416) to “0”.) Tables 1.11.2 and 1.11.3 show the operation of these signals. _____ ______ ________ After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected. _____ _________ _________ When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the processor mode register 0 (address 000416) has been set (Note). Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000A16) to “1”. _____ ________ _________ SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.11.2. Operation of RD, WRL, and WRH signals Data bus width 16-bit (BYTE = “L”) RD L H H H WRL H L H L WRH H H L L Status of external data bus Read data Write 1 byte of data to even address Write 1 byte of data to odd address Write data to both even and odd addresses _____ ______ ________ Table 1.11.3. Operation of RD, WR, and BHE signals Data bus width RD H L H L H L H L WR L H L H L H L H BHE L L H H L L Not used Not used A0 H H L L L L H/L H/L Status of external data bus Write 1 byte of data to odd address Read 1 byte of data from odd address Write 1 byte of data to even address Read 1 byte of data from even address Write data to both even and odd addresses Read data from both even and odd addresses Write 1 byte of data Read 1 byte of data 16-bit (BYTE = “L”) 8-bit (BYTE = “H”) (4) ALE signal The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the ALE signal falls. When BYTE pin = “H” ALE D0/A0 to D7/A7 A8 to A19 Address Data (Note 1) When BYTE pin = “L” ALE A0 D0/A1 to D7/A8 Address Address Data (Note 1) Address Address (Note 2) A9 to A19 Note 1: Floating when reading. Note 2: When multiplexed bus for the entire space is selected, these are I/O ports. Figure 1.11.2. ALE signal and address/data bus 25 Mitsubishi microcomputers M16C / 61 Group Bus Control ________ SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (5) The RDY signal ________ RDY is a signal that facilitates access to an external device that requires long access time. As shown in ________ Figure 1.11.3, if an “L” is being input to the RDY at the BCLK falling edge, the bus turns to the wait state. ________ If an “H” is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table 1.11.4 shows the state of the microcomputer with the bus in the wait state, and Figure 1.11.3 shows an ____ ________ example in which the RD signal is prolonged by the RDY signal. ________ The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the ________ chip select control register (address 000816) are set to “0”. The RDY signal is invalid when setting “1” to all ________ bits 4 to 7 of the chip select control register (address 000816), but the RDY pin should be treated as properly as in non-using. Table 1.11.4. Microcomputer status in ready state (Note) Item Oscillation ___ _____ Status On ________ R/W signal, address bus, data bus, CS __________ ALE signal, HLDA, programmable I/O ports Internal peripheral circuits ________ Maintain status when RDY signal received On Note: The RDY signal cannot be received immediately prior to a software wait. In an instance of separate bus BCLK RD CSi (i=0 to 3) RDY tsu(RDY - BCLK) Accept timing of RDY signal In an instance of multiplexed bus BCLK RD CSi (i=0 to 3) RDY tsu(RDY - BCLK) : Wait using RDY signal : Wait using software _____ Accept timing of RDY signal ________ Figure 1.11.3. Example of RD signal extended by RDY signal 26 Mitsubishi microcomputers M16C / 61 Group Bus Control (6) Hold signal The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to __________ the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status __________ __________ is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table 1.11.5 shows the microcomputer status in the hold state. __________ Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence. __________ SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER HOLD > DMAC > CPU Figure 1.11.4. Bus-using priorities Table 1.11.5. Microcomputer status in hold state Item Oscillation ___ _____ _______ Status ON Floating Floating Maintains status when hold signal is received Output “L” ON (but watchdog timer stops) Undefined R/W signal, address bus, data bus, CS, BHE Programmable I/O ports P0, P1, P2, P3, P4, P5 P6, P7, P8, P9, P10 __________ HLDA Internal peripheral circuits ALE signal (7) External bus status when the internal area is accessed Table 1.11.6 shows the external bus status when the internal area is accessed. Table 1.11.6. External bus status when the internal area is accessed Item Address bus SFR accessed Address output Internal ROM/RAM accessed Maintain status before accessed address of external area Data bus When read When write RD, WR, WRL, WRH BHE Floating Output data RD, WR, WRL, WRH output BHE output Floating Undefined Output "H" Maintain status before accessed status of external area CS ALE Output "H" Output "L" Output "H" Output "L" 27 Mitsubishi microcomputers M16C / 61 Group Bus Control (8) BCLK output The user can choose the BCLK output by use of bit 7 of processor mode register 0 (000416) (Note). When set to “1”, the output floating. Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000A16) to “1”. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (9) Software wait A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 000516) (Note) and bits 4 to 7 of the chip select control register (address 000816). A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle. When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been reset, this bit defaults to “0”. When set to “1”, a wait is applied to all memory areas (two or three BCLK cycles), regardless of the contents of bits 4 to 7 of the chip select control register. Set this bit after referring to the recommended operating conditions (main clock input oscillation frequency) of the electric character________ istics. However, when the user is using the RDY signal, the relevant bit in the chip select control register’s bits 4 to 7 must be set to “0”. When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register _______ _______ correspond to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed in one BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits default to “0” after the microcomputer has been reset. The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also, insert a software wait if using the multiplex bus to access the external memory area. Table 1.11.7 shows the software wait and bus cycles. Figure 1.11.5 shows example bus timing when using software waits. Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000A16) to “1”. Table 1.11.7. Software waits and bus cycles Area SFR Internal ROM/RAM Separate bus Separate bus External memory area Separate bus Multiplex bus Multiplex bus Bus status Wait bit Invalid 0 1 0 0 1 0 1 Bits 4 to 7 of chip select control register Invalid Invalid Invalid 1 0 0 (Note) 0 0 (Note) Bus cycle 2 BCLK cycles 1 BCLK cycle 2 BCLK cycles 1 BCLK cycle 2 BCLK cycles 2 BCLK cycles 3 BCLK cycles 3 BCLK cycles Note: When using the RDY signal, always set to “0”. 28 Mitsubishi microcomputers M16C / 61 Group Bus Control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER < Separate bus (no wait) > Bus cycle BCLK Write signal Read signal Output Input Data bus Address bus Chip select Address Address < Separate bus (with wait) > Bus cycle BCLK Write signal Read signal Output Input Data bus Address bus Chip select Address Address < Multiplexed bus > Bus cycle BCLK Write signal Read signal ALE Address bus Address bus/ Data bus Chip select Address Address Data output Address Address Input Figure 1.11.5. Typical bus timings using software wait 29 Mitsubishi microcomputers M16C / 61 Group Clock Generating Circuit Clock Generating Circuit The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units. Table 1.12.1. Main clock and sub-clock generating circuits Use of clock Main clock generating circuit Sub-clock generating circuit • CPU’s operating clock source • CPU’s operating clock source • Internal peripheral units’ • Timer A/B’s count clock operating clock source source Ceramic or crystal oscillator Crystal oscillator XIN, XOUT XCIN, XCOUT Available Available Oscillating Stopped Externally derived clock can be input SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Usable oscillator Pins to connect oscillator Oscillation stop/restart function Oscillator status immediately after reset Other Example of oscillator circuit Figure 1.12.1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Figure 1.12.2 shows some examples of sub-clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Circuit constants in Figures 1.12.1 and 1.12.2 vary with each oscillator used. Use the values recommended by the manufacturer of your oscillator. Microcomputer (Built-in feedback resistor) Microcomputer (Built-in feedback resistor) XIN XOUT (Note) Rd XIN XOUT Open Externally derived clock CIN COUT Vcc Vss Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN and XOUT following the instruction. Figure 1.12.1. Examples of main clock Microcomputer (Built-in feedback resistor) Microcomputer (Built-in feedback resistor) XCIN XCOUT (Note) RCd XCIN XCOUT Open Externally derived clock CCIN CCOUT Vcc Vss Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN and XCOUT following the instruction. Figure 1.12.2. Examples of sub-clock 30 Mitsubishi microcomputers Clock Generating Circuit Clock Control M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.12.3 shows the block diagram of the clock generating circuit. XCIN CM04 XCOUT 1/32 fC32 f1 f1SIO2 fC fAD f8 f32 f8SIO2 f32SIO2 Sub clock CM10 “1” Write signal SQ XIN R RESET Software reset NMI Interrupt request level judgment output WAIT instruction CM05 Main clock CM02 XOUT b a c d Divider CM07=0 fC CM07=1 BCLK SQ R b a 1/2 1/2 1/2 1/2 1/2 c CM06=0 CM17,CM16=11 CM06=1 CM06=0 CM17,CM16=10 d CM06=0 CM17,CM16=01 CM06=0 CM17,CM16=00 CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 WDCi : Bit i at address 000F16 Details of divider Figure 1.12.3. Clock generating circuit 31 Mitsubishi microcomputers M16C / 61 Group Clock Generating Circuit SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The following paragraphs describes the clocks generated by the clock generating circuit. (1) Main clock The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (2) Sub-clock The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset. After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub-clock can be selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the sub-clock oscillation has fully stabilized before switching. After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting to stop mode and at a reset. (3) BCLK The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal can be output from BCLK pin by the BCLK output disable bit (bit 7 at address 000416) in the memory expansion and the microprocessor modes. The main clock division select bit 0(bit 6 at address 000616) changes to “1” when shifting from highspeed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (4) Peripheral function clock(f1, f8, f32, f1SIO2, f8SIO2,f32SIO2,fAD) The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction. (5) fC32 This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts. (6) fC This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer. 32 Mitsubishi microcomputers Clock Generating Circuit Figure 1.12.4 shows the system clock control registers 0 and 1. M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER System clock control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol CM0 Bit symbol CM00 CM01 CM02 CM03 CM04 CM05 CM06 CM07 Address 000616 Bit name Clock output function select bit (Valid only in single-chip mode) WAIT peripheral function clock stop bit XCIN-XCOUT drive capacity select bit (Note 2) Port XC select bit Main clock (XIN-XOUT) stop bit (Note 3, 4, 5) Main clock division select bit 0 (Note 7) System clock select bit (Note 6) When reset 4816 Function b1 b0 RW 0 0 : I/O port P57 0 1 : fC output 1 0 : f8 output 1 1 : f32 output 0 : Do not stop peripheral function clock in wait mode 1 : Stop peripheral function clock in wait mode (Note 8) 0 : LOW 1 : HIGH 0 : I/O port 1 : XCIN-XCOUT generation 0 : On 1 : Off 0 : CM16 and CM17 valid 1 : Division by 8 mode 0 : XIN, XOUT 1 : XCIN, XCOUT Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register. Note 2: Changes to “1” when shiffing to stop mode and at a reset. Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop mode and operating with XIN, set this bit to “0”. When main clock oscillation is operating by itself, set system clock select bit (CM07) to “1” before setting this bit to “1”. Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. Note 5: If this bit is set to “1”, XOUT turns “H”. The built-in feedback resistor remains being connected, so XIN turns pulled up to XOUT (“H”) via the feedback resistor. Note 6: Set port Xc select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting to this bit from “0” to “1”. Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the main clock oscillating before setting this bit from “1” to “0”. Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 8: fC32 is not included. System clock control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 00 0 0 Symbol CM1 Bit symbol CM10 Address 000716 Bit name All clock stop control bit (Note4) When reset 2016 Function 0 : Clock on 1 : All clocks off (stop mode) Always set to “0” Always set to “0” Always set to “0” Always set to “0” 0 : LOW 1 : HIGH b7 b6 RW Reserved bit Reserved bit Reserved bit Reserved bit CM15 CM16 CM17 XIN-XOUT drive capacity select bit (Note 2) Main clock division select bit 1 (Note 3) 0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register. Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”. If “1”, division mode is fixed at 8. Note 4: If this bit is set to “1”, XOUT turns “H”, and the built-in feedback resistor is cut off. XCIN and XCOUT turn highimpedance state. Figure 1.12.4. Clock control registers 0 and 1 33 Mitsubishi microcomputers M16C / 61 Group Clock Generating Circuit Clock Output In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32, or fC to be output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address 000616) is set to “1”, the output of f8 and f32 stops when a WAIT instruction is executed. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Stop Mode Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V. Because the oscillation, BCLK, f1 to f32, f1SIO2 to f32SIO2, fC, fC32, and fAD stops in stop mode, peripheral functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2) functions provided an external clock is selected. Table 1.12.2 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division select bit 0 (bit 6 at address 000616) is set to “1”. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Table 1.12.2. Port status during stop mode Pin _______ _______ Memory expansion mode Microprocessor mode Retains status before stop mode “H” Single-chip mode Address bus, data bus, CS0 to CS3 _____ ______ ________ ________ _________ RD, WR, BHE, WRL, WRH __________ HLDA, BCLK ALE Port CLKOUT When fC selected When f8, f32 selected “H” “H” Retains status before stop mode Retains status before stop mode Valid only in single-chip mode “H” Valid only in single-chip mode Retains status before stop mode 34 Mitsubishi microcomputers Wait Mode Wait Mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER When a WAIT instruction is executed, BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. Table 1.12.3 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, the microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the WAIT instruction was executed. Table 1.12.3. Port status during wait mode Pin _______ _______ Memory expansion mode Microprocessor mode Retains status before wait mode “H” Single-chip mode Address bus, data bus, CS0 to CS3 _____ ______ ________ ________ _________ RD, WR, BHE, WRL, WRH __________ HLDA,BCLK ALE Port CLKOUT “H” “H” Retains status before wait mode When fC selected Valid only in single-chip mode When f8, f32 selected Valid only in single-chip mode Retains status before wait mode Does not stop Does not stop when the WAIT peripheral function clock stop bit is “0”. When the WAIT peripheral function clock stop bit is “1”, the status immediately prior to entering wait mode is maintained. 35 Mitsubishi microcomputers M16C / 61 Group Status Transition Of BCLK Status Transition Of BCLK Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 1.13.4 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address 000616) changes to “1” when shifting from high-speed/medium-speed to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. The following shows the operational modes of BCLK. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Division by 2 mode The main clock is divided by 2 to obtain the BCLK. (2) Division by 4 mode The main clock is divided by 4 to obtain the BCLK. (3) Division by 8 mode The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption mode, make sure the sub-clock is oscillating stably. (4) Division by 16 mode The main clock is divided by 16 to obtain the BCLK. (5) No-division mode The main clock is divided by 1 to obtain the BCLK. (6) Low-speed mode fC is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the subclock starts. Therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (7) Low power dissipation mode fC is the BCLK and the main clock is stopped. Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Allow a wait time in software for the oscillation to stabilize before switching over the clock. Table 1.12.4. Operating modes dictated by settings of system clock control registers 0 and 1 CM17 CM16 CM07 CM06 CM05 CM04 Operating mode of BCLK 0 1 Invalid 1 0 Invalid Invalid 1 0 Invalid 1 0 Invalid Invalid 0 0 0 0 0 1 1 0 0 1 0 0 Invalid Invalid 0 0 0 0 0 0 1 Invalid Invalid Invalid Invalid Invalid 1 1 Division by 2 mode Division by 4 mode Division by 8 mode Division by 16 mode No-division mode Low-speed mode Low power dissipation mode 36 Mitsubishi microcomputers Power control Power control M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The following is a description of the three available power control modes: Modes Power control is available in three modes. (a) Normal operation mode • High-speed mode Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal clock selected. Each peripheral function operates according to its assigned clock. • Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK. The CPU operates according to the internal clock selected. Each peripheral function operates according to its assigned clock. • Low-speed mode fC becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the secondary clock. Each peripheral function operates according to its assigned clock. • Low power consumption mode The main clock operating in low-speed mode is stopped. The CPU operates according to the fC clock. The fC clock is supplied by the secondary clock. The only peripheral functions that operate are those with the sub-clock selected as the count source. (b) Wait mode The CPU operation is stopped. The oscillators do not stop. (c) Stop mode All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three modes listed here, is the most effective in decreasing power consumption. Figure 1.12.5 is the state transition diagram of the above modes. 37 Mitsubishi microcomputers M16C / 61 Group Power control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Transition of stop mode, wait mode Reset All oscillators stopped WAIT instruction Interrupt WAIT instruction Interrupt WAIT instruction Interrupt CPU operation stopped Stop mode All oscillators stopped CM10 = “1” Interrupt Interrupt CM10 = “1” Medium-speed mode (divided-by-8 mode) Wait mode CPU operation stopped Stop mode All oscillators stopped High-speed/mediumspeed mode Wait mode CPU operation stopped Stop mode CM10 = “1” Interrupt Low-speed/low power dissipation mode Wait mode Normal mode (Refer to the following for the transition of normal mode.) Transition of normal mode Main clock is oscillating Sub clock is stopped Medium-speed mode (divided-by-8 mode) CM06 = “1” BCLK : f(XIN)/8 CM07 = “0” CM06 = “1” CM04 = “1” (Notes 1, 3) CM07 = “0” (Note 1) CM06 = “1” CM04 = “0” Main clock is oscillating CM04 = “0” Sub clock is oscillating High-speed mode BCLK : f(XIN) CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “0” Medium-speed mode (divided-by-2 mode) BCLK : f(XIN)/2 CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “1” Medium-speed mode (divided-by-8 mode) BCLK : f(XIN)/8 CM07 = “0” CM06 = “1” Main clock is oscillating Sub clock is oscillating Low-speed mode CM07 = “0” (Note 1, 3) BCLK : f(XCIN) CM07 = “1” CM07 = “1” (Note 2) Medium-speed mode (divided-by-4 mode) BCLK : f(XIN)/4 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “0” Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/16 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “1” CM05 = “0” CM04 = “0” CM05 = “1” Main clock is oscillating Sub clock is stopped CM04 = “1” High-speed mode BCLK : f(XIN) CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “0” CM06 = “0” (Notes 1,3) Medium-speed mode (divided-by-2 mode) BCLK : f(XIN)/2 CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “1” Main clock is stopped Sub clock is oscillating Low power dissipation mode CM07 = “1” (Note 2) CM05 = “1” BCLK : f(XCIN) CM07 = “1” CM07 = “0” (Note 1) CM06 = “0” (Note 3) CM04 = “1” Medium-speed mode (divided-by-4 mode) BCLK : f(XIN)/4 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “0” Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/16 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “1” Note 1: Switch clock after oscillation of main clock is sufficiently stable. Note 2: Switch clock after oscillation of sub clock is sufficiently stable. Note 3: Change CM06 after changing CM17 and CM16. Note 4: Transit in accordance with arrow. Figure 1.12.5. State transition diagram of Power control mode 38 Mitsubishi microcomputers Protection Protection M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.12.6 shows the protect register. The values in the processor mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716) and port P9 direction register (address 03F316) can only be changed when the respective bit in the protect register is set to “1”. Therefore, important outputs can be allocated to port P9. If, after “1” (write-enabled) has been written to the port P9 direction register write-enable bit (bit 2 at address 000A16), a value is written to any address, the bit automatically reverts to “0” (write-inhibited). However, the system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written to an address. The program must therefore be written to return these bits to “0”. Protect register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PRCR Bit symbol PRC0 Address 000A16 Bit name When reset XXXXX0002 Function RW Enables writing to system clock control registers 0 and 1 (addresses 0 : Write-inhibited 1 : Write-enabled 000616 and 000716) Enables writing to processor mode 0 : Write-inhibited registers 0 and 1 (addresses 000416 1 : Write-enabled and 000516) Enables writing to port P9 direction register (address 03F316) (Note) 0 : Write-inhibited 1 : Write-enabled PRC1 PRC2 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note: Writing a value to an address after “1” is written to this bit returns the bit to “0” . Other bits do not automatically return to “0” and they must therefore be reset by the program. Figure 1.12.6. Protect register 39 Mitsubishi microcomputers M16C / 61 Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Overview of Interrupt Type of Interrupts Figure 1.13.1 lists the types of interrupts. Software Interrupt Special Hardware Peripheral I/O (Note) Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system. Figure 1.13.1. Classification of interrupts • Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level. • Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level. 40                  Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Reset NMI ________ DBC Watchdog timer Single step Address matched _______          Mitsubishi microcomputers Interrupt M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. • Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction. • Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to “1”. The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB • BRK interrupt A BRK interrupt occurs when executing the BRK instruction. • INT interrupt An INT interrupt occurs when assiging one of software interrupt numbers 0 through 63 and executing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O interrupt does. The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is involved. So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift. 41 Mitsubishi microcomputers M16C / 61 Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts. • Reset ____________ Reset occurs if an “L” is input to the RESET pin. _______ • NMI interrupt _______ _______ An NMI interrupt occurs if an “L” is input to the NMI pin. ________ • DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. • Watchdog timer interrupt Generated by the watchdog timer. • Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed. • Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to “1”. If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. For address match interrupt, see 2.11 Address match Interrupt. (2) Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral functions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts. • Bus collision detection interrupt This is an interrupt that the serial I/O bus collision detection generates. • DMA0 interrupt, DMA1 interrupt These are interrupts that DMA generates. • Key-input interrupt ___ A key-input interrupt occurs if an “L” is input to the KI pin. • A-D conversion interrupt This is an interrupt that the A-D converter generates. • UART0, UART1 and UART2 transmission interrupt These are interrupts that the serial I/O transmission generates. • UART0, UART1 and UART2 reception interrupt These are interrupts that the serial I/O reception generates. • Timer A0 interrupt through timer A4 interrupt These are interrupts that timer A generates • Timer B0 interrupt through timer B2 interrupt These are interrupts that timer B generates. ________ ________ • INT0 interrupt through INT2 interrupt ______ ______ An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin. 42 Mitsubishi microcomputers Interrupt M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts and Interrupt Vector Tables If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure 1.13.2 shows the format for specifying the address. Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. MSB LSB Low address Mid address 0000 0000 High address 0000 Vector address + 0 Vector address + 1 Vector address + 2 Vector address + 3 Figure 1.13.2. Format for specifying interrupt vector addresses • Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 1.13.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. Table 1.13.1. Interrupts assigned to the fixed vector tables and addresses of vector tables Interrupt source Undefined instruction Overflow BRK instruction Vector table addresses Address (L) to address (H) FFFDC16 to FFFDF16 FFFE016 to FFFE316 FFFE416 to FFFE716 Remarks Interrupt on UND instruction Interrupt on INTO instruction If the vector contains FF16, program execution starts from the address shown by the vector in the variable vector table There is an address-matching interrupt enable bit Do not use Address match FFFE816 to FFFEB16 Single step (Note) FFFEC16 to FFFEF16 Watchdog timer FFFF016 to FFFF316 ________ DBC (Note) FFFF416 to FFFF716 Do not use _______ NMI FFFF816 to FFFFB16 External interrupt by input to NMI pin Reset FFFFC16 to FFFFF16 Note: Interrupts used for debugging purposes only. 43 Mitsubishi microcomputers M16C / 61 Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER • Variable vector tables The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 1.13.2 shows the interrupts assigned to the variable vector tables and addresses of vector tables. Table 1.13.2. Interrupts assigned to the variable vector tables and addresses of vector tables Software interrupt number Software interrupt number 0 Vector table address Address (L) to address (H) Interrupt source BRK instruction Remarks Cannot be masked I flag +0 to +3 (Note) Software interrupt number 10 Software interrupt number 11 Software interrupt number 12 Software interrupt number 13 Software interrupt number 14 Software interrupt number 15 Software interrupt number 16 Software interrupt number 17 Software interrupt number 18 Software interrupt number 19 Software interrupt number 20 Software interrupt number 21 Software interrupt number 22 Software interrupt number 23 Software interrupt number 24 Software interrupt number 25 Software interrupt number 26 Software interrupt number 27 Software interrupt number 28 Software interrupt number 29 Software interrupt number 30 Software interrupt number 31 Software interrupt number 32 to Software interrupt number 63 +40 to +43 (Note) +44 to +47 (Note) +48 to +51 (Note) +52 to +55 (Note) +56 to +59 (Note) +60 to +63 (Note) +64 to +67 (Note) +68 to +71 (Note) +72 to +75 (Note) +76 to +79 (Note) +80 to +83 (Note) +84 to +87 (Note) +88 to +91 (Note) +92 to +95 (Note) +96 to +99 (Note) +100 to +103 (Note) +104 to +107 (Note) +108 to +111 (Note) +112 to +115 (Note) +116 to +119 (Note) +120 to +123 (Note) +124 to +127 (Note) +128 to +131 (Note) to +252 to +255 (Note) Bus collision detection DMA0 DMA1 Key input interrupt A-D UART2 transmit UART2 receive UART0 transmit UART0 receive UART1 transmit UART1 receive Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 INT0 INT1 INT2 Software interrupt Cannot be masked I flag Note: Address relative to address in interrupt table register (INTB) 44 Mitsubishi microcomputers Interrupt M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a non-maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Figure 1.13.3 shows the memory map of the interrupt control registers. 45 Mitsubishi microcomputers M16C / 61 Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt control register Symbol BCNIC DMiIC(i=0, 1) KUPIC ADIC SiTIC(i=0 to 2) SiRIC(i=0 to 2) TAiIC(i=0 to 4) TBiIC(i=0 to 2) Address 004A16 004B16, 004C16 004D16 004E16 005116, 005316, 004F16 005216, 005416, 005016 005516 to 005916 005A16 to 005C16 When reset XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 b7 b6 b5 b4 b3 b2 b1 b0 Bit symbol ILVL0 Bit name Interrupt priority level select bit b2 b1 b0 Function 000: 001: 010: 011: 100: 101: 110: 111: Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 R W ILVL1 ILVL2 IR Interrupt request bit 0 : Interrupt not requested 1 : Interrupt requested (Note 1) Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts. Symbol INTiIC(i=0 to 2) Address 005D16 to 005F16 When reset XX00X0002 b7 b6 b5 b4 b3 b2 b1 b0 0 Bit symbol ILVL0 Bit name Interrupt priority level select bit b2 b1 b0 Function 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Always set to “0” R W ILVL1 ILVL2 IR Interrupt request bit (Note 1) POL Polarity select bit Reserved bit Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts. Figure 1.13.3. Interrupt control registers 46 Mitsubishi microcomputers Interrupt M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Enable Flag (I flag) The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set to “0” after reset. Interrupt Request Bit The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1"). Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to “0” disables the interrupt. Table 1.13.3 shows the settings of interrupt priority levels and Table 1.13.4 shows the interrupt levels enabled, according to the consist of the IPL. The following are conditions under which an interrupt is accepted: · interrupt enable flag (I flag) = 1 · interrupt request bit = 1 · interrupt priority level > IPL The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another. Table 1.13.3. Settings of interrupt priority levels Table 1.13.4. Interrupt levels enabled according to the contents of the IPL IPL IPL2 IPL1 IPL0 Interrupt priority level select bit b2 b1 b0 Interrupt priority level Priority order Enabled interrupt priority levels 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High Low 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled 47 Mitsubishi microcomputers M16C / 61 Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rewrite the interrupt control register To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: Example 1: INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET 48 Mitsubishi microcomputers Interrupt M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given: (1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 0000016. (2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to “0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed) (4) Saves the content of the temporary register (Note 1) within the CPU in the stack area. (5) Saves the content of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL. After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user. Interrupt Response Time 'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure 1.13.4 shows the interrupt response time. Interrupt request generated Interrupt request acknowledged Time Instruction (a) Interrupt sequence (b) Instruction in interrupt routine Interrupt response time Figure 1.13.4. Interrupt response time 49 Mitsubishi microcomputers M16C / 61 Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time (b) is as shown in Table 1.13.5. Table 1.13.5. Time required for executing the interrupt sequence Interrupt vector address Even Even Odd (Note 2) Odd (Note 2) Stack pointer (SP) value Even Odd Even Odd ________ 16-Bit bus, without wait 18 cycles (Note 1) 19 cycles (Note 1) 19 cycles (Note 1) 20 cycles (Note 1) 8-Bit bus, without wait 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence interrupt or of a single-step interrupt. Note 2: Locate an interrupt vector address in an even address, if possible. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 BCLK Address bus Data bus R W The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. Address 0000 Interrupt information Indeterminate Indeterminate Indeterminate SP-2 SP-2 contents SP-4 SP-4 contents vec vec contents vec+2 vec+2 contents PC Figure 1.13.5. Time required for executing the interrupt sequence Variation of IPL when Interrupt Request is Accepted If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table 1.13.6 is set in the IPL. Table 1.13.6. Relationship between interrupts without interrupt priority levels and IPL Interrupt sources without priority levels _______ Value set in the IPL 7 0 Not changed Watchdog timer, NMI Reset Other 50 Mitsubishi microcomputers Interrupt M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Saving Registers In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. Figure 1.13.6 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM instruction alone can save all the registers except the stack pointer (SP). Address MSB Stack area LSB Address MSB Stack area LSB [SP] New stack pointer value m–4 m–3 m–2 m–1 m m+1 Content of previous stack Content of previous stack [SP] Stack pointer value before interrupt occurs m–4 m–3 m–2 m–1 m m+1 Program counter (PCL) Program counter (PCM) Flag register (FLGL) Flag register (FLGH) Program counter (PCH) Content of previous stack Content of previous stack Stack status before interrupt request is acknowledged Stack status after interrupt request is acknowledged Figure 1.13.6. State of stack before and after acceptance of interrupt request 51 Mitsubishi microcomputers M16C / 61 Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Figure 1.13.7 shows the operation of the saving registers. Note: Stack pointer indicated by U flag. (1) Stack pointer (SP) contains even number Address Stack area Sequence in which order registers are saved [SP] – 5 (Odd) [SP] – 4 (Even) [SP] – 3(Odd) [SP] – 2 (Even) [SP] – 1(Odd) [SP] (Even) Finished saving registers in two operations. Program counter (PCL) Program counter (PCM) Flag register (FLGL) Flag register (FLGH) Program counter (PCH) (1) Saved simultaneously, all 16 bits (2) Saved simultaneously, all 16 bits (2) Stack pointer (SP) contains odd number Address Stack area Sequence in which order registers are saved [SP] – 5 (Even) [SP] – 4(Odd) [SP] – 3 (Even) [SP] – 2(Odd) [SP] – 1 (Even) [SP] (Odd) Finished saving registers in four operations. Program counter (PCL) Program counter (PCM) Flag register (FLGL) Flag register (FLGH) Program counter (PCH) (3) (4) (1) (2) Saved simultaneously, all 8 bits Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. Figure 1.13.7. Operation of saving registers 52 Mitsubishi microcomputers Interrupt M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Returning from an Interrupt Routine Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter (PC), both of which have been saved in the stack area. Then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. Return the other registers saved by software within the interrupt routine using the POPM or similar instruction before executing the REIT instruction. Interrupt Priority If there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. Figure 1.13.8 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine. _______ ________ Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match Figure 1.13.8. Hardware interrupts priorities Interrupt resolution circuit When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. Figure 1.13.9 shows the circuit that judges the interrupt priority level. 53 Mitsubishi microcomputers M16C / 61 Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Priority level of each interrupt INT1 Timer B2 Timer B0 Timer A3 Timer A1 INT2 INT0 Timer B1 Timer A4 Timer A2 UART1 reception UART0 reception UART2 reception A-D conversion DMA1 Bus collision detection Timer A0 UART1 transmission UART0 transmission UART2 transmission Key input interrupt DMA0 Processor interrupt priority level (IPL) Level 0 (initial value) High Priority of peripheral I/O interrupts (if priority levels are same) Low Interrupt enable flag (I flag) Address match Watchdog timer DBC NMI Reset Interrupt request accepted Figure 1.13.9. Maskable interrupts priorities (peripheral I/O interrupts) 54 Mitsubishi microcomputers ________ NMI Interrupt ______ M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER INT Interrupt ________ ________ INT0 to INT2 are triggered by the edges of external inputs. The edge polarity is selected using the polarity select bit. ______ NMI Interrupt ______ ______ ______ An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI interrupt is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address 03F016). This pin cannot be used as a normal port input. Key Input Interrupt If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to P107 as A-D input ports. Figure 1.13.10 shows the block diagram of the key input interrupt. Note that if an “L” level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt. Port P104-P107 pull-up select bit Pull-up transistor Key input interrupt control register Port P107 direction register Port P107 direction register (address 004D16) P107/KI3 Pull-up transistor P106/KI2 Pull-up transistor P105/KI1 Pull-up transistor P104/KI0 Port P104 direction register Port P105 direction register Port P106 direction register Interrupt control circuit Key input interrupt request Figure 1.13.10. Block diagram of key input interrupt 55 Mitsubishi microcomputers M16C / 61 Group Address Match Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Address Match Interrupt An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the program counter (PC) for an address match interrupt varies depending on the instruction being executed. Figure 1.13.11 shows the address match interrupt-related registers. Address match interrupt enable register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Bit symbol Address 000916 Bit name Address match interrupt 0 enable bit Address match interrupt 1 enable bit When reset XXXXXX002 Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled RW AIER0 AIER1 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminated. Address match interrupt register i (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol RMAD0 RMAD1 Address 001216 to 001016 001616 to 001416 When reset X0000016 X0000016 Function Address setting register for address match interrupt Values that can be set R W 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminated. Figure 1.13.11. Address match interrupt-related registers 56 Mitsubishi microcomputers Precautions for Interrupts M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Precautions for Interrupts (1) Reading address 0000016 • When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”. Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”. Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 0000016 by software. (2) Setting the stack pointer • The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in _______ the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point at the beginning of a program. Concerning the first instruction immediately after reset, generating any _______ interrupts including the NMI interrupt is prohibited. _______ (3) The NMI interrupt _______ • As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the VCC pin via a resistor (pull-up) if unused. Be sure to work on it. _______ • The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time _______ when the NMI interrupt is input. _______ • Do not reset the CPU with the input to the NMI pin being in the “L” state. _______ • Do not attempt to go into stop mode with the input to the NMI pin being in the “L” state. With the input to _______ the NMI being in the “L” state, the CM10 is fixed to “0”, so attempting to go into stop mode is turned down. _______ • Do not attempt to go into wait mode with the input to the NMI pin being in the “L” state. With the input to _______ the NMI pin being in the “L” state, the CPU stops but the oscillation does not stop, so no power is saved. In this instance, the CPU is returned to the normal state by a later interrupt. _______ • Signals input to the NMI pin require an "L" level of 1 clock or more, from the operation clock of the CPU. (4) External interrupt ________ • Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0 ________ through INT2 regardless of the CPU operation clock. ________ ________ • When the polarity of the INT0 to INT2 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". Figure 1.13.12 shows the procedure for ______ changing the INT interrupt generate factor. 57 Mitsubishi microcomputers M16C / 61 Group Precautions for Interrupts SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clear the interrupt enable flag to “0” (Disable interrupt) Set the interrupt priority level to level 0 (Disable INTi interrupt) Set the polarity select bit Clear the interrupt request bit to “0” Set the interrupt priority level to level 1 to 7 (Enable the accepting of INTi interrupt request) Set the interrupt enable flag to “1” (Enable interrupt) ______ Figure 1.13.12. Switching condition of INT interrupt request (5) Rewrite the interrupt control register • To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: Example 1: INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. • When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET 58 Mitsubishi microcomputers Watchdog Timer Watchdog Timer M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). Thus the watchdog timer's period can be calculated as given below. The watchdog timer's period is, however, subject to an error due to the pre-scaler. With XIN chosen for BCLK Watchdog timer period = pre-scaler dividing ratio (16 or 128) X watchdog timer count (32768) BCLK With XCIN chosen for BCLK Watchdog timer period = pre-scaler dividing ratio (2) X watchdog timer count (32768) BCLK For example, suppose that BCLK runs at 10 MHZ and that 16 has been chosen for the dividing ratio of the pre-scaler, then the watchdog timer's period becomes approximately 52.4 ms. The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E16). Figure 1.14.1 shows the block diagram of the watchdog timer. Figure 1.14.2 shows the watchdog timerrelated registers. Prescaler “CM07 = 0” “WDC7 = 0” 1/16 BCLK HOLD 1/128 “CM07 = 0” “WDC7 = 1” Watchdog timer Watchdog timer interrupt request “CM07 = 1” 1/2 Write to the watchdog timer start register (address 000E16) Set to “7FFF16” RESET Figure 1.14.1. Block diagram of watchdog timer 59 Mitsubishi microcomputers Watchdog Timer M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol WDC Bit symbol Address 000F16 Bit name When reset 000XXXXX2 Function RW High-order bit of watchdog timer Reserved bit Reserved bit WDC7 Must always be set to “0” Must always be set to “0” Prescaler select bit 0 : Divided by 16 1 : Divided by 128 Watchdog timer start register b7 b0 Symbol WDTS Address 000E16 When reset Indeterminate RW Function The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to “7FFF16” regardless of whatever value is written. Figure 1.14.2. Watchdog timer control and start registers 60 Mitsubishi microcomputers DMAC DMAC M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 1.15.1 shows the block diagram of the DMAC. Table 1.15.1 shows the DMAC specifications. Figure 1.15.2 to Figure 1.15.3 show the registers used by the DMAC. Address bus DMA0 source pointer SAR0(20) (addresses 002216 to 002016) DMA0 destination pointer DAR0 (20) (addresses 002616 to 002416) DMA0 forward address pointer (20) (Note) DMA0 transfer counter reload register TCR0 (16) DMA1 source pointer SAR1 (20) (addresses 003216 to 003016) DMA1 destination pointer DAR1 (20) (addresses 003616 to 003416) (addresses 002916, 002816) DMA0 transfer counter TCR0 (16) DMA1 transfer counter reload register TCR1 (16) DMA1 forward address pointer (20) (Note) (addresses 003916, 003816) DMA1 transfer counter TCR1 (16) DMA latch high-order bits DMA latch low-order bits Data bus low-order bits Data bus high-order bits Note: Pointer is incremented by a DMA request. Figure 1.15.1. Block diagram of DMAC Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level. The DMA transfer doesn't affect any interrupts either. If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the number of transfers. For details, see the description of the DMA request bit. 61 Mitsubishi microcomputers DMAC M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.15.1. DMAC specifications Item Specification No. of channels 2 (cycle steal method) Transfer memory space • From any address in the 1M bytes space to a fixed address • From a fixed address to any address in the 1M bytes space • From a fixed address to a fixed address (Note that DMA-related registers [002016 to 003F16] cannot be accessed) Maximum No. of bytes transferred 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers) ________ ________ ________ ________ Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 by DMA1) Timer A0 to timer A4 interrupt requests Timer B0 to timer B2 interrupt requests UART0 transmission and reception interrupt requests UART1 transmission and reception interrupt requests (UART1 transmission can be selected by DMA0, UART1 reception by DMA1) UART2 transmission and reception interrupt requests A-D conversion interrupt requests Software triggers Channel priority DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously Transfer unit 8 bits or 16 bits Transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) Transfer mode • Single transfer mode After the transfer counter underflows, the DMA enable bit turns to “0”, and the DMAC turns inactive • Repeat transfer mode After the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. The DMAC remains active unless a “0” is written to the DMA enable bit. DMA interrupt request generation timing When an underflow occurs in the transfer counter Active When the DMA enable bit is set to “1”, the DMAC is active. When the DMAC is active, data transfer starts every time a DMA transfer request signal occurs. Inactive • When the DMA enable bit is set to “0”, the DMAC is inactive. • After the transfer counter underflows in single transfer mode Forward address pointer and At the time of starting data transfer immediately after turning the DMAC active, re load timing for transfer the value of one of source pointer and destination pointer - the one specified for the counter forward direction - is reloaded to the forward direction address pointer,and the value of the transfer counter reload register is reloaded to the transfer counter. Writing to register Registers specified for forward direction transfer are always write enabled. Registers specified for fixed address transfer are write-enabled when the DMA enable bit is “0”. Reading the register Can be read at any time. However, when the DMA enable bit is “1”, reading the register set up as the forward register is the same as reading the value of the forward address pointer. Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level. DMA request factors (Note) 62 Mitsubishi microcomputers DMAC M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAi request cause select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DMiSL(i=0,1) Address 03B816,03BA16 When reset 0016 Bit symbol Bit name DMA request cause select bit b3 b2 b1 b0 Function 0 0 0 0 : Falling edge of INT0 / INT1 pin (Note 1) 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3 0 1 1 0 : Timer A4 0 1 1 1 : Timer B0 1 0 0 0 : Timer B1 1 0 0 1 : Timer B2 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 transmit / UART1 receive (Note 2) R W DSEL0 DSEL1 DSEL2 DSEL3 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. DSR Software DMA request bit If software trigger is selected, a DMA request is generated by setting this bit to “1” (When read, the value of this bit is always “0”) Note 1: Address 03B816 is for INT0 ; address 03BA16 is for INT1. Note 2: Address 03B816 is for UART1 transmit ; address 03BA16 is for UART1 receive. DMAi control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DMiCON(i=0,1) Address 002C16, 003C16 When reset 00000X002 Bit symbol DMBIT DMASL DMAS DMAE DSD DAD Bit name Transfer unit bit select bit Repeat transfer mode select bit DMA request bit (Note 1) DMA enable bit Source address direction select bit (Note 3) 0 : 16 bits 1 : 8 bits Function R W 0 : Single transfer 1 : Repeat transfer 0 : DMA not requested 1 : DMA requested 0 : Disabled 1 : Enabled 0 : Fixed 1 : Forward (Note 2) Destination address 0 : Fixed direction select bit (Note 3) 1 : Forward Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Note 1: DMA request can be cleared by resetting the bit. Note 2: This bit can only be set to “0”. Note 3: Source address direction select bit and destination address direction select bit cannot be set to “1” simultaneously. Figure 1.15.2. DMAC register (1) 63 Mitsubishi microcomputers DMAC M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAi source pointer (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol SAR0 SAR1 Address 002216 to 002016 003216 to 003016 Transfer count specification When reset Indeterminate Indeterminate Function • Source pointer Stores the source address RW 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. DMAi destination pointer (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol DAR0 DAR1 Address 002616 to 002416 003616 to 003416 Transfer count specification When reset Indeterminate Indeterminate RW Function • Destination pointer Stores the destination address 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. DMAi transfer counter (i = 0, 1) (b15) b7 (b8) b0 b7 b0 Symbol TCR0 TCR1 Address 002916, 002816 003916, 003816 When reset Indeterminate Indeterminate RW Function • Transfer counter Set a value one less than the transfer count Transfer count specification 000016 to FFFF16 Figure 1.15.3. DMAC register (2) 64 Mitsubishi microcomputers DMAC (1) Transfer cycle M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to the SFR area (destination write). The number of read and write bus cycles depends on the source and destination addresses. In memory expansion mode and microprocessor mode, the number of read and write bus cycles also depends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted. (a) Effect of source and destination addresses When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. (b) Effect of BYTE pin level When transferring 16-bit data over an 8-bit data bus (BYTE pin = “H”) in memory expansion mode and microprocessor mode, the 16 bits of data are sent in two 8-bit blocks. Therefore, two bus cycles are required for reading the data and two are required for writing the data. Also, in contrast to when the CPU accesses internal memory, when the DMAC accesses internal memory (internal ROM, internal RAM, and SFR), these areas are accessed using the data size selected by the BYTE pin. (c) Effect of software wait When the SFR area or a memory area with a software wait is accessed, the number of cycles is increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK. Figure 1.15.4 shows the example of the transfer cycles for a source read. For convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle. For example (2) in Figure 36, if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the source read cycle and the destination write cycle. 65 Mitsubishi microcomputers DMAC M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) 8-bit transfers 16-bit transfers from even address and the source address is even. BCLK Address bus RD signal WR signal Data bus CPU use Source Destination Dummy cycle CPU use CPU use Source Destination Dummy cycle CPU use (2) 16-bit transfers and the source address is odd Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination write cycles). BCLK Address bus RD signal WR signal Data bus CPU use Source Source + 1 Destination Dummy cycle CPU use CPU use Source Source + 1 Destination Dummy cycle CPU use (3) One wait is inserted into the source read under the conditions in (1) BCLK Address bus RD signal WR signal Data bus CPU use Source Destination Dummy cycle CPU use CPU use Source Destination Dummy cycle CPU use (4) One wait is inserted into the source read under the conditions in (2) (When 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles). BCLK Address bus RD signal WR signal Data bus CPU use Source Source + 1 Destination Dummy cycle CPU use CPU use Source Source + 1 Destination Dummy cycle CPU use Note: The same timing changes occur with the respective conditions at the destination as at the source. Figure 1.15.4. Example of the transfer cycles for a source read 66 Mitsubishi microcomputers DMAC (2) DMAC transfer cycles M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Any combination of even or odd transfer read and write addresses is possible. Table 1.15.2 shows the number of DMAC transfer cycles. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k Table 1.15.2. No. of DMAC transfer cycles Transfer unit Memory expansion mode Bus width Access address Microprocessor mode No. of read No. of write No. of read No. of write cycles cycles cycles cycles 16-bit Even 1 1 1 1 (BYTE= “L”) Odd 1 1 1 1 8-bit Even — — 1 1 (BYTE = “H”) Odd — — 1 1 16-bit Even 1 1 1 1 (BYTE = “L”) Odd 2 2 2 2 8-bit Even — — 2 2 (BYTE = “H”) Odd — — 2 2 Single-chip mode 8-bit transfers (DMBIT= “1”) 16-bit transfers (DMBIT= “0”) Coefficient j, k Internal memory Internal ROM/RAM Internal ROM/RAM SFR area No wait With wait 1 2 2 External memory Separate bus Separate bus No wait With wait 1 2 Multiplex bus 3 67 Mitsubishi microcomputers DMAC M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMA enable bit Setting the DMA enable bit to 1 makes the DMAC active. The DMAC carries out the following operations at the time data transfer starts immediately after DMAC is turned active. (1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the forward direction - to the forward direction address pointer. (2) Reloads the value of the transfer counter reload register to the transfer counter. Thus overwriting 1 to the DMA enable bit with the DMAC being active carries out the operations given above, so the DMAC operates again from the initial state at the instant 1 is overwritten to the DMA enable bit. DMA request bit The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of DMA request factors for each channel. DMA request factors include the following. * Factors effected by using the interrupt request signals from the built-in peripheral functions and software DMA factors (internal factors) effected by a program. * External factors effected by utilizing the input from external interrupt signals. For the selection of DMA request factors, see the descriptions of the DMAi factor selection register. The DMA request bit turns to 1 if the DMA transfer request signal occurs regardless of the DMAC's state (regardless of whether the DMA enable bit is set 1 or to 0). It turns to 0 immediately before data transfer starts. In addition, it can be set to 0 by use of a program, but cannot be set to 1. There can be instances in which a change in DMA request factor selection bit causes the DMA request bit to turn to 1. So be sure to set the DMA request bit to 0 after the DMA request factor selection bit is changed. The DMA request bit turns to 1 if a DMA transfer request signal occurs, and turns to 0 immediately before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the DMA request bit, if read by use of a program, turns out to be 0 in most cases. To examine whether the DMAC is active, read the DMA enable bit. Here follows the timing of changes in the DMA request bit. (1) Internal factors Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to 1 due to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to turn to 1 due to several factors. Turning the DMA request bit to 1 due to an internal factor is timed to be effected immediately before the transfer starts. (2) External factors An external factor is a factor caused to occur by the leading edge of input from the INTi pin (i depends on which DMAC channel is used). Selecting the INTi pins as external factors using the DMA request factor selection bit causes input from these pins to become the DMA transfer request signals. The timing for the DMA request bit to turn to 1 when an external factor is selected synchronizes with the signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes with the trailing edge of the input signal to each INTi pin, for example). With an external factor selected, the DMA request bit is timed to turn to 0 immediately before data transfer starts similarly to the state in which an internal factor is selected. 68 Mitsubishi microcomputers DMAC M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (3) The priorities of channels and DMA transfer timing If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels concurrently turn to 1. If the channels are active at that moment, DMA0 is given a high priority to start data transfer. When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus access, then DMA1 starts data transfer and gives the bus right to the CPU. An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer request signals due to external factors concurrently occur. Figure 1.15.5 An example of DMA transfer effected by external factors. An example in which DMA transmission is carried out in minimum cycles at the time when DMA transmission request signals due to external factors concurrently occur. BCLK DMA0 DMA1 CPU INT0 DMA0 request bit INT1 DMA1 request bit Obtainm ent of the bus right Figure 1.15.5. An example of DMA transfer effected by external factors 69 Mitsubishi microcomputers Timer Timer M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER There are eight 16-bit timers. These timers can be classified by function into timers A (five) and timers B (three). All these timers function independently. Figure 1.16.1 shows the block diagram of timers. Clock prescaler XIN 1/8 1/4 f1 f8 f32 fC32 f1 f8 f32 XCIN Clock prescaler reset flag (bit 7 at address 038116) set to “1” 1/32 Reset fC32 • Timer mode • One-shot mode • PWM mode Timer A0 interrupt TA0IN Noise filter Timer A0 • Event counter mode • Timer mode • One-shot mode • PWM mode Timer A1 interrupt Timer A1 TA1IN Noise filter • Event counter mode • Timer mode • One-shot mode • PWM mode Timer A2 interrupt TA2IN Noise filter Timer A2 • Event counter mode • Timer mode • One-shot mode • PWM mode Timer A3 interrupt TA3IN Noise filter Timer A3 • Event counter mode • Timer mode • One-shot mode • PWM mode Timer A4 interrupt TA4IN Noise filter Timer A4 • Event counter mode • Timer mode • Pulse width measuring mode TB0IN Noise filter Timer B0 interrupt Timer B0 • Event counter mode • Timer mode • Pulse width measuring mode Timer B1 interrupt TB1IN Noise filter Timer B1 • Event counter mode • Timer mode • Pulse width measuring mode TB2IN Noise filter Timer B2 interrupt Timer B2 • Event counter mode Figure 1.16.1. Block diagram of timer 70 Mitsubishi microcomputers Timer A Timer A M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.16.2 shows the block diagram of timer A. Figures 1.16.3 to 1.16.5 show the timer A-related registers. Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. Timer A has the four operation modes listed as follows: • Timer mode: The timer counts an internal count source. • Event counter mode: The timer counts pulses from an external source or a timer over flow. • One-shot timer mode: The timer stops counting when the count reaches “000016”. • Pulse width modulation (PWM) mode: The timer outputs pulses of a given width. Data bus high-order bits Clock source selection f1 f8 f32 fC32 Polarity selection TAiIN (i = 0 to 4) • Timer • One shot • PWM • Timer (gate function) • Event counter Data bus low-order bits Low-order 8 bits Reload register (16) High-order 8 bits Counter (16) Clock selection Up count/down count Always down count except in event counter mode TAi Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Addresses 038716 038616 038916 038816 038B16 038A16 038D16 038C16 038F16 038E16 TAj Timer A4 Timer A0 Timer A1 Timer A2 Timer A3 TAk Timer A1 Timer A2 Timer A3 Timer A4 Timer A0 Count start flag (Address 038016) Down count External trigger TB2 overflow TAj overflow (j = i – 1. Note, however, that j = 4 when i = 0) Up/down flag (Address 038416) TAk overflow (k = i + 1. Note, however, that k = 0 when i = 4) TAiOUT (i = 0 to 4) Pulse output Toggle flip-flop Figure 1.16.2. Block diagram of timer A Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TAiMR(i=0 to 4) Address When reset 0016 039616 to 039A16 Bit symbol TMOD0 Bit name Operation mode select bit b1 b0 Function 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode RW TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 Function varies with each operation mode Count source select bit (Function varies with each operation mode) Figure 1.16.3. Timer A-related registers (1) 71 Mitsubishi microcomputers Timer A M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer Ai register (Note) (b15) b7 (b8) b0 b7 b0 Symbol TA0 TA1 TA2 TA3 TA4 Address 038716,038616 038916,038816 038B16,038A16 038D16,038C16 038F16,038E16 When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Function • Timer mode Counts an internal count source Values that can be set RW 000016 to FFFF16 • Event counter mode 000016 to FFFF16 Counts pulses from an external source or timer overflow • One-shot timer mode Counts a one shot width • Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator • Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 000016 to FFFF16 000016 to FFFE16 0016 to FE16 (Both high-order and low-order addresses) Note: Read and write data in 16-bit units. Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Address 038016 When reset 0016 Bit symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Bit name Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag Function 0 : Stops counting 1 : Starts counting RW Up/down flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol UDF Address 038416 When reset 0016 Bit symbol TA0UD TA1UD TA2UD TA3UD TA4UD TA2P TA3P TA4P Bit name Timer A0 up/down flag Timer A1 up/down flag Timer A2 up/down flag Timer A3 up/down flag Timer A4 up/down flag Function 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause RW Timer A2 two-phase pulse 0 : two-phase pulse signal processing disabled signal processing select bit 1 : two-phase pulse signal processing enabled Timer A3 two-phase pulse signal processing select bit When not using the two-phase Timer A4 two-phase pulse pulse signal processing function, signal processing select bit set the select bit to “0” Figure 1.16.4. Timer A-related registers (2) 72 Mitsubishi microcomputers Timer A M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER One-shot start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol ONSF Address 038216 When reset 00X000002 Bit symbol TA0OS TA1OS TA2OS TA3OS TA4OS Bit name Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag Function 1 : Timer start When read, the value is “0” RW Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. TA0TGL TA0TGH Timer A0 event/trigger select bit b7 b6 0 0 : Input on TA0IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA4 overflow is selected 1 1 : TA1 overflow is selected Note: Set the corresponding port direction register to “0”. Trigger select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRGSR Address 038316 When reset 0016 Bit symbol TA1TGL Bit name Timer A1 event/trigger select bit Function b1 b0 RW TA1TGH TA2TGL 0 0 : Input on TA1IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected b3 b2 Timer A2 event/trigger select bit TA2TGH TA3TGL TA3TGH 0 0 : Input on TA2IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected b5 b4 Timer A3 event/trigger select bit 0 0 : Input on TA3IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected b7 b6 TA4TGL TA4TGH Timer A4 event/trigger select bit 0 0 : Input on TA4IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected Note: Set the corresponding port direction register to “0”. Clock prescaler reset flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Address 038116 When reset 0XXXXXXX2 Bit symbol Bit name Function RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) Figure 1.16.5. Timer A-related registers (3) 73 Mitsubishi microcomputers Timer A (1) Timer mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In this mode, the timer counts an internally generated count source. (See Table 1.16.1.) Figure 1.16.6 shows the timer Ai mode register in timer mode. Table 1.16.1. Specifications of timer mode Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Specification f1, f8, f32, fC32 • Down count • When the timer underflows, it reloads the reload register contents before continuing counting 1/(n+1) n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) When the timer underflows Programmable I/O port or gate input Programmable I/O port or pulse output Count value can be read out by reading timer Ai register • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter • When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) • Gate function Counting can be started and stopped by the TAiIN pin’s input signal • Pulse output function Each time the timer underflows, the TAiOUT pin’s polarity is reversed Select function Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 0 00 Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0 Address When reset 0016 039616 to 039A16 Bit name Function b1 b0 RW Operation mode select bit Pulse output function select bit 0 0 : Timer mode 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin) b4 b3 MR1 Gate function select bit 0 X (Note 2): Gate function not available (TAiIN pin is a normal port pin) MR2 1 0 : Timer counts only when TAiIN pin is held “L” (Note 3) 1 1 : Timer counts only when TAiIN pin is held “H” (Note 3) 0 (Must always be fixed to “0” in timer mode) Count source select bit b7 b6 MR3 TCK0 TCK1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: The bit can be “0” or “1”. Note 3: Set the corresponding port direction register to “0”. Figure 1.16.6. Timer Ai mode register in timer mode 74 Mitsubishi microcomputers Timer A (2) Event counter mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase external signal. Table 1.16.2 lists timer specifications when counting a single-phase external signal. Figure 1.16.7 shows the timer Ai mode register in event counter mode. Table 1.16.3 lists timer specifications when counting a two-phase external signal. Figure 1.16.8 shows the timer Ai mode register in event counter mode. Table 1.16.2. Timer specifications in event counter mode (when not processing two-phase pulse signal) Item Specification Count source • External signals input to TAiIN pin (effective edge can be selected by software) • TB2 overflow, TAj overflow Count operation • Up count or down count can be selected by external signal or software • When the timer overflows or underflows, it reloads the reload register con tents before continuing counting (Note) Divide ratio 1/ (FFFF16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer overflows or underflows TAiIN pin function Programmable I/O port or count source input TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input Read from timer Count value can be read out by reading timer Ai register Write to timer • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter • When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Select function • Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it • Pulse output function Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed Note: This does not apply when the free-run function is selected. Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 0 01 Symbol TAiMR(i = 0, 1) Bit symbol TMOD0 TMOD1 MR0 Address 039616, 039716 When reset 0016 Function RW Bit name Operation mode select bit Pulse output function select bit b1 b0 0 1 : Event counter mode (Note 1) 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 2) (TAiOUT pin is a pulse output pin) 0 : Counts external signal's falling edge 1 : Counts external signal's rising edge 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 4) MR1 MR2 MR3 TCK0 TCK1 Count polarity select bit (Note 3) Up/down switching cause select bit 0 (Must always be fixed to “0” in event counter mode) Count operation type select bit 0 : Reload type 1 : Free-run type Invalid in event counter mode Can be “0” or “1” Note 1: In event counter mode, the count source is selected by the event / trigger select bit (addresses 038216 and 038316). Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Valid only when counting an external signal. Note 4: When an “L” signal is input to the TAiOUT pin, the downcount is activated. When “H”, the upcount is activated. Set the corresponding port direction register to “0”. Figure 1.16.7. Timer Ai mode register in event counter mode 75 Mitsubishi microcomputers Timer A M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.16.3. Timer specifications in event counter mode (when processing two-phase pulse signal with timers A2, A3, and A4) Item Count source Count operation Specification • Two-phase pulse signals input to TAiIN or TAiOUT pin • Up count or down count can be selected by two-phase pulse signal • When the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (Note) 1/ (FFFF16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) Timer overflows or underflows Two-phase pulse input Two-phase pulse input Count value can be read out by reading timer A2, A3, or A4 register • When counting stopped When a value is written to timer A2, A3, or A4 register, it is written to both reload register and counter • When counting in progress When a value is written to timer A2, A3, or A4 register, it is written to only reload register. (Transferred to counter at next reload time.) • Normal processing operation The timer counts up rising edges or counts down falling edges on the TAiIN pin when input signal on the TAiOUT pin is “H” Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Select function TAiOUT TAiIN (i=2,3) Up count Up count Up Down count count Down count Down count • Multiply-by-4 processing operation If the phase relationship is such that the TAiIN pin goes “H” when the input signal on the TAiOUT pin is “H”, the timer counts up rising and falling edges on the TAiOUT and TAiIN pins. If the phase relationship is such that the TAiIN pin goes “L” when the input signal on the TAiOUT pin is “H”, the timer counts down rising and falling edges on the TAiOUT and TAiIN pins. TAiOUT Count up all edges Count down all edges TAiIN (i=3,4) Count up all edges Count down all edges Note: This does not apply when the free-run function is selected. 76 Mitsubishi microcomputers Timer A M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer Ai mode register (When not using two-phase pulse signal processing) b7 b6 b5 b4 b3 b2 b1 b0 0 01 Symbol Address When reset 0016 TAiMR(i = 2 to 4) 039816 to 039A16 Bit symbol TMOD0 TMOD1 MR0 Bit name Operation mode select bit Pulse output function select bit b1 b0 Function 0 1 : Event counter mode 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin) 0 : Counts external signal's falling edges 1 : Counts external signal's rising edges 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 3) RW MR1 MR2 MR3 TCK0 TCK1 Count polarity select bit (Note 2) Up/down switching cause select bit 0 : (Must always be “0” in event counter mode) Count operation type select bit Two-phase pulse signal processing operation select bit (Note 4)(Note 5) 0 : Reload type 1 : Free-run type 0 : Normal processing operation 1 : Multiply-by-4 processing operation Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: This bit is valid when only counting an external signal. Note 3: Set the corresponding port direction register to “0”. Note 4: This bit is valid for the timer A3 mode register. For timer A2 and A4 mode registers, this bit can be “0 ”or “1”. Note 5: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 038416) is set to “1”. Also, always be sure to set the event/trigger select bit (addresses 038216 and 038316) to “00”. Timer Ai mode register (When using two-phase pulse signal processing) b7 b6 b5 b4 b3 b2 b1 b0 010001 Symbol Address When reset TAiMR(i = 2 to 4) 039816 to 039A16 0016 Bit symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 Bit name Operation mode select bit b1 b0 Function 0 1 : Event counter mode RW 0 (Must always be “0” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) 1 (Must always be “1” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) Count operation type select bit Two-phase pulse processing operation select bit (Note 1)(Note 2) 0 : Reload type 1 : Free-run type 0 : Normal processing operation 1 : Multiply-by-4 processing operation Note 1: This bit is valid for timer A3 mode register. For timer A2 and A4 mode registers, this bit can be “0” or “1”. Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 038416) is set to “1”. Also, always be sure to set the event/trigger select bit (addresses 038216 and 038316) to “00”. Figure 1.16.8. Timer Ai mode register in event counter mode 77 Mitsubishi microcomputers Timer A (3) One-shot timer mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In this mode, the timer operates only once. (See Table 1.16.4.) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.16.9 shows the timer Ai mode register in one-shot timer mode. Table 1.16.4. Timer specifications in one-shot timer mode Item Count source Count operation Specification f1, f8, f32, fC32 • The timer counts down • When the count reaches 000016, the timer stops counting after reloading a new count • If a trigger occurs when counting, the timer reloads a new count and restarts counting 1/n n : Set value • An external trigger is input • The timer overflows • The one-shot start flag is set (= 1) • A new count is reloaded after the count has reached 000016 • The count start flag is reset (= 0) The count reaches 000016 Programmable I/O port or trigger input Programmable I/O port or pulse output When timer Ai register is read, it indicates an indeterminate value • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter • When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 0 10 Symbol Address When reset TAiMR(i = 0 to 4) 039616 to 039A16 0016 Bit symbol TMOD0 TMOD1 MR0 Pulse output function select bit Bit name Operation mode select bit b1 b0 Function 1 0 : One-shot timer mode 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin) 0 : Falling edge of TAiIN pin's input signal (Note 3) 1 : Rising edge of TAiIN pin's input signal (Note 3) RW MR1 MR2 External trigger select bit (Note 2) Trigger select bit 0 : One-shot start flag is valid 1 : Selected by event/trigger select register MR3 TCK0 TCK1 0 (Must always be “0” in one-shot timer mode) Count source select bit b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”. Note 3: Set the corresponding port direction register to “0”. Figure 1.16.9. Timer Ai mode register in one-shot timer mode 78 Mitsubishi microcomputers Timer A (4) Pulse width modulation (PWM) mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In this mode, the timer outputs pulses of a given width in succession. (See Table 1.16.5.) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.16.10 shows the configuration of the timer Ai mode register in pulse width modulation mode. Figure 1.16.11 shows an example of how a 16-bit pulse width modulator operates. Figure 1.16.12 shows an example of how an 8-bit pulse width modulator operates. Table 1.16.5. Timer specifications in pulse width modulation mode Item Count source Count operation Specification f1, f8, f32, fC32 • The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) • The timer reloads a new count at a rising edge of PWM pulse and continues counting • The timer is not affected by a trigger that occurs when counting • High level width n / fi n : Set value • Cycle time (216 - 1) / fi fixed • High level width n X (m+1) / fi n : values set to timer Ai register’s high-order address • Cycle time (28 - 1) X (m +1) / fi m : values set to timer Ai register’s low-order address • External trigger is input • The timer overflows • The count start flag is set (= 1) • The count start flag is reset (= 0) PWM pulse goes “L” Programmable I/O port or trigger input Pulse output When timer Ai register is read, it indicates an indeterminate value • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter • When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) 16-bit PWM 8-bit PWM Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 111 Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0 MR1 MR2 Address When reset 039616 to 039A16 0016 Function b1 b0 Bit name Operation mode select bit 1 1 : PWM mode RW 1 (Must always be fixed to “1” in PWM mode) External trigger select bit (Note 1) Trigger select bit 0: Falling edge of TAiIN pin's input signal (Note 2) 1: Rising edge of TAiIN pin's input signal (Note 2) 0: Count start flag is valid 1: Selected by event/trigger select register 0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator b7 b6 MR3 16/8-bit PWM mode select bit Count source select bit TCK0 TCK1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0 Note 2: Set the corresponding port direction register to “0”. Figure 1.16.10. Configuration of timer Ai mode register in pulse width modulation mode 79 Mitsubishi microcomputers Timer A M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Condition : Reload register = 000316, when external trigger (rising edge of TAiIN pin input signal) is selected 1 / fi X (2 16 – 1) Count source TAiIN pin input signal “H” “L” Trigger is not generated by this signal 1 / fi X n PWM pulse output from TAiOUT pin Timer Ai interrupt request bit “H” “L” “1” “0” fi : Frequency of count source (f1, f8, f32, fC32) Cleared to “0” when interrupt request is accepted, or cleared by software Note: n = 000016 to FFFE16. Figure 1.16.11. Example of how a 16-bit pulse width modulator operates Condition : Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 External trigger (falling edge of TAiIN pin input signal) is selected 1 / fi X (m + 1) X (2 8 – 1) Count source (Note1) TAiIN pin input signal “H” “L” 1 / fi X (m + 1) Underflow signal of 8-bit prescaler (Note2) “L” “H” 1 / fi X (m + 1) X n PWM pulse output from TAiOUT pin Timer Ai interrupt request bit “H” “L” “1” “0” fi : Frequency of count source (f1, f8, f32, fC32) Cleared to “0” when interrupt request is accepted, or cleaerd by software Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 0016 to FE16; n = 0016 to FE16. Figure 1.16.12. Example of how an 8-bit pulse width modulator operates 80 Mitsubishi microcomputers Timer B Timer B M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.16.13 shows the block diagram of timer B. Figures 1.16.14 and 1.16.15 show the timer B-related registers. Use the timer Bi mode register (i = 0 to 2) bits 0 and 1 to choose the desired mode. Timer B has three operation modes listed as follows: • Timer mode: The timer counts an internal count source. • Event counter mode: The timer counts pulses from an external source or a timer overflow. • Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or pulse width. Data bus high-order bits Data bus low-order bits Low-order 8 bits High-order 8 bits Clock source selection f1 f8 f32 fC32 TBiIN (i = 0 to 2) • Timer • Pulse period/pulse width measurement Reload register (16) • Event counter Polarity switching and edge pulse Count start flag (address 038016) Counter reset circuit Can be selected in only event counter mode TBj overflow (j = i – 1. Note, however, j = 2 when i = 0) TBi Timer B0 Timer B1 Timer B2 Counter (16) Address 039116 039016 039316 039216 039516 039416 TBj Timer B2 Timer B0 Timer B1 Figure 1.16.13. Block diagram of timer B Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address TBiMR(i = 0 to 2) 039B16 to 039D16 When reset 00XX00002 Bit symbol TMOD0 TMOD1 Bit name Operation mode select bit b1 b0 Function 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/pulse width measurement mode 1 1 : Inhibited R W MR0 MR1 MR2 Function varies with each operation mode (Note 1) (Note 2) MR3 TCK0 TCK1 Count source select bit (Function varies with each operation mode) Note 1: Timer B0. Note 2: Timer B1, timer B2. Figure 1.16.14. Timer B-related registers (1) 81 Mitsubishi microcomputers Timer B M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer Bi register (Note) (b15) b7 (b8) b0 b7 b0 Symbol TB0 TB1 TB2 Address 039116, 039016 039316, 039216 039516, 039416 When reset Indeterminate Indeterminate Indeterminate Function • Timer mode Counts the timer's period • Event counter mode Counts external pulses input or a timer overflow • Pulse period / pulse width measurement mode Measures a pulse period or width Values that can be set RW 000016 to FFFF16 000016 to FFFF16 Note: Read and write data in 16-bit units. Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Address 038016 When reset 0016 Bit symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Bit name Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag Function 0 : Stops counting 1 : Starts counting RW Clock prescaler reset flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Address 038116 When reset 0XXXXXXX2 Bit symbol Bit name Function RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) Figure 1.16.15. Timer B-related registers (2) 82 Mitsubishi microcomputers Timer B (1) Timer mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In this mode, the timer counts an internally generated count source. (See Table 1.16.6.) Figure 1.16.16 shows the timer Bi mode register in timer mode. Table 1.16.6. Timer specifications in timer mode Item Count source Count operation Specification f1, f8, f32, fC32 • Counts down • When the timer underflows, it reloads the reload register contents before continuing counting 1/(n+1) n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) The timer underflows Programmable I/O port Count value is read out by reading timer Bi register • When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter • When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) Divide ratio Count start condition Count stop condition Interrupt request generation timing TBiIN pin function Read from timer Write to timer Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol TBiMR(i=0 to 2) Bit symbol TMOD0 TMOD1 MR0 MR1 MR2 Address 039B16 to 039D16 When reset 00XX00002 Bit name Operation mode select bit b1 b0 Function 0 0 : Timer mode R W Invalid in timer mode Can be “0” or “1” 0 (Fixed to “0” in timer mode ; i = 0) Nothing is assiigned (i = 1,2). In an attempt to write to this bit, write “0” . The value, if read, turns out to be indeterminate. (Note 1) (Note 2) MR3 Invalid in timer mode. In an attempt to write to this bit, write “0” . The value, if read in timer mode, turns out to be indeterminate. Count source select bit b7 b6 TCK0 TCK1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: Timer B0. Note 2: Timer B1, timer B2. Figure 1.16.16. Timer Bi mode register in timer mode 83 Mitsubishi microcomputers Timer B (2) Event counter mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.16.7.) Figure 1.16.17 shows the timer Bi mode register in event counter mode. Table 1.16.7. Timer specifications in event counter mode Item Count source Specification • External signals input to TBiIN pin • Effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software Count operation • Counts down • When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer underflows TBiIN pin function Read from timer Write to timer Count source input Count value can be read out by reading timer Bi register • When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter • When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 01 Symbol TBiMR(i=0 to 2) Address 039B16 to 039D16 When reset 00XX00002 Bit symbol TMOD0 TMOD1 MR0 Bit name Operation mode select bit b1 b0 Function 0 1 : Event counter mode b3 b2 R W Count polarity select bit (Note 1) MR1 0 0 : Counts external signal's falling edges 0 1 : Counts external signal's rising edges 1 0 : Counts external signal's falling and rising edges 1 1 : Inhibited (Note 2) MR2 0 (Fixed to “0” in event counter mode; i = 0) Nothing is assigned (i = 1, 2). In an attempt to write to this bit, write “0” . The value, if read, turns out to be indeterminate. Invalid in event counter mode. In an attempt to write to this bit, write “0” . The value, if read in event counter mode, turns out to be indeterminate. Invalid in event counter mode. Can be “0” or “1”. Event clock select 0 : Input from TBiIN pin (Note 4) 1 : TBj overflow (j = i – 1; however, j = 2 when i = 0) (Note 3) MR3 TCK0 TCK1 Note 1: Valid only when input from the TBiIN pin is selected as the event clock. If timer's overflow is selected, this bit can be “0” or “1”. Note 2: Timer B0. Note 3: Timer B1, timer B2. Note 4: Set the corresponding port direction register to “0”. Figure 1.16.17. Timer Bi mode register in event counter mode 84 Mitsubishi microcomputers Timer B (3) Pulse period/pulse width measurement mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.16.8.) Figure 1.16.18 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure 1.16.19 shows the operation timing when measuring a pulse period. Figure 1.16.20 shows the operation timing when measuring a pulse width. Table 1.16.8. Timer specifications in pulse period/pulse width measurement mode Item Count source Count operation Specification f1, f8, f32, fC32 • Up count • Counter value “000016” is transferred to reload register at measurement pulse's effective edge and the timer continues counting Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing • When measurement pulse's effective edge is input (Note 1) • When an overflow occurs. (Simultaneously, the timer Bi overflow flag changes to “1”. The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the timer Bi mode register.) TBiIN pin function Measurement pulse input Read from timer When timer Bi register is read, it indicates the reload register’s content (measurement result) (Note 2) Write to timer Cannot be written to Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting. Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer. Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 10 Symbol TBiMR(i=0 to 2) Address 039B16 to 039D16 When reset 00XX00002 Bit symbol TMOD0 TMOD1 MR0 Bit name Operation mode select bit Measurement mode select bit b1 b0 Function 1 0 : Pulse period / pulse width measurement mode b3 b2 R W MR1 0 0 : Pulse period measurement (Interval between measurement pulse's falling edge to falling edge) 0 1 : Pulse period measurement (Interval between measurement pulse's rising edge to rising edge) 1 0 : Pulse width measurement (Interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : Inhibited MR2 0 (Fixed to “0” in pulse period/pulse width measurement mode; i = 0) Nothing is assigned (i = 1, 2). In an attempt to write to this bit, write “0” . The value, if read, turns out to be indeterminate. (Note 2) (Note 3) MR3 TCK0 TCK1 Timer Bi overflow flag ( Note 1) Count source select bit 0 : Timer did not overflow 1 : Timer has overflowed b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the timer Bi mode register. This flag cannot be set to “1” by software. Note 2: Timer B0. Note 3: Timer B1, timer B2. Figure 1.16.18. Timer Bi mode register in pulse period/pulse width measurement mode 85 Mitsubishi microcomputers Timer B M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER When measuring measurement pulse time interval from falling edge to falling edge Count source Measurement pulse “H” “L” Transfer (indeterminate value) Transfer (measured value) Reload register transfer timing counter (Note 1) (Note 1) (Note 2) Timing at which counter reaches “000016” Count start flag “1” “0” Timer Bi interrupt request bit “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software. Timer Bi overflow flag “1” “0” Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. Figure 1.16.19. Operation timing when measuring a pulse period Count source Measurement pulse “H” “L” Transfer (indeterminate value) Transfer (measured value) Transfer (measured value) Transfer (measured value) Reload register transfer timing counter (Note 1) (Note 1) (Note 1) (Note 1) (Note 2) Timing at which counter reaches “000016” “1” “0” Count start flag Timer Bi interrupt request bit “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software. Timer Bi overflow flag “1” “0” Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. Figure 1.16.20. Operation timing when measuring a pulse width 86 Mitsubishi microcomputers Serial I/O Serial I/O M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O is configured as three channels: UART0, UART1 and UART2. UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 1.17.1 shows the block diagram of UART0, UART1 and UART2. Figure 1.17.2 and figure 1.17.3 show the block diagram of the transmit/receive unit. UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 03A016, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART. UART0 through UART2 are almost equal in their functions with minor exceptions. UART2, in particular, is compliant with the SIM interface with some extra settings added in clock-asynchronous serial I/O mode (Note). It also has the bus collision detection function that generates an interrupt request if the TXD pin and the RXD pin are different in level. Note: SIM : Subscriber Identity Module Table 1.17.1 shows the comparison of functions of UART0 through UART2, and Figures 1.17.4 through 1.17.8 show the registers related to UARTi. Table 1.17.1. Comparison of functions of UART0 through UART2 Function CLK polarity selection LSB first / MSB first selection Continuous receive mode selection Transfer clock output from multiple pins selection Separate CTS/RTS pins Serial data logic switch Sleep mode selection TxD, RxD I/O polarity switch TxD, RxD port output format Parity error signal output Bus collision detection UART0 Possible Possible Possible Impossible Possible Impossible Possible Impossible CMOS output Impossible Impossible (Note 3) (Note 1) (Note 1) (Note 1) UART1 Possible Possible Possible Possible Impossible Impossible Possible Impossible CMOS output Impossible Impossible (Note 3) (Note 1) (Note 1) (Note 1) (Note 1) UART2 Possible Possible Possible Impossible Impossible Possible Impossible Possible N-channel open-drain output Possible Possible (Note 4) (Note 4) (Note 1) (Note 2) (Note 1) Note 1: Only when clock synchronous serial I/O mode. Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode. Note 3: Only when UART mode. Note 4: Using for SIM interface. 87 Mitsubishi microcomputers Serial I/O M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (UART0) RxD0 UART reception TxD0 1/16 Clock source selection f1 f8 f32 Bit rate generator Internal (address 03A116) Clock synchronous type 1/16 Reception control circuit Receive clock Transmit/ receive unit 1 / (n0+1) External UART transmission Clock synchronous type Transmission control circuit Transmit clock Clock synchronous type 1/2 (when internal clock is selected) Clock synchronous type (when internal clock is selected) CLK0 CLK polarity reversing circuit CTS/RTS disabled CTS/RTS selected Clock synchronous type (when external clock is selected) CTS0 / RTS0 Vcc CTS/RTS disabled CTS/RTS separated CTS0 from UART1 RTS0 CTS0 (UART1) RxD1 Clock source selection f1 f8 f32 Bit rate generator Internal (address 03A916) 1/16 TxD1 UART reception Reception control circuit Receive clock Transmit/ receive unit Clock synchronous type UART transmission 1/16 1 / (n1+1) External Clock synchronous type Clock synchronous type 1/2 (when internal clock is selected) Transmission control circuit Transmit clock CLK1 CTS1 / RTS1 CTS0/ CLKS1 CLK polarity reversing circuit Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) CTS/RTS disabled CTS/RTS separated Clock output pin select switch VCC CTS/RTS disabled CTS0 RTS1 CTS1 CTS0 to UART0 TxD polarity reversing circuit Transmit/ receive unit (UART2) RxD2 RxD polarity reversing circuit UART reception 1/16 TxD2 Clock source selection f1 f8 f32 Bit rate generator Internal (address 037916) Clock synchronous type UART transmission 1/16 Reception control circuit Receive clock 1 / (n2+1) External Clock synchronous type Clock synchronous type 1/2 Transmission control circuit Transmit clock (when internal clock is selected) CLK2 CLK polarity reversing circuit Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) CTS/RTS selected CTS/RTS disabled CTS2 / RTS2 Vcc CTS/RTS disabled RTS2 CTS2 n0 : Values set to UART0 bit rate generator (BRG0) n1 : Values set to UART1 bit rate generator (BRG1) n2 : Values set to UART2 bit rate generator (BRG2) Figure 1.17.1. Block diagram of UARTi (i = 0 to 2) 88 Mitsubishi microcomputers Serial I/O M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous type UART (7 bits) UART (8 bits) 1SP PAR disabled Clock synchronous type UART (7 bits) UARTi receive register RxDi SP 2SP SP PAR PAR enabled UART UART (9 bits) Clock synchronous type UART (8 bits) UART (9 bits) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UARTi receive buffer register Address 03A616 Address 03A716 Address 03AE16 Address 03AF16 MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits MSB/LSB conversion circuit D8 D7 D6 D5 D4 D3 D2 D1 D0 UARTi transmit buffer register Address 03A216 Address 03A316 Address 03AA16 Address 03AB16 UART (8 bits) UART (9 bits) UART (9 bits) Clock synchronous type 2SP SP SP 1SP PAR PAR enabled UART TxDi PAR disabled Clock synchronous type UART (7 bits) UART (7 bits) UART (8 bits) Clock synchronous type UARTi transmit register “0” SP: Stop bit PAR: Parity bit Figure 1.17.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit 89 Mitsubishi microcomputers Serial I/O M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER No reverse RxD2 RxD data reverse circuit Reverse Clock synchronous type 1SP SP 2SP SP PAR PAR disabled Clock synchronous type UART (7 bits) UART (8 bits) UART(7 bits) UART2 receive register PAR enabled UART UART (9 bits) Clock synchronous type UART (8 bits) UART (9 bits) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UART2 receive buffer register Address 037E16 Address 037F16 Logic reverse circuit + MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits Logic reverse circuit + MSB/LSB conversion circuit D8 D7 D6 D5 D4 D3 D2 D1 D0 UART2 transmit buffer register Address 037A16 Address 037B16 UART (8 bits) UART (9 bits) PAR enabled UART (9 bits) UART Clock synchronous type 2SP SP SP 1SP PAR PAR disabled Clock synchronous type “0” UART (7 bits) UART (8 bits) Clock synchronous type UART(7 bits) UART2 transmit register Error signal output disable No reverse Error signal output circuit Error signal output enable Reverse TxD data reverse circuit TxD2 SP: Stop bit PAR: Parity bit Figure 1.17.3. Block diagram of UART2 transmit/receive unit 90 Mitsubishi microcomputers Serial I/O M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit buffer register (b15) b7 (b8) b0 b7 b0 Symbol U0TB U1TB U2TB Address 03A316, 03A216 03AB16, 03AA16 037B16, 037A16 When reset Indeterminate Indeterminate Indeterminate Function RW Transmit data Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. UARTi receive buffer register (b15) b7 (b8) b0 b7 b0 Symbol U0RB U1RB U2RB Address 03A716, 03A616 03AF16, 03AE16 037F16, 037E16 When reset Indeterminate Indeterminate Indeterminate Function (During UART mode) Receive data Bit symbol Bit name Function (During clock synchronous serial I/O mode) Receive data RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. OER Overrun error flag (Note) 0 : No overrun error 1 : Overrun error found Invalid Invalid Invalid 0 : No overrun error 1 : Overrun error found 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found FER PER SUM Framing error flag (Note) Parity error flag (Note) Error sum flag (Note) Note: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses 03A016, 03A816 and 037816) are set to “0002” or the receive enable bit is set to “0”. (Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer register (addresses 03A616, 03AE16 and 037E16) is read out. UARTi bit rate generator b7 b0 Symbol U0BRG U1BRG U2BRG Address 03A116 03A916 037916 Function When reset Indeterminate Indeterminate Indeterminate Values that can be set 0016 to FF16 RW Assuming that set value = n, BRGi divides the count source by n+1 Figure 1.17.4. Serial I/O-related registers (1) 91 Mitsubishi microcomputers Serial I/O M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiMR(i=0,1) Address 03A016, 03A816 When reset 0016 Bit symbol SMD0 SMD1 SMD2 Bit name Serial I/O mode select bit Function (During clock synchronous serial I/O mode) Must be fixed to 001 b2 b1 b0 Function (During UART mode) b2 b1 b0 RW 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited 0 : Internal clock 1 : External clock 0 : One stop bit 1 : Two stop bits Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected CKDIR Internal/external clock select bit STPS PRY Stop bit length select bit 0 : Internal clock 1 : External clock Invalid Odd/even parity select bit Invalid PRYE SLEP Parity enable bit Sleep select bit Invalid Must always be “0” UART2 transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2MR Address 037816 When reset 0016 Bit symbol SMD0 SMD1 SMD2 Bit name Serial I/O mode select bit Function (During clock synchronous serial I/O mode) Must be fixed to 001 b2 b1 b0 Function (During UART mode) b2 b1 b0 RW 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited Must always be “0” 0 : One stop bit 1 : Two stop bits Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse Usually set to “0” CKDIR Internal/external clock select bit STPS PRY Stop bit length select bit 0 : Internal clock 1 : External clock Invalid Odd/even parity select bit Invalid PRYE IOPOL Parity enable bit TxD, RxD I/O polarity reverse bit Invalid 0 : No reverse 1 : Reverse Usually set to “0” Figure 1.17.5. Serial I/O-related registers (2) 92 Mitsubishi microcomputers Serial I/O M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiC0(i=0,1) Bit symbol CLK0 CLK1 CRS Address When reset 03A416, 03AC16 0816 Function (During clock synchronous serial I/O mode) b1 b0 b1 b0 Bit name BRG count source select bit Function (During UART mode) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) RW 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) CTS/RTS function select bit TXEPT 0 : Data present in transmit 0 : Data present in transmit register Transmit register empty register (during transmission) (during transmission) flag 1 : No data present in transmit 1 : No data present in transmit register (transmission completed) register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output CRD CTS/RTS disable bit 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge NCH Data output select bit CKPOL CLK polarity select bit Must always be “0” UFORM Transfer format select bit 0 : LSB first 1 : MSB first Must always be “0” Note 1: Set the corresponding port direction register to “0”. Note 2: The settings of the corresponding port register and port direction register are invalid. UART2 transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2C0 Bit symbol CLK0 CLK1 CRS CTS/RTS function select bit Address 037C16 When reset 0816 Function (During clock synchronous serial I/O mode) Function (During UART mode) b1 b0 Bit name BRG count source select bit RW b1 b0 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) TXEPT 0 : Data present in transmit 0 : Data present in transmit register Transmit register empty register (during transmission) (during transmission) flag 1 : No data present in transmit 1 : No data present in transmit register (transmission completed) register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) CRD CTS/RTS disable bit 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) 0: TXDi pin is CMOS output 0 : TXDi pin is CMOS output Nothing is assigned. 1: to be “0”. : TXDi pin is N-channel In an attempt to write to this bit, write1“0”. The value, if read, turns out TXDi pin is N-channel CKPOL CLK polarity select bit open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge open-drain output Must always be “0” UFORM Transfer format select bit 0 : LSB first 1 : MSB first (Note 3) 0 : LSB first 1 : MSB first Note 1: Set the corresponding port direction register to “0”. Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid. Figure 1.17.6. Serial I/O-related registers (3) 93 Mitsubishi microcomputers Serial I/O M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiC1(i=0,1) Address 03A516,03AD16 When reset 0216 Bit symbol TE TI Bit name Transmit enable bit Transmit buffer empty flag Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register RW RE RI Receive enable bit Receive complete flag Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. UART2 transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2C1 Address 037D16 When reset 0216 Bit symbol TE TI Bit name Transmit enable bit Transmit buffer empty flag Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled 0 : No reverse 1 : Reverse Must be fixed to “0” Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) Invalid RW RE RI Receive enable bit Receive complete flag U2IRS UART2 transmit interrupt cause select bit U2RRM UART2 continuous receive mode enable bit U2LCH Data logic select bit U2ERE Error signal output enable bit 0 : No reverse 1 : Reverse 0 : Output disabled 1 : Output enabled Figure 1.17.7. Serial I/O-related registers (4) 94 Mitsubishi microcomputers Serial I/O M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART transmit/receive control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UCON Address 03B016 When reset X00000002 Bit symbol U0IRS Bit name UART0 transmit interrupt cause select bit UART1 transmit interrupt cause select bit Function (During clock synchronous serial I/O mode) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) Function (During UART mode) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) RW U1IRS 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) U0RRM UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Valid when bit 5 = “1” 0 : Clock output to CLK1 1 : Clock output to CLKS1 0 : Normal mode (CLK output is CLK1 only) Invalid U1RRM UART1 continuous receive mode enable bit Invalid CLKMD0 CLK/CLKS select bit 0 Invalid CLKMD1 CLK/CLKS select bit 1 (Note) Must always be “0” 1 : Transfer clock output from multiple pins function selected RCSP Separate CTS/RTS bit 0 : CTS/RTS shared pin 1 : CTS/RTS separated 0 : CTS/RTS shared pin 1 : CTS/RTS separated Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. Note: When using multiple pins to output the transfer clock, the following requirements must be met: • UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”. Figure 1.17.8. Serial I/O-related registers (5) 95 Mitsubishi microcomputers Clock synchronous serial I/O mode (1) Clock synchronous serial I/O mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.17.2 and table 1.17.3 list the specifications of the clock synchronous serial I/O mode. Figure 1.17.9 shows the UARTi transmit/receive mode register. Table 1.17.2. Specifications of clock synchronous serial I/O mode (1) Item Specification Transfer data format • Transfer data length: 8 bits Transfer clock • When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”) : fi/ 2(n+1) (Note 1) fi = f1, f8, f32 • When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “1”) : Input from CLKi pin _______ _______ _______ _______ Transmission/reception control • CTS function/RTS function/CTS, RTS function chosen to be invalid Transmission start condition • To start transmission, the following requirements must be met: _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1” _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0” _______ _______ _ When CTS function selected, CTS input level = “L” • Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”: CLKi input level = “H” _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”: CLKi input level = “L” Reception start condition • To start reception, the following requirements must be met: _ Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1” _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1” _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0” • Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”: CLKi input level = “H” _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”: CLKi input level = “L” • When transmitting Interrupt request _ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at generation timing address 037D16) = “0”: Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed _ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at address 037D16) = “1”: Interrupts requested when data transmission from UARTi transfer register is completed • When receiving _ Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Error detection • Overrun error (Note 2) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit is not set to “1”. 96 Mitsubishi microcomputers Clock synchronous serial I/O mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.17.3. Specifications of clock synchronous serial I/O mode (2) Item Select function Specification • CLK polarity selection Whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected • LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected • Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register • Transfer clock output from multiple pins selection (UART1) (Note) UART1 transfer clock can be chosen by software to be output from one of the two pins set _______ _______ • Separate CTS/RTS pins (UART0) (Note) _______ _______ UART0 CTS and RTS pins each can be assigned to separate pins • Switching serial data logic (UART2) Whether to reverse data in writing to the transmission buffer register or reading the reception buffer register can be selected. • TXD, RXD I/O polarity reverse (UART2) This function is reversing TXD port output and RXD port input. All I/O data level is reversed. _______ _______ Note: The transfer clock output from multiple pins and the separate CTS/RTS pins functions cannot be selected simultaneously. 97 Mitsubishi microcomputers Clock synchronous serial I/O mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive mode registers b7 b6 b5 b4 b3 b2 b1 b0 0 001 Symbol UiMR(i=0,1) Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE SLEP Address 03A016, 03A816 Bit name When reset 0016 Function b2 b1 b0 RW Serial I/O mode select bit 0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock 1 : External clock Internal/external clock select bit Invalid in clock synchronous serial I/O mode 0 (Must always be “0” in clock synchronous serial I/O mode) UART2 transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 0 001 Symbol U2MR Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE IOPOL Address 037816 Bit name When reset 0016 Function b2 b1 b0 RW Serial I/O mode select bit 0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock 1 : External clock Internal/external clock select bit Invalid in clock synchronous serial I/O mode TxD, RxD I/O polarity reverse bit (Note) 0 : No reverse 1 : Reverse Note: Usually set to “0”. Figure 1.17.9. UARTi transmit/receive mode register in clock synchronous serial I/O mode 98 Mitsubishi microcomputers Clock synchronous serial I/O mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.17.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This _______ table shows the pin functions when the transfer clock output from multiple pins and the separate CTS/ _______ RTS pins functions are not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TXDi pin outputs a “H”. (If the N-channel open-drain is selected, this pin is in floating state.) Table 1.17.4. Input/output pin functions in clock synchronous serial I/O mode Pin name Function Method of selection (Outputs dummy data when performing reception only) Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16, bit 1 at address 03EF16)= “0” (Can be used as an input port when performing transmission only) Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “0” Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “1” Port P61, P65 and P72 direction register (bits 1 and 5 at address 03EE16, bit 2 at address 03EF16) = “0” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) =“0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “0” Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16, bit 3 at address 03EF16) = “0” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “1” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “1” _______ _______ TxDi Serial data output (P63, P67, P70) Serial data input RxDi (P62, P66, P71) CLKi Transfer clock output (P61, P65, P72) Transfer clock input CTSi/RTSi CTS input (P60, P64, P73) RTS output Programmable I/O port (when transfer clock output from multiple pins and separate CTS/RTS pins functions are not selected) 99 Mitsubishi microcomputers Clock synchronous serial I/O mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER • Example of transmit timing (when internal clock is selected) Tc Transfer clock “1” “0” “1” “0” Transferred from UARTi transmit buffer register to UARTi transmit register “H” Data is set in UARTi transmit buffer register Transmit enable bit (TE) Transmit buffer empty flag (Tl) CTSi “L” TCLK Stopped pulsing because CTS = “H” Stopped pulsing because transfer enable bit = “0” CLKi TxDi Transmit register empty flag (TXEPT) “1” “0” D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D 0 D 1 D 2 D 3 D 4 D 5 D6 D 7 Transmit interrupt “1” request bit (IR) “0” Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: • Internal clock is selected. • CTS function is selected. • CLK polarity select bit = “0”. • Transmit interrupt cause select bit = “0”. Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f1, f8, f32) n: value set to BRGi • Example of receive timing (when external clock is selected) Receive enable bit (RE) Transmit enable bit (TE) Transmit buffer empty flag (Tl) RTSi “1” “0” “1” “0” “1” “0” “H” “L” Dummy data is set in UARTi transmit buffer register Transferred from UARTi transmit buffer register to UARTi transmit register 1 / fEXT Receive data is taken in CLKi RxDi Receive complete “1” flag (Rl) “0” Receive interrupt request bit (IR) “1” “0” D 0 D1 D 2 D3 D 4 D5 D6 D 7 Transferred from UARTi receive register to UARTi receive buffer register D0 D 1 D 2 D3 D4 D5 Read out from UARTi receive buffer register Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: • External clock is selected. • RTS function is selected. • CLK polarity select bit = “0”. fEXT: frequency of external clock Meet the following conditions are met when the CLK input before data reception = “H” • Transmit enable bit “1” • Receive enable bit “1” • Dummy data write to UARTi transmit buffer register Figure 1.17.10. Typical transmit/receive timings in clock synchronous serial I/O mode 100 Mitsubishi microcomputers Clock synchronous serial I/O mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (a) Polarity select function As shown in Figure 1.17.11, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) allows selection of the polarity of the transfer clock. • When CLK polarity select bit = “0” CLKi TXDi R XD i D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Note 1: The CLK pin level when not transferring data is “H”. • When CLK polarity select bit = “1” CLKi TXDi R XD i D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Note 2: The CLK pin level when not transferring data is “L”. Figure 1.17.11. Polarity of transfer clock (b) LSB first/MSB first select function As shown in Figure 1.17.12, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16, 037C16) = “0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”. • When transfer format select bit = “0” CLKi TXDi R XD i D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 LSB first D7 • When transfer format select bit = “1” CLKi TXDi R XD i D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 MSB first D0 Note: This applies when the CLK polarity select bit = “0”. Figure 1.17.12. Transfer format 101 Mitsubishi microcomputers Clock synchronous serial I/O mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (c) Transfer clock output from multiple pins function (UART1) This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.17.13.) The multiple pins function is valid only when the internal clock is selected for UART1. Note that when _______ _______ this function is selected, UART1 CTS/RTS function cannot be used. Microcomputer TXD1 (P67) CLKS1 (P64) CLK1 (P65) IN CLK IN CLK Note: This applies when the internal clock is selected and transmission is performed only in clock synchronous serial I/O mode. Figure 1.17.13. The transfer clock output from the multiple pins function usage (d) Continuous receive mode If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) is set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. _______ _______ (e) Separate CTS/RTS pins function (UART0) This function works the same way as in the clock asynchronous serial I/O (UART) mode. The method of setting and the input/output pin functions are both the same, so refer to select function in the next section, “(2) Clock asynchronous serial I/O (UART) mode.” Note that this function is invalid if the transfer clock output from the multiple pins function is selected. (f) Serial data logic switch function (UART2) When the data logic select bit (bit6 at address 037D16) = “1”, and writing to transmit buffer register or reading from receive buffer register, data is reversed. Figure 1.17.14 shows the example of serial data logic switch timing. •When LSB first Transfer clock TxD2 “H” “L” “H” (no reverse) “L” D0 D1 D2 D3 D4 D5 D6 D7 TxD2 “H” (reverse) “L” D0 D1 D2 D3 D4 D5 D6 D7 Figure 1.17.14. Serial data logic switch timing 102 Mitsubishi microcomputers Clock asynchronous serial I/O (UART) mode (2) Clock asynchronous serial I/O (UART) mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Table 1.17.5 and table 1.17.6 list the specifications of the UART mode. Figure 1.17.15 shows the UARTi transmit/receive mode register. Table 1.17.5. Specifications of UART Mode (1) Item Transfer data format Specification • Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected • Start bit: 1 bit • Parity bit: Odd, even, or nothing as selected • Stop bit: 1 bit or 2 bits as selected • When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”) : fi/16(n+1) (Note 1) fi = f1, f8, f32 • When external clock is selected (bit 3 at addresses 03A016, 03A816 =“1”) : fEXT/16(n+1) (Note 1) (Note 2) (Do not set external clock for UART2) _______ _______ _______ _______ Transfer clock Transmission/reception control • CTS function/RTS function/CTS, RTS function chosen to be invalid Transmission start condition • To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1” - Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0” _______ _______ - When CTS function selected, CTS input level = “L” Reception start condition • To start reception, the following requirements must be met: - Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1” - Start bit detection Interrupt request • When transmitting generation timing - Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at address 037D16) = “0”: Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed - Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at address 037D16) = “1”: Interrupts requested when data transmission from UARTi transfer register is completed • When receiving - Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Error detection • Overrun error (Note 3) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out • Framing error This error occurs when the number of stop bits set is not detected • Parity error This error occurs when if parity is enabled, the number of 1’s in parity and character bits does not match the number of 1’s set • Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: fEXT is input from the CLKi pin. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit is not set to “1”. 103 Mitsubishi microcomputers Clock asynchronous serial I/O (UART) mode Table 1.17.6. Specifications of UART Mode (2) Item _______ _______ M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Specification • Separate CTS/RTS pins (UART0) _______ _______ UART0 CTS and RTS pins each can be assigned to separate pins • Sleep mode selection (UART0, UART1) This mode is used to transfer data to and from one of multiple slave microcomputers • Serial data logic switch (UART2) This function is reversing logic value of transferring data. Start bit, parity bit and stop bit are not reversed. • TXD, RXD I/O polarity switch This function is reversing TXD port output and RXD port input. All I/O data level is reversed. Select function 104 Mitsubishi microcomputers Clock asynchronous serial I/O (UART) mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit / receive mode registers b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiMR(i=0,1) Address 03A016, 03A816 When reset 0016 Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY Bit name Serial I/O mode select bit b2 b1 b0 Function 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 : Internal clock 1 : External clock 0 : One stop bit 1 : Two stop bits Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected RW Internal / external clock select bit Stop bit length select bit Odd / even parity select bit Parity enable bit Sleep select bit PRYE SLEP UART2 transmit / receive mode register b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol U2MR Address 037816 When reset 0016 Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY Bit name Serial I/O mode select bit b2 b1 b0 Function 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long Must always be “0” 0 : One stop bit 1 : Two stop bits Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse RW Internal / external clock select bit Stop bit length select bit Odd / even parity select bit Parity enable bit TxD, RxD I/O polarity reverse bit (Note) PRYE IOPOL Note: Usually set to “0”. Figure 1.17.15. UARTi transmit/receive mode register in UART mode 105 Mitsubishi microcomputers Clock asynchronous serial I/O (UART) mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.17.7 lists the functions of the input/output pins during UART mode. This table shows the pin _______ _______ functions when the separate CTS/RTS pins function is not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TXDi pin outputs a “H”. (If the N-channel open-drain is selected, this pin is in floating state.) Table 1.17.7. Input/output pin functions in UART mode Pin name Function TxDi Serial data output (P63, P67, P70) RxDi Serial data input (P62, P66, P71) CLKi Programmable I/O port (P61, P65, P72) Transfer clock input Method of selection Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16, bit 1 at address 03EF16)= “0” (Can be used as an input port when performing transmission only) Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “0” Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “1” Port P61, P65 direction register (bits 1 and 5 at address 03EE16) = “0” (Do not set external clock for UART2) CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) =“0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “0” Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16, bit 3 at address 03EF16) = “0” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “1” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “1” CTSi/RTSi CTS input (P60, P64, P73) RTS output Programmable I/O port ________ _______ (when separate CTS/RTS pins function is not selected) 106 Mitsubishi microcomputers Clock asynchronous serial I/O (UART) mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) The transfer clock stops momentarily as CTS is “H” when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTS changes to “L”. Tc Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI) “1” “0” “1” “0” Data is set in UARTi transmit buffer register. Transferred from UARTi transmit buffer register to UARTi transmit register “H” CTSi “L” Start bit TxDi “1” Transmit register empty flag (TXEPT) “0” “1” “0” Parity bit P Stop bit SP Stopped pulsing because transmit enable bit = “0” ST D0 D1 ST D0 D1 D2 D3 D4 D5 D6 D7 ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Transmit interrupt request bit (IR) Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is enabled. • One stop bit. • CTS function is selected. • Transmit interrupt cause select bit = “1”. Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi • Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) Tc Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI) “1” “0” “1” “0” Data is set in UARTi transmit buffer register Transferred from UARTi transmit buffer register to UARTi transmit register Start bit TxDi “1” Transmit register empty flag (TXEPT) “0” “1” “0” Stop bit Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP ST D0 D1 ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP Transmit interrupt request bit (IR) Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is disabled. • Two stop bits. • CTS function is disabled. • Transmit interrupt cause select bit = “0”. Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Figure 1.17.16. Typical transmit timings in UART mode (UART0, UART1) 107 Mitsubishi microcomputers Clock asynchronous serial I/O (UART) mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Tc Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI) “1” “0” “1” “0” Data is set in UART2 transmit buffer register Note Transferred from UART2 transmit buffer register to UARTi transmit register Start bit Parity bit P TxD2 Stop bit SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 “1” Transmit register empty flag (TXEPT) “0” Transmit interrupt request bit (IR) “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is enabled. • One stop bit. • Transmit interrupt cause select bit = “1”. Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2 Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing. Figure 1.17.17. Typical transmit timings in UART mode (UART2) 108 Mitsubishi microcomputers Clock asynchronous serial I/O (UART) mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) BRGi count source Receive enable bit RxDi “1” “0” Start bit Sampled “L” Receive data taken in Transfer clock Receive complete flag RTSi Receive interrupt request bit “1” “0” “H” “L” “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software The above timing applies to the following settings : •Parity is disabled. •One stop bit. •RTS function is selected. Reception triggered when transfer clock is generated by falling edge of start bit Transferred from UARTi receive register to UARTi receive buffer register Stop bit D0 D1 D7 Figure 1.17.18. Typical receive timing in UART mode _______ _______ (a) Separate CTS/RTS pins function (UART0) _______ _______ _______ Setting the CTS/RTS separate bit (bit 6 of address 03B016) to "1" inputs/outputs the CTS signal and _______ _______ _______ _______ _______ RTS signal from different pins. Choose which to use, CTS or RTS, by use of the CTS/RTS function select bit (bit 2 of address 03A416). This function is effective in UART0 only. With this function chosen, _______ _______ _______ _______ the user cannot use the CTS/RTS function. Set "0" both to the CTS/RTS function select bit (bit 2 of _______ _______ address 03AC16) and to the CTS/RTS disable bit (bit 4 of address 03AC16). Microcomputer TXD0 (P63) RXD0 (P62) IN OUT IC RTS0 (P60) CTS0 (P64) CTS RTS Note : The user cannot use CTS and RTS at the same time. _______ _______ Figure 1.17.19. The separate CTS/RTS pins function usage (b) Sleep mode (UART0, UART1) This mode is used to transfer data between specific microcomputers among multiple microcomputers connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”. 109 Mitsubishi microcomputers Clock asynchronous serial I/O (UART) mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (c) Function for switching serial data logic (UART2) When the data logic select bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. Figure 1.17.20 shows the example of timing for switching serial data logic. • When LSB first, parity enabled, one stop bit Transfer clock TxD2 (no reverse) “H” “L” “H” “L” “H” “L” ST D0 D1 D2 D3 D4 D5 D6 D7 P SP TxD2 (reverse) ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST : Start bit P : Even parity SP : Stop bit Figure 1.17.20. Timing for switching serial data logic (d) TxD, RxD I/O polarity reverse function (UART2) This function is to reverse TXD pin output and RXD pin input. The level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for usual use. (e) Bus collision detection function (UART2) This function is to sample the output level of the TXD pin and the input level of the RXD pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.17.21 shows the example of detection timing of a buss collision (in UART mode). Transfer clock “H” “L” TxD2 “H” “L” ST SP RxD2 Bus collision detection interrupt request signal Bus collision detection interrupt request bit “H” “L” “1” “0” “1” “0” ST SP ST : Start bit SP : Stop bit Figure 1.17.21. Detection timing of a bus collision (in UART mode) 110 Mitsubishi microcomputers Clock asynchronous serial I/O (UART) mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (3) Clock-asynchronous serial I/O mode (compliant with the SIM interface) The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table 1.17.8 shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface). Table 1.17.8. Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface) Item Transfer data format Specification • Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = “1012”) • One stop bit (bit 4 of address 037816 = “0”) • With the direct format chosen Set parity to “even” (bit 5 and bit 6 of address 037816 = “1” and “1” respectively) Set data logic to “direct” (bit 6 of address 037D16 = “0”). Set transfer format to LSB (bit 7 of address 037C16 = “0”). • With the inverse format chosen Set parity to “odd” (bit 5 and bit 6 of address 037816 = “0” and “1” respectively) Set data logic to “inverse” (bit 6 of address 037D16 = “1”) Set transfer format to MSB (bit 7 of address 037C16 = “1”) • With the internal clock chosen (bit 3 of address 037816 = “0”) : fi / 16 (n + 1) (Note 1) : fi=f1, f8, f32 (Do not set external clock) _______ _______ Transfer clock Transmission / reception control • Disable the CTS and RTS function (bit 4 of address 037C16 = “1”) Other settings • The sleep mode select function is not available for UART2 • Set transmission interrupt factor to “transmission completed” (bit 4 of address 037D16 = “1”) Transmission start condition • To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 of address 037D16) = “1” - Transmit buffer empty flag (bit 1 of address 037D16) = “0” Reception start condition • To start reception, the following requirements must be met: - Reception enable bit (bit 2 of address 037D16) = “1” - Detection of a start bit Interrupt request • When transmitting generation timing When data transmission from the UART2 transfer register is completed (bit 4 of address 037D16 = “1”) • When receiving When data transfer from the UART2 receive register to the UART2 receive buffer register is completed Error detection • Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 3) • Framing error (see the specifications of clock-asynchronous serial I/O) • Parity error (see the specifications of clock-asynchronous serial I/O) - On the reception side, an “L” level is output from the TXD2 pin by use of the parity error signal output function (bit 7 of address 037D16 = “1”) when a parity error is detected - On the transmission side, a parity error is detected by the level of input to the RXD2 pin when a transmission interrupt occurs • The error sum flag (see the specifications of clock-asynchronous serial I/O) Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: fEXT is input from the CLK2 pin. Note 3: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit is not set to “1”. 111 Mitsubishi microcomputers Clock asynchronous serial I/O (UART) mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Tc Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI) “1” “0” “1” “0” Data is set in UART2 transmit buffer register Note Transferred from UART2 transmit buffer register to UART2 transmit register Start bit Parity bit P Stop bit SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP TxD2 RxD2 ST D0 D1 D2 D3 D4 D5 D6 D7 A “L” level returns from TxD2 due to the occurrence of a parity error. Signal conductor level (Note 1) “1” Transmit register empty flag (TXEPT) “0” “1” “0” ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 The level is detected by the interrupt routine. P SP The level is detected by the interrupt routine. Transmit interrupt request bit (IR) Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is enabled. • One stop bit. • Transmit interrupt cause select bit = “1”. Cleared to “0” when interrupt request is accepted, or cleared by software Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2 Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing. Tc Transfer clock Receive enable bit (RE) “1” “0” Start bit Parity bit P Stop bit SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP RxD2 TxD2 ST D0 D1 D2 D3 D4 D5 D6 D7 A “L” level returns from TxD2 due to the occurrence of a parity error. Signal conductor level (Note 1) Receive complete flag (RI) Receive interrupt request bit (IR) “1” “0” “1” “0” ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Read to receive buffer Read to receive buffer Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is enabled. • One stop bit. • Transmit interrupt cause select bit = “0” Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2 Figure 1.17.22. Typical transmit/receive timing in UART mode (compliant with the SIM interface) 112 Mitsubishi microcomputers Clock asynchronous serial I/O (UART) mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (a) Function for outputting a parity error signal With the error signal output enable bit (bit 7 of address 037D16) assigned “1”, you can output an “L” level from the TXD2 pin when a parity error is detected. In step with this function, the generation timing of a transmission completion interrupt changes to the detection timing of a parity error signal. Figure 1.17.23 shows the output timing of the parity error signal. • LSB first Transfer clock RxD2 TxD2 Receive complete flag “H” “L” “H” “L” “H” “L” “1” “0” ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Hi-Z ST : Start bit P : Even Parity SP : Stop bit Figure 1.17.23. Output timing of the parity error signal (b) Direct format/inverse format Connecting the SIM card allows you to switch between direct format and inverse format. If you choose the direct format, D0 data is output from TXD2. If you choose the inverse format, D7 data is inverted and output from TXD2. Figure 1.17.24 shows the SIM interface format. Transfer clcck TxD2 (direct) TxD2 (inverse) D0 D1 D2 D3 D4 D5 D6 D7 P D7 D6 D5 D4 D3 D2 D1 D0 P P : Even parity Figure 1.17.24. SIM interface format 113 Mitsubishi microcomputers Clock asynchronous serial I/O (UART) mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.17.25 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pullup. Microcomputer SIM card TxD2 RxD2 Figure 1.17.25. Connecting the SIM interface 114 Mitsubishi microcomputers A-D Converter A-D Converter M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P100 to P107, P95, and P96 also function as the analog signal input pins. The direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF. The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Table 1.18.1 shows the performance of the A-D converter. Figure 1.18.1 shows the block diagram of the AD converter, and Figures 1.18.2 and 1.18.3 show the A-D converter-related registers. Table 1.18.1. Performance of A-D converter Item Performance Method of A-D conversion Successive approximation (capacitive coupling amplifier) Analog input voltage (Note 1) 0V to AVCC (VCC) Operating clock φAD (Note 2) VCC = 5V fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN) VCC = 3V divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN) Resolution 8-bit or 10-bit (selectable) Absolute precision VCC = 5V • Without sample and hold function ±3LSB • With sample and hold function (8-bit resolution) ±2LSB • With sample and hold function (10-bit resolution) AN0 to AN7 input : ±3LSB ANEX0 and ANEX1 input (including mode in which external operation amp is connected) : ±7LSB VCC = 3V • Without sample and hold function (8-bit resolution) ±2LSB Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 Analog input pins 8pins (AN0 to AN7) + 2pins (ANEX0 and ANEX1) A-D conversion start condition • Software trigger A-D conversion starts when the A-D conversion start flag changes to “1” • External trigger (can be retriggered) A-D conversion starts when the A-D conversion start flag is “1” and the ___________ ADTRG/P97 input changes from “H” to “L” Conversion speed per pin • Without sample and hold function 8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles • With sample and hold function 8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles Note 1: Does not depend on use of sample and hold function. Note 2: Without sample and hold function, set the φAD frequency to 250kHz min. With the sample and hold function, set the φAD frequency to 1MHz min. 115 Mitsubishi microcomputers A-D Converter M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CKS1=1 fAD 1/2 1/2 CKS0=1 CKS1=0 φAD A-D conversion rate selection CKS0=0 V REF VCUT=0 Resistor ladder AV SS VCUT=1 Successive conversion register A-D control register 1 (address 03D716) A-D control register 0 (address 03D616) Addresses (03C116, 03C016) (03C316, 03C216) (03C516, 03C416) (03C716, 03C616) (03C916, 03C816) (03CB16, 03CA16) (03CD16, 03CC16) (03CF16, 03CE16) A-D register 0(16) A-D register 1(16) A-D register 2(16) A-D register 3(16) A-D register 4(16) A-D register 5(16) A-D register 6(16) A-D register 7(16) VIN Comparator Vref Decoder Data bus high-order Data bus low-order AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 CH2,CH1,CH0=000 CH2,CH1,CH0=001 CH2,CH1,CH0=010 CH2,CH1,CH0=011 CH2,CH1,CH0=100 CH2,CH1,CH0=101 CH2,CH1,CH0=110 CH2,CH1,CH0=111 OPA1, OPA0 OPA1,OPA0=0,0 OPA1,OPA0=1,1 OPA0=1 0 0 1 1 0 : Normal operation 1 : ANEX0 0 : ANEX1 1 : External op-amp mode ANEX0 OPA1,OPA0=0,1 ANEX1 OPA1=1 Figure 1.18.1. Block diagram of A-D converter 116 Mitsubishi microcomputers A-D Converter M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON0 Bit symbol CH0 Address 03D616 Bit name When reset 00000XXX2 Function b2 b1 b0 RW Analog input pin select bit CH1 CH2 MD0 MD1 TRG ADST CKS0 Trigger select bit A-D conversion start flag Frequency select bit 0 A-D operation mode select bit 0 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b4 b3 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D control register 1 (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON1 Bit symbol SCAN0 Address 03D716 Bit name When reset 0016 Function When single sweep and repeat sweep mode 0 are selected b1 b0 RW A-D sweep pin select bit 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) SCAN1 When repeat sweep mode 1 is selected b1 b0 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) MD2 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit External op-amp connection mode bit 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 0 : Vref not connected 1 : Vref connected b7 b6 BITS CKS1 VCUT OPA0 OPA1 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Figure 1.18.2. A-D converter-related registers (1) 117 Mitsubishi microcomputers A-D Converter M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D control register 2 (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON2 Address 03D416 When reset 0000XXX02 000 Bit symbol SMP Reserved bit Bit name A-D conversion method select bit Function 0 : Without sample and hold 1 : With sample and hold Always set to “0” RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D register i (b15) b7 (b8) b0 b7 Symbol ADi(i=0 to 7) Address When reset 03C016 to 03CF16 Indeterminate b0 Function Eight low-order bits of A-D conversion result • During 10-bit mode Two high-order bits of A-D conversion result • During 8-bit mode When read, the content is indeterminate Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. RW Figure 1.18.3. A-D converter-related registers (2) 118 Mitsubishi microcomputers A-D Converter (1) One-shot mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conversion. Table 1.18.2 shows the specifications of one-shot mode. Figure 1.18.4 shows the A-D control register in one-shot mode. Table 1.18.2. One-shot mode specifications Item Function Start condition Stop condition Specification The pin selected by the analog input pin select bit is used for one A-D conversion Writing “1” to A-D conversion start flag • End of A-D conversion (A-D conversion start flag changes to “0”, except when external trigger is selected) • Writing “0” to A-D conversion start flag End of A-D conversion One of AN0 to AN7, as selected Read A-D register corresponding to selected pin Interrupt request generation timing Input pin Reading of result of A-D converter A-D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol ADCON0 Bit symbol CH0 Address 03D616 Bit name When reset 00000XXX2 Function b2 b1 b0 RW Analog input pin select bit CH1 CH2 MD0 MD1 TRG ADST CKS0 A-D operation mode select bit 0 Trigger select bit 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b4 b3 (Note 2) (Note 2) 0 0 : One-shot mode 0 : Software trigger 1 : ADTRG trigger A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0: fAD/4 is selected 1: fAD/2 is selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. A-D control register 1 (Note) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit symbol SCAN0 SCAN1 MD2 BITS CKS1 VCUT OPA0 OPA1 Address 03D716 Bit name When reset 0016 Function Invalid in one-shot mode RW A-D sweep pin select bit A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit1 Vref connect bit External op-amp connection mode bit 0 : Any mode other than repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected b7 b6 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Figure 1.18.4. A-D conversion register in one-shot mode 119 Mitsubishi microcomputers A-D Converter (2) Repeat mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. Table 1.18.3 shows the specifications of repeat mode. Figure 1.18.5 shows the A-D control register in repeat mode. Table 1.18.3. Repeat mode specifications Item Function Star condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter Specification The pin selected by the analog input pin select bit is used for repeated A-D conversion Writing “1” to A-D conversion start flag Writing “0” to A-D conversion start flag None generated One of AN0 to AN7, as selected Read A-D register corresponding to selected pin A-D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 01 Symbol ADCON0 Bit symbol CH0 CH1 Address 03D616 Bit name When reset 00000XXX2 Function b2 b1 b0 RW Analog input pin select bit CH2 MD0 MD1 TRG ADST CKS0 A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b4 b3 (Note 2) (Note 2) 0 1 : Repeat mode 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. A-D control register 1 (Note) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit symbol SCAN0 SCAN1 MD2 BITS CKS1 VCUT OPA0 OPA1 Address 03D716 Bit name When reset 0016 Function Invalid in repeat mode RW A-D sweep pin select bit A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit External op-amp connection mode bit 0 : Any mode other than repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected b7 b6 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Figure 1.18.5. A-D conversion register in repeat mode 120 Mitsubishi microcomputers A-D Converter (3) Single sweep mode M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D conversion. Table 1.18.4 shows the specifications of single sweep mode. Figure 1.18.6 shows the A-D control register in single sweep mode. Table 1.18.4. Single sweep mode specifications Item Specification Function The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion Start condition Writing “1” to A-D converter start flag Stop condition • End of A-D conversion (A-D conversion start flag changes to “0”, except when external trigger is selected) • Writing “0” to A-D conversion start flag Interrupt request generation timing End of A-D conversion Input pin AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Reading of result of A-D converter Read A-D register corresponding to selected pin A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 10 Symbol ADCON0 Bit symbol CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 Address 03D616 Bit name When reset 00000XXX2 Function Invalid in single sweep mode RW Analog input pin select bit A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0 b4 b3 1 0 : Single sweep mode 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit symbol SCAN0 Address 03D716 Bit name When reset 0016 Function When single sweep and repeat sweep mode 0 are selected b1 b0 RW A-D sweep pin select bit SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit External op-amp connection mode bit (Note 2) 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) 0 : Any mode other than repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected b7 b6 MD2 BITS CKS1 VCUT OPA0 OPA1 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit. Figure 1.18.6. A-D conversion register in single sweep mode 121 Mitsubishi microcomputers A-D Converter (4) Repeat sweep mode 0 M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep A-D conversion. Table 1.18.5 shows the specifications of repeat sweep mode 0. Figure 1.18.7 shows the A-D control register in repeat sweep mode 0. Table 1.18.5. Repeat sweep mode 0 specifications Item Function Start condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter Specification The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion Writing “1” to A-D conversion start flag Writing “0” to A-D conversion start flag None generated AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Read A-D register corresponding to selected pin (at any time) A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 11 Symbol ADCON0 Bit symbol CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 Address 03D616 Bit name When reset 00000XXX2 Function Invalid in repeat sweep mode 0 RW Analog input pin select bit A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0 b4 b3 1 1 : Repeat sweep mode 0 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit symbol SCAN0 Address 03D716 Bit name When reset 0016 Function When single sweep and repeat sweep mode 0 are selected b1 b0 RW A-D sweep pin select bit SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit External op-amp connection mode bit (Note 2) 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) 0 : Any mode other than repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected b7 b6 MD2 BITS CKS1 VCUT OPA0 OPA1 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: Neither “01” nor “10” can be selected with the external op-amp connection mode bit. Figure 1.18.7. A-D conversion register in repeat sweep mode 0 122 Mitsubishi microcomputers A-D Converter (5) Repeat sweep mode 1 M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the A-D sweep pin select bit. Table 1.18.6 shows the specifications of repeat sweep mode 1. Figure 1.18.8 shows the A-D control register in repeat sweep mode 1. Table 1.18.6. Repeat sweep mode 1 specifications Item Function Specification All pins perform repeat sweep A-D conversion, with emphasis on the pin or pins selected by the A-D sweep pin select bit Example : AN0 selected AN0 AN1 AN0 AN2 AN0 AN3, etc Writing “1” to A-D conversion start flag Writing “0” to A-D conversion start flag None generated AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins) Read A-D register corresponding to selected pin (at any time) Start condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 11 Symbol ADCON0 Bit symbol CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 Address 03D616 Bit name When reset 00000XXX2 Function Invalid in repeat sweep mode 1 RW Analog input pin select bit A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0 b4 b3 1 1 : Repeat sweep mode 1 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol ADCON1 Bit symbol SCAN0 Address 03D716 Bit name When reset 0016 Function When repeat sweep mode 1 is selected b1 b0 RW A-D sweep pin select bit SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit External op-amp connection mode bit (Note 2) 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) 1 : Repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected b7 b6 MD2 BITS CKS1 VCUT OPA0 OPA1 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit. Figure 1.18.8. A-D conversion register in repeat sweep mode 1 123 Mitsubishi microcomputers A-D Converter (a) Sample and hold M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 φAD cycle is achieved with 8-bit resolution and 33 φAD with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold is to be used. (b) Extended analog input pins In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can also be converted from analog to digital. When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “0”, input via ANEX0 is converted from analog to digital. The result of conversion is stored in A-D register 0. When bit 6 of the A-D control register 1 (address 03D716) is “0” and bit 7 is “1”, input via ANEX1 is converted from analog to digital. The result of conversion is stored in A-D register 1. (c) External operation amp connection mode In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can be amplified together by just one operation amp and used as the input for A-D conversion. When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “1”, input via AN0 to AN7 is output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in the corresponding A-D register. The speed of A-D conversion depends on the response of the external operation amp. Do not connect the ANEX0 and ANEX1 pins directly. Figure 1.18.9 is an example of how to connect the pins in external operation amp mode. Resistor ladder Successive conversion register Analog input AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ANEX0 ANEX1 Comparator External op-amp Figure 1.18.9. Example of external op-amp connection mode 124 Mitsubishi microcomputers D-A Converter D-A Converter M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of this type. D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the target port to output mode if D-A conversion is to be performed. Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register. V = VREF X n/ 256 (n = 0 to 255) VREF : reference voltage Table 1.19.1 lists the performance of the D-A converter. Figure 1.19.1 shows the block diagram of the D-A converter. Figure 1.19.2 shows the D-A control register. Figure 1.19.3 shows the D-A converter equivalent circuit. Table 1.19.1. Performance of D-A converter Item Conversion method Resolution Analog output pin Performance R-2R method 8 bits 2 channels Data bus low-order bits D-A register0 (8) (Address 03D816) D-A0 output enable bit R-2R resistor ladder P93/DA0 D-A register1 (8) (Address 03DA16) D-A1 output enable bit R-2R resistor ladder P94/DA1 Figure 1.19.1. Block diagram of D-A converter 125 Mitsubishi microcomputers D-A Converter M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER D-A control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DACON Bit symbol DA0E DA1E Address 03DC16 Bit name D-A0 output enable bit D-A1 output enable bit When reset 0016 Function 0 : Output disabled 1 : Output enabled 0 : Output disabled 1 : Output enabled RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. D-A register b7 b0 Symbol DAi (i = 0,1) Address 03D816, 03DA16 When reset Indeterminate Function Output value of D-A conversion RW RW Figure 1.19.2. D-A control register D-A0 output enable bit "0" DA0 "1" 2R MSB D-A0 register0 2R 2R 2R 2R 2R 2R 2R LSB R R R R R R R 2R AVSS VREF Note 1: The above diagram shows an instance in which the D-A register is assigned 2A16. Note 2: The same circuit as this is also used for D-A1. Note 3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to 0 and set the D-A register to 0016 so that no current flows in the resistors Rs and 2Rs. Figure 1.19.3. D-A converter equivalent circuit 126 Mitsubishi microcomputers CRC M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CRC Calculation Circuit The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcomputer uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code. The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC code is set in a CRC data register each time one byte of data is transferred to a CRC input register after writing an initial value into the CRC data register. Generation of CRC code for one byte of data is completed in two machine cycles. Figure 1.20.1 shows the block diagram of the CRC circuit. Figure 1.20.2 shows the CRC-related registers. Figure 1.20.3 shows the calculation example using the CRC calculation circuit Data bus high-order bits Data bus low-order bits Eight low-order bits CRC data register (16) Eight high-order bits (Addresses 03BD16, 03BC16) CRC code generating circuit x16 + x12 + x5 + 1 CRC input register (8) (Address 03BE16) Figure 1.20.1. Block diagram of CRC circuit CRC data register (b15) b7 (b8) b0 b7 b0 Symbol CRCD Address 03BD16, 03BC16 When reset Indeterminate Values that can be set 000016 to FFFF16 Function CRC calculation result output register RW CRC input register b7 b0 Symbo CRCIN Function Data input register Address 03BE16 When reset Indeterminate Values that can be set 0016 to FF16 RW Figure 1.20.2. CRC-related registers 127 Mitsubishi microcomputers CRC M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER b15 b0 (1) Setting 000016 CRC data register CRCD [03BD16, 03BC16] b7 b0 (2) Setting 0116 CRC input register CRCIN [03BE16] 2 cycles After CRC calculation is complete b15 b0 118916 CRC data register CRCD [03BD16, 03BC16] Stores CRC code The code resulting from sending 0116 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial, (X16 + X12 + X5 + 1), becomes the remainder resulting from dividing (1000 0000) X16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. LSB 1000 1000 1 0001 0000 0010 0001 1000 0000 0000 1000 1000 0001 1000 0001 1000 1000 1001 LSB 8 1 0000 0000 0000 0001 0001 1 0000 1 1000 0000 1000 0000 0 1 1000 MSB MSB Modulo-2 operation is operation that complies with the law given below. 0+0=0 0+1=1 1+0=1 1+1=0 -1 = 1 9 Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000) corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC operation. Also switch between the MSB and LSB of the result as stored in CRC data. b7 b0 (3) Setting 2316 CRC input register CRCIN [03BE16] After CRC calculation is complete b15 b0 0A4116 CRC data register CRCD [03BD16, 03BC16] Stores CRC code Figure 1.20.3. Calculation example using the CRC calculation circuit 128 Mitsubishi microcomputers Programmable I/O Port M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Ports There are 87 programmable I/O ports: P0 to P10 (excluding P85). Each port can be set independently for input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P85 is an input-only port and has no built-in pull-up resistance. Figures 1.21.1 to 1.21.4 show the programmable I/O ports. Figure 1.21.5 shows the I/O pins. Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices. To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A converter), they function as outputs regardless of the contents of the direction registers. When pins are to be used as the outputs for the D-A converter, do not set the direction registers to output mode. See the descriptions of the respective functions for how to set up the built-in peripheral devices. (1) Direction registers Figure 1.21.6 shows the direction registers. These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin. Note: There is no direction register bit for P85. (2) Port registers Figure 1.21.7 shows the port registers. These registers are used to write and read data for input and output to and from an external device. A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port registers corresponds one for one to each I/O pin. (3) Pull-up control registers Figure 1.21.8 shows the pull-up control registers. The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. However, in memory expansion mode and microprocessor mode, the pull-up control register of P0 to P5 is invalid. 129 Mitsubishi microcomputers Programmable I/O Port M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up selection P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P54, P56 Data bus Direction register Port latch (Note) Pull-up selection P55, P62, P66, P75, P77, P81 to P84, P90 to P92, P97 Data bus Direction register Port latch (Note) Input to respective peripheral functions Pull-up selection P63, P67 Direction register “1” Output Data bus Port latch (Note) Pull-up selection P57, P60, P61, P64, P65, P72 to P74, P76, P80 Direction register “1” Output Data bus Port latch (Note) Input to respective peripheral functions Note : symbolizes a parasitic diode. Do not apply a voltage higher than VCC to each port. Figure 1.21.1. Programmable I/O ports (1) 130 Mitsubishi microcomputers Programmable I/O Port M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up selection P82 to P84 Direction register Data bus Port latch (Note 1) Input to respective peripheral functions P70 Direction register “1” Data bus Port latch output (Note 2) P71 Direction register Data bus Port latch (Note 2) Input to respective peripheral functions P85 Data bus NMI interrupt input (Note 1) Note 1 : symbolizes a parasitic diode. Do not apply a voltage higher than VCC to each port. Note 2 : symbolizes a parasitic diode. Figure 1.21.2. Programmable I/O ports (2) 131 Mitsubishi microcomputers Programmable I/O Port M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up selection P95, P96, P100 to P103 (inside dotted-line not included) P104 to P107 (inside dotted-line included) Data bus Direction register Port latch (Note) Analog input Pull-up selection D-A output enabled P93, P94 Direction register Data bus Port latch (Note) Analog input D-A output enabled Note : symbolizes a parasitic diode. Do not apply a voltage higher than VCC to each port. Figure 1.21.3. Programmable I/O ports (3) 132 Mitsubishi microcomputers Programmable I/O Port M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up selection P87 Direction register Data bus Port latch (Note) fc Input to respective peripheral functions Pull-up selection P86 Direction register “1” Data bus Port latch output (Note) Rf Rd Note : symbolizes a parasitic diode. Do not apply a voltage higher than VCC to each port. Figure 1.21.4. Programmable I/O ports (4) BYTE BYTE signal input (Note 2) (Note 1) CNVSS CNVSS signal input (Note 2) (Note 1) RESET RESET signal input (Note 1) Note 1 : symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each pin. Note 2 : A parasitic diode on the VCC side is added to the mask ROM version. Do not apply a voltage higher than Vcc to each pin. Figure 1.21.5. I/O pins 133 Mitsubishi microcomputers Programmable I/O Port M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Port Pi direction register (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PDi (i = 0 to 10, except 8) Bit symbol PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7 Address 03E216, 03E316, 03E616, 03E716, 03EA16 03EB16, 03EE16, 03EF16, 03F316, 03F616 Function 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 0 to 10 except 8) When reset 0016 Bit name Port Pi0 direction register Port Pi1 direction register Port Pi2 direction register Port Pi3 direction register Port Pi4 direction register Port Pi5 direction register Port Pi6 direction register Port Pi7 direction register RW Note: Set bit 2 of protect register (address 000A16) to “1” before rewriting to the port P9 direction register. Port P8 direction register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PD8 Address 03F216 Bit name Port P80 direction register Port P81 direction register Port P82 direction register Port P83 direction register Port P84 direction register When reset 00X000002 Function 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Bit symbol PD8_0 PD8_1 PD8_2 PD8_3 PD8_4 RW Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. PD8_6 PD8_7 Port P86 direction register Port P87 direction register 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Figure 1.21.6. Direction register 134 Mitsubishi microcomputers Programmable I/O Port M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Port Pi register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Pi (i = 0 to 10, except 8) Address 03E016, 03E116, 03E416, 03E516, 03E816 03E916, 03EC16, 03ED16, 03F116, 03F416 Function Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : “L” level data 1 : “H” level data (Note) (i = 0 to 10 except 8) When reset Indeterminate Indeterminate RW Bit symbol Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7 Bit name Port Pi0 register Port Pi1 register Port Pi2 register Port Pi3 register Port Pi4 register Port Pi5 register Port Pi6 register Port Pi7 register Note : Since P70 and P71 are N-channel open drain ports, the data is high-impedance. Port P8 register b7 b6 b5 b4 b3 b2 b1 b0 Symbol P8 Bit symbol P8_0 P8_1 P8_2 P8_3 P8_4 P8_5 P8_6 P8_7 Address 03F016 Bit name Port P80 register Port P81 register Port P82 register Port P83 register Port P84 register Port P85 register Port P86 register Port P87 register When reset Indeterminate Function Data is input and output to and from each pin by reading and writing to and from each corresponding bit (except for P85) 0 : “L” level data 1 : “H” level data RW Figure 1.21.7. Port register 135 Mitsubishi microcomputers Programmable I/O Port M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR0 Bit symbol PU00 PU01 PU02 PU03 PU04 PU05 PU06 PU07 Address 03FC16 Bit name P00 to P03 pull-up P04 to P07 pull-up P10 to P13 pull-up P14 to P17 pull-up P20 to P23 pull-up P24 to P27 pull-up P30 to P33 pull-up P34 to P37 pull-up When reset 0016 Function The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high RW Pull-up control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR1 Bit symbol PU10 PU11 PU12 PU13 PU14 PU15 PU16 Address 03FD16 Bit name P40 to P43 pull-up P44 to P47 pull-up P50 to P53 pull-up P54 to P57 pull-up P60 to P63 pull-up P64 to P67 pull-up P70 to P73 pull-up (Note) When reset 0016 Function The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high RW PU17 P74 to P77 pull-up Note: Since P70 and P71 are N-channel open drain ports, pull-up is not available for them. Pull-up control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR2 Bit symbol PU20 PU21 PU22 PU23 PU24 PU25 Address 03FE16 Bit name P80 to P83 pull-up P84 to P87 pull-up (Except P85) P90 to P93 pull-up P94 to P97 pull-up P100 to P103 pull-up P104 to P107 pull-up When reset 0016 Function The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Figure 1.21.8. Pull-up control register 136 Mitsubishi microcomputers Programmable I/O Port M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.21.1. Example connection of unused pins in single-chip mode Pin name Ports P0 to P10 (excluding P85) XOUT (Note) NMI AVCC AVSS, VREF, BYTE CNVSS Connection After setting for input mode, connect every pin to VSS via a resistor; or after setting for output mode, leave these pins open. Open Connect via resistor to VCC (pull-up) Connect to VCC Connect to VSS Connect via resistor to VSS (pull-down) Note: With external clock input to XIN pin. Table 1.21.2. Example connection of unused pins in memory expansion mode and microprocessor mode Pin name Ports P6 to P10 (excluding P85) BHE, ALE, HLDA, XOUT(Note), BCLK HOLD, RDY, NMI AVCC AVSS, VREF CNVSS Connection After setting for input mode, connect every pin to VSS or VCC via a resistor; or after setting for output mode, leave these pins open. Open Connect via resistor to VCC (pull-up) Connect to VCC Connect to VSS Connect via resistor to VSS (pull-down) in the memory expansion mode Connect via resistor to VCC (pull-up) in the microprocessor mode Note: With external clock input to XIN pin. Microcomputer Port P0 to P10 (except for P85) (Input mode) · · · (Input mode) (Output mode) · · · Microcomputer Port P6 to P10 (except for P85) (Input mode) · · · (Input mode) (Output mode) · · · Open Open NMI XOUT Open VCC AVCC 0.47µs BYTE AVSS VREF CNVSS NMI BHE HLDA ALE XOUT BCLK HOLD RDY CNVSS(microprocessor mode) AVCC AVSS VREF CNVSS(memory expansion mode) VSS Open VCC 0.47µs VSS In single-chip mode In memory expansion mode or in microprocessor mode Figure 1.21.9. Example connection of unused pins 137 Mitsubishi microcomputers M16C / 61 Group Usage precaution Usage Precaution Timer A (timer mode) (1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing gets “FFFF16”. Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A (event counter mode) (1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing gets “FFFF16” by underflow or “000016” by overflow. Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value. (2) When stop counting in free run type, set timer again. Timer A (one-shot timer mode) (1) Setting the count start flag to “0” while a count is in progress causes as follows: • The counter stops counting and a content of reload register is reloaded. • The TAiOUT pin outputs “L” level. • The interrupt request generated and the timer Ai interrupt request bit goes to “1”. (2) The timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of the following procedures: • Selecting one-shot timer mode after reset. • Changing operation mode from timer mode to one-shot timer mode. • Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after the above listed changes have been made. Timer A (pulse width modulation mode) (1) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance with any of the following procedures: • Selecting PWM mode after reset. • Changing operation mode from timer mode to PWM mode. • Changing operation mode from event counter mode to PWM mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after the above listed changes have been made. (2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop counting. If the TAiOUT pin is outputting an “H” level in this instance, the output level goes to “L”, and the timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an “L” level in this instance, the level does not change, and the timer Ai interrupt request bit does not becomes “1”. Timer B (timer mode, event counter mode) (1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. Reading the timer Bi register with the reload timing gets “FFFF16”. Reading the timer Bi register after setting a value in the timer Bi register with a count halted but before the counter starts counting gets a proper value. 138 Mitsubishi microcomputers M16C / 61 Group Usage precaution SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B (pulse period/pulse width measurement mode) (1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt request bit goes to “1”. (2) When the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. At this time, timer Bi interrupt request is not generated. A-D Converter (1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs). In particular, when the Vref connection bit is changed from “0” to “1”, start A-D conversion after an elapse of 1 µs or longer. (2) When changing A-D operation mode, select analog input pin again. (3) Using one-shot mode or single sweep mode Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by AD conversion interrupt request bit.) (4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 Use the undivided main clock as the internal CPU clock. Stop Mode and Wait Mode ____________ (1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock oscillation is stabilized. (2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the WAIT instruction or from the instruction that sets the every-clock stop bit to “1” within the instruction queue are prefetched and then the program stops. So put at least four NOPs in succession either to the WAIT instruction or to the instruction that sets the every-clock stop bit to 1. Interrupts (1) Reading address 0000016 • When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”. Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”. Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 0000016 by software. (2) Setting the stack pointer • The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. _______ When using the NMI interrupt, initialize the stack point at the beginning of a program. Concerning _______ the first instruction immediately after reset, generating any interrupts including the NMI interrupt is prohibited. 139 Mitsubishi microcomputers M16C / 61 Group Usage precaution _______ SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (3) The NMI interrupt _______ • As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the VCC pin via a resistor (pull-up) if unused. Be sure to work on it. _______ • Do not get either into stop mode or into wait mode with the NMI pin set to “L”. (4) External interrupt ________ ________ • When the polarity of the INT0 to INT2 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". (5) Rewrite the interrupt control register • To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: Example 1: INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. • When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET 140 Mitsubishi microcomputers M16C / 61 Group Usage precaution External ROM version The external ROM version is operated only in microprocessor mode, so be sure to perform the following: • Connect CNVSS pin to VCC. • Fix the processor mode bit to “112” SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Built-in PROM version (1) All built-in PROM versions High voltage is required to program to the built-in PROM. Be careful not to apply excessive voltage. Be especially careful during power-on. (2) One Time PROM version One Time PROM versions shipped in blank (M30612E4FP, M30612E4GP, M30610ECFP, M30610ECGP), of which built-in PROMs are programmed by users, are also provided. For these microcomputers, a programming test and screening are not performed in the assembly process and the following processes. Therefore ROM write defectiveness occurs around 5 %. To improve their reliability after programming, we recommend to program and test as flow shown in Figure 1.22.1 before use. Programming with PROM programmer Screening (Note) (Leave at 150˚C for 40 hours) Verify test PROM programmer Function check in target device Note: Never expose to 150˚C exceeding 100 hours. Figure 1.22.1. Programming and test flow for One Time PROM version (3) EPROM version • Cover the transparent glass window with a shield or others during the read mode because exposing to sun light or fluorescent lamp can cause erasing the information. A shield to cover the transparent window is available from Mitsubishi Electric Corp. Be careful that the shield does not touch the EPROM lead pins. • Clean the transparent glass before erasing. Fingers’ flat and paste disturb the passage of ultraviolet rays and may affect badly the erasure capability. • The EPROM version is a tool only for program development (for evaluation), and do not use it for the mass product run. 141 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Items to be submitted when ordering masked ROM version Please submit the following when ordering masked ROM products: (1) Mask ROM confirmation form (2) Mark specification sheet (3) ROM data : EPROMs or floppy disks *: In the case of EPROMs, there sets of EPROMs are required per pattern. *: In the case of floppy disks, 3.5-inch double-sided high-density disk (IBM format) is required per pattern. 142 Mitsubishi microcomputers Electrical characteristics M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.24.1. Absolute maximum ratings Symbol Vcc AVcc VI Supply voltage Analog supply voltage P00 to P07, P10 to P17, P20 to P27, Input voltage P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P87, P90 to P97, P100 to P107, RESET, VREF, XIN Input voltage P70, P71, CNVss, BYTE Output voltage P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86,P87, P90 to P97, P100 to P107, XOUT Output voltage P70, P71 Power dissipation Operating ambient temperature Storage temperature Ta=25 C Parameter Condition VCC = AVCC VCC = AVCC Rated value –0.3 to 6.5 –0.3 to 6.5 (Note 3) (Note 3) Unit V V –0.3 to Vcc+0.3 V VI VO –0.3 to 6.5 (Note 1, Note 3) V –0.3 to Vcc+0.3 V VO Pd Topr Tstg –0.3 to 6.5 300 –20 to 85 / –40 to 85 –65 to 150 (Note 3) (Note 2) V mW C C Note 1: When writing to EPROM ,only CNVSS is –0.3 to 13 (V) . Note 2: Specify a product of –40 to 85°C to use it. Note 3: –0.3V to 6.5V for M30610M8A, M30610MAA, M30610MCA, M30612M4A, M30612M8A, M30612MAA, M30612MCA, M30610SA and M30612SA. Otherwise, –0.3V to 7.0V is used. 143 Mitsubishi microcomputers Electrical characteristics (Vcc = 5V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.24.2. Recommended operating conditions (referenced to VCC = 2.7V to 5.5V at Ta = –20 to 85oC / –40 to 85oC (Note 3) unless otherwise specified) Symbol Vcc AVcc Vss AVss VIH Parameter Supply voltage Analog supply voltage Supply voltage Analog supply voltage HIGH input voltage P31 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P87, P90 to P97, P100 to P107, X IN, RESET, CNVSS, BYTE P70, P71 P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode) P00 to P07, P10 to P17, P20 to P27, P30 (data input function during memory expansion and microprocessor modes) Min 2.7 Standard Typ. 5.0 Vcc 0 0 Max. 5.5 Unit V V V V 0.8Vcc 0.8Vcc 0.8Vcc Vcc 6.5 Vcc V V V 0.5Vcc Vcc V V IL LOW input voltage P31 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, X IN, RESET, CNVSS, BYTE P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode) P00 to P07, P10 to P17, P20 to P27, P30 (data input function during memory expansion and microprocessor modes) 0 0.2Vcc V 0 0.2Vcc V 0 0.16Vcc V I OH (peak) HIGH peak output current HIGH average output current LOW peak output current LOW average output current I OH (avg) I OL (peak) P00 to P07, P10 to P17, P20 to P27,P30 to P37, P40 to P47, P50 to P57, P60 to P67,P72 to P77, P80 to P84,P86,P87,P90 to P97,P100 to P107 P00 to P07, P10 to P17, P20 to P27,P30 to P37, P40 to P47, P50 to P57, P60 to P67,P72 to P77, P80 to P84,P86,P87,P90 to P97,P100 to P107 P00 to P07, P10 to P17, P20 to P27,P30 to P37, P40 to P47, P50 to P57, P60 to P67,P70 to P77, P80 to P84,P86,P87,P90 to P97,P100 to P107 P00 to P07, P10 to P17, P20 to P27,P30 to P37, P40 to P47, P50 to P57, P60 to P67,P70 to P77, P80 to P84,P86,P87,P90 to P97,P100 to P107 VCC =4.0V to 5.5V 0 0 0 0 32.768 -10.0 mA -5.0 mA 10.0 mA I OL (avg) 5.0 10 5 X VCC –10.000 10 2.31 X VCC +0.760 50 mA MHz MHz MHz MHz kHz f (XIN) Main clock input oscillation frequency No wait VCC =2.7V to 4.0V VCC =4.0V to 5.5V With wait f (XcIN) VCC =2.7V to 4.0V Subclock oscillation frequency Note 1: The mean output current is the mean value within 100ms. Note 2: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, and P10 must be 80mA max. The total IOH (peak) for ports P0, P1, P2, P86, P87, P9, and P10 must be 80mA max. The total IOL (peak) for ports P3, P4, P5, P6, P7, and P80 to P84 must be 80mA max. The total IOH (peak) for ports P3, P4, P5, P6, P72 to P77, and P80 to P84 must be 80mA max. Note 3: Specify a product of –40 to 85°C to use it. Note 4: The relationship between main clock input frequency and power supply voltage is as below. Main clock input oscillation frequency (No wait) Main clock input oscillation frequency (With wait) Operating maximum frequency [MHZ] 10.0 5 X VCC –10.000MHZ Operating maximum frequency [MHZ] 10.0 2.31 X VCC –0.760MHZ 7.0 3.5 0.0 2.7 4.2 Supply voltage[V] 0.0 2.7 Supply voltage[V] 5.5 4.2 (BCLK: no division) 5.5 (BCLK: no division) 144 Mitsubishi microcomputers Electrical characteristics (Vcc = 5V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 5V Table 1.24.3. Electrical characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC, f(XIN) = 10MHZ unless otherwise specified) Symbol VOH Parameter Measuring condition Standard Min Typ. Max. 3.0 Unit HIGH output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37, P40 to P47, P50 to P57, IOH=-5mA P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 HIGH output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37, P40 to P47, P50 to P57, IOH=-200µA P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 IOH=-1mA HIGHPOWER HIGH output XOUT voltage LOWPOWER IOH=-0.5mA HIGH output voltage XCOUT HIGHPOWER LOWPOWER V VOH 4.7 3.0 3.0 3.0 1.6 V V V VOH With no load applied With no load applied IOL=5mA VOL LOW output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 LOW output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 LOW output voltage XOUT XCOUT HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER 2.0 V VOL IOL=200µA IOL=1mA IOL=0.5mA 0.45 V 2.0 2.0 0 0 V V VOL LOW output voltage Hysteresis VT+-VT- With no load applied With no load applied HOLD, RDY, TA0IN to TA4IN, TB0IN to TB2IN, INT0 to INT2, ADTRG, CTS0 to CTS2, CLK0 to CLK2,TA2OUT to TA4OUT,NMI, KI0 to KI3, RxD0 to RxD2 0.2 0.8 V VT+-VT- Hysteresis RESET 0.2 1.8 V IIH HIGH input P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, current P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVss, BYTE LOW input current P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVss, BYTE P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 VI=5V 5.0 µA I IL VI=0V -5.0 µA RPULLUP Pull-up resistance VI=0V 30.0 50.0 167.0 k kΩ M MΩ M MΩ V RfXIN RfXCIN V RAM Feedback resistance XIN Feedback resistance XCIN RAM retention voltage 1.0 6.0 When clock is stopped In single-chip f(XIN)=10MHz mode, the output pins are open and other pins are VSS Square wave, no division 2.0 19.0 90.0 38.0 mA µA f(XCIN)=32kHz Square wave Icc Power supply current f(XCIN)=32kHz When a WAIT instruction is executed(Note) 4.0 µA Ta=25°C when clock is stopped Ta=85°C when clock is stopped 1.0 µA 20.0 Note: With one timer operated using fc32. 145 Mitsubishi microcomputers Electrical characteristics (Vcc = 5V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 5V Table 1.24.4. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 5V, VSS = AVSS = 0V at Ta = 25oC, f(XIN) = 10MHZ unless otherwise specified) Standard Symbol Parameter Measuring condition Unit Min. Typ. Max. VREF = VCC 10 Bits Resolution Absolute Sample & hold function not available accuracy Sample & hold function available(10bit) VREF = VCC = 5V AN0 to AN7 input VREF =VCC ANEX0, ANEX1 input, = 5V External op-amp connection mode VREF = VCC = 5V ±3 ±3 ±7 ±2 40 LSB LSB LSB LSB Sample & hold function available(8bit) RLADDER tCONV tCONV tSAMP VREF VIA Ladder resistance Conversion time(10bit) Conversion time(8bit) Sampling time Reference voltage Analog input voltage VREF = VCC 10 3.3 2.8 0.3 2 0 VCC VREF kΩ µs µs µs V V Table 1.24.5. D-A conversion characteristics (referenced to VCC = 5V, VSS = AVSS = 0V, VREF = 5V at Ta = 25oC, f(XIN) = 10MHZ unless otherwise specified) Symbol Parameter Resolution Absolute accuracy Setup time Output resistance Reference power supply input current Measuring condition Min. Standard Typ. Max. 8 1.0 3 20 1.5 Unit Bits % µs kΩ k mA tsu RO IVREF 4 (Note) 10 Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “0016”. The A-D converter's ladder resistance is not included. Also, when the Vref is unconnected at the A-D control register, IVREF is sent. 146 Mitsubishi microcomputers Timing (Vcc = 5V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 5V Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified) Table 1.24.6. External clock input Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Standard Min. Max. 100 40 40 15 15 Unit ns ns ns ns ns Table 1.24.7. Memory expansion and microprocessor modes Symbol tac1(RD-DB) tac2(RD-DB) tac3(RD-DB) tsu(DB-RD) tsu(RDY-BCLK ) tsu(HOLD-BCLK ) th(RD-DB) th(BCLK -RDY) th(BCLK-HOLD ) td(BCLK-HLDA ) Parameter Data input access time (no wait) Data input access time (with wait) Data input access time (when accessing multiplex bus area) Data input setup time RDY input setup time HOLD input setup time Data input hold time RDY input hold time HOLD input hold time HLDA output delay time Standard Max. Min. (Note) (Note) (Note) 40 30 40 0 0 0 40 Unit ns ns ns ns ns ns ns ns ns ns Note: Calculated according to the BCLK frequency as follows: tac1(RD – DB) = tac2(RD – DB) = tac3(RD – DB) = 10 9 – 45 f(BCLK) X 2 3 X 10 – 45 f(BCLK) X 2 3 X 10 – 45 f(BCLK) X 2 9 9 [ns] [ns] [ns] 147 Mitsubishi microcomputers Timing (Vcc = 5V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 5V Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified) Table 1.24.8. Timer A input (counter input in event counter mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 100 40 40 Unit ns ns ns Table 1.24.9. Timer A input (gating input in timer mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 400 200 200 Unit ns ns ns Table 1.24.10. Timer A input (external trigger input in one-shot timer mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 200 100 100 Unit ns ns ns Table 1.24.11. Timer A input (external trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 100 100 Unit ns ns Table 1.24.12. Timer A input (up/down input in event counter mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time Parameter Standard Min. Max. 2000 1000 1000 400 400 Unit ns ns ns ns ns 148 Mitsubishi microcomputers Timing (Vcc = 5V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 5V Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified) Table 1.24.13. Timer B input (counter input in event counter mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) Standard Min. 100 40 40 200 80 80 Max. Unit ns ns ns ns ns ns Table 1.24.14. Timer B input (pulse period measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 400 200 200 Max. Unit ns ns ns Table 1.24.15. Timer B input (pulse width measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 400 200 200 Max. Unit ns ns ns Table 1.24.16. A-D trigger input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (trigger able minimum) ADTRG input LOW pulse width Standard Min. 1000 125 Max. Unit ns ns Table 1.24.17. Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time _______ Parameter Standard Min. 200 100 100 80 0 30 90 Max. Unit ns ns ns ns ns ns ns Table 1.24.18. External interrupt INTi inputs Symbol tw(INH) tw(INL) INTi input HIGH pulse width INTi input LOW pulse width Parameter Standard Min. 250 250 Max. Unit ns ns 149 Mitsubishi microcomputers Timing (Vcc = 5V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 5V Switching characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC, CM15 = “1” unless otherwise specified) Table 1.24.19. Memory expansion mode and microprocessor mode (no wait) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard)(Note2) 10 9 – 40 f(BCLK) X 2 Measuring condition Standard Min. Max. 25 4 0 0 25 4 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 1.24.1 –4 25 0 25 0 40 4 (Note1) 0 Note 1: Calculated according to the BCLK frequency as follows: td(DB – WR) = [ns] Note 2: This is standard value shows the timing when the output is off, and doesn't show hold time of data bus. Hold time of data bus is different by capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = –CR X ln (1 – VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time of output “L” level is t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC) = 6.7ns. R DBi C 150 Mitsubishi microcomputers Timing (Vcc = 5V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 5V Switching characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC, CM15 = “1” unless otherwise specified) Table 1.24.20. Memory expansion mode and microprocessor mode (with wait, accessing external memory) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard)(Note2) 10 9 f(BCLK) Measuring condition Standard Min. Max. 25 4 0 0 25 4 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 1.24.1 –4 25 0 25 0 40 4 (Note1) 0 Note 1: Calculated according to the BCLK frequency as follows: td(DB – WR) = – 40 [ns] Note 2: This is standard value shows the timing when the output is off, and doesn't show hold time of data bus. Hold time of data bus is different by capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = –CR X ln (1 – VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time of output “L” level is t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC) = 6.7ns. R DBi C 151 Mitsubishi microcomputers Timing (Vcc = 5V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 5V Switching characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC, CM15 = “1” unless otherwise specified) Table 1.24.21. Memory expansion mode and microprocessor mode (with wait, accessing external memory, multiplex bus area selected) Standard Measuring condition Parameter Unit Symbol Min. Max. td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) td(AD-RD) td(AD-WR) tdZ(RD-AD) Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) Chip select output hold time (RD standard) Chip select output hold time (WR standard) RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard) ALE signal output delay time (BCLK standard) ALE signal output hold time (BCLK standard) ALE signal output delay time (Address standard) ALE signal output hold time (Adderss standard) Post-address RD signal output delay time Post-address WR signal output delay time Address output floating start time 10 9 f(BCLK) X 2 10 f(BCLK) X 2 10 9 f(BCLK) X 2 10 f(BCLK) X 2 10 X 3 – 40 f(BCLK) X 2 10 f(BCLK) X 2 10 9 – 25 f(BCLK) X 2 9 9 9 9 25 4 (Note) (Note) ns ns ns ns 25 4 (Note) (Note) ns ns ns ns ns ns ns ns ns ns ns 25 0 25 Figure 1.24.1 0 40 4 (Note) (Note) 25 –4 (Note) ns ns ns ns ns ns 50 0 0 8 ns ns Note: Calculated according to the BCLK frequency as follows: th(RD – AD) = [ns] th(WR – AD) = [ns] th(RD – CS) = [ns] th(WR – CS) = [ns] td(DB – WR) = [ns] th(WR – DB) = [ns] td(AD – ALE) = [ns] 152 Mitsubishi microcomputers Timing (Vcc = 5V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 30pF Figure 1.24.1. Port P0 to P10 measurement circuit 153 Mitsubishi microcomputers Timing (Vcc = 5V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 5V tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected) th(TIN–UP) tsu(UP–TIN) TAiIN input (When count on rising edge is selected) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) TxDi td(C–Q) RxDi tw(INL) INTi input tw(INH) tsu(D–C) th(C–D) th(C–Q) Figure 1.24.2. VCC=5V timing diagram (1) 154 Mitsubishi microcomputers Timing (Vcc = 5V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 5V Memory Expansion Mode and Microprocessor Mode (Valid only with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY–BCLK) th(BCLK–RDY) (Valid with or without wait) BCLK tsu(HOLD–BCLK) HOLD input th(BCLK–HOLD) HLDA output td(BCLK–HLDA) P0, P1, P2, P3, P4, P50 to P52 Hi–Z td(BCLK–HLDA) Note: The above pins are set to high-impedance regardless of the input level of the BYTE pin and bit (PM06) of processor mode register 0 selects the function of ports P40 to P43. Measuring conditions : • VCC=5V • Input timing voltage : Determined with VIL=1.0V, VIH=4.0V • Output timing voltage : Determined with VOL=2.5V, VOH=2.5V Figure 1.24.3. VCC=5V timing diagram (2) 155 Mitsubishi microcomputers Timing (Vcc = 5V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Expansion Mode and Microprocessor Mode (With no wait) Read timing VCC = 5V BCLK td(BCLK–CS) 25ns.max th(BCLK–CS) 4ns.min CSi tcyc th(RD–CS) 0ns.min td(BCLK–AD) 25ns.max th(BCLK–AD) 4ns.min ADi BHE ALE RD td(BCLK–ALE) th(BCLK–ALE) 25ns.max –4ns.min th(RD–AD) 0ns.min td(BCLK–RD) 25ns.max th(BCLK–RD) 0ns.min tac1(RD–DB) DB Hi–Z tSU(DB–RD) 40ns.min th(RD–DB) 0ns.min Write timing BCLK td(BCLK–CS) 25ns.max th(BCLK–CS) 4ns.min CSi tcyc th(WR–CS) 0ns.min td(BCLK–AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE ALE td(BCLK–ALE) th(BCLK–ALE) 25ns.max th(WR–AD) 0ns.min th(BCLK–WR) 0ns.min –4ns.min td(BCLK–WR) WR,WRL, WRH DB 25ns.max td(BCLK–DB) 40ns.max Hi-Z td(DB–WR) th(BCLK–DB) 4ns.min th(WR–DB) 0ns.min (tcyc/2–40)ns.min Figure 1.24.4. VCC=5V timing diagram (3) 156 Mitsubishi microcomputers Timing (Vcc = 5V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Expansion Mode and Microprocessor Mode (When accessing external memory area with wait) Read timing BCLK td(BCLK–CS) 25ns.max VCC = 5V th(BCLK–CS) 4ns.min CSi tcyc th(RD–CS) 0ns.min td(BCLK–AD) 25ns.max th(BCLK–AD) 4ns.min ADi BHE ALE td(BCLK–ALE) 25ns.max th(RD–AD) 0ns.min th(BCLK–ALE) –4ns.min td(BCLK–RD) RD DB 25ns.max th(BCLK–RD) 0ns.min tac2(RD–DB) Hi–Z tSU(DB–RD) 40ns.min th(RD–DB) 0ns.min Write timing BCLK td(BCLK–CS) 25ns.max th(BCLK–CS) 4ns.min CSi tcyc th(WR–CS) 0ns.min td(BCLK–AD) 25ns.max th(BCLK–AD) 4ns.min ADi BHE ALE td(BCLK–ALE) 25ns.max th(WR–AD) 0ns.min th(BCLK–ALE) –4ns.min td(BCLK–WR) WR,WRL, WRH DBi td(DB–WR) (tcyc–40)ns.min 25ns.max th(BCLK–WR) 0ns.min td(BCLK–DB) 40ns.max th(BCLK–DB) 4ns.min th(WR–DB) 0ns.min Measuring conditions : • VCC=5V • Input timing voltage : Determined with: VIL=0.8V, VIH=2.5V • Output timing voltage : Determined with: VOL=0.8V, VOH=2.0V Figure 1.24.5. VCC=5V timing diagram (4) 157 Mitsubishi microcomputers Timing (Vcc = 5V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Expansion Mode and Microprocessor Mode Read timing BCLK td(BCLK–CS) 25ns.max tcyc VCC = 5V (When accessing external memory area with wait, and select multiplexed bus) th(RD–CS) (tcyc/2)ns.min th(BCLK–CS) 4ns.min CSi ADi /DBi td(AD–ALE) (tcyc/2-25)ns.min Address th(ALE–AD) 50ns.min Data input tac3(RD–DB) Address tdz(RD–AD) 8ns.max th(RD–DB) tSU(DB–RD) 40ns.min 0ns.min td(AD–RD) 0ns.min td(BCLK–AD) 25ns.max th(BCLK–AD) 4ns.min ADi BHE ALE RD td(BCLK–ALE) 25ns.max th(BCLK–ALE) –4ns.min th(RD–AD) (tcyc/2)ns.min th(BCLK–RD) 0ns.min 25ns.max td(BCLK–RD) Write timing BCLK td(BCLK–CS) 25ns.max tcyc th(BCLK–CS) th(WR–CS) (tcyc/2)ns.min 4ns.min CSi td(BCLK–DB) 40ns.max th(BCLK–DB) 4ns.min Data output Address ADi /DBi Address td(AD–ALE) (tcyc/2–25)ns.min td(DB–WR) (tcyc*3/2–40)ns.min th(WR–DB) (tcyc/2)ns.min th(BCLK–AD) 4ns.min td(BCLK–AD) 25ns.max ADi BHE ALE td(BCLK–ALE) 25ns.max th(BCLK–ALE) –4ns.min td(AD–WR) 0ns.min th(WR–AD) (tcyc/2)ns.min th(BCLK–WR) 0ns.min td(BCLK–WR) WR,WRL, WRH 25ns.max Measuring conditions : • VCC=5V • Input timing voltage : Determined with VIL=0.8V, VIH=2.5V • Output timing voltage : Determined with VOL=0.8V, VOH=2.0V Figure 1.24.6. VCC=5V timing diagram (5) 158 Mitsubishi microcomputers Electrical characteristics (Vcc = 3V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Table 1.24.22. Electrical characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, f(XIN) = 7MHZ, with wait) Symbol VOH HIGH output voltage Parameter Measuring condition Standard Min Typ. Max. 2.5 Unit P00 to P07,P10 to P17,P20 to P27, P30 to P37,P40 to P47,P50 to P57, IOH=-1mA P60 to P67,P72 to P77,P80 to P84, P86,P87,P90 to P97,P100 to P107 HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER V VOH HIGH output voltage XOUT HIGH output voltage LOW output voltage XCOUT IOH=-0.1mA IOH=-50µA With no load applied With no load applied 2.5 2.5 3.0 1.6 V V VOL P00 to P07,P10 to P17,P20 to P27, P30 to P37,P40 to P47,P50 to P57, IOL=1mA P60 to P67,P70 to P77,P80 to P84, P86,P87,P90 to P97,P100 to P107 XOUT HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER 0.5 V VOL LOW output voltage IOL=0.1mA IOL=50µA With no load applied With no load applied 0 0 0.5 0.5 V V LOW output voltage XCOUT Hysteresis VT+-VT- HOLD, RDY, TA0IN to TA4IN, TB0IN to TB2IN, INT0 to INT2, ADTRG, CTS0 to CTS2, CLK0 to CLK2,TA2OUT to TA4OUT,NMI, KI0 to KI3, RxD0 to RxD2 RESET P00 to P07,P10 to P17,P20 to P27, P30 to P37,P40 to P47,P50 to P57, P60 to P67,P70 to P77,P80 to P87, VI=3V P90 to P97,P100 to P107, XIN, RESET, CNVss, BYTE 0.2 0.8 V VT+-VT- Hysteresis HIGH input current 0.2 1.8 V IIH 4.0 µA LOW input current I IL P00 to P07,P10 to P17,P20 to P27, P30 to P37,P40 to P47,P50 to P57, P60 to P67,P70 to P77,P80 to P87, VI=0V P90 to P97,P100 to P107, XIN, RESET, CNVss, BYTE -4.0 µA R PULLUP Pull-up resistance P00 to P07,P10 to P17,P20 to P27, P30 to P37,P40 to P47,P50 to P57, P60 to P67,P72 to P77,P80 to P84, VI=0V P86,P87,P90 to P97,P100 to P107 66.0 120.0 3.0 10.0 500.0 k kΩ M MΩ M MΩ R fXIN R fXCIN V RAM Feedback resistance XIN Feedback resistance XCIN RAM retention voltage When clock is stopped f(XIN)=7MHz Square wave, no division 2.0 6.0 40.0 15.0 V mA µA Icc Power supply current In single-chip Square wave mode, the f(XCIN)=32kHz output pins When a WAITinstruction is executed. are open Oscillation capacity High and other (Note) pins are VSS f(XCIN)=32kHz When a WAIT instruction is executed. Oscillation capacity Low (Note) f(XCIN)=32kHz 2.8 µA 0.9 µA Ta=25°C when clock is stopped Ta=85°C when clock is stopped 1.0 µA 20.0 Note: With one timer operated using fc32. 159 Mitsubishi microcomputers Timing (Vcc = 3V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Table 1.24.23. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 3V, VSS = AVSS = 0V at Ta = 25oC, f(XIN) = 7MHZ unless otherwise specified) Symbol Resolution Absolute accuracy Sample & hold function not available (8 bit) Parameter Measuring condition VREF = VCC VREF = VCC = 3V, φAD = f(XIN)/2 Standard Min. Typ. Max 10 ±2 10 14.0 2.7 0 40 VCC VREF Unit Bits LSB RLADDER tCONV VREF VIA Ladder resistance Conversion time(8bit) Reference voltage Analog input voltage VREF = VCC kΩ k µs V V Table 1.24.24. D-A conversion characteristics (referenced to VCC = 3V, VSS = AVSS = 0V, VREF = 3V at Ta = 25oC, f(XIN) = 7MHZ unless otherwise specified) Symbol Parameter Resolution Absolute accuracy Setup time Output resistance Reference power supply input current Measuring condition Standard Min. Typ. Max 8 1.0 3 20 1.0 Unit Bits % µs kΩ k mA tsu RO IVREF 4 (Note) 10 Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “0016”. The A-D converter's ladder resistance is not included. Also, when the Vref is unconnected at the A-D control register, IVREF is sent. 160 Mitsubishi microcomputers Timing (Vcc = 3V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified) Table 1.24.25. External clock input Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Standard Min. Max. 143 60 60 18 18 Unit ns ns ns ns ns Table 1.24.26. Memory expansion and microprocessor modes Symbol tac1(RD-DB) tac2(RD-DB) tac3(RD-DB) tsu(DB-RD) tsu(RDY-BCLK ) tsu(HOLD-BCLK ) th(RD-DB) th(BCLK -RDY) th(BCLK-HOLD ) td(BCLK-HLDA) Parameter Data input access time (no wait) Data input access time (with wait) Data input access time (when accessing multiplex bus area) Data input setup time RDY input setup time HOLD input setup time Data input hold time RDY input hold time HOLD input hold time HLDA output delay time 10 9 – 90 f(BCLK) X 2 3 X 10 – 90 f(BCLK) X 2 3 X 10 9 – 90 f(BCLK) X 2 9 Standard Min. Max. (Note) (Note) (Note) 80 60 80 0 0 0 100 Unit ns ns ns ns ns ns ns ns ns ns Note: Calculated according to the BCLK frequency as follows: tac1(RD – DB) = tac2(RD – DB) = tac3(RD – DB) = [ns] [ns] [ns] 161 Mitsubishi microcomputers Timing (Vcc = 3V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified) Table 1.24.27. Timer A input (counter input in event counter mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 150 60 60 Unit ns ns ns Table 1.24.28. Timer A input (gating input in timer mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. 600 300 300 Max. Unit ns ns ns Table 1.24.29. Timer A input (external trigger input in one-shot timer mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 300 150 150 Unit ns ns ns Table 1.24.30. Timer A input (external trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 150 150 Unit ns ns Table 1.24.31. Timer A input (up/down input in event counter mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time Parameter Standard Min. 3000 1500 1500 600 600 Max. Unit ns ns ns ns ns 162 Mitsubishi microcomputers Timing (Vcc = 3V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified) Table 1.24.32. Timer B input (counter input in event counter mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) Standard Min. 150 60 60 300 160 160 Max. Unit ns ns ns ns ns ns Table 1.24.33. Timer B input (pulse period measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 600 300 300 Max. Unit ns ns ns Table 1.24.34. Timer B input (pulse width measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. Max. 600 300 300 Unit ns ns ns Table 1.24.35. A-D trigger input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (trigger able minimum) ADTRG input LOW pulse width Standard Min. 1500 200 Max. Unit ns ns Table 1.24.36. Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time _______ Parameter Standard Min. 300 150 150 160 0 50 90 Max. Unit ns ns ns ns ns ns ns Table 1.24.37. External interrupt INTi inputs Symbol tw(INH) tw(INL) INTi input HIGH pulse width INTi input LOW pulse width Parameter Standard Min. 380 380 Max. Unit ns ns 163 Mitsubishi microcomputers Timing (Vcc = 3V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Switching characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, CM15 = “1” unless otherwise specified) Table 1.24.38. Memory expansion and microprocessor modes (with no wait) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard)(Note2) Measuring condition Standard Min. Max. 60 4 0 0 60 4 60 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 1.24.1 —4 60 0 60 0 80 4 (Note1) 0 Note 1: Calculated according to the BCLK frequency as follows: td(DB – WR) = 10 f(BCLK) X 2 9 – 80 [ns] Note 2: This is standard value shows the timing when the output is off, and doesn't show hold time of data bus. Hold time of data bus is different by capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = –CR X ln (1 – VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time of output “L” level is t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC) = 6.7ns. R DBi C 164 Mitsubishi microcomputers Timing (Vcc = 3V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Switching characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, CM15 = “1” unless otherwise specified) Table 1.24.39. Memory expansion and microprocessor modes (when accessing external memory area with wait) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) Standard Min. Max. 60 4 0 0 60 4 60 –4 60 0 60 0 80 4 (Note1) 0 Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard)(Note2) Measuring condition Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 1.24.1 Note 1: Calculated according to the BCLK frequency as follows: td(DB – WR) = 10 f(BCLK) 9 – 80 [ns] Note 2: This is standard value shows the timing when the output is off, and doesn't show hold time of data bus. Hold time of data bus is different by capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = –CR X ln (1 – VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time of output “L” level is t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC) = 6.7ns. R DBi C 165 Mitsubishi microcomputers Timing (Vcc = 3V) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Switching characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, CM15 = “1” unless otherwise specified) Table 1.24.40. Memory expansion and microprocessor modes (when accessing external memory area with wait, and select multiplexed bus) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) td(AD-RD) td(AD-WR) tdZ(RD-AD) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) Chip select output hold time (RD standard) Chip select output hold time (WR standard) RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard) ALE signal output delay time (BCLK standard) ALE signal output hold time (BCLK standard) ALE signal output delay time (Address standard) ALE signal output hold time(Address standard) Post-address RD signal output delay time Post-address WR signal output delay time Address output floating start time Measuring condition Standard Min. Max. 60 4 (Note) (Note) 60 4 (Note) (Note) 60 0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 1.24.1 0 60 80 4 (Note) (Note) 60 –4 (Note) 50 0 0 8 ns ns ns ns ns ns ns Note: Calculated according to the BCLK frequency as follows: th(RD – AD) = 10 f(BCLK) X 2 10 9 f(BCLK) X 2 th(RD – CS) = 10 f(BCLK) X 2 10 9 f(BCLK) X 2 td(DB – WR) = 10 X 3 – 80 f(BCLK) X 2 10 9 f(BCLK) X 2 td(AD – ALE) = 10 9 f(BCLK) X 2 – 60 [ns] 9 9 9 [ns] th(WR – AD) = [ns] [ns] th(WR – CS) = [ns] [ns] th(WR – DB) = [ns] 166 Mitsubishi microcomputers M16C / 61 Group Timing (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected) th(TIN–UP) tsu(UP–TIN) TAiIN input (When count on rising edge is selected) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) TxDi td(C–Q) RxDi tw(INL) INTi input tw(INH) tsu(D–C) th(C–D) th(C–Q) Figure 1.24.7. VCC=3V timing diagram (1) 167 Mitsubishi microcomputers M16C / 61 Group Timing (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Memory Expansion Mode and Microprocessor Mode (Valid only with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY–BCLK) th(BCLK–RDY) (Valid with or without wait) BCLK tsu(HOLD–BCLK) HOLD input th(BCLK–HOLD) HLDA output td(BCLK–HLDA) P0, P1, P2, P3, P4, P50 to P52 Hi–Z td(BCLK–HLDA) Note: The above pins are set to high-impedance regardless of the input level of the BYTE pin and bit (PM06) of processor mode register 0 selects the function of ports P40 to P43. Measuring conditions : • VCC=3V • Input timing voltage : Determined with VIL=0.6V, VIH=2.4V • Output timing voltage : Determined with VOL=1.5V, VOH=1.5V Figure 1.24.8. VCC=3V timing diagram (2) 168 Mitsubishi microcomputers M16C / 61 Group Timing (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Expansion Mode and Microprocessor Mode (With no wait) Read timing BCLK td(BCLK–CS) 60ns.max VCC = 3V th(BCLK–CS) 4ns.min CSi tcyc th(RD–CS) 0ns.min td(BCLK–AD) 60ns.max th(BCLK–AD) 4ns.min ADi BHE ALE RD td(BCLK–ALE) th(BCLK–ALE) –4ns.min 60ns.max th(RD–AD) 0ns.min th(BCLK–RD) 0ns.min td(BCLK–RD) 60ns.max tac1(RD–DB) DB Hi–Z th(RD–DB) tSU(DB–RD) 80ns.min 0ns.min Write timing BCLK td(BCLK–CS) 60ns.max th(BCLK–CS) 4ns.min CSi tcyc th(WR–CS) 0ns.min td(BCLK–AD) 60ns.max th(BCLK–AD) 4ns.min ADi BHE ALE td(BCLK–ALE) th(BCLK–ALE) 60ns.max –4ns.min th(WR–AD) 0ns.min WR,WRL, WRH DB td(BCLK–WR) 60ns.max td(BCLK–DB) 80ns.max Hi–Z th(BCLK–WR) 0ns.min th(BCLK–DB) 4ns.min th(WR–DB) td(DB–WR) (tcyc/2–80)ns.min 0ns.min Figure 1.24.9. VCC=3V timing diagram (3) 169 Mitsubishi microcomputers M16C / 61 Group Timing (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Expansion Mode and Microprocessor Mode (When accessing external memory area with wait) Read timing BCLK td(BCLK–CS) 60ns.max VCC = 3V th(BCLK–CS) 4ns.min CSi tcyc th(RD–CS) 0ns.min td(BCLK–AD) 60ns.max th(BCLK–AD) 4ns.min ADi BHE ALE td(BCLK–ALE) 60ns.max th(RD–AD) 0ns.min th(BCLK–ALE) –4ns.min td(BCLK–RD) 60ns.max th(BCLK–RD) 0ns.min RD tac2(RD–DB) DB Hi–Z th(RD–DB) 0ns.min tSU(DB–RD) 80ns.min Write timing BCLK td(BCLK–CS) 60ns.max th(BCLK–CS) 4ns.min CSi tcyc th(WR–CS) 0ns.min td(BCLK–AD) 60ns.max th(BCLK–AD) 4ns.min ADi BHE ALE td(BCLK–ALE) 60ns.max th(WR–AD) 0ns.min th(BCLK–ALE) –4ns.min td(BCLK–WR) 60ns.max th(BCLK–WR) 0ns.min WR,WRL, WRH DBi td(BCLK–DB) 80ns.max th(BCLK–DB) 4ns.min td(DB–WR) (tcyc–80)ns.min th(WR–DB) 0ns.min Measuring conditions : • VCC=3V • Input timing voltage : Determined with VIL=0.48V, VIH=1.5V • Output timing voltage : Determined with VOL=1.5V, VOH=1.5V Figure 1.24.10. VCC=3V timing diagram (4) 170 Mitsubishi microcomputers M16C / 61 Group Timing (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Memory Expansion Mode and Microprocessor Mode (When accessing external memory area with wait, and select multiplexed bus) Read timing BCLK td(BCLK–CS) 60ns.max tcyc th(BCLK–CS) th(RD–CS) (tcyc/2)ns.min 4ns.min CSi td(AD–ALE) (tcyc/2–60)ns.min ADi /DBi Address tdz(RD–AD) 8ns.max Data input tac3(RD–DB) Address th(ALE–AD) 50ns.min th(RD–DB) tSU(DB–RD) 80ns.min 0ns.min td(BCLK–AD) ADi BHE ALE RD 60ns.max td(AD–RD) 0ns.min th(BCLK–AD) 4ns.min td(BCLK–ALE) 60ns.max th(BCLK–ALE) –4ns.min th(RD–AD) (tcyc/2)ns.min th(BCLK–RD) 0ns.min 60ns.max td(BCLK–RD) Write timing BCLK td(BCLK–CS) 60ns.max tcyc th(WR–CS) (tcyc/2)ns.min th(BCLK–CS) 4ns.min CSi td(BCLK–DB) 80ns.max th(BCLK–DB) 4ns.min Address ADi /DBi Address Data output td(AD–ALE) (tcyc/2–60)ns.min td(BCLK–AD) ADi BHE ALE 60ns.max td(DB–WR) (tcyc*3/2–80)ns.min th(WR–DB) (tcyc/2)ns.min th(BCLK–AD) 4ns.min td(BCLK–ALE) th(BCLK–ALE) 60ns.max –4ns.min td(AD–WR) 0ns.min th(WR–AD) (tcyc/2)ns.min th(BCLK–WR) 0ns.min td(BCLK–WR) WR,WRL, WRH 60ns.max Measuring conditions : • VCC=3V • Input timing voltage : Determined with VIL=0.48V,VIH=1.5V • Output timing voltage : Determined with VOL=1.5V,VOH=1.5V Figure 1.24.11. VCC=3V timing diagram (5) 171 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ SH11 53B Mask ROM number MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30610M8A-XXXFP/GP MASK ROM CONFIRMATION FORM Receipt Date : Section head signature Supervisor signature Note : Please complete all items marked . ) Customer Date issued Date : 1. Check sheet Name the product you order, and choose which to give in, EPROMs or floppy disks. If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by means of floppy disks, one floppy disk is required per pattern. In the case of EPROMs Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any discrepancy between the data on the EPROM sets and the ROM data written to the product. Please carefully check the data on the EPROMs being submitted to Mitsubishi. Microcomputer type No. : M30610M8A-XXXFP M30610M8A-XXXGP (hex) Checksum code for total EPROM area : EPROM type : 27C201 Address 0000016 Product : Area containing ASCII 0000F16 code for M30610M8A 0001016 2FFFF16 3000016 ROM(64K) 3FFFF16 7FFFF16 27C401 Address 0000016 Product : Area containing ASCII 0000F16 code for M30610M8A 0001016 6FFFF16 7000016 ROM(64K) signature Issuance Company name TEL ( Submitted by Supervisor (1) Write “FF16” to the lined area. (2) The area from 0000016 to 0000F16 is for storing data on the product type name. The ASCII code for 'M30610M8A-' is shown at right. The data in this table must be written to address 0000016 to 0000F16. Both address and data are shown in hex. Address 0000016 0000116 0000216 0000316 0000416 0000516 0000616 0000716 Address 'M ' '3 ' '0 ' '6 ' '1 ' '0 ' 'M ' '8 ' = 4D16 = 3316 = 3016 = 3616 = 3116 = 3016 = 4D16 = 3816 0000816 ' A ' = 4116 0000916 ' — ' = 2D16 0000A16 FF16 FF16 0000B16 FF16 0000C16 FF16 0000D16 FF16 0000E16 FF16 0000F16 172 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ SH11 53B MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30610M8A-XXXFP/GP MASK ROM CONFIRMATION FORM Mask ROM number The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the assembler source program. EPROM type Code entered in source program 27C201 .SECTION ASCIICODE, ROM DATA .ORG 0C0000H .BYTE ' M30610M8A- ' 27C401 .SECTION ASCIICODE, ROM DATA .ORG 080000H .BYTE ' M30610M8A- ' Note: The ROM cannot be processed if the type No. written to the EPROM does not match the type No. in the check sheet. In the case of floppy disks Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that there is any discrepancy between the contents of these mask files and the ROM data to be burned into products we produce. Check thoroughly the contents of the mask files you give in. Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk. Microcomputer type No. : File code : M30610M8A-XXXFP M30610M8A-XXXGP (hex) Mask file name : .MSK (alpha-numeric 8-digit) 2. Mark specification The mark specification differs according to the type of package. After entering the mark specification on the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for submission to Mitsubishi. For the M30610M8A-XXXFP, submit the 100P6S mark specification sheet. For the M30610M8A-XXXGP, submit the 100P6Q mark specification sheet. 3. Usage Conditions For our reference when of testing our products, please reply to the following questions about the usage of the products you ordered. (1) Which kind of XIN-XOUT oscillation circuit is used? Ceramic resonator Quartz-crystal oscillator External clock input Other ( ) What frequency do you use? MHZ f(XIN) = 173 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ SH11 53B MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30610M8A-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind of XCIN-XCOUT oscillation circuit is used? Ceramic resonator Quartz-crystal oscillator External clock input Other ( ) What frequency do you use? kHZ f(XCIN) = (3) Which operation mode do you use? Single-chip mode Memory expansion mode Microprocessor mode (4) Which operating ambient temperature do you use? –10 °C to 75 °C –20 °C to 75 °C –10 °C to 85 °C –20 °C to 85 °C (5) Which operating supply voltage do you use? 2.7V to 3.2V 3.2V to 3.7V 4.2V to 4.7V 4.7V to 5.2V Thank you cooperation. 4. Special item (Indicate none if there is no specified item) Mask ROM number –40 °C to 75 °C –40 °C to 85 °C 3.7V to 4.2V 5.2V to 5.5V 174 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ SH11 52B Mask ROM number MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30610MAA-XXXFP/GP MASK ROM CONFIRMATION FORM Receipt Date : Section head signature Supervisor signature Note : Please complete all items marked signature Issuance . Company name Customer Date issued Date : TEL ( Submitted by Supervisor ) 1. Check sheet Name the product you order, and choose which to give in, EPROMs or floppy disks. If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by means of floppy disks, one floppy disk is required per pattern. In the case of EPROMs Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any discrepancy between the data on the EPROM sets and the ROM data written to the product. Please carefully check the data on the EPROMs being submitted to Mitsubishi. Microcomputer type No. : M30610MAA-XXXFP M30610MAA-XXXGP (hex) Checksum code for total EPROM area : EPROM type : 27C201 Address 0000016 Product : Area containing ASCII 0000F16 code for M30610MAA 0001016 27FFF16 2800016 ROM(96K) 3FFFF16 7FFFF16 27C401 Address 0000016 Product : Area containing ASCII 0000F16 code for M30610MAA 0001016 67FFF16 6800016 ROM(96K) Address (1) Write “FF16” to the lined area. 0000016 ' M ' (2) The area from 0000016 to 0000F16 is for storing 0000116 ' 3 ' data on the product type name. 0000216 ' 0 ' The ASCII code for 'M30610MAA-' is shown at right. 0000316 ' 6 ' The data in this table must be written to address 0000416 ' 1 ' 0000016 to 0000F16. 0000516 ' 0 ' Both address and data are shown in hex. 0000616 ' M ' 0000716 ' A ' Address = 4D16 = 3316 = 3016 = 3616 = 3116 = 3016 = 4D16 = 4116 0000816 ' A ' = 4116 0000916 ' — ' = 2D16 0000A16 FF16 FF16 0000B16 FF16 0000C16 FF16 0000D16 FF16 0000E16 FF16 0000F16 175 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ SH11 52B MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30610MAA-XXXFP/GP MASK ROM CONFIRMATION FORM Mask ROM number The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the assembler source program. EPROM type Code entered in source program 27C201 .SECTION ASCIICODE, ROM DATA .ORG 0C0000H .BYTE ' M30610MAA- ' 27C401 .SECTION ASCIICODE, ROM DATA .ORG 080000H .BYTE ' M30610MAA- ' Note: The ROM cannot be processed if the type No. written to the EPROM does not match the type No. in the check sheet. In the case of floppy disks Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that there is any discrepancy between the contents of these mask files and the ROM data to be burned into products we produce. Check thoroughly the contents of the mask files you give in. Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk. Microcomputer type No. : File code : M30610MAA-XXXFP M30610MAA-XXXGP (hex) Mask file name : .MSK (alpha-numeric 8-digit) 2. Mark specification The mark specification differs according to the type of package. After entering the mark specification on the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for submission to Mitsubishi. For the M30610MAA-XXXFP, submit the 100P6S mark specification sheet. For the M30610MAA-XXXGP, submit the 100P6Q mark specification sheet. 3. Usage Conditions For our reference when of testing our products, please reply to the following questions about the usage of the products you ordered. (1) Which kind of XIN-XOUT oscillation circuit is used? Ceramic resonator Quartz-crystal oscillator External clock input Other ( ) What frequency do you use? f(XIN) = MHZ 176 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ SH11 52B MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30610MAA-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind of XCIN-XCOUT oscillation circuit is used? Ceramic resonator Quartz-crystal oscillator External clock input Other ( ) What frequency do you use? f(XCIN) = kHZ (3) Which operation mode do you use? Single-chip mode Memory expansion mode Microprocessor mode (4) Which operating ambient temperature do you use? –10 °C to 75 °C –20 °C to 75 °C –10 °C to 85 °C –20 °C to 85 °C (5) Which operating supply voltage do you use? 2.7V to 3.2V 3.2V to 3.7V 4.2V to 4.7V 4.7V to 5.2V Thank you cooperation. 4. Special item (Indicate none if there is no specified item) Mask ROM number –40 °C to 75 °C –40 °C to 85 °C 3.7V to 4.2V 5.2V to 5.5V 177 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ SH11 51B Mask ROM number MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30610MCA-XXXFP/GP MASK ROM CONFIRMATION FORM Receipt Date : Section head signature Supervisor signature Note : Please complete all items marked signature Issuance . Company name Customer Date issued Date : TEL ( ) Submitted by Supervisor 1. Check sheet Name the product you order, and choose which to give in, EPROMs or floppy disks. If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by means of floppy disks, one floppy disk is required per pattern. In the case of EPROMs Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any discrepancy between the data on the EPROM sets and the ROM data written to the product. Please carefully check the data on the EPROMs being submitted to Mitsubishi. Microcomputer type No. : M30610MCA-XXXFP M30610MCA-XXXGP (hex) Checksum code for total EPROM area : EPROM type : 27C201 Address 0000016 Product : Area containing ASCII 0000F16 code for M30610MCA 0001016 1FFFF16 2000016 ROM(128K) 3FFFF16 7FFFF16 27C401 Address 0000016 Product : Area containing ASCII 0000F16 code for M30610MCA 0001016 5FFFF16 6000016 ROM(128K) Address (1) Write “FF16” to the lined area. 0000016 ' M ' (2) The area from 0000016 to 0000F16 is for storing 0000116 ' 3 ' data on the product type name. 0000216 ' 0 ' The ASCII code for 'M30610MCA-' is shown at right. 0000316 ' 6 ' The data in this table must be written to address 0000416 ' 1 ' 0000016 to 0000F16. 0000516 ' 0 ' Both address and data are shown in hex. 0000616 ' M ' 0000716 ' C ' Address = 4D16 = 3316 = 3016 = 3616 = 3116 = 3016 = 4D16 = 4316 0000816 ' A ' = 4116 0000916 ' — ' = 2D16 0000A16 FF16 FF16 0000B16 FF16 0000C16 FF16 0000D16 FF16 0000E16 FF16 0000F16 178 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ SH11 51B MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30610MCA-XXXFP/GP MASK ROM CONFIRMATION FORM Mask ROM number The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the assembler source program. EPROM type Code entered in source program 27C201 .SECTION ASCIICODE, ROM DATA .ORG 0C0000H .BYTE ' M30610MCA- ' 27C401 .SECTION ASCIICODE, ROM DATA .ORG 080000H .BYTE ' M30610MCA- ' Note: The ROM cannot be processed if the type No. written to the EPROM does not match the type No. in the check sheet. In the case of floppy disks Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that there is any discrepancy between the contents of these mask files and the ROM data to be burned into products we produce. Check thoroughly the contents of the mask files you give in. Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk. Microcomputer type No. : File code : M30610MCA-XXXFP M30610MCA-XXXGP (hex) Mask file name : .MSK (alpha-numeric 8-digit) 2. Mark specification The mark specification differs according to the type of package. After entering the mark specification on the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for submission to Mitsubishi. For the M30610MCA-XXXFP, submit the 100P6S mark specification sheet. For the M30610MCA-XXXGP, submit the 100P6Q mark specification sheet. 3. Usage Conditions For our reference when of testing our products, please reply to the following questions about the usage of the products you ordered. (1) Which kind of XIN-XOUT oscillation circuit is used? Ceramic resonator Quartz-crystal oscillator External clock input Other ( ) What frequency do you use? f(XIN) = MHZ 179 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ SH11 51B MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30610MCA-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind of XCIN-XCOUT oscillation circuit is used? Ceramic resonator Quartz-crystal oscillator External clock input Other ( ) What frequency do you use? kHZ f(XCIN) = (3) Which operation mode do you use? Single-chip mode Memory expansion mode Microprocessor mode (4) Which operating ambient temperature do you use? –10 °C to 75 °C –20 °C to 75 °C –10 °C to 85 °C –20 °C to 85 °C (5) Which operating supply voltage do you use? 2.7V to 3.2V 3.2V to 3.7V 4.2V to 4.7V 4.7V to 5.2V Thank you cooperation. 4. Special item (Indicate none if there is no specified item) Mask ROM number –40 °C to 75 °C –40 °C to 85 °C 3.7V to 4.2V 5.2V to 5.5V 180 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ SH12 35B Mask ROM number MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612M4A-XXXFP/GP MASK ROM CONFIRMATION FORM Receipt Date : Section head signature Supervisor signature Note : Please complete all items marked signature Issuance . Company name Customer Date issued Date : TEL ( Submitted by Supervisor ) 1. Check sheet Name the product you order, and choose which to give in, EPROMs or floppy disks. If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by means of floppy disks, one floppy disk is required per pattern. In the case of EPROMs Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any discrepancy between the data on the EPROM sets and the ROM data written to the product. Please carefully check the data on the EPROMs being submitted to Mitsubishi. Microcomputer type No. : M30612M4A-XXXFP M30612M4A-XXXGP (hex) Checksum code for total EPROM area : EPROM type : 27C201 Address 0000016 Product : Area containing ASCII 0000F16 code for M30612M4A 0001016 37FFF16 3800016 ROM(32K) 3FFFF16 7FFFF16 27C401 Address 0000016 Product : Area containing ASCII 0000F16 code for M30612M4A 0001016 77FFF16 7800016 ROM(32K) (1) Write “FF16” to the lined area. (2) The area from 0000016 to 0000F16 is for storing data on the product type name. The ASCII code for 'M30612M4A-' is shown at right. The data in this table must be written to address 0000016 to 0000F16. Both address and data are shown in hex. Address 0000016 0000116 0000216 0000316 0000416 0000516 0000616 0000716 Address 'M ' '3 ' '0 ' '6 ' '1 ' '2 ' 'M ' '4 ' = 4D16 = 3316 = 3016 = 3616 = 3116 = 3216 = 4D16 = 3416 0000816 ' A ' = 4116 0000916 ' — ' = 2D16 0000A16 FF16 FF16 0000B16 FF16 0000C16 FF16 0000D16 FF16 0000E16 FF16 0000F16 181 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ SH12 35B MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612M4A-XXXFP/GP MASK ROM CONFIRMATION FORM Mask ROM number The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the assembler source program. EPROM type Code entered in source program 27C201 .SECTION ASCIICODE, ROM DATA .ORG 0C0000H .BYTE ' M30612M4A- ' 27C401 .SECTION ASCIICODE, ROM DATA .ORG 080000H .BYTE ' M30612M4A- ' Note: The ROM cannot be processed if the type No. written to the EPROM does not match the type No. in the check sheet. In the case of floppy disks Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that there is any discrepancy between the contents of these mask files and the ROM data to be burned into products we produce. Check thoroughly the contents of the mask files you give in. Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk. Microcomputer type No. : File code : M30612M4A-XXXFP M30612M4A-XXXGP (hex) Mask file name : .MSK (alpha-numeric 8-digit) 2. Mark specification The mark specification differs according to the type of package. After entering the mark specification on the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for submission to Mitsubishi. For the M30612M4A-XXXFP, submit the 100P6S mark specification sheet. For the M30612M4A-XXXGP, submit the 100P6Q mark specification sheet. 3. Usage Conditions For our reference when of testing our products, please reply to the following questions about the usage of the products you ordered. (1) Which kind of XIN-XOUT oscillation circuit is used? Ceramic resonator Quartz-crystal oscillator External clock input Other ( ) What frequency do you use? MHZ f(XIN) = 182 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ SH12 35B MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612M4A-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind of XCIN-XCOUT oscillation circuit is used? Ceramic resonator Quartz-crystal oscillator External clock input Other ( ) What frequency do you use? kHZ f(XCIN) = (3) Which operation mode do you use? Single-chip mode Memory expansion mode Microprocessor mode (4) Which operating ambient temperature do you use? –10 °C to 75 °C –20 °C to 75 °C –10 °C to 85 °C –20 °C to 85 °C (5) Which operating supply voltage do you use? 2.7V to 3.2V 3.2V to 3.7V 4.2V to 4.7V 4.7V to 5.2V Thank you cooperation. 4. Special item (Indicate none if there is no specified item) Mask ROM number –40 °C to 75 °C –40 °C to 85 °C 3.7V to 4.2V 5.2V to 5.5V 183 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ SH12 34B Mask ROM number MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612M8A-XXXFP/GP MASK ROM CONFIRMATION FORM Receipt Date : Section head signature Supervisor signature Note : Please complete all items marked . ) Customer Date issued Date : 1. Check sheet Name the product you order, and choose which to give in, EPROMs or floppy disks. If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by means of floppy disks, one floppy disk is required per pattern. In the case of EPROMs Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any discrepancy between the data on the EPROM sets and the ROM data written to the product. Please carefully check the data on the EPROMs being submitted to Mitsubishi. Microcomputer type No. : M30612M8A-XXXFP M30612M8A-XXXGP (hex) Checksum code for total EPROM area : EPROM type : 27C201 Address 0000016 Product : Area containing ASCII 0000F16 code for M30612M8A 0001016 2FFFF16 3000016 ROM(64K) 3FFFF16 7FFFF16 27C401 Address 0000016 Product : Area containing ASCII 0000F16 code for M30612M8A 0001016 6FFFF16 7000016 ROM(64K) signature Issuance Company name TEL ( Submitted by Supervisor (1) Write “FF16” to the lined area. (2) The area from 0000016 to 0000F16 is for storing data on the product type name. The ASCII code for 'M30612M8A-' is shown at right. The data in this table must be written to address 0000016 to 0000F16. Both address and data are shown in hex. Address 0000016 0000116 0000216 0000316 0000416 0000516 0000616 0000716 Address 'M ' '3 ' '0 ' '6 ' '1 ' '2 ' 'M ' '8 ' = 4D16 = 3316 = 3016 = 3616 = 3116 = 3216 = 4D16 = 3816 0000816 ' A ' = 4116 0000916 ' — ' = 2D16 0000A16 FF16 FF16 0000B16 FF16 0000C16 FF16 0000D16 FF16 0000E16 FF16 0000F16 184 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ SH12 34B MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612M8A-XXXFP/GP MASK ROM CONFIRMATION FORM Mask ROM number The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the assembler source program. EPROM type Code entered in source program 27C201 .SECTION ASCIICODE, ROM DATA .ORG 0C0000H .BYTE ' M30612M8A- ' 27C401 .SECTION ASCIICODE, ROM DATA .ORG 080000H .BYTE ' M30612M8A- ' Note: The ROM cannot be processed if the type No. written to the EPROM does not match the type No. in the check sheet. In the case of floppy disks Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that there is any discrepancy between the contents of these mask files and the ROM data to be burned into products we produce. Check thoroughly the contents of the mask files you give in. Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk. Microcomputer type No. : File code : M30612M8A-XXXFP M30612M8A-XXXGP (hex) Mask file name : .MSK (alpha-numeric 8-digit) 2. Mark specification The mark specification differs according to the type of package. After entering the mark specification on the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for submission to Mitsubishi. For the M30612M8A-XXXFP, submit the 100P6S mark specification sheet. For the M30612M8A-XXXGP, submit the 100P6Q mark specification sheet. 3. Usage Conditions For our reference when of testing our products, please reply to the following questions about the usage of the products you ordered. (1) Which kind of XIN-XOUT oscillation circuit is used? Ceramic resonator Quartz-crystal oscillator External clock input Other ( ) What frequency do you use? MHZ f(XIN) = 185 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ SH12 34B MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612M8A-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind of XCIN-XCOUT oscillation circuit is used? Ceramic resonator Quartz-crystal oscillator External clock input Other ( ) What frequency do you use? kHZ f(XCIN) = (3) Which operation mode do you use? Single-chip mode Memory expansion mode Microprocessor mode (4) Which operating ambient temperature do you use? –10 °C to 75 °C –20 °C to 75 °C –10 °C to 85 °C –20 °C to 85 °C (5) Which operating supply voltage do you use? 2.7V to 3.2V 3.2V to 3.7V 4.2V to 4.7V 4.7V to 5.2V Thank you cooperation. 4. Special item (Indicate none if there is no specified item) Mask ROM number –40 °C to 75 °C –40 °C to 85 °C 3.7V to 4.2V 5.2V to 5.5V 186 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ SH12 55B Mask ROM number MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612MAA-XXXFP/GP MASK ROM CONFIRMATION FORM Receipt Date : Section head signature Supervisor signature Note : Please complete all items marked signature Issuance . Company name Customer Date issued Date : TEL ( Submitted by Supervisor ) 1. Check sheet Name the product you order, and choose which to give in, EPROMs or floppy disks. If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by means of floppy disks, one floppy disk is required per pattern. In the case of EPROMs Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any discrepancy between the data on the EPROM sets and the ROM data written to the product. Please carefully check the data on the EPROMs being submitted to Mitsubishi. Microcomputer type No. : M30612MAA-XXXFP M30612MAA-XXXGP (hex) Checksum code for total EPROM area : EPROM type : 27C201 Address 0000016 Product : Area containing ASCII 0000F16 code for M30612MAA 0001016 27FFF16 2800016 ROM(96K) 3FFFF16 7FFFF16 27C401 Address 0000016 Product : Area containing ASCII 0000F16 code for M30612MAA 0001016 67FFF16 6800016 ROM(96K) Address (1) Write “FF16” to the lined area. 0000016 ' M ' (2) The area from 0000016 to 0000F16 is for storing 0000116 ' 3 ' data on the product type name. 0000216 ' 0 ' The ASCII code for 'M30612MAA-' is shown at right. 0000316 ' 6 ' The data in this table must be written to address 0000416 ' 1 ' 0000016 to 0000F16. 0000516 ' 2 ' Both address and data are shown in hex. 0000616 ' M ' 0000716 ' A ' Address = 4D16 = 3316 = 3016 = 3616 = 3116 = 3216 = 4D16 = 4116 0000816 ' A ' = 4116 0000916 ' — ' = 2D16 0000A16 FF16 FF16 0000B16 FF16 0000C16 FF16 0000D16 FF16 0000E16 FF16 0000F16 187 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ SH11 55B MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612MAA-XXXFP/GP MASK ROM CONFIRMATION FORM Mask ROM number The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the assembler source program. EPROM type Code entered in source program 27C201 .SECTION ASCIICODE, ROM DATA .ORG 0C0000H .BYTE ' M30612MAA- ' 27C401 .SECTION ASCIICODE, ROM DATA .ORG 080000H .BYTE ' M30612MAA- ' Note: The ROM cannot be processed if the type No. written to the EPROM does not match the type No. in the check sheet. In the case of floppy disks Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that there is any discrepancy between the contents of these mask files and the ROM data to be burned into products we produce. Check thoroughly the contents of the mask files you give in. Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk. Microcomputer type No. : File code : M30612MAA-XXXFP M30612MAA-XXXGP (hex) Mask file name : .MSK (alpha-numeric 8-digit) 2. Mark specification The mark specification differs according to the type of package. After entering the mark specification on the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for submission to Mitsubishi. For the M30612MAA-XXXFP, submit the 100P6S mark specification sheet. For the M30612MAA-XXXGP, submit the 100P6Q mark specification sheet. 3. Usage Conditions For our reference when of testing our products, please reply to the following questions about the usage of the products you ordered. (1) Which kind of XIN-XOUT oscillation circuit is used? Ceramic resonator Quartz-crystal oscillator External clock input Other ( ) What frequency do you use? f(XIN) = MHZ 188 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ SH11 55B MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612MAA-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind of XCIN-XCOUT oscillation circuit is used? Ceramic resonator Quartz-crystal oscillator External clock input Other ( ) What frequency do you use? f(XCIN) = kHZ (3) Which operation mode do you use? Single-chip mode Memory expansion mode Microprocessor mode (4) Which operating ambient temperature do you use? –10 °C to 75 °C –20 °C to 75 °C –10 °C to 85 °C –20 °C to 85 °C (5) Which operating supply voltage do you use? 2.7V to 3.2V 3.2V to 3.7V 4.2V to 4.7V 4.7V to 5.2V Thank you cooperation. 4. Special item (Indicate none if there is no specified item) Mask ROM number –40 °C to 75 °C –40 °C to 85 °C 3.7V to 4.2V 5.2V to 5.5V 189 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ SH11 54B Mask ROM number MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612MCA-XXXFP/GP MASK ROM CONFIRMATION FORM Receipt Date : Section head signature Supervisor signature Note : Please complete all items marked . ) Customer Date issued Date : 1. Check sheet Name the product you order, and choose which to give in, EPROMs or floppy disks. If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by means of floppy disks, one floppy disk is required per pattern. In the case of EPROMs Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any discrepancy between the data on the EPROM sets and the ROM data written to the product. Please carefully check the data on the EPROMs being submitted to Mitsubishi. Microcomputer type No. : M30612MCA-XXXFP M30612MCA-XXXGP (hex) Checksum code for total EPROM area : EPROM type : 27C201 Address 0000016 Product : Area containing ASCII 0000F16 code for M30612MCA 0001016 1FFFF16 2000016 ROM(128K) 3FFFF16 7FFFF16 27C401 Address 0000016 Product : Area containing ASCII 0000F16 code for M30612MCA 0001016 5FFFF16 6000016 ROM(128K) signature Issuance Company name TEL ( Submitted by Supervisor Address (1) Write “FF16” to the lined area. 0000016 ' M ' (2) The area from 0000016 to 0000F16 is for storing 0000116 ' 3 ' data on the product type name. 0000216 ' 0 ' The ASCII code for 'M30612MCA-' is shown at right. 0000316 ' 6 ' The data in this table must be written to address 0000416 ' 1 ' 0000016 to 0000F16. 0000516 ' 2 ' Both address and data are shown in hex. 0000616 ' M ' 0000716 ' C ' Address = 4D16 = 3316 = 3016 = 3616 = 3116 = 3216 = 4D16 = 4316 0000816 ' A ' = 4116 0000916 ' — ' = 2D16 0000A16 FF16 FF16 0000B16 FF16 0000C16 FF16 0000D16 FF16 0000E16 FF16 0000F16 190 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ SH11 54B MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612MCA-XXXFP/GP MASK ROM CONFIRMATION FORM Mask ROM number The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the assembler source program. EPROM type Code entered in source program 27C201 .SECTION ASCIICODE, ROM DATA .ORG 0C0000H .BYTE ' M30612MCA- ' 27C401 .SECTION ASCIICODE, ROM DATA .ORG 080000H .BYTE ' M30612MCA- ' Note: The ROM cannot be processed if the type No. written to the EPROM does not match the type No. in the check sheet. In the case of floppy disks Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that there is any discrepancy between the contents of these mask files and the ROM data to be burned into products we produce. Check thoroughly the contents of the mask files you give in. Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk. Microcomputer type No. : File code : M30612MCA-XXXFP M30612MCA-XXXGP (hex) Mask file name : .MSK (alpha-numeric 8-digit) 2. Mark specification The mark specification differs according to the type of package. After entering the mark specification on the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for submission to Mitsubishi. For the M30612MCA-XXXFP, submit the 100P6S mark specification sheet. For the M30612MCA-XXXGP, submit the 100P6Q mark specification sheet. 3. Usage Conditions For our reference when of testing our products, please reply to the following questions about the usage of the products you ordered. (1) Which kind of XIN-XOUT oscillation circuit is used? Ceramic resonator Quartz-crystal oscillator External clock input Other ( ) What frequency do you use? f(XIN) = MHZ 191 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ SH11 54B MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30612MCA-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind of XCIN-XCOUT oscillation circuit is used? Ceramic resonator Quartz-crystal oscillator External clock input Other ( ) What frequency do you use? f(XCIN) = kHZ (3) Which operation mode do you use? Single-chip mode Memory expansion mode Microprocessor mode (4) Which operating ambient temperature do you use? –10 °C to 75 °C –20 °C to 75 °C –10 °C to 85 °C –20 °C to 85 °C (5) Which operating supply voltage do you use? 2.7V to 3.2V 3.2V to 3.7V 4.2V to 4.7V 4.7V to 5.2V Thank you cooperation. 4. Special item (Indicate none if there is no specified item) Mask ROM number –40 °C to 75 °C –40 °C to 85 °C 3.7V to 4.2V 5.2V to 5.5V 192 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 100P6S-A EIAJ Package Code QFP100-P-1420-0.65 HD D 100 1 81 80 Plastic 100pin 14!20mm body QFP JEDEC Code – Weight(g) 1.58 Lead Material Alloy 42 e MD b2 I2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 y b2 I2 MD ME Dimension in Millimeters Min Nom Max 3.05 – – 0.1 0.2 0 2.8 – – 0.25 0.3 0.4 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 0.65 – – 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 – – 0.1 – – 0° 10° – 0.35 – – 1.3 – – 14.6 – – – – 20.6 HE E 30 51 31 50 A L1 A2 b A1 e y F Detail F 100P6Q-A EIAJ Package Code LQFP100-P-1414-0.50 JEDEC Code – Weight(g) Lead Material Cu Alloy c L Plastic 100pin 14!14mm body LQFP MD D 100 76 1 75 b2 I2 Recommended Mount Pad HE E Symbol A A1 A2 b c D E e HD HE L L1 y b2 I2 MD ME 25 51 26 50 A e F L1 y A1 b L Detail F Dimension in Millimeters Min Nom Max 1.7 – – 0.1 0.2 0 1.4 – – 0.13 0.18 0.28 0.105 0.125 0.175 13.9 14.0 14.1 13.9 14.0 14.1 0.5 – – 15.8 16.0 16.2 15.8 16.0 16.2 0.3 0.5 0.7 1.0 – – 0.1 – – 0° 10° – 0.225 – – – – 1.0 14.4 – – 14.4 – – A2 c ME HD e ME 193 Mitsubishi microcomputers M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Differences between M16C/61 group and M30600M8 Type name Internal memory size Chip select M16C/61 group ROM See Figure 4. ROM Expansion RAM 4 K to 10 K bytes CS0 3000016 to FFFFF16 (besides internal area) CS1 2800016 to 2FFFF16 CS2 0800016 to 27FFF16 CS3 0400016 to 07FFF16 SFR area 0000016 to 003FF16 RAM area 0040016 to 03FFF16 ROM area D000016 to FFFFF16 (PM16=0) ROM area F800016 to FFFFF16 (PM16=1) (Note) 3 channel (clocked SIO / UART) :2 channel (clocked SIO / UART / SIM) Port P70 Port P71 Port P72 Port P73 TXD2 / TA0OUT RXD2 / TA0IN CLK2 / TA1OUT CTS2 / RTS2 / TA1IN CS0 CS1 CS2 CS3 M30600M8 64 K bytes 10 K bytes 9000016 to FFFFF16 (besides internal area) 1000016 to 8FFFF16 0800016 to 0FFFF16 0400016 to 07FFF16 Internal area on memory expansion mode SFR area 0000016 to 003FF16 RAM area 0040016 to 03FFF16 ROM area D000016 to FFFFF16 (FIX) Serial I/O 2 channel (clocked SIO / UART) Port P70 Port P71 Port P72 Port P73 TA0OUT TA0IN TA1OUT TA1IN Port P70 to P73 function Port output style Port P93 and P94 pull-up set up condition Port P70 and Port P71 are N-channel open drain Others are CMOS All of the following: • Pull-up is selected. • DA output is enabled. • Input port is selected. Internal 20 sources External 5 sources Software 4 sources Add 3 sources -trans., recv. and arbit. for UART2 All Ports are CMOS Both of the following: • Pull-up is selected. • Input port is selected. Internal 17 sources External 5 sources Software 4 sources Interrupt sources DMA request 1100 1101 1110 1111 Note: M30612M4A/E4 only. DMA0 DMA1 UART2 trans. UART2 trans. UART2 recv. UART2 recv. A-D A-D UART1 trans. UART1 recv. 1100 1101 1110 1111 DMA0 DMA1 UART1 trans. UART1 trans. UART1 recv. UART1 recv. A-D A-D prohibited prohibited 194 Memory map Comparison M30612M4A Memory area ( ROM 32K bytes, RAM 4K bytes) M30600M8 Memory area ( ROM 64K bytes, RAM 10K bytes) 0000016 0000016 SFR area SFR area SFR area SFR area Internal RAM Internal RAM Internally reserved Internally reserved Internally reserved SFR area SFR area 003FF16 0040016 003FF16 0040016 Internal RAM Internal RAM Internal RAM 013FF16 0140016 Internal RAM 02BFF16 02C0016 Internally reserved 0400016 07FFF16 0800016 CS3(16K) CS2(32K) CS2(128K) 27FFF16 2800016 2FFFF16 3000016 CS1(32K) CS1(512K) 8FFFF16 9000016 CS0 (800K:Memory expansion) (256K:Memory expansion) (448K:Microprocessor) (832K:Microprocessor) CS3(16K) 1000016 Inhibited 0400016 07FFF16 0800016 0FFFF16 1000016 External memory area Inhibited 1000016 External memory area External memory area External memory area CFFFF16 D000016 F7FFF16 F800016 CS0 Internally reserved Internally reserved CFFFF16 D000016 EFFFF16 F000016 Internal ROM FFFFF16 Microprocessor mode Internal ROM FFFFF16 Microprocessor mode Internal ROM Memory expansion mode Internal ROM FFFFF16 Single-chip mode FFFFF16 Single-chip mode Memory expansion mode Internal area External area(possible to use for external devices) Inhibited Internally reserved for ROM(possible to use for external devices under PM16=1) M16C / 61 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Mitsubishi microcomputers 195 Keep safety first in your circuit designs! q Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials q q q q q q q q These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http:// www.mitsubishichips.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semicon ductor product distributor for further details on these materials or the products con tained therein. MITSUBISHI SEMICONDUCTORS M16C/61 Group Specification REV.E Apr. First Edition 1999 Editioned by Committee of editing of Mitsubishi Semiconductor Published by Mitsubishi Electric Corp., Kitaitami Works This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©1999 MITSUBISHI ELECTRIC CORPORATION