M30620FCNFP

Rev.1.0 Mitsubishi microcomputers M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description Description The M16C/62N group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, low voltage (2.4V(mask ROM version is 2.2V) to 3.6V), they are capable of executing instructions at high speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communications, industrial equipment, and other high-speed processing applications. The M16C/62N group includes a wide range of products with different internal memory types and sizes and various package types. Features • Memory capacity .................................. ROM (See Figure 1.1.4. ROM Expansion) RAM 10K to 20K bytes • Shortest instruction execution time ...... 62.5ns (f(XIN)=16MHZ, VCC=3.0V to 3.6V) 142.9ns (f(XIN)=7MHZ, VCC=2.4V to 3.6V without software wait) • Supply voltage ..................................... 3.0V to 3.6V (f(XIN)=16MHZ, without software wait) 2.4V to 3.0V (f(XIN)=7MHZ, without software wait) 2.2V to 3.0V (f(XIN)=7MHZ, with software one-wait) :mask ROM version • Low power consumption ...................... 34.0mW (VCC = 3V, f(XIN)=10MHZ, without software wait) 66.0mW (VCC = 3.3V, f(XIN)=16MHZ, without software wait) • Interrupts .............................................. 25 internal and 8 external interrupt sources, 4 software interrupt sources; 7 levels (including key input interrupt) • Multifunction 16-bit timer ...................... 5 output timers + 6 input timers • Serial I/O .............................................. 5 channels (3 for UART or clock synchronous, 2 for clock synchronous) • DMAC .................................................. 2 channels (trigger: 24 sources) • A-D converter ....................................... 10 bits X 8 channels (Expandable up to 18 channels) • D-A converter ....................................... 8 bits X 2 channels • CRC calculation circuit ......................... 1 circuit • Watchdog timer .................................... 1 line • Programmable I/O ............................... 87 lines _______ • Input port .............................................. 1 line (P85 shared with NMI pin) • Memory expansion .............................. Available (to 4M bytes) • Chip select output ................................ 4 lines • Clock generating circuit ....................... 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) Applications Audio, cameras, office equipment, communications equipment, portable equipment ------Table of Contents-----Central Processing Unit (CPU) ..................... 11 Reset ............................................................. 14 Processor Mode ............................................ 25 Clock Generating Circuit ............................... 39 Protection ...................................................... 48 Interrupts ....................................................... 49 Watchdog Timer ............................................ 69 DMAC ........................................................... 71 Timer ............................................................. 81 Serial I/O ..................................................... 111 A-D Converter ............................................. 152 D-A Converter ............................................. 162 CRC Calculation Circuit .............................. 164 Programmable I/O Ports ............................. 166 Electrical characteristics ............................. 176 Flash memory version ................................. 191 1 Mitsubishi microcomputers M16C / 62N Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Configuration Figures 1.1.1 and 1.1.2 show the pin configurations (top view). PIN CONFIGURATION (top view) P10/D8 P11/D9 P12/D10 P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P20/A0(/D0/-) P21/A1(/D1/D0) P22/A2(/D2/D1) P23/A3(/D3/D2) P24/A4(/D4/D3) P25/A5(/D5/D4) P26/A6(/D6/D5) P27/A7(/D7/D6) Vss P30/A8(/-/D7) Vcc P31/A9 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 P42/A18 P43/A19 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P07/AN07/D7 P06/AN06/D6 P05/AN05/D5 P04/AN04/D4 P03/AN03/D3 P02/AN02/D2 P01/AN01/D1 P00/AN00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/SIN4 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 23 45 M16C/62N Group 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P44/CS0 P45/CS1 P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE P52/RD P53/BCLK P54/HLDA P55/HOLD P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P96/ANEX1/SOUT4 P95/ANEX0/CLK4 P94/DA1/TB4IN P93/DA0/TB3IN P92/TB2IN/SOUT3 P91/TB1IN/SIN3 P90/TB0IN/CLK3 BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V P72/CLK2/TA1OUT/V P71/RxD2/SCL/TA0IN/TB5IN (Note) P70/TXD2/SDA/TA0OUT (Note) Note: P70 and P71 are N channel open-drain output pin. Package: 100P6S-A Figure 1.1.1. Pin configuration (top view) 2 Mitsubishi microcomputers M16C / 62N Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (top view) P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P20/A0(/D0/-) P21/A1(/D1/D0) P22/A2(/D2/D1) P23/A3(/D3/D2) P24/A4(/D4/D3) P25/A5(/D5/D4) P26/A6(/D6/D5) P27/A7(/D7/D6) Vss P30/A8(/-/D7) Vcc P31/A9 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P12/D10 P11/D9 P10/D8 P07/AN07/D7 P06/AN06/D6 P05/AN05/D5 P04/AN04/D4 P03/AN03/D3 P02/AN02/D2 P01/AN01/D1 P00/AN00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/SIN4 P96/ANEX1/SOUT4 P95/ANEX0/CLK4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 12 345 67 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 M16C/62N Group P42/A18 P43/A19 P44/CS0 P45/CS1 P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE P52/RD P53/BCLK P54/HLDA P55/HOLD P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 P70/TXD2/SDA/TA0OUT (Note) P71/RxD2/SCL/TA0IN/TB5IN (Note) P72/CLK2/TA1OUT/V P94/DA1/TB4IN P93/DA0/TB3IN P92/TB2IN/SOUT3 P91/TB1IN/SIN3 P90/TB0IN/CLK3 BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V Note: P70 and P71 are N channel open-drain output pin. Package: 100P6Q-A Figure 1.1.2. Pin configuration (top view) 3 Mitsubishi microcomputers M16C / 62N Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Block Diagram Figure 1.1.3 is a block diagram of the M16C/62N group. 8 8 8 8 8 8 8 I/O ports Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7 Internal peripheral functions Timer Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer TA3 (16 bits) Timer TA4 (16 bits) Timer TB0 (16 bits) Timer TB1 (16 bits) Timer TB2 (16 bits) Timer TB3 (16 bits) Timer TB4 (16 bits) Timer TB5 (16 bits) A-D converter (10 bits X 8 channels Expandable up to 18 channels) System clock generator XIN-XOUT XCIN-XCOUT Clock synchronous SI/O 8 Port P8 UART/clock synchronous SI/O (8 bits X 3 channels) CRC arithmetic circuit (CCITT ) (Polynomial : X16+X12+X5+1) (8 bits X 2 channels) 7 Port P85 M16C/60 series16-bit CPU core Registers Program counter PC Stack pointer ISP USP Vector table INTB Flag register FLG R0H R0L R0H R0L R1H R1L R1H R1L R2 R2 R3 R3 A0 A0 A1 A1 FB FB SB Memory ROM (Note 1) RAM (Note 2) Watchdog timer (15 bits) Port P9 8 DMAC (2 channels) Port P10 D-A converter (8 bits X 2 channels) Multiplier 8 Note 1: ROM size depends on MCU type. Note 2: RAM size depends on MCU type. Figure 1.1.3. Block diagram of M16C/62N group 4 Mitsubishi microcomputers M16C / 62N Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Performance Outline Table 1.1.1 is a performance outline of M16C/62N group. Table 1.1.1. Performance outline of M16C/62N group Item Number of basic instructions Shortest instruction execution time Performance 91 instructions 62.5ns(f(XIN)=16MHZ, VCC=3.0V to 3.6V) 142.9ns(f(XIN)=7MHZ, VCC=2.4V to 3.6V, without software wait) Memory ROM (See the figure 1.1.4. ROM Expansion) capacity RAM 10K to 20K bytes I/O port P0 to P10 (except P85) 8 bits x 10, 7 bits x 1 Input port P85 1 bit x 1 Multifunction TA0, TA1, TA2, TA3, TA4 16 bits x 5 timer TB0, TB1, TB2, TB3, TB4, TB5 16 bits x 6 Serial I/O UART0, UART1, UART2 (UART or clock synchronous) x 3 SI/O3, SI/O4 A-D converter D-A converter DMAC CRC calculation circuit Watchdog timer Interrupt Clock generating circuit Supply voltage (Clock synchronous) x 2 10 bits x (8 x 2 + 2) channels 8 bits x 2 2 channels (trigger: 24 sources) CRC-CCITT 15 bits x 1 (with prescaler) 25 internal and 8 external sources, 4 software sources, 7 levels 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) 3.0V to 3.6V (f(XIN)=16MHZ, without software wait) 2.4V to 3.0V (f(XIN)=7MHZ, without software wait) 2.2V to 3.0V (f(XIN)=7MHZ, with software one-wait):mask ROM version 34.0mW (VCC=3V, f(XIN)=10MHZ, without software wait) 66.0mW (VCC=3.3V, f(XIN)=16MHZ, without software wait) 3.3V 1mA Available (to 4M bytes) CMOS high performance silicon gate 100-pin plastic molded QFP Power consumption I/O I/O withstand voltage characteristics Output current Memory expansion Device configuration Package 5 Mitsubishi microcomputers M16C / 62N Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Mitsubishi plans to release the following products in the M16C/62N group: (1) Support for mask ROM version and flash memory version (2) ROM capacity (3) Package 100P6S-A : Plastic molded QFP (mask ROM and flash memory versions) 100P6Q-A : Plastic molded QFP (mask ROM and flash memory versions) ROM Size (Bytes) External ROM 256K 128K 96K 64K 32K Mask ROM version Flash memory version M30624MGN-XXXFP/GP M30622MGN-XXXFP/GP M30620MCN-XXXFP/GP M30624FGNFP/GP M30620FCNFP/GP Figure 1.1.4. ROM expansion The M16C/62N group products currently supported are listed in Table 1.1.2. Table 1.1.2. M16C/62N group As of May 2002 Remarks Type No. M30620MCN-XXXFP M30620MCN-XXXGP M30622MGN-XXXFP M30622MGN-XXXGP M30624MGN-XXXFP M30624MGN-XXXGP M30620FCNFP M30620FCNGP M30624FGNFP M30624FGNGP ROM capacity RAM capacity 128K bytes 256K bytes 256K bytes 128K bytes 256K bytes 10K bytes 12K bytes 20K bytes 10K bytes 20K bytes Package type 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A Mask ROM version Flash memory version 6 Mitsubishi microcomputers M16C / 62N Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Type No. M 3 0 6 2 0 M C N– X X X F P Package type: FP : Package GP : 100P6S-A 100P6Q-A ROM No. Omitted for flash memory version ROM capacity: C : 128K bytes G: 256K bytes Memory type: M : Mask ROM version F : Flash memory version Shows RAM capacity, pin count, etc (The value itself has no specific meaning) M16C/62 Group M16C Family Figure 1.1.5. Type No., memory size, and package 7 Mitsubishi microcomputers M16C / 62N Group Pin Description Pin Description Pin name VCC, VSS CNVSS Signal name Power supply input CNVSS Input I/O type Function Supply 2.4V to 3.6 V to the VCC pin. Supply 0 V to the VSS pin. This pin switches between processor modes. Connect this pin to the VSS pin when after a reset you want to start operation in single-chip mode (memory expansion mode) or the VCC pin when starting operation in microprocessor mode. A “L” on this input resets the microcomputer. These pins are provided for the main clock generating circuit.Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. This pin selects the width of an external data bus. A 16-bit width is selected when this input is “L”; an 8-bit width is selected when this input is “H”. This input must be fixed to either “H” or “L”. Connect this pin to the VSS pin when not using external data bus. This pin is a power supply input for the A-D converter. Connect this pin to VCC. This pin is a power supply input for the A-D converter. Connect this pin to VSS. Input Input/output This pin is a reference voltage input for the A-D converter. This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When used for input in single-chip mode, the port can be set to have or not have a pull-up resistor in units of four bits by software. In memory expansion and microprocessor modes, selection of the internal pull-resistor is not available. When used for single-chip mode, P0 also function as A-D converter extended input pins as selected by software. When set as a separate bus, these pins input and output data (D0–D7). This is an 8-bit I/O port equivalent to P0. P15 to P17 also function as external interrupt pins as selected by software. When set as a separate bus, these pins input and output data (D8–D15). This is an 8-bit I/O port equivalent to P0. These pins output 8 low-order address bits (A0–A7). If the external bus is set as an 8-bit wide multiplexed bus, these pins input and output data (D0–D7) and output 8 low-order address bits (A0–A7) separated in time by multiplexing. If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D0–D6) and output address (A1–A7) separated in time by multiplexing. They also output address (A0). This is an 8-bit I/O port equivalent to P0. These pins output 8 middle-order address bits (A8–A15). If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D7) and output address (A8) separated in time by multiplexing. They also output address (A9–A15). This is an 8-bit I/O port equivalent to P0. These pins output A16–A19 and CS0–CS3 signals. A16–A19 are 4 highorder address bits. CS0–CS3 are chip select signals used to specify an access space. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER RESET XIN XOUT Reset input Clock input Clock output Input Input Output BYTE External data bus width select input Analog power supply input Analog power supply input Reference voltage input I/O port P0 Input AVCC AVSS VREF P00 to P07 D0 to D7 P10 to P17 I/O port P1 Input/output Input/output D8 to D15 P20 to P27 A0 to A7 A0/D0 to A7/D7 I/O port P2 Input/output Input/output Output Input/output A0 A1/D0 to A7/D6 P30 to P37 A8 to A15 A8/D7, A9 to A15 P40 to P47 A16 to A19, CS0 to CS3 I/O port P4 I/O port P3 Output Input/output Input/output Output Input/output Output Input/output Output Output 8 Mitsubishi microcomputers M16C / 62N Group Pin Description Pin Description Pin name P50 to P57 Signal name I/O port P5 I/O type Input/output Function This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of the same frequency as XCIN as selected by software. Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE signals. WRL and WRH, and BHE and WR can be switched using software control. WRL, WRH, and RD selected With a 16-bit external data bus, data is written to even addresses when the WRL signal is “L” and to the odd addresses when the WRH signal is “L”. Data is read when RD is “L”. WR, BHE, and RD selected Data is written when WR is “L”. Data is read when RD is “L”. Odd addresses are accessed when BHE is “L”. Use this mode when using an 8-bit external data bus. While the input level at the HOLD pin is “L”, the microcomputer is placed in the hold state. While in the hold state, HLDA outputs a “L” level. ALE is used to latch the address. While the input level of the RDY pin is “L”, the microcomputer is in the ready state. This is an 8-bit I/O port equivalent to P0. When used for input in singlechip, memory expansion, and microprocessor modes, the port can be set to have or not have a pull-up resistor in units of four bits by software. Pins in this port also function as UART0 and UART1 I/O pins as selected by software. This is an 8-bit I/O port equivalent to P6 (P70 and P71 are N channel open-drain output). Pins in this port also function as timer A0–A3, timer B5 or UART2 I/O pins as selected by software. P80 to P84, P86, and P87 are I/O ports with the same functions as P6. Using software, they can be made to function as the I/O pins for timer A4 and the input pins for external interrupts. P86 and P87 can be set using software to function as the I/O pins for a sub clock generation circuit. In this case, connect a quartz oscillator between P86 (XCOUT pin) and P87 (XCIN pin). P85 is an input-only port that also functions for NMI. The NMI interrupt is generated when the input at this pin changes from “H” to “L”. The NMI function cannot be cancelled using software. The pull-up cannot be set for this pin. This is an 8-bit I/O port equivalent to P6. Pins in this port also function as SI/O3, 4 I/O pins, Timer B0–B4 input pins, D-A converter output pins, A-D converter extended input pins, or A-D trigger input pins as selected by software. This is an 8-bit I/O port equivalent to P6. Pins in this port also function as A-D converter input pins as selected by software. Furthermore, P104 –P107 also function as input pins for the key input interrupt function. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER WRL / WR, WRH / BHE, RD, BCLK, HLDA, HOLD, ALE, RDY Output Output Output Output Output Input Output Input P60 to P67 I/O port P6 Input/output P70 to P77 I/O port P7 Input/output P80 to P84, P86, P87, P85 I/O port P8 Input/output Input/output Input/output I/O port P85 Input P90 to P97 I/O port P9 Input/output P100 to P107 I/O port P10 Input/output 9 Mitsubishi microcomputers Memory M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Operation of Functional Blocks The M16C/62N group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC calculation circuit, A-D converter, and I/O ports. The following explains each unit. Memory Figure 1.3.1 is a memory map of the M16C/62N group. The address space extends the 1M bytes from address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30620MCN-XXXFP, there is 128K bytes of internal ROM from E000016 to FFFFF16. The vector table for fixed interrupts such as _______ the reset and NMI are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details. From 0040016 up is RAM. For example, in the M30620MCN-XXXFP, 12K bytes of internal RAM is mapped to the space from 0040016 to 033FF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated. The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Figures 1.6.1 to 1.6.3 are location of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes. The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps. In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be used. For example, in the M30620MCN-XXXFP, the following spaces cannot be used. • The space between 0340016 and 03FFF16 (Memory expansion and microprocessor modes) • The space between D000016 and DFFFF16 (Memory expansion mode) 0000016 SFR area For details, see Figures 1.6.1 to 1.6.3 FFE0016 0040016 Address XXXXX16 02BFF16 033FF16 053FF16 XXXXX16 Internal reserved area (Note 1) RAM size 10K bytes 12K bytes 20K bytes Internal RAM area Special page vector table 0400016 External area ROM size 128K bytes 256K bytes Address YYYYY16 E000016 C000016 D000016 YYYYY16 Internal reserved area (Note 2) FFFDC16 Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer DBC NMI Reset Internal ROM area FFFFF16 FFFFF16 Note 1: During memory expansion and microprocessor modes, can not be used. Note 2: In memory expansion mode, can not be used. Note 3: These memory maps show an instance in which PM13 is set to 0; but in the case of products in which the internal RAM and the internal ROM are expanded to over 15 Kbytes and 192 Kbytes, respectively, they show an instance in which PM13 is set to 1. Figure 1.3.1. Memory map 10 Mitsubishi microcomputers M16C / 62N Group CPU SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Central Processing Unit (CPU) The CPU has a total of 13 registers shown in Figure 1.4.1. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks. b15 b8 b7 b0 R0(Note) H L b15 b8 b7 b0 b19 b0 R1(Note) H L Data registers PC Program counter b15 b0 b19 b0 R2(Note) INTB H L Interrupt table register b0 b15 b0 b15 R3(Note) USP User stack pointer b15 b0 b15 b0 A0(Note) Address registers ISP Interrupt stack pointer b15 b0 b15 b0 A1(Note) SB Static base register b15 b0 b15 b0 FB(Note) Frame base registers FLG Flag register IPL U I OBS Z DC Note: These registers consist of two register banks. Figure 1.4.1. Central processing unit register (1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3) Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0/R3R1). (2) Address registers (A0 and A1) Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). 11 Mitsubishi microcomputers M16C / 62N Group CPU (3) Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (4) Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed. (5) Interrupt table register (INTB) Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) Stack pointer (USP/ISP) Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG). (7) Static base register (SB) Static base register (SB) is configured with 16 bits, and is used for SB relative addressing. (8) Flag register (FLG) Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.4.2 shows the flag register (FLG). The following explains the function of each flag: • Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. • Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to “0” when the interrupt is acknowledged. • Bit 2: Zero flag (Z flag) This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”. • Bit 3: Sign flag (S flag) This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”. • Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”. • Bit 5: Overflow flag (O flag) This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”. • Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0” when the interrupt is acknowledged. 12 Mitsubishi microcomputers M16C / 62N Group CPU SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER • Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this flag is “1”. This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed. • Bits 8 to 11: Reserved area • Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled. • Bit 15: Reserved area The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details. b15 b0 IPL U I OBSZDC Flag register (FLG) Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Figure 1.4.2. Flag register (FLG) 13 Mitsubishi microcomputers Reset Reset M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See “Software Reset” for details of software resets.) This section explains on hardware resets. When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H” level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. The RAM is undefined at power on. The initial values must therfore be set. When a reset signal is applied while the CPU is writing a value to the RAM, the value may be set as unknown due to the termination of the CPU access. Figure 1.5.1 shows the example reset circuit. Figure 1.5.2 shows the reset sequence. 3V 2.4V VCC 0V 3V RESET 0.48V 0V More than 20 cycles of XIN are needed. Example when VCC = 3V. RESET VCC Figure 1.5.1. Example reset circuit XIN More than 20 cycles are needed Microprocessor mode BYTE = “H” RESET BCLK 28cycles BCLK Content of reset vector Address FFFFC16 FFFFD16 FFFFE16 RD WR CS0 Microprocessor mode BYTE = “L” Address FFFFC16 FFFFE16 Content of reset vector RD WR CS0 Single chip mode Address FFFFC16 FFFFE16 Content of reset vector Figure 1.5.2. Reset sequence 14 Mitsubishi microcomputers Reset M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ____________ Table 1.5.1 shows the statuses of the other pins while the RESET pin level is “L”. Figures 1.5.3 and 1.5.4 show the internal status of the microcomputer immediately after the reset is cancelled. ____________ Table 1.5.1. Pin status when RESET pin level is “L” Status Pin name P0 P1 P2, P3, P40 to P43 P44 P45 to P47 CNVSS = VCC CNVSS = VSS BYTE = VSS Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Data input (floating) Data input (floating) Address output (undefined) CS0 output (“H” level is output) Input port (floating) (pull-up resistor is on) WR output (“H” level is output) BHE output (undefined) RD output (“H” level is output) BCLK output BYTE = VCC Data input (floating) Input port (floating) Address output (undefined) CS0 output (“H” level is output) Input port (floating) (pull-up resistor is on) WR output (“H” level is output) BHE output (undefined) RD output (“H” level is output) BCLK output P50 P51 P52 P53 P54 Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) HLDA output (The output value HLDA output (The output value depends on the input to the depends on the input to the HOLD pin) HOLD pin) HOLD input (floating) ALE output (“L” level is output) RDY input (floating) Input port (floating) HOLD input (floating) ALE output (“L” level is output) RDY input (floating) Input port (floating) P55 P56 P57 Input port (floating) Input port (floating) Input port (floating) P6, P7, P80 to P84, P86, P87, P9, P10 Input port (floating) 15 Mitsubishi microcomputers Reset M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Processor mode register 0 (Note) (2) Processor mode register 1 (3) System clock control register 0 (4) System clock control register 1 (5) Chip select control register (6) Address match interrupt enable register (7) Protect register (8) Data bank register (9) Watchdog timer control register (10) Address match interrupt register 0 (000416)··· 0016 0 (29) UART1 transmit interrupt control register (30) UART1 receive interrupt control register (31) Timer A0 interrupt control register (32) Timer A1 interrupt control register (33) Timer A2 interrupt control register (34) Timer A3 interrupt control register (35) Timer A4 interrupt control register (36) Timer B0 interrupt control register (37) Timer B1 interrupt control register (38)Timer B2 interrupt control register (39) INT0 interrupt control register (40) INT1 interrupt control register (41) INT2 interrupt control register (42) Timer B3,4,5 count start flag (43) Three-phase PWM control register 0 (44) Three-phase PWM control register 1 (45) Three-phase output buffer register 0 (46) Three-phase output buffer register 1 (47) Timer B3 mode register (48) Timer B4 mode register (49) Timer B5 mode register (50) Interrupt cause select register (51) SI/O3 control register (52) SI/O4 control register (53) UART2 special mode register 3 (54) UART2 special mode register 2 (55) UART2 special mode register (56) UART2 transmit/receive mode register (57) UART2 transmit/receive control register 0 (58) UART2 transmit/receive control register 1 (005316)··· (005416)··· (005516)··· (005616)··· (005716)··· (005816)··· (005916)··· (005A16)··· (005B16)··· (005C16)··· (005D16)··· (005E16)··· (005F16)··· ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 00?000 00?000 00?000 (000516)··· 0 0 0 0 0 0 (000616)··· 0 1 0 0 1 0 0 0 (000716)··· 0 0 1 0 0 0 0 0 (000816)··· 0 0 0 0 0 0 0 1 (000916)··· (000A16)··· (000B16)··· 0016 00 000 (000F16)··· 0 0 0 ? ? ? ? ? (001016)··· (001116)··· (001216)··· 0016 0016 0000 0016 0016 0000 (11) Address match interrupt register 1 (001416)··· (001516)··· (001616)··· (034016)··· 0 0 0 (034816)··· (034916)··· (034A16)··· (034B16)··· 0016 0016 0016 0016 (12) DMA0 control register (13) DMA1 control register (14) INT3 interrupt control register (15) Timer B5 interrupt control register (16) Timer B4 interrupt control register (17) Timer B3 interrupt control register (18) SI/O4 interrupt control register (19) SI/O3 interrupt control register Bus collision detection interrupt (20) control register (21) DMA0 interrupt control register (22) DMA1 interrupt control register (23) Key input interrupt control register (24) A-D conversion interrupt control register (25) UART2 transmit interrupt control register (26) UART2 receive interrupt control register (27) UART0 transmit interrupt control register (28)UART0 receive interrupt control register (002C16)··· 0 0 0 0 0 ? 0 0 (003C16)··· 0 0 0 0 0 ? 0 0 (004416)··· (004516)··· (004616)··· (004716)··· (004816)··· (004916)··· (004A16)··· (004B16)··· (004C16)··· (004D16)··· (004E16)··· (004F16)··· (005016)··· (005116)··· (005216)··· 00?000 ?000 ?000 ?000 00?000 00?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 (035B16)··· 0 0 ? ? 0 0 0 0 (035C16)··· 0 0 ? (035D16)··· 0 0 ? (035F16)··· (036216)··· (036616)··· (037516)··· (037616)··· (037716)··· (037816)··· 0000 0000 0016 4016 4016 0016 0016 8016 0016 (037C16)··· 0 0 0 0 1 0 0 0 (037D16)··· 0 0 0 0 0 0 1 0 x : Nothing is mapped to this bit ? : Undefined The content of other registers are undefined when the microcomputer is reset. The initial values must therefore be set. The RAM is undefined at power on. The initial values must therefore be set. When a reset signal is applied while the CPU is writing a value to the RAM, the value may be set as unknown due to the termination of the CPU access. Note : When the VCC level is applied to the CNVSS pin, it is 0316 at a reset. Figure 1.5.3. Device's internal status after a reset is cleared 16 Mitsubishi microcomputers Reset M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (59) Count start flag (60) Clock prescaler reset flag (61) One-shot start flag (62) Trigger select flag (63) Up-down flag (64) Timer A0 mode register (65) Timer A1 mode register (66) Timer A2 mode register (67) Timer A3 mode register (68) Timer A4 mode register (69) Timer B0 mode register (70) Timer B1 mode register (71) Timer B2 mode register (72) UART0 transmit/receive mode register (73) UART0 transmit/receive control register 0 (74) UART0 transmit/receive control register 1 (75) UART1 transmit/receive mode register (038016)··· (038116)··· 0 (038216)··· 0 0 (038316)··· (038416)··· (039616)··· (039716)··· (039816)··· (039916)··· (039A16)··· 0016 (85) A-D control register 1 (86) D-A control register (03D716)··· (03DC16)··· (03E216)··· (03E316)··· (03E616)··· (03E716)··· (03EA16)··· (03EB16)··· (03EE16)··· (03EF16)··· (03F216)··· 0 0 (03F316)··· (03F616)··· (03FC16)··· 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 00000 0016 0016 0016 0016 0016 0016 000016 000016 000016 0000016 000016 000016 000016 000016 00000 0016 0016 0016 0016 0016 0016 0016 (87) Port P0 direction register (88) Port P1 direction register (89) Port P2 direction register (90) Port P3 direction register (91) Port P4 direction register (92) Port P5 direction register (93) Port P6 direction register (94) Port P7 direction register (95) Port P8 direction register (96) Port P9 direction register (97) Port P10 direction register (98) Pull-up control register 0 (039B16)··· 0 0 ? ? 0 0 0 0 (039C16)··· 0 0 ? (039D16)··· 0 0 ? (03A016)··· 0000 0000 0016 (03A416)··· 0 0 0 0 1 0 0 0 (03A516)··· 0 0 0 0 0 0 1 0 (03A816)··· 0016 (99) Pull-up control register 1(Note1) (03FD16)··· (100) Pull-up control register 2 (101) Port control register (102) Data registers (R0/R1/R2/R3) (103) Address registers (A0/A1) (104) Frame base register (FB) (105) Interrupt table register (INTB) (106) User stack pointer (USP) (107) Interrupt stack pointer (ISP) (108) Static base register (SB) (03FE16)··· (03FF16)··· (76) UART1 transmit/receive control register 0 (03AC16)··· 0 0 0 0 1 0 0 0 (77) UART1 transmit/receive control register 1 (03AD16)··· 0 0 0 0 0 0 1 0 (78) UART transmit/receive control register 2 (79) Flash identification register (Note2) (80) Flash memory control register 0 (Note2) (81) DMA0 cause select register (82) DMA1 cause select register (83) A-D control register 2 (84) A-D control register 0 (03B016)··· (03B416)··· (03B716)··· (03B816)··· (03BA16)··· 0000000 0016 000001 0016 0016 0 (03D416)··· 0 0 0 0 (109) Flag register (FLG) (03D616)··· 0 0 0 0 0 ? ? ? x : Nothing is mapped to this bit ? : Undefined The content of other registers are undefined when the microcomputer is reset. The initial values must therefore be set. The RAM is undefined at power on. The initial values must therefore be set. When a reset signal is applied while the CPU is writing a value to the RAM, the value may be set as unknown due to the termination of the CPU access. Note 1: When the VCC level is applied to the CNVSS pin, it is 0216 at a reset. Note 2: This register is only exist in flash memory version. Figure 1.5.4. Device's internal status after a reset is cleared 17 Mitsubishi microcomputers SFR M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 004016 004116 004216 004316 Processor mode register 0 (PM0) Processor mode register 1(PM1) System clock control register 0 (CM0) System clock control register 1 (CM1) Chip select control register (CSR) Address match interrupt enable register (AIER) Protect register (PRCR) Data bank register (DBR) 004416 004516 004616 004716 004816 004916 004A16 004B16 INT3 interrupt control register (INT3IC) Timer B5 interrupt control register (TB5IC) Timer B4 interrupt control register (TB4IC) Timer B3 interrupt control register (TB3IC) SI/O4 interrupt control register (S4IC) INT5 interrupt control register (INT5IC) SI/O3 interrupt control register (S3IC) INT4 interrupt control register (INT4IC) Bus collision detection interrupt control register (BCNIC) Watchdog timer start register (WDTS) Watchdog timer control register (WDC) Address match interrupt register 0 (RMAD0) 004C16 004D16 004E16 004F16 005016 005116 005216 DMA0 interrupt control register (DM0IC) DMA1 interrupt control register (DM1IC) Key input interrupt control register (KUPIC) A-D conversion interrupt control register (ADIC) UART2 transmit interrupt control register (S2TIC) UART2 receive interrupt control register (S2RIC) UART0 transmit interrupt control register (S0TIC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control register (S1TIC) UART1 receive interrupt control register (S1RIC) Address match interrupt register 1 (RMAD1) 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 DMA0 source pointer (SAR0) 005F16 006016 006116 006216 Timer A0 interrupt control register (TA0IC) Timer A1 interrupt control register (TA1IC) Timer A2 interrupt control register (TA2IC) Timer A3 interrupt control register (TA3IC) Timer A4 interrupt control register (TA4IC) Timer B0 interrupt control register (TB0IC) Timer B1 interrupt control register (TB1IC) Timer B2 interrupt control register (TB2IC) INT0 interrupt control register (INT0IC) INT1 interrupt control register (INT1IC) INT2 interrupt control register (INT2IC) DMA0 destination pointer (DAR0) 006316 006416 006516 DMA0 transfer counter (TCR0) DMA0 control register (DM0CON) 032A16 032B16 032C16 032D16 032E16 DMA1 source pointer (SAR1) 032F16 033016 033116 033216 DMA1 destination pointer (DAR1) 033316 033416 033516 033616 033716 033816 033916 DMA1 transfer counter (TCR1) DMA1 control register (DM1CON) 033A16 033B16 033C16 033D16 033E16 033F16 Note 1: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. Figure 1.6.1. Location of peripheral unit control registers (1) 18 Mitsubishi microcomputers SFR M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16 Timer B3, 4, 5 count start flag (TBSR) Timer A1-1 register (TA11) Timer A2-1 register (TA21) Timer A4-1 register (TA41) Three-phase PWM control register 0(INVC0) Three-phase PWM control register 1(INVC1) Three-phase output buffer register 0(IDB0) Three-phase output buffer register 1(IDB1) Dead time timer(DTT) Timer B2 interrupt occurrence frequency set counter(ICTB2) 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 Count start flag (TABSR) Clock prescaler reset flag (CPSRF) One-shot start flag (ONSF) Trigger select register (TRGSR) Up-down flag (UDF) Timer A0 (TA0) Timer A1 (TA1) Timer A2 (TA2) Timer A3 (TA3) Timer A4 (TA4) Timer B0 (TB0) Timer B1 (TB1) Timer B2 (TB2) Timer A0 mode register (TA0MR) Timer A1 mode register (TA1MR) Timer A2 mode register (TA2MR) Timer A3 mode register (TA3MR) Timer A4 mode register (TA4MR) Timer B0 mode register (TB0MR) Timer B1 mode register (TB1MR) Timer B2 mode register (TB2MR) Timer B3 register (TB3) Timer B4 register (TB4) Timer B5 register (TB5) Timer B3 mode register (TB3MR) Timer B4 mode register (TB4MR) Timer B5 mode register (TB5MR) Interrupt cause select register (IFSR) SI/O3 transmit/receive register (S3TRR) SI/O3 control register (S3C) SI/O3 bit rate generator (S3BRG) SI/O4 transmit/receive register (S4TRR) SI/O4 control register (S4C) SI/O4 bit rate generator (S4BRG) 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 UART0 transmit/receive mode register (U0MR) UART0 bit rate generator (U0BRG) UART0 transmit buffer register (U0TB) UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1) UART0 receive buffer register (U0RB) UART1 transmit/receive mode register (U1MR) UART1 bit rate generator (U1BRG) UART1 transmit buffer register (U1TB) UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1) UART1 receive buffer register (U1RB) UART transmit/receive control register 2 (UCON) Flash identification register (FIDR) (Note1) UART2 special mode register 3(U2SMR3) UART2 special mode register 2(U2SMR2) UART2 special mode register (U2SMR) UART2 transmit/receive mode register (U2MR) UART2 bit rate generator (U2BRG) UART2 transmit buffer register (U2TB) UART2 transmit/receive control register 0 (U2C0) UART2 transmit/receive control register 1 (U2C1) UART2 receive buffer register (U2RB) 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 Flash memory control register 0 (FMR0) (Note1) DMA0 request cause select register (DM0SL) DMA1 request cause select register (DM1SL) CRC data register (CRCD) CRC input register (CRCIN) Note 1: This register is only exist in flash memory version. Note 2: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. Figure 1.6.2. Location of peripheral unit control registers (2) 19 Mitsubishi microcomputers SFR M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 A-D register 0 (AD0) A-D register 1 (AD1) A-D register 2 (AD2) A-D register 3 (AD3) A-D register 4 (AD4) A-D register 5 (AD5) A-D register 6 (AD6) A-D register 7 (AD7) A-D control register 2 (ADCON2) A-D control register 0 (ADCON0) A-D control register 1 (ADCON1) D-A register 0 (DA0) D-A register 1 (DA1) D-A control register (DACON) Port P0 (P0) Port P1 (P1) Port P0 direction register (PD0) Port P1 direction register (PD1) Port P2 (P2) Port P3 (P3) Port P2 direction register (PD2) Port P3 direction register (PD3) Port P4 (P4) Port P5 (P5) Port P4 direction register (PD4) Port P5 direction register (PD5) Port P6 (P6) Port P7 (P7) Port P6 direction register (PD6) Port P7 direction register (PD7) Port P8 (P8) Port P9 (P9) Port P8 direction register (PD8) Port P9 direction register (PD9) Port P10 (P10) Port P10 direction register (PD10) Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Pull-up control register 2 (PUR2) Port control register (PCR) Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. Figure 1.6.3. Location of peripheral unit control registers (3) 20 Mitsubishi microcomputers Memory Space Expansion Features Memory Space Expansion Features M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Here follows the description of the memory space expansion features. With the processor running in memory expansion mode or in microprocessor mode, the memory space expansion features provide the means of expanding the accessible space. The memory space expansion features run in one of the three modes given below. (1) Normal mode (no expansion) (2) Memory space expansion mode (to be referred as expansion mode) Use bits 5 and 4 (PM15, PM14) of processor mode register 1 to select a desired mode. The external memory area the chip select signal indicates is different in mode so that the accessible memory space varies. Table 1.7.1 shows how to set individual modes and corresponding accessible memory spaces. For external memory area the chip select signal indicates, see Table 1.10.1 on page 31. Table 1.7.1. The way of setting memory space expansion mode and corresponding memory space Expansion mode How to set PM15 and PM14 Accessible memory space Normal mode (no expansion) 0, 0 Up to 1M byte Expansion mode 1, 1 Up to 4M bytes Here follows the description of individual modes. (1) Normal mode (a mode with memory not expanded) ‘Normal mode’ means a mode in which memory is not expanded. Figure 1.7.1 shows the memory maps and the chip select areas in normal mode. Normal mode (memory area = 1M bytes for PM15 = 0, PM14 = 0) Memory expansion mode 0000016 0040016 Internal RAM area XXXXX16 Internal area reserved 0400016 0800016 Internal area reserved Internal RAMarea SFR area Microprocessor mode SFR area CS3 (16K bytes) CS2 (128K bytes) 2800016 CS1 (32K bytes) 3000016 External area External area CS0 Memory expansion mode: 640K bytes Microprocessor mode: 832K bytes D000016 YYYYY16 Internal area reserved Internal ROM area FFFFF16 RAM size 10K bytes 12K bytes 20K bytes Address XXXXX16 02BFF16 033FF16 053FF16 ROM size 128K bytes 256K bytes Address YYYYY16 E000016 C000016 Note 1: These memory maps show an instance in which PM13 is set to 0; but in the case of products in which the internal RAM and the internal ROM are expanded to over 15 Kbytes and 192 Kbytes, respectively, they show an instance in which PM13 is set to 1. Note 2: The memory maps in single-chip mode are omitted. Figure 1.7.1. The memory maps and the chip select areas in normal mode 21 Mitsubishi microcomputers Memory Space Expansion Features (2) Expansion mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In expansion mode, the data bank register (0000B16) goes effective. Figure 1.7.2 shows the data bank register. Data bank register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DBR Bit symbol Address 000B16 When reset 0016 Bit name Description RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. OFS BSR Offset bit Bank selection bits 0: Not offset 1: Offset b5 b4 b3 b5 b4 b3 0 0 0: Bank 0 0 1 0: Bank 2 1 0 0: Bank 4 1 1 0: Bank 6 0 0 1: Bank 1 0 1 1: Bank 3 1 0 1: Bank 5 1 1 1: Bank 7 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Figure 1.7.2. Data bank register Expansion mode (memory space = 4M bytes for PM15 = 1, PM14 = 1) Memory expansion mode 0000016 0040016 Internal RAM area XXXXX16 Internal area reserved Internal area reserved Microprocessor mode SFR area Internal RAM area SFR area 0400016 0800016 CS3 (16K bytes) CS2 (128K bytes) 2800016 4000016 External area External area CS1 (96K bytes) CS0 Memory expansion mode: 512K bytes x 7banks + 256K bytes Microprocessor mode: 512K bytes x 8banks D000016 YYYYY16 Internal area reserved Addresses from 4000016 through BFFFF16 Bank 7 in fetching a program A bank selected by use of the bank selection bits in accessing data Addresses from C000016 through FFFFF16 Bank 7 invariably Bank number is output to CS3 to CS1 Internal ROM area FFFFF16 RAM size 10K bytes 12K bytes 20K bytes Address XXXXX16 02BFF16 033FF16 053FF16 ROM size 128K bytes 256K bytes Address YYYYY16 E000016 C000016 Note 1: These memory maps show an instance in which PM13 is set to 0; but in the case of products in which the internal RAM and the internal ROM are expanded to over 15 Kbytes and 192 Kbytes, respectively, they show an instance in which PM13 is set to 1. Note 2: The memory maps in single-chip mode are omitted. Figure 1.7.3. Memory location and chip select area in expansion mode 2 22 Mitsubishi microcomputers Memory Space Expansion Features M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The data bank register is made up of the bank selection bits (bits 5 through 3) and the offset bit (bit 2). The bank selection bits are used to set a bank number for accessing data lying between 4000016 and BFFFF16. Assigning 1 to the offset bit provides the means to set offsets covering 4000016. Figure 1.7.3 shows the memory location and chip select areas in expansion mode. _______ The area relevant to CS0 ranges from 4000016 through FFFFF16. As for the area from 4000016 through _______ BFFFF16, the bank number set by use of the bank selection bits are output from the output terminals CS3 _______ _______ _______ - CS1 only in accessing data. In fetching a program, bank 7 (1112) is output from CS3 - CS1. As for the _______ _______ area from C000016 through FFFFF16, bank 7 (1112) is output from CS3 - CS1 without regard to accessing data or to fetching a program. _______ _______ _______ In accessing an area irrelevant to CS0, a chip select signal CS3 (400016 - 7FFF16), CS2 (800016 _______ 27FFF16), and CS1 (2800016 - 3FFFF16) is output depending on the address as in the past. Figure 1.7.4 shows an example of connecting the MCU with a 4-M byte ROM and to a 128-K byte SRAM. _______ _______ _______ _______ Connect the chip select of 4-M byte ROM with CS0. Connect M16C’s CS3, CS2, and CS1 with address inputs AD21, AD20, and AD19 respectively. Connect M16C’s output A19 with address input AD18. Figure 1.7.5 shows the relationship between addresses of the 4-M byte ROM and those of M16C. In this mode, memory is banked every 512 K bytes, so that data access in different banks requires switching over banks. However, data on bank boundaries when offset bit = 0 can be accessed successively by setting the offset bit to 1, because in which case the memory address is offset by 40000 16. For example, two bytes of data located at addresses 0FFFFF16 and 10000016 o f 4-Mbyte ROM can be accessed successively without having to change the bank bit by setting the offset bit to 1 and then accessing addresses 07FFFF16 and 80000016. On the other hand, the SRAM’s chip select assumes _______ that CS0=1 (not selected) _______ and CS2=0 (selected), so _______ connect CS0 with S2 and _______ ____ CS2 with S1. If the SRAM doesn’t have a bipolar chip select input terminal, decode _______ _______ CS0 and CS2 externally. An example of connecting the MCU with external memories in expansion mode (M30620MCN, Microprocessor mode) D0 to D7 A0 to A16 A17 A19 8 DQ0 to DQ7 17 AD0 to AD16 M30620MCN CS1 CS2 CS3 RD CS0 AD19 AD20 AD21 OE CS WR AD0 to AD16 OE S2 S1 W Note: If only one chip select terminal (S1 or S2) is present, decoding by use of an external circuit is required. Figure 1.7.4. An example of connecting the MCU with external memories in expansion mode 128-K byte SRAM DQ0 to DQ7 4-M byte ROM AD17 AD18 23 Mitsubishi microcomputers Memory Space Expansion Features M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Address area map of 4-M byte ROM ROM address Offset bit = 0 000000 40000 M16C address Offset bit = 1 040000 Bank 0 BFFFF 40000 40000 080000 Bank 0 BFFFF 40000 0C0000 Bank 1 BFFFF 40000 Data area 100000 Bank 1 BFFFF 40000 140000 Bank 2 BFFFF 40000 180000 Bank 2 BFFFF 40000 Areas used for data only 00000016 to 38000016 200000 1C0000 Bank 3 BFFFF 40000 Bank 3 BFFFF 40000 240000 Bank 4 BFFFF 40000 280000 Bank 4 BFFFF 40000 2C0000 Bank 5 BFFFF 40000 Data area 300000 Bank 5 BFFFF 40000 340000 Bank 6 BFFFF 40000 Program/ data area Area commonly used for data and programs 38000016 to 3BFFFF16 Area commonly used for data and programs 3C000016 to 3FFFFF16 380000 Bank 6 BFFFF Bank 7 3C0000 Program/ data area 3FFFFF 7FFFF C0000 FFFFF Figure 1.7.5. Relationship between addresses on 4-M byte ROM and those on M16C 24 Mitsubishi microcomputers Software Software Reset Software Reset M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the microcomputer. A software reset has the same effect as a hardware reset. The contents of internal RAM are preserved. Processor Mode (1) Types of Processor Mode One of three processor modes can be selected: single-chip mode, memory expansion mode, and microprocessor mode. The functions of some pins, the memory map, and the access space differ according to the selected processor mode. • Single-chip mode In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be accessed. However, after the reset has been released and the operation of shifting from the microprocessor mode has started (“H” applied to the CNVSS pin), the internal ROM area cannot be accessed even if the CPU shifts to the single-chip mode. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal peripheral functions. • Memory expansion mode In memory expansion mode, external memory can be accessed in addition to the internal memory space (SFR, internal RAM, and internal ROM). However, after the reset has been released and the operation of shifting from the microprocessor mode has started (“H” applied to the CNVSS pin), the internal ROM area cannot be accessed even if the CPU shifts to the memory expansion mode. In this mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus and register settings. (See “Bus Settings” for details.) • Microprocessor mode In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The internal ROM area cannot be accessed. In this mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus width and register settings. (See “Bus Settings” for details.) In the memory expansion and microprocessor modes, the addressable space can be expanded by using the memory space expansion features. (See “Memory Space Expansion Features” for details.) (2) Setting Processor Modes The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address 000416). Do not set the processor mode bits to “102”. Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore, never change the processor mode bits when changing the contents of other bits. Do not change the processor mode bits simultaneously with other bits when changing the processor mode bits “012” or “112”. Change the processor mode bits after changing the other bits. Also do not attempt to shift to or from the microprocessor mode within the program stored in the internal ROM area. • Applying VSS to CNVSS pin The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode is selected by writing “012” to the processor mode bits. • Applying VCC to CNVSS pin The microcomputer starts to operate in microprocessor mode after being reset. 25 Mitsubishi microcomputers Processor Mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.8.1 shows the processor mode register 0 and 1. Figure 1.8.2 shows the memory maps in each processor mode (without memory area expansion, normal mode). Processor mode register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PM0 Address 000416 When reset 0016 (Note 2) Bit symbol PM00 PM01 PM02 PM03 Bit name Processor mode bit b1 b0 Function 0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Must not be set 1 1: Microprocessor mode 0 : RD,BHE,WR 1 : RD,WRH,WRL The device is reset when this bit is set to “1”. The value of this bit is “0” when read. b5 b4 RW R/W mode select bit Software reset bit PM04 PM05 PM06 Multiplexed bus space select bit 0 0 : Multiplexed bus is not used 0 1 : Allocated to CS2 space 1 0 : Allocated to CS1 space 1 1 : Allocated to entire space (Note4) Port P40 to P43 function select bit (Note 3) BCLK output disable bit 0 : Address output 1 : Port function (Address is not output) 0 : BCLK is output 1 : BCLK is not output (Pin is left floating) PM07 Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register. Note 2: If the VCC voltage is applied to the CNVSS, the value of this register when reset is 0316. (PM00 and PM01 both are set to “1”.) Note 3: Valid in microprocessor and memory expansion modes. Note 4: If the entire space is of multiplexed bus in memory expansion mode, choose an 8bit width.The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. P31 to P37 become a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. Processor mode register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol PM1 Address 000516 When reset 000000X02 Bit symbol Reserved bit Bit name Function Must always be set to “0” RW Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. PM12 PM13 Watchdog timer function select bit Internal reserved area expansion bit (Note 2) 0 : Interrupt 1 : Reset (Note 3) 0: The internal RAM area is 15 kbytes or less and the internal ROM area is 192 kbytes or less 1: Expands the internal RAM area and internal ROM area to over 15 kbytes and to over 192 kbytes respectively. (Note 2) b5 b4 (Note 3) PM14 Memory area expansion bit (Note 4) PM15 0 0 : Normal mode (Do not expand) 0 1 : Must not be set 1 0 : Must not be set 1 1 : Memory area expansion mode Must always be set to “0” Reserved bit PM17 Wait bit 0 : No wait state 1 : Wait state inserted Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register. Note 2: When the reset is revoked, this bit is set to “0”. To expand the internal area, set this bit to “1” in user program. And the top of user program must be allocated to D000016 or subsequent address. Note 3: This bit can only be set to “1”. Note 4: With the processor running in memory expansion mode or in microprocessor mode, setting this bit provides the means of expanding the external memory area. (Normal mode: up to 1M byte, expansion mode : up to 4M bytes) For details, see “Memory space expansion features”. Figure 1.8.1. Processor mode register 0 and 1 26 Mitsubishi microcomputers Processor Mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Single-chip mode 0000016 Memory expansion mode SFR area Internal RAM area Internally reserved area Microprocessor mode SFR area Internal RAM area Internally reserved area SFR area 0040016 Internal RAM area XXXXX16 0400016 Inhibited External area Internally reserved area External area D000016 YYYYY16 Internal ROM area FFFFF16 Internal ROM area RAM size 10K bytes 12K bytes 20K bytes Address XXXXX16 02BFF16 033FF16 053FF16 ROM size 128K bytes 256K bytes Address YYYYY16 E000016 C000016 External area : Accessing this area allows the user to access a device connected externally to the microcomputer. Note : These memory maps show an instance in which PM13 is set to 0; but in the case of products in which the internal RAM and the internal ROM are expanded to over 15 Kbytes and 192 Kbytes, respectively, they show an instance in which PM13 is set to 1. Figure 1.8.2. Memory maps in each processor mode (without memory area expansion, normal mode) Internal Reserved Area Expansion Bit (PM13) This bit expands the internal RAM area and the internal ROM area, and changes the chip select area. In M30624FGN, for example, to set this bit to “1” expands the internal RAM area and the internal ROM area to 20 Kbytes and 256 Kbytes respectively. Refer to Figure 1.8.3 for the chip select area. When the reset is revoked, this bit is set to “0”. To expand the internal area, set this bit to “1” in user program. And the top of user program must be allocated to D000016 or subsequent address. In the case of the product in which the internal ROM is 192 Kbytes or less and the internal RAM is 15 Kbytes or less, set this bit to “0” when this product is used in the memory expansion mode or the microprocessor mode. When the product is used in the single chip mode, the internal area is not expanded and any action is not affected, even if this bit is set to “1”. 27 Mitsubishi microcomputers Processor Mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.8.3 shows the memory maps and the chip selection areas effected by PM13 (the internal reserved area expansion bit) in each processor mode for the product having an internal RAM of more than 15K bytes and a ROM of more than 192K bytes. (1)Normal mode Internal reserved area expansion bit="0" Memory expansion mode 0000016 0040016 0400016 0800016 SFR area (1K bytes) Internal RAM area (15K bytes) Internal reserved area expansion bit="1" (Note) Memory expansion mode 0000016 0040016 SFR area (1K bytes) Internal RAM area (20K bytes) Microprocessor mode SFR area (1K bytes) Internal RAM area (15K bytes) Microprocessor mode SFR area (1K bytes) Internal RAM area (20K bytes) Internal reserved area CS3(16K bytes) CS2 (128K bytes) 0540016 Internal reserved area 0600016 0800016 CS3(8K bytes) CS2 (128K bytes) 2800016 3000016 External area CFFFF16 D000016 Internal ROM area (192K bytes) FFFFF16 After reset External area CS1(32K bytes) 2800016 3000016 External area External area CS1(32K bytes) CS0 Memory expansion mode : 640K bytes Microprocessor mode : 832K bytes BFFFF16 C000016 Internal ROM area (256K bytes) CS0 Memory expansion mode : 576K bytes Microprocessor mode : 832K bytes FFFFF16 After reset, and set the Internal reserved area expansion bit to "1" Note: When the reset is revoked, this bit is set to “0”. Therefore, the top of the user program must be allocated to D000016 or subsequent address. (2)Expansion mode Internal reserved area expansion bit="0" Memory expansion mode 0000016 0040016 0400016 0800016 SFR area (1K bytes) Internal RAM area (15K bytes) Internal reserved area expansion bit="1" (Note) Memory expansion mode 0000016 0040016 SFR area (1K bytes) Microprocessor mode SFR area (1K bytes) Internal RAM area (15K bytes) Microprocessor mode SFR area (1K bytes) Internal RAM area (20K bytes) Internal reserved area CS3(16K bytes) CS2 (128K bytes) Internal RAM area (20K bytes) 0540016 Internal reserved area 0600016 0800016 CS3(8K bytes) CS2(128K bytes) 2800016 2800016 CS1(96K bytes) 4000016 External area External area 4000016 BFFFF16 C000016 External area External area CS1(96K bytes) CS0 CFFFF16 D000016 Internal ROM area (192K bytes) FFFFF16 After reset Memory expansion mode : 512K bytes x 7banks + 256K bytes Microprocessor mode : 512K bytes x 8banks CS0 Internal ROM area (256K bytes) Memory expansion mode : 512K bytes x 7banks + 256K bytes Microprocessor mode : 512K bytes x 8banks FFFFF16 After reset, and set the Internal reserved area expansion bit to "1" Note: When the reset is revoked, this bit is set to “0”. Therefore, the top of the user program must be allocated to D000016 or subsequent address. Figure 1.8.3. Memory location and chip select area in each processor mode 28 Mitsubishi microcomputers M16C / 62N Group Bus Settings Bus Settings The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 000416) are used to change the bus settings. Table 1.9.1 shows the factors used to change the bus settings. Table 1.9.1. Factors for switching bus settings Bus setting Switching external address bus width Switching external data bus width Switching between separate and multiplex bus Switching factor Bit 6 of processor mode register 0 BYTE pin Bits 4 and 5 of processor mode register 0 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Selecting external address bus width The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K bytes address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register 0 is set to “1”, the external address bus width is set to 16 bits, and P2 and P3 become part of the address bus. P40 to P43 can be used as programmable I/O ports. When bit 6 of processor mode register 0 is set to “0”, the external address bus width is set to 20 bits, and P2, P3, and P40 to P43 become part of the address bus. (2) Selecting external data bus width The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can be set.) When the BYTE pin is “L”, the bus width is set to 16 bits; when “H”, it is set to 8 bits. (The internal bus width is permanently set to 16 bits.) While operating, fix the BYTE pin either to “H” or to “L”. (3) Selecting separate/multiplex bus The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0. • Separate bus In this mode, the data and address are input and output separately. The data bus can be set using the BYTE pin to be 8 or 16 bits. When the BYTE pin is “H”, the data bus is set to 8 bits and P0 functions as the data bus and P1 as a programmable I/O port. When the BYTE pin is “L”, the data bus is set to 16 bits and P0 and P1 are both used for the data bus. When the separate bus is used for access, a software wait can be selected. • Multiplex bus In this mode, data and address I/O are time multiplexed. With the BYTE pin = “H”, the 8 bits from D0 to D7 are multiplexed with A0 to A7. With the BYTE pin = “L”, the 8 bits from D0 to D7 are multiplexed with A1 to A8. D8 to D15 are not multiplexed. In this case, the external devices connected to the multiplexed bus are mapped to the microcomputer’s even addresses (every 2nd address). To access these external devices, access the even addresses as bytes. The ALE signal latches the address. It is output from P56. Before using the multiplex bus for access, be sure to insert a software wait. If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width. The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. P31 to P37 become a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. 29 Mitsubishi microcomputers M16C / 62N Group Bus Settings Table 1.9.2. Pin functions for each processor mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Processor mode Single-chip mode Memory expansion mode/microprocessor modes “01”, “10” “00” (separate bus) 8 bits “H” Data bus I/O port Address bus Address bus Address bus Address bus I/O port 16 bits “L” Data bus Data bus Address bus Address bus Address bus Address bus I/O port Memory expansion mode Multiplexed bus space select bit Either CS1 or CS2 is for multiplexed bus and others are for separate bus 8 bits “H” I/O port I/O port I/O port I/O port I/O port I/O port I/O port Data bus I/O port 16 bits “L” Data bus Data bus “11” (Note 1) multiplexed bus for the entire space 8 bit “H” I/O port I/O port Address bus /data bus Address bus /data bus A8/D7 I/O port I/O port Data bus width BYTE pin level P00 to P07 P10 to P17 P20 P21 to P27 P30 P31 to P37 P40 to P43 Port P40 to P43 function select bit = 1 P40 to P43 Port P40 to P43 function select bit = 0 P44 to P47 P50 to P53 P54 P55 P56 P57 Address bus Address bus /data bus(Note 2) Address bus /data bus(Note 2) Address bus Address bus /data bus(Note 2) Address bus /data bus(Note 2) Address bus I/O port Address bus I/O port I/O port Address bus Address bus Address bus Address bus I/O port I/O port I/O port I/O port I/O port I/O port I/O port CS (chip select) or programmable I/O port (For details, refer to “Bus control”) Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK (For details, refer to “Bus control”) HLDA HOLD ALE RDY HLDA HOLD ALE RDY HLDA HOLD ALE RDY HLDA HOLD ALE RDY HLDA HOLD ALE RDY Note 1: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width. The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. P31 to P37 become a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. Note 2: Address bus when in separate bus mode. 30 Mitsubishi microcomputers Bus Control Bus Control M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The following explains the signals required for accessing external devices and software waits. The signals required for accessing the external devices are valid when the processor mode is set to memory expansion mode and microprocessor mode. The software waits are valid in all processor modes. (1) Address bus/data bus The address bus consists of the 20 pins A0 to A19 for accessing the 1M bytes of address space. The data bus consists of the pins for data I/O. When the BYTE pin is “H”, the 8 ports D0 to D7 function as the data bus. When BYTE is “L”, the 16 ports D0 to D15 function as the data bus. When a change is made from single-chip mode to memory expansion mode, the value of the address bus is undefined until external memory is accessed. (2) Chip select signal The chip select signal is output using the same pins as P44 to P47. Bits 0 to 3 of the chip select control register (address 000816) set each pin to function as a port or to output the chip select signal. The chip select control register is valid in memory expansion mode and microprocessor mode. In single-chip mode, P44 to P47 function as programmable I/O ports regardless of the value in the chip select control register. _______ In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been can_______ _______ celled. CS1 to CS3 function as input ports. Figure 1.10.1 shows the chip select control register. The chip select signal can be used to split the external area into as many as four blocks. Tables 1.10.1 and 1.10.2 show the external memory areas specified using the chip select signal. Table 1.10.1. External areas specified by the chip select signals (A product having an internal RAM equal to or less than 15K bytes and a ROM equal to or less than 192K bytes)(Note) Memory space expansion mode Processor mode CS0 3000016 to CFFFF16 (640K bytes) 3000016 to FFFFF16 (832K bytes) 4000016 to BFFFF16 (512K bytes X 7 + 256K bytes) 4000016 to FFFFF16 (512K bytes X 8) Chip select signal CS1 CS2 CS3 Memory expansion mode Specified address range Normal mode (PM15,14=0,0) Microprocessor mode 2800016 to 2FFFF16 (32K bytes) 0800016 to 27FFF16 (128K bytes) 2800016 to 3FFFF16 (96K bytes) 0400016 to 07FFF16 (16K bytes) Memory expansion mode Expansion mode (PM15,14=1,1) Microprocessor mode Note :Be sure to set bit 3 (PM13) of processor mode register 1 to “0”. 31 Mitsubishi microcomputers Bus Control M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.10.2. External areas specified by the chip select signals (A product having an internal RAM of more than 15K bytes and a ROM of more than 192K bytes) Memory space expansion mode Processor mode CS0 When PM13=0 3000016 to CFFFF16 (640K bytes) When PM13=1 3000016 to BFFFF16 (576K bytes) 3000016 to FFFFF16 (816K bytes) 4000016 to BFFFF16 (512K bytes X 7 +256K bytes) 4000016 to FFFFF16 (512K bytes X 8) Chip select signal CS1 CS2 CS3 Specified address range Memory expansion mode Normal mode (PM15,14=0,0) 2800016 to 2FFFF16 (32K bytes) Microprocessor mode 0800016 to 27FFF16 (128K bytes) When PM13=0 0400016 to 07FFF16 (16K bytes) Memory expansion mode Expansion mode (PM15,14=1,1) Microprocessor mode 2800016 to 3FFFF16 (96K bytes) When PM13=1 0600016 to 07FFF16 (8K bytes) Chip select control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol CSR Address 000816 When reset 0116 Bit symbol CS0 CS1 CS2 CS3 CS0W CS1W CS2W CS3W Bit name CS0 output enable bit CS1 output enable bit CS2 output enable bit CS3 output enable bit CS0 wait bit CS1 wait bit CS2 wait bit CS3 wait bit Function 0 : Chip select output disabled (Normal port pin) 1 : Chip select output enabled RW 0 : Wait state inserted 1 : No wait state Figure 1.10.1. Chip select control register The timing of the chip select signal changing to “L”(active) is synchronized with the address bus. But the timing of the chip select signal changing to “H” depends on the area which will be accessed in the next cycle. Figure 1.10.2 shows the output example of the address bus and chip select signal. 32 Mitsubishi microcomputers Bus Control M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Example 1) After access the external area, both the address signal and the chip select signal change concurrently in the next cycle. In this example, after access to the external area(i), an access to the area indicated by the other chip select signal(j) will occur in the next cycle. In this case, both the address bus and the chip select signal change between the two cycles. Example 2) After access the external area, only the chip select signal changes in the next cycle (the address bus does not change). In this example, an access to the internal ROM or the internal RAM in the next cycle will occur, after access to the external area. In this case, the chip select signal changes between the two cycles, but the address does not change. Access to the Access to the Other External Area( i ) External Area( j ) Access to the External Area Internal ROM/RAM Access BCLK Read/Write signal Data bus Address bus Chip select (CS i) Chip select (CS j) Data Address BCLK Read/Write signal Data bus Address bus Chip select Data Address Example 3) After access the external area, only the address bus changes in the next cycle (the chip select signal does not change). In this example, after access to the external area(i), an access to the area indicated by the same chip select signal(i) will occur in the next cycle. In this case, the address bus changes between the two cycles, but the chip select signal does not change. Example 4) After access the external area, either the address signal and the chip select signal do not change in the next cycle. In this example, any access to any area does not occur in the next cycle (either instruction prefetch does not occur). In this case,either the address bus and chip select signal do not change between the two cycles. Access to the External Area( i ) Access to the Same External Area( i ) Access to the External Area No Access BCLK Read/Write signal Data bus Address bus Chip select (CS i) Data Address BCLK Read/Write signal Data bus Address bus Chip select Data Address Note : These examples show the address bus and chip select signal within the successive two cycles. According to the combination of these examples, the chip select can be elongated to over 2cycles. Figure 1.10.2. Output Examples about Address Bus and Chip Select Signal (Separated Bus without Wait) 33 Mitsubishi microcomputers Bus Control (3) Read/write signals M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select the _____ ________ ______ _____ ________ _________ combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE _____ ______ _______ pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0 (address 000416) to “0”.) Tables 1.10.3 and 1.10.4 show the operation of these signals. _____ ______ ________ After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected. _____ _________ _________ When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the processor mode register 0 (address 000416) has been set (Note). Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000A16) to “1”. _____ ________ _________ Table 1.10.3. Operation of RD, WRL, and WRH signals Data bus width 16-bit (BYTE = “L”) RD L H H H WRL H L H L WRH H H L L Status of external data bus Read data Write 1 byte of data to even address Write 1 byte of data to odd address Write data to both even and odd addresses _____ ______ ________ Table 1.10.4. Operation of RD, WR, and BHE signals Data bus width RD H L H L H L H L WR L H L H L H L H BHE L L H H L L Not used Not used A0 H H L L L L H/L H/L Status of external data bus Write 1 byte of data to odd address Read 1 byte of data from odd address Write 1 byte of data to even address Read 1 byte of data from even address Write data to both even and odd addresses Read data from both even and odd addresses Write 1 byte of data Read 1 byte of data 16-bit (BYTE = “L”) 8-bit (BYTE = “H”) (4) ALE signal The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the ALE signal falls. When BYTE pin = “H” ALE D0/A0 to D7/A7 A8 to A19 Address Data (Note 1) When BYTE pin = “L” ALE A0 D0/A1 to D7/A8 Address (Note 2) A9 to A19 Address Address Address Data (Note 1) Note 1: Floating when reading. Note 2: When multiplexed bus for the entire space is selected, these are I/O ports. Figure 1.10.3. ALE signal and address/data bus 34 Mitsubishi microcomputers Bus Control ________ M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (5) The RDY signal ________ RDY is a signal that facilitates access to an external device that requires long access time. As shown in ________ Figure 1.10.4, if an “L” is being input to the RDY at the BCLK falling edge, the bus turns to the wait state. ________ If an “H” is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table 1.10.5 shows the state of the microcomputer with the bus in the wait state, and Figure 1.10.4 shows an ____ ________ example in which the RD signal is prolonged by the RDY signal. ________ The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the ________ chip select control register (address 000816) are set to “0”. The RDY signal is invalid when setting “1” to ________ all bits 4 to 7 of the chip select control register (address 000816), but the RDY pin should be treated as properly as in non-using. Table 1.10.5. Microcomputer status in wait state (Note) Item Oscillation ___ _____ Status On ________ R/W signal, address bus, data bus, CS __________ ALE signal, HLDA, programmable I/O ports Internal peripheral circuits ________ Maintain status when RDY signal received On Note: The RDY signal cannot be received immediately prior to a software wait. In an instance of separate bus BCLK RD CSi (i=0 to 3) RDY tsu(RDY - BCLK) Accept timing of RDY signal In an instance of multiplexed bus BCLK RD CSi (i=0 to 3) RDY tsu(RDY - BCLK) : Wait using RDY signal : Wait using software _____ Accept timing of RDY signal ________ Figure 1.10.4. Example of RD signal extended by RDY signal 35 Mitsubishi microcomputers Bus Control (6) Hold signal M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to __________ the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status __________ __________ is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table 1.10.6 shows the microcomputer status in the hold state. __________ Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence. __________ HOLD > DMAC > CPU Figure 1.10.5. Bus-using priorities Table 1.10.6. Microcomputer status in hold state Item Oscillation ___ _____ _______ Status ON Floating Floating Maintains status when hold signal is received Output “L” ON (but watchdog timer stops) Undefined R/W signal, address bus, data bus, CS, BHE Programmable I/O ports P0, P1, P2, P3, P4, P5 P6, P7, P8, P9, P10 __________ HLDA Internal peripheral circuits ALE signal (7) External bus status when the internal area is accessed Table 1.10.7 shows the external bus status when the internal area is accessed. Table 1.10.7. External bus status when the internal area is accessed Item Address bus SFR accessed Address output Internal ROM/RAM accessed Maintain status before accessed address of external area Data bus When read When write RD, WR, WRL, WRH BHE Floating Output data RD, WR, WRL, WRH output BHE output Floating Undefined Output “H” Maintain status before accessed status of external area CS ALE Output “H” Output “L” Output “H” Output “L” 36 Mitsubishi microcomputers Bus Control (8) BCLK output M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The user can choose the BCLK output by use of bit 7 of processor mode register 0 (000416) (Note). When set to “1”, the output floating. Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000A16) to “1”. (9) Software wait A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 000516) (Note) and bits 4 to 7 of the chip select control register (address 000816). A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle. When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been reset, this bit defaults to “0”. When set to “1”, a wait is applied to all memory areas (two or three BCLK cycles), regardless of the contents of bits 4 to 7 of the chip select control register. Set this bit after referring to the recommended operating conditions (main clock input oscillation frequency) of the electric character________ istics. However, when the user is using the RDY signal, the relevant bit in the chip select control register’s bits 4 to 7 must be set to “0”. When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register _______ _______ correspond to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed in one BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits default to “0” after the microcomputer has been reset. The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also, insert a software wait if using the multiplex bus to access the external memory area. Table 1.10.8 shows the software wait and bus cycles. Figure 1.10.6 shows example of bus timing when using software waits. Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000A16) to “1”. Table 1.10.8. Software waits and bus cycles Area SFR Internal ROM/RAM Separate bus Separate bus External memory area Separate bus Multiplex bus Multiplex bus Bus status Wait bit Invalid 0 1 0 0 1 0 1 Bits 4 to 7 of chip select control register Invalid Invalid Invalid 1 0 0 (Note) 0 0 (Note) Bus cycle 2 BCLK cycles 1 BCLK cycle 2 BCLK cycles 1 BCLK cycle 2 BCLK cycles 2 BCLK cycles 3 BCLK cycles 3 BCLK cycles Note: When using the RDY signal, always set to “0”. 37 Mitsubishi microcomputers Bus Control M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER < Separate bus (no wait) > Bus cycle (Note 1) Bus cycle (Note 1) BCLK Write signal Read signal Output Input Data bus Address bus (Note 2) Chip select (Note 2) Address Address < Separate bus (with wait) > Bus cycle (Note 1) Bus cycle (Note 1) BCLK Write signal Read signal Output Input Data bus Address bus (Note 2) Chip select (Note 2) Address Address < Multiplexed bus > Bus cycle (Note 1) Bus cycle (Note 1) BCLK Write signal Read signal ALE Address bus (Note 2) Address bus/ Data bus Chip select (Note 2) Address Address Data output Address Address Input Note 1: These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in succession. Note 2: The address bus and chip select may be extended depending on the CPU status such as that of the instruction queue buffer. Figure 1.10.6. Typical bus timings using software wait 38 Mitsubishi microcomputers Clock Generating Circuit M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Generating Circuit The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units. Table 1.11.1. Main clock and sub-clock generating circuits Use of clock Main clock generating circuit Sub-clock generating circuit • CPU’s operating clock source • CPU’s operating clock source • Internal peripheral units’ • Timer A/B’s count clock operating clock source source Ceramic or crystal oscillator Crystal oscillator XIN, XOUT XCIN, XCOUT Available Available Oscillating Stopped Externally derived clock can be input Usable oscillator Pins to connect oscillator Oscillation stop/restart function Oscillator status immediately after reset Other Example of oscillator circuit Figure 1.11.1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Figure 1.11.2 shows some examples of sub-clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Circuit constants in Figures 1.11.1 and 1.11.2 vary with each oscillator used. Use the values recommended by the manufacturer of your oscillator. Microcomputer (Built-in feedback resistor) Microcomputer (Built-in feedback resistor) XIN XOUT (Note) Rd XIN XOUT Open Externally derived clock CIN COUT Vcc Vss Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN and XOUT following the instruction. Figure 1.11.1. Examples of main clock Microcomputer (Built-in feedback resistor) Microcomputer (Built-in feedback resistor) XCIN XCOUT (Note) RCd XCIN XCOUT Open Externally derived clock CCIN CCOUT Vcc Vss Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN and XCOUT following the instruction. Figure 1.11.2. Examples of sub-clock 39 Mitsubishi microcomputers Clock Generating Circuit Clock Control M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.11.3 shows the block diagram of the clock generating circuit. XCIN CM04 XCOUT 1/32 fC32 f1 f1SIO2 fC fAD f8 f32 f8SIO2 f32SIO2 Sub clock CM10 “1” Write signal SQ XIN R RESET Software reset NMI Interrupt request level judgment output WAIT instruction Main clock CM02 CM05 XOUT b a c d Divider CM07=0 BCLK fC CM07=1 SQ R b a 1/2 1/2 1/2 1/2 1/2 c CM06=0 CM17,CM16=11 CM06=1 CM06=0 CM17,CM16=10 d CM06=0 CM17,CM16=01 CM06=0 CM17,CM16=00 CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 WDCi : Bit i at address 000F16 Details of divider Figure 1.11.3. Clock generating circuit 40 Mitsubishi microcomputers Clock Generating Circuit M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The following paragraphs describes the clocks generated by the clock generating circuit. (1) Main clock The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode, shifting to low power dissipation mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/medium-speed mode is retained. (2) Sub-clock The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset. After oscillation is started using the port XC select bit (bit 4 at address 000616), the sub-clock can be selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the sub-clock oscillation has fully stabilized before switching. After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit changes to “1” when the port XC select bit (bit 4 at address 000616) is set to “0” , shifting to stop mode and at a reset. When the XCIN/XCOUT is used, set ports P86 and P87 as the input ports without pull-up. (3) BCLK The BCLK is the clock that drives the CPU, and is fC or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal can be output from BCLK pin by the BCLK output disable bit (bit 7 at address 000416) in the memory expansion and the microprocessor modes. The main clock division select bit 0 (bit 6 at address 000616) changes to “1” when shifting from highspeed/medium-speed to stop mode, shifting to low power dissipation mode and at reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/medium-speed mode is retained. (4) Peripheral function clock(f1, f8, f32, f1SIO2, f8SIO2,f32SIO2,fAD) The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction. (5) fC32 This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts. (6) fC This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer. 41 Mitsubishi microcomputers Clock Generating Circuit Figure 1.11.4 shows the system clock control registers 0 and 1. M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER System clock control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol CM0 Bit symbol CM00 CM01 CM02 CM03 CM04 CM05 CM06 CM07 Address 000616 Bit name Clock output function select bit (Valid only in single-chip mode) WAIT peripheral function clock stop bit When reset 4816 Function b1 b0 RW 0 0 : I/O port P57 0 1 : fC output 1 0 : f8 output 1 1 : f32 output 0 : Do not stop peripheral function clock in wait mode 1 : Stop peripheral function clock in wait mode (Note 8) XCIN-XCOUT drive capacity 0 : LOW select bit (Note 2) 1 : HIGH Port XC select bit (Note 10) Main clock (XIN-XOUT) stop bit (Note 3, 4, 5) Main clock division select bit 0 (Note 7) System clock select bit (Note 6) 0 : I/O port 1 : XCIN-XCOUT generation (Note 9) 0 : On 1 : Off 0 : CM16 and CM17 valid 1 : Division by 8 mode 0 : XIN, XOUT 1 : XCIN, XCOUT Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register. Note 2: Changes to “1” when the port XC select bit (CM04) is set to “0”, shiffing to stop mode and at a reset. Note 3: When entering low power dissipation mode, main clock stops by using this bit. To stop the main clock, when the sub clock oscillation is stable, set system clock select bit (CM07) to “1” before setting this bit to “1”. The main clock division select bit 0 (CM06) and the XIN-XOUT drive capacity select bit (CM15) change to “1” when this bit is set to “1”. Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. Note 5: If this bit is set to “1”, XOUT turns “H”. The built-in feedback resistor remains being connected, so XIN turns pulled up to XOUT (“H”) via the feedback resistor. Note 6: Set port XC select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting this bit from “0” to “1”. Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the main clock oscillating before setting this bit from “1” to “0”. Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode, shifting to low power dissipation mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/ medium-speed mode is retained. Note 8: fC32 is not included. Do not set to “1” when using low-speed or low power dissipation mode. Note 9: When the XCIN/XCOUT is used, set ports P86 and P87 as the input ports without pull-up. Note10: The XCIN-XCOUT drive capacity select bit changes to “1” when this bit is set to “0”. System clock control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 00 0 0 Symbol CM1 Bit symbol CM10 Address 000716 Bit name All clock stop control bit (Note4) When reset 2016 Function 0 : Clock on 1 : All clocks off (stop mode) Must always be set to “0” Must always be set to “0” Must always be set to “0” Must always be set to “0” 0 : LOW 1 : HIGH b7 b6 RW Reserved bit Reserved bit Reserved bit Reserved bit CM15 CM16 CM17 XIN-XOUT drive capacity select bit (Note 2) Main clock division select bit 1 (Note 3) 0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register. Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode, shifting to low power dissipation mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/ medium-speed mode is retained. Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”. If “1”, division mode is fixed at 8. Note 4: If this bit is set to “1”, XOUT turns “H”, and the built-in feedback resistor is cut off. XCIN and XCOUT turn high-impedance state. Figure 1.11.4. Clock control registers 0 and 1 42 Mitsubishi microcomputers Clock Generating Circuit M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Output In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32, or fc to be output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address 000616) is set to “1”, the output of f8 and f32 stops when a WAIT instruction is executed. Stop Mode Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V. Because the oscillation , BCLK, f1 to f32, f1SIO2 to f32SIO2, fC, fC32, and fAD stops in stop mode, peripheral functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2), SI/O3,4 functions provided an external clock is selected. Table 1.11.2 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel must have been changed to 0. If returning by an interrupt, that interrupt routine is executed. If only a _______ hardware reset or an NMI interrupt is used to cancel stop mode, change the priority level of all interrupt to 0, then shift to stop mode. The main clock division select bit 0 (bit 6 at address 000616) changes to “1” when shifting from high-speed/ medium-speed mode to stop mode, shifting to low power dissipation mode and at reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/medium-speed mode is retained. Table 1.11.2. Port status during stop mode Pin _______ _______ Memory expansion mode Microprocessor mode Single-chip mode Address bus, data bus, CS0 to CS3, ________ Retains status before stop mode BHE _____ ______ ________ _________ RD, WR, WRL, WRH __________ “H” “H” “H” Retains status before stop mode Retains status before stop mode Valid only in single-chip mode “H” Valid only in single-chip mode Retains status before stop mode HLDA, BCLK ALE Port CLKOUT When fc selected When f8, f32 selected 43 Mitsubishi microcomputers Wait Mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Wait Mode When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. However, peripheral function clock fC32 does not stop so that the peripherals using fC32 do not contribute to the power saving. When the MCU running in low-speed or low power dissipation mode, do not enter WAIT mode with this bit set to “1”. Table 1.11.3 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, that interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel must have been changed to 0. If returning by an interrupt, the clock in which the WAIT instruction executed is set to BCLK by the microcomputer, and the action is resumed from the interrupt routine. If only a hardware _______ reset or an NMI interrupt is used to cancel wait mode, change the priority level of all interrupt to 0,then shift to wait mode. Table 1.11.3. Port status during wait mode Pin _______ _______ Memory expansion mode Microprocessor mode Retains status before wait mode Single-chip mode Address bus, data bus, CS0 to CS3, ________ BHE _____ ______ ________ _________ RD, WR, WRL, WRH __________ “H” HLDA,BCLK ALE Port CLKOUT “H” “H” Retains status before wait mode When fC selected Valid only in single-chip mode When f8, f32 selected Valid only in single-chip mode Retains status before wait mode Does not stop Does not stop when the WAIT peripheral function clock stop bit is “0”. When the WAIT peripheral function clock stop bit is “1”, the status immediately prior to entering wait mode is maintained. 44 Mitsubishi microcomputers Status Transition of BCLK M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Status Transition of BCLK Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 1.11.4 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. When reset, the device starts in division by 8 mode. The main clock division select bit 0 (bit 6 at address 000616) and the XIN-XOUT drive capacity select bit (bit 5 at address 000716) change to “1” when shifting from high-speed/medium-speed mode to stop mode, shifting to low power dissipation mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/ medium-speed mode is retained. The following shows the operational modes of BCLK. (1) Division by 2 mode The main clock is divided by 2 to obtain the BCLK. (2) Division by 4 mode The main clock is divided by 4 to obtain the BCLK. (3) Division by 8 mode The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption mode, make sure the sub-clock is oscillating stably. (4) Division by 16 mode The main clock is divided by 16 to obtain the BCLK. (5) No-division mode The main clock is divided by 1 to obtain the BCLK. (6) Low-speed mode fC is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the subclock starts. Therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (7) Low power dissipation mode fC is the BCLK and the main clock is stopped. Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Allow a wait time in software for the oscillation to stabilize before switching over the clock. Table 1.11.4. Operating modes dictated by settings of system clock control registers 0 and 1 CM17 CM16 CM07 CM06 CM05 CM04 Operating mode of BCLK 0 1 0 1 0 0 Invalid Invalid 0 1 1 0 0 0 0 Invalid Invalid 1 Invalid Invalid 1 CM1i : bit i of the address 000716 CM0i : bit i of the address 000616 0 0 1 0 0 Invalid Invalid 0 0 0 0 0 0 1 Invalid Invalid Invalid Invalid Invalid 1 1 Division by 2 mode Division by 4 mode Division by 8 mode Division by 16 mode No-division mode Low-speed mode Low power dissipation mode 45 Mitsubishi microcomputers Power control M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Power control The following is a description of the three available power control modes: Modes Power control is available in three modes. (a) Normal operation mode • High-speed mode Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK. Each peripheral function operates according to its assigned clock. • Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK. Each peripheral function operates according to its assigned clock. • Low-speed mode fC becomes the BCLK. The CPU operates according to the fC clock. The fC clock is supplied by the subclock. Each peripheral function operates according to its assigned clock. • Low power dissipation mode The main clock operating in low-speed mode is stopped. The CPU operates according to the fC clock. The fC clock is supplied by the subclock. The only peripheral functions that operate are those with the subclock selected as the count source. (b) Wait mode The CPU operation is stopped. The oscillators do not stop. (c) Stop mode All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three modes listed here, is the most effective in decreasing power consumption. Figure 1.11.5 is the state transition diagram of the above modes. 46 Mitsubishi microcomputers Power control M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Transition of stop mode, wait mode Reset All oscillators stopped CM10 = “1” Interrupt WAIT instruction Interrupt CPU operation stopped Stop mode Medium-speed mode (divided-by-8 mode) Wait mode Interrupt All oscillators stopped Stop mode CM10 = “1” High-speed/mediumspeed mode Low power dissipation mode Low-speed mode WAIT instruction Interrupt CPU operation stopped Wait mode All oscillators stopped Stop mode CM10 = “1” Interrupt Low-speed/low power dissipation mode WAIT instruction Interrupt CPU operation stopped Wait mode Normal mode (Refer to the following for the transition of normal mode.) Transition of normal mode Main clock is oscillating Sub clock is stopped Medium-speed mode (divided-by-8 mode) CM06 = “1” BCLK : f(XIN)/8 CM07 = “0” CM06 = “1” CM04 = “1” (Notes 1, 3) CM07 = “0” (Note 1) CM06 = “1” CM04 = “0” Main clock is oscillating CM04 = “0” Sub clock is oscillating High-speed mode BCLK : f(XIN) CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “0” Medium-speed mode (divided-by-2 mode) BCLK : f(XIN)/2 CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “1” Medium-speed mode (divided-by-8 mode) BCLK : f(XIN)/8 CM07 = “0” CM06 = “1” Main clock is oscillating Sub clock is oscillating Low-speed mode CM07 = “0” (Note 1, 3) BCLK : f(XCIN) CM07 = “1” CM07 = “1” (Note 2) Medium-speed mode (divided-by-4 mode) BCLK : f(XIN)/4 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “0” Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/16 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “1” CM05 = “0” CM04 = “0” CM05 = “1” Main clock is oscillating Sub clock is stopped CM04 = “1” High-speed mode BCLK : f(XIN) CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “0” CM06 = “0” (Notes 1,3) Medium-speed mode (divided-by-2 mode) BCLK : f(XIN)/2 CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “1” Main clock is stopped Sub clock is oscillating Low power dissipation mode CM07 = “1” (Note 2) CM05 = “1” BCLK : f(XCIN) CM07 = “1” CM06 = “1” CM15 = “1” CM07 = “0” (Note 1) CM06 = “0” (Note 3) CM04 = “1” Medium-speed mode (divided-by-4 mode) BCLK : f(XIN)/4 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “0” Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/16 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “1” CM03 = “1” Note 1: Switch clock after oscillation of main clock is sufficiently stable. Note 2: Switch clock after oscillation of sub clock is sufficiently stable. Note 3: Change CM06 after changing CM17 and CM16. Note 4: Transit in accordance with arrow. Figure 1.11.5. State transition diagram of Power control mode 47 Mitsubishi microcomputers M16C / 62N Group Protection SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.11.6 shows the protect register. The values in the processor mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716), port P9 direction register (address 03F316) , SI/O3 control register (address 036216) and SI/O4 control register (address 036616) can only be changed when the respective bit in the protect register is set to “1”. Therefore, important outputs can be allocated to port P9. If, after “1” (write-enabled) has been written to the port P9 direction register and SI/Oi control register (i=3,4) write-enable bit (bit 2 at address 000A16), a value is written to any address, the bit automatically reverts to “0” (write-inhibited). However, the system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written to an address. The program must therefore be written to return these bits to “0”. Protect register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PRCR Bit symbol PRC0 Address 000A16 Bit name When reset XXXXX0002 Function RW Enables writing to system clock control registers 0 and 1 (addresses 0 : Write-inhibited 1 : Write-enabled 000616 and 000716) Enables writing to processor mode 0 : Write-inhibited registers 0 and 1 (addresses 000416 1 : Write-enabled and 000516) Enables writing to port P9 direction register (address 03F316) and SI/Oi control register (i=3,4) (addresses 036216 and 036616) (Note) 0 : Write-inhibited 1 : Write-enabled PRC1 PRC2 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note: Writing a value to an address after “1” is written to this bit returns the bit to “0” . Other bits do not automatically return to “0” and they must therefore be reset by the program. Figure 1.11.6. Protect register 48 Mitsubishi microcomputers Interrupt M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Overview of Interrupt Type of Interrupts Figure 1.12.1 lists the types of interrupts. Software Interrupt Special Hardware Peripheral I/O (Note) Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system. Figure 1.12.1. Classification of interrupts • Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level. • Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level.                  Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Reset NMI ________ DBC Watchdog timer Single step Address matched _______          49 Mitsubishi microcomputers Interrupt M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. • Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction. • Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to “1”. The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB • BRK interrupt A BRK interrupt occurs when executing the BRK instruction. • INT interrupt An INT interrupt occurs when specifying one of software interrupt numbers 0 through 63 and executing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/ O interrupt does. The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is involved. So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift. 50 Mitsubishi microcomputers Interrupt M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts. • Reset ____________ Reset occurs if an “L” is input to the RESET pin. _______ • NMI interrupt _______ _______ An NMI interrupt occurs if an “L” is input to the NMI pin. ________ • DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. • Watchdog timer interrupt Generated by the watchdog timer. Write to the watchdog timer start register after the watchdog timer interrupt occurs (initialize watchdog timer). • Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed. • Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to “1”. If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. (2) Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral functions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts. • Bus collision detection interrupt This is an interrupt that the serial I/O bus collision detection generates. • DMA0 interrupt, DMA1 interrupt These are interrupts that DMA generates. • Key-input interrupt ___ A key-input interrupt occurs if an “L” is input to the KI pin. • A-D conversion interrupt This is an interrupt that the A-D converter generates. • UART0, UART1, UART2/NACK, SI/O3 and SI/O4 transmission interrupt These are interrupts that the serial I/O transmission generates. • UART0, UART1, UART2/ACK, SI/O3 and SI/O4 reception interrupt These are interrupts that the serial I/O reception generates. • Timer A0 interrupt through timer A4 interrupt These are interrupts that timer A generates • Timer B0 interrupt through timer B5 interrupt These are interrupts that timer B generates. ________ ________ • INT0 interrupt through INT5 interrupt ______ ______ An INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to the INT pin. 51 Mitsubishi microcomputers Interrupt M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts and Interrupt Vector Tables If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure 1.12.2 shows the format for specifying the address. Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. MSB LSB Low address Mid address 0000 0000 High address 0000 Vector address + 0 Vector address + 1 Vector address + 2 Vector address + 3 Figure 1.12.2. Format for specifying interrupt vector addresses • Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 1.12.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. Table 1.12.1. Interrupts assigned to the fixed vector tables and addresses of vector tables Interrupt source Undefined instruction Overflow BRK instruction Vector table addresses Address (L) to address (H) FFFDC16 to FFFDF16 FFFE016 to FFFE316 FFFE416 to FFFE716 Remarks Interrupt on UND instruction Interrupt on INTO instruction If the vector contains FF16, program execution starts from the address shown by the vector in the variable vector table There is an address-matching interrupt enable bit Do not use Address match FFFE816 to FFFEB16 Single step (Note) FFFEC16 to FFFEF16 Watchdog timer FFFF016 to FFFF316 ________ DBC (Note) FFFF416 to FFFF716 Do not use _______ _______ NMI FFFF816 to FFFFB16 External interrupt by input to NMI pin Reset FFFFC16 to FFFFF16 Note: Interrupts used for debugging purposes only. 52 Mitsubishi microcomputers Interrupt M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER • Variable vector tables The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 1.12.2 shows the interrupts assigned to the variable vector tables and addresses of vector tables. Table 1.12.2. Interrupts assigned to the variable vector tables and addresses of vector tables Software interrupt number Software interrupt number 0 Vector table address Address (L) to address (H) Interrupt source BRK instruction Remarks Cannot be masked I flag +0 to +3 (Note 1) Software interrupt number 4 Software interrupt number 5 Software interrupt number 6 Software interrupt number 7 Software interrupt number 8 Software interrupt number 9 Software interrupt number 10 Software interrupt number 11 Software interrupt number 12 Software interrupt number 13 Software interrupt number 14 Software interrupt number 15 Software interrupt number 16 Software interrupt number 17 Software interrupt number 18 Software interrupt number 19 Software interrupt number 20 Software interrupt number 21 Software interrupt number 22 Software interrupt number 23 Software interrupt number 24 Software interrupt number 25 Software interrupt number 26 Software interrupt number 27 Software interrupt number 28 Software interrupt number 29 Software interrupt number 30 Software interrupt number 31 Software interrupt number 32 to Software interrupt number 63 +16 to +19 (Note 1) +20 to +23 (Note 1) +24 to +27 (Note 1) +28 to +31 (Note 1) +32 to +35 (Note 1) +36 to +39 (Note 1) +40 to +43 (Note 1) +44 to +47 (Note 1) +48 to +51 (Note 1) +52 to +55 (Note 1) +56 to +59 (Note 1) +60 to +63 (Note 1) +64 to +67 (Note 1) +68 to +71 (Note 1) +72 to +75 (Note 1) +76 to +79 (Note 1) +80 to +83 (Note 1) +84 to +87 (Note 1) +88 to +91 (Note 1) +92 to +95 (Note 1) +96 to +99 (Note 1) +100 to +103 (Note 1) +104 to +107 (Note 1) +108 to +111 (Note 1) +112 to +115 (Note 1) +116 to +119 (Note 1) +120 to +123 (Note 1) +124 to +127 (Note 1) +128 to +131 (Note 1) to +252 to +255 (Note 1) INT3 Timer B5 Timer B4 Timer B3 SI/O4/INT5 SI/O3/INT4 (Note 2) (Note 2) Bus collision detection DMA0 DMA1 Key input interrupt A-D UART2 transmit/NACK (Note 3) UART2 receive/ACK (Note 3) UART0 transmit UART0 receive UART1 transmit UART1 receive Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 INT0 INT1 INT2 Software interrupt Cannot be masked I flag Note 1: Address relative to address in interrupt table register (INTB). Note 2: It is selected by interrupt request cause bit (bit 6, 7 in address 035F16 ). Note 3: When IIC mode is selected, NACK and ACK interrupts are selected. 53 Mitsubishi microcomputers Interrupt M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Figure 1.12.3 shows the memory map of the interrupt control registers. 54 Mitsubishi microcomputers Interrupt M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt control register (Note 2) Symbol TBiIC(i=3 to 5) BCNIC DMiIC(i=0, 1) KUPIC ADIC SiTIC(i=0 to 2) SiRIC(i=0 to 2) TAiIC(i=0 to 4) TBiIC(i=0 to 2) Address 004516 to 004716 004A16 004B16, 004C16 004D16 004E16 005116, 005316, 004F16 005216, 005416, 005016 005516 to 005916 005A16 to 005C16 When reset XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 b7 b6 b5 b4 b3 b2 b1 b0 Bit symbol ILVL0 Bit name Interrupt priority level select bit b2 b1 b0 Function 000: 001: 010: 011: 100: 101: 110: 111: Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 R W ILVL1 ILVL2 IR Interrupt request bit 0 : Interrupt not requested 1 : Interrupt requested (Note 1) Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. For details, see the precautions for interrupts. b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol Address INTiIC(i=3) 004416 SiIC/INTjIC (i=4, 3) 004816, 004916 (j=5, 4) 004816, 004916 INTiIC(i=0 to 2) 005D16 to 005F16 When reset XX00X0002 XX00X0002 XX00X0002 XX00X0002 Bit symbol ILVL0 Bit name Interrupt priority level select bit b2 b1 b0 Function 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Must always be set to “0” R W ILVL1 ILVL2 IR Interrupt request bit (Note 1) POL Polarity select bit Reserved bit Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. For details, see the precautions for interrupts. Figure 1.12.3. Interrupt control registers 55 Mitsubishi microcomputers Interrupt M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Enable Flag (I flag) The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set to “0” after reset. Interrupt Request Bit The interrupt request bit is set to “1” by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to “0” by hardware. The interrupt request bit can also be set to “0” by software. (Do not set this bit to “1”). Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to “0” disables the interrupt. Table 1.12.3 shows the settings of interrupt priority levels and Table 1.12.4 shows the interrupt levels enabled, according to the contents of the IPL. The following are conditions under which an interrupt is accepted: · interrupt enable flag (I flag) = “1” · interrupt request bit = “1” · interrupt priority level > IPL The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another. Table 1.12.3. Settings of interrupt priority levels Interrupt priority level select bit b2 b1 b0 Table 1.12.4. Interrupt levels enabled according to the contents of the IPL IPL IPL2 IPL1 IPL0 Interrupt priority level Priority order Enabled interrupt priority levels 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High Low 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled 56 Mitsubishi microcomputers Interrupt M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rewrite the interrupt control register To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: Example 1: INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. When changing an interrupt control register in a sate of interrupts being disabled, please read the following precautions on instructions used before changing the register. (1) Changing a non-interrupt request bit If an interrupt request for an interrupt control register is generated during an instruction to rewrite the register is being executed, there is a case that the interrupt request bit is not set and consequently the interrupt is ignored. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET (2) Changing the interrupt request bit When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit is not cleared sometimes. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : MOV 57 Mitsubishi microcomputers Interrupt M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given: (1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 0000016. After this, the corresponding interrupt request bit becomes “0”. (2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to “0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed) (4) Saves the content of the temporary register (Note) within the CPU in the stack area. (5) Saves the content of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL. After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user. Interrupt Response Time 'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure 1.12.4 shows the interrupt response time. Interrupt request generated Interrupt request acknowledged Time Instruction (a) Interrupt sequence (b) Instruction in interrupt routine Interrupt response time (a) Time from interrupt request is generated to when the instruction then under execution is completed. (b) Time in which the instruction sequence is executed. Figure 1.12.4. Interrupt response time 58 Mitsubishi microcomputers Interrupt M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time (b) is as shown in Table 1.12.5. Table 1.12.5. Time required for executing the interrupt sequence Interrupt vector address Even Even Odd (Note 2) Odd (Note 2) Stack pointer (SP) value Even Odd Even Odd ________ 16-Bit bus, without wait 18 cycles (Note 1) 19 cycles (Note 1) 19 cycles (Note 1) 20 cycles (Note 1) 8-Bit bus, without wait 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match interrupt or of a single-step interrupt. Note 2: Locate an interrupt vector address in an even address, if possible. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 BCLK Address bus Data bus R W The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. Address 0000 Interrupt information Indeterminate Indeterminate Indeterminate SP-2 SP-2 contents SP-4 SP-4 contents vec vec contents vec+2 vec+2 contents PC Figure 1.12.5. Time required for executing the interrupt sequence Variation of IPL when Interrupt Request is Accepted If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table 1.12.6 is set in the IPL. Table 1.12.6. Relationship between interrupts without interrupt priority levels and IPL Interrupt sources without priority levels _______ Value set in the IPL 7 0 Not changed Watchdog timer, NMI Reset Other 59 Mitsubishi microcomputers Interrupt M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Saving Registers In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. Figure 1.12.6 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM instruction alone can save all the registers except the stack pointer (SP). Address MSB Stack area LSB Address MSB Stack area LSB [SP] New stack pointer value m–4 m–3 m–2 m–1 m m+1 Content of previous stack Content of previous stack [SP] Stack pointer value before interrupt occurs m–4 m–3 m–2 m–1 m m+1 Program counter (PCL) Program counter (PCM) Flag register (FLGL) Flag register (FLGH) Program counter (PCH) Content of previous stack Content of previous stack Stack status before interrupt request is acknowledged Stack status after interrupt request is acknowledged Figure 1.12.6. State of stack before and after acceptance of interrupt request 60 Mitsubishi microcomputers Interrupt M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer (Note) , at the time of acceptance of an interrupt request, is even or odd. If the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Figure 1.12.7 shows the operation of the saving registers. Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the stack pointer indicated by the U flag. Otherwise, it is the interrupt stack pointer (ISP). (1) Stack pointer (SP) contains even number Address Stack area Sequence in which order registers are saved [SP] – 5 (Odd) [SP] – 4 (Even) [SP] – 3(Odd) [SP] – 2 (Even) [SP] – 1(Odd) [SP] (Even) Finished saving registers in two operations. Program counter (PCL) Program counter (PCM) Flag register (FLGL) Flag register (FLGH) Program counter (PCH) (1) Saved simultaneously, all 16 bits (2) Saved simultaneously, all 16 bits (2) Stack pointer (SP) contains odd number Address Stack area Sequence in which order registers are saved [SP] – 5 (Even) [SP] – 4(Odd) [SP] – 3 (Even) [SP] – 2(Odd) [SP] – 1 (Even) [SP] (Odd) Finished saving registers in four operations. Program counter (PCL) Program counter (PCM) Flag register (FLGL) Flag register (FLGH) Program counter (PCH) (3) (4) (1) (2) Saved simultaneously, all 8 bits Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. Figure 1.12.7. Operation of saving registers 61 Mitsubishi microcomputers Interrupt M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Returning from an Interrupt Routine Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter (PC), both of which have been saved in the stack area. Then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. Return the other registers saved by software within the interrupt routine using the POPM or similar instruction before executing the REIT instruction. Interrupt Priority If there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. Figure 1.12.8 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine. _______ ________ Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match Figure 1.12.8. Hardware interrupts priorities Interrupt resolution circuit When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. Figure 1.12.9 shows the circuit that judges the interrupt priority level. 62 Mitsubishi microcomputers Interrupt M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Priority level of each interrupt INT1 Timer B2 Timer B0 Timer A3 Timer A1 Timer B4 INT3 INT2 INT0 Timer B1 Timer A4 Timer A2 Timer B3 Timer B5 UART1 reception UART0 reception UART2 reception/ACK A-D conversion DMA1 Bus collision detection Serial I/O4/INT5 Timer A0 UART1 transmission UART0 transmission UART2 transmission/NACK Key input interrupt DMA0 Serial I/O3/INT4 Processor interrupt priority level (IPL) Level 0 (initial value) High Priority of peripheral I/O interrupts (if priority levels are same) Low Interrupt request level judgment output to clock generating circuit (Fig.1.11.3) Interrupt enable flag (I flag) Address match Watchdog timer DBC NMI Reset Interrupt request accepted Figure 1.12.9. Maskable interrupts priorities (peripheral I/O interrupts) 63 Mitsubishi microcomputers ______ INT Interrupt ______ M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER INT Interrupt ________ ________ INT0 to INT5 are triggered by the edges of external inputs. The edge polarity is selected using the polarity select bit. ________ Of interrupt control registers, 004816 is used both as serial I/O4 and external interrupt INT5 input control ________ register, and 004916 is used both as serial I/O3 and as external interrupt INT4 input control register. Use the interrupt request cause select bits - bits 6 and 7 of the interrupt request cause select register (035F16) - to specify which interrupt request cause to select. After having set an interrupt request cause, be sure to clear the corresponding interrupt request bit before enabling an interrupt. Either of the interrupt control registers - 004816, 004916 - has the polarity-switching bit. Be sure to set this bit to “0” to select an serial I/O as the interrupt request cause. As for external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge by setting “1” in the INTi interrupt polarity switching bit of the interrupt request cause select register (035F16). To select both edges, set the polarity switching bit of the corresponding interrupt control register to ‘falling edge’ (“0”). Figure 1.12.10 shows the Interrupt request cause select register. Interrupt request cause select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol IFSR Bit symbol Address 035F16 When reset 0016 Bit name INT0 interrupt polarity switching bit INT1 interrupt polarity switching bit INT2 interrupt polarity switching bit INT3 interrupt polarity switching bit INT4 interrupt polarity switching bit INT5 interrupt polarity switching bit Interrupt request cause select bit Interrupt request cause select bit Function 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : SIO3 1 : INT4 0 : SIO4 1 : INT5 RW IFSR0 IFSR1 IFSR2 IFSR3 IFSR4 IFSR5 IFSR6 IFSR7 Figure 1.12.10. Interrupt request cause select register 64 Mitsubishi microcomputers ________ NMI Interrupt ______ M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER NMI Interrupt ______ ______ ______ An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI interrupt is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address 03F016). This pin cannot be used as a normal port input. Key Input Interrupt If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to P107 as A-D input ports. Figure 1.12.11 shows the block diagram of the key input interrupt. Note that if an “L” level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt. Port P104-P107 pull-up select bit Pull-up transistor Key input interrupt control register Port P107 direction register Port P107 direction register (address 004D16) P107/KI3 Pull-up transistor P106/KI2 Pull-up transistor P105/KI1 Pull-up transistor P104/KI0 Port P104 direction register Port P105 direction register Port P106 direction register Interrupt control circuit Key input interrupt request Figure 1.12.11. Block diagram of key input interrupt 65 Mitsubishi microcomputers Address Match Interrupt M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Address Match Interrupt An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). For an address match interrupt, the value of the program counter (PC) that is saved to the stack area varies depending on the instruction being executed. Note that when using the external data bus in width of 8 bits, the address match interrupt cannot be used for external area. Figure 1.12.12 shows the address match interrupt-related registers. Address match interrupt enable register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Bit symbol Address 000916 Bit name Address match interrupt 0 enable bit Address match interrupt 1 enable bit When reset XXXXXX002 Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled RW AIER0 AIER1 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminated. Address match interrupt register i (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol RMAD0 RMAD1 Address 001216 to 001016 001616 to 001416 When reset X0000016 X0000016 Function Address setting register for address match interrupt Values that can be set R W 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminated. Figure 1.12.12. Address match interrupt-related registers 66 Mitsubishi microcomputers Precautions for Interrupts M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Precautions for Interrupts (1) Reading address 0000016 • When maskable interrupt is occurred, CPU reads the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”. Even if the address 0000016 is read out by software, “0” is set to the enabled highest priority interrupt source request bit. Therefore interrupt can be canceled and unexpected interrupt can occur. Do not read address 0000016 by software. (2) Setting the stack pointer • The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in _______ the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack pointer at the beginning of a program. Concerning the first instruction immediately after reset, generat_______ ing any interrupts including the NMI interrupt is prohibited. _______ (3) The NMI interrupt _______ _______ •The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc via a pull-up resistor if unused. Be sure to work on it. _______ • The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time _______ when the NMI interrupt is input. _______ • Do not attempt to go into stop mode with the input to the NMI pin being in the “L” state. With the input to _______ the NMI being in the “L” state, the CM10 is fixed to “0”, so attempting to go into stop mode is turned down. _______ • Do not attempt to go into wait mode with the input to the NMI pin being in the “L” state. With the input to _______ the NMI pin being in the “L” state, the CPU stops but the oscillation does not stop, so no power is saved. In this instance, the CPU is returned to the normal state by a later interrupt. _______ • Signals input to the NMI pin require “L” level and “H” level of 2 clock +300ns or more, from the operation clock of the CPU. (4) External interrupt ________ • Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0 ________ through INT5 regardless of the CPU operation clock. ________ ________ • When the polarity of the INT0 to INT5 pins is changed or the interrupt request cause of the software interrupt numbers 8 to 9 is changed, the interrupt request bit is sometimes set to “1”. After these changes were made, set the interrupt request bit to “0”. Figure 1.12.13 shows the procedure for chang______ ing the INT interrupt generate factor. (5) Watchdog timer interrupt • Write to the watchdog timer start register after the watchdog timer interrupt occurs (initialize watchdog timer). 67 Mitsubishi microcomputers Precautions for Interrupts M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clear the interrupt enable flag to “0” (Disable interrupt) Set the interrupt priority level to level 0 (Disable INTi interrupt) Set the polarity select bit NOP X 2 Clear the interrupt request bit to “0” Set the interrupt priority level to level 1 to 7 (Enable the accepting of INTi interrupt request) Set the interrupt enable flag to “1” (Enable interrupt) Note: Execute the setting above individually. Don't execute two or more settings at once(by one instruction). ______ Figure 1.12.13. Switching condition of INT interrupt request (6) Rewrite the interrupt control register • To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: Example 1: INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. When changing an interrupt control register in a sate of interrupts being disabled, please read the following precautions on instructions used before changing the register. (1) Changing a non-interrupt request bit If an interrupt request for an interrupt control register is generated during an instruction to rewrite the register is being executed, there is a case that the interrupt request bit is not set and consequently the interrupt is ignored. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET (2) Changing the interrupt request bit When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit is not cleared sometimes. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : MOV 68 Mitsubishi microcomputers Watchdog Timer M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Watchdog Timer The watchdog timer has the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. Whether a watchdog timer interrupt is generated or reset is selected when an underflow occurs in the watchdog timer. When the watchdog timer interrupt is selected, write to the watchdog timer start register after the watchdog timer interrupt occurs (initialize watchdog timer). Watchdog timer interrupt is selected when bit 2 (PM12) of the processor mode register 1 (address 000516) is "0" and reset is selected when PM12 is "1". No value other than "1" can be written in PM12. Once when reset is selected (PM12="1"), watchdog timer interrupt cannot be selected by software. When XIN is selected for the BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). Thus the watchdog timer's period can be calculated as given below. The watchdog timer's period is, however, subject to an error due to the prescaler. With XIN chosen for BCLK prescaler dividing ratio (16 or 128) X watchdog timer count (32768) Watchdog timer period = BCLK With XCIN chosen for BCLK Watchdog timer period = prescaler dividing ratio (2) X watchdog timer count (32768) BCLK For example, suppose that BCLK runs at 16 MHz and that 16 has been chosen for the dividing ratio of the prescaler, then the watchdog timer's period becomes approximately 32.8 ms. The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E16). In stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes or state are released. Also PM12 is initialized only when reset. The watchdog timer interrupt is selected after reset is cancelled. Figure 1.13.1 shows the block diagram of the watchdog timer. Figure 1.13.2 shows the watchdog timerrelated registers. 69 Mitsubishi microcomputers Watchdog Timer M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Prescaler “CM07 = 0” “WDC7 = 0” “PM12 = 0” 1/16 BCLK HOLD 1/128 “CM07 = 0” “WDC7 = 1” Watchdog timer interrupt request Watchdog timer Reset “PM12 = 1” “CM07 = 1” 1/2 Write to the watchdog timer start register (address 000E16) Set to “7FFF16” RESET Figure 1.13.1. Block diagram of watchdog timer Watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol WDC Bit symbol Address 000F16 Bit name When reset 000XXXXX2 Function RW High-order bit of watchdog timer Reserved bit Reserved bit WDC7 Must always be set to “0” Must always be set to “0” Prescaler select bit 0 : Divided by 16 1 : Divided by 128 Watchdog timer start register b7 b0 Symbol WDTS Address 000E16 When reset Indeterminate RW Function The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to “7FFF16” regardless of whatever value is written. Figure 1.13.2. Watchdog timer control and start registers 70 Mitsubishi microcomputers M16C / 62N Group DMAC DMAC This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 1.14.1 shows the block diagram of the DMAC. Table 1.14.1 shows the DMAC specifications. Figures 1.14.2 to 1.14.4 show the registers used by the DMAC. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Address bus DMA0 source pointer SAR0(20) (addresses 002216 to 002016) DMA0 destination pointer DAR0 (20) (addresses 002616 to 002416) DMA0 forward address pointer (20) (Note) DMA0 transfer counter reload register TCR0 (16) DMA1 source pointer SAR1 (20) (addresses 003216 to 003016) DMA1 destination pointer DAR1 (20) (addresses 003616 to 003416) (addresses 002916, 002816) DMA0 transfer counter TCR0 (16) DMA1 transfer counter reload register TCR1 (16) DMA1 forward address pointer (20) (Note) (addresses 003916, 003816) DMA1 transfer counter TCR1 (16) DMA latch high-order bits DMA latch low-order bits Data bus low-order bits Data bus high-order bits Note: Pointer is incremented by a DMA request. Figure 1.14.1. Block diagram of DMAC Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level. The DMA transfer doesn't affect any interrupts either. If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the number of transfers. For details, see the description of the DMA request bit. 71 Mitsubishi microcomputers M16C / 62N Group DMAC Table 1.14.1. DMAC specifications Item No. of channels Transfer memory space Specification 2 (cycle steal method) • From any address in the 1M bytes space to a fixed address • From a fixed address to any address in the 1M bytes space • From a fixed address to a fixed address (Note that DMA-related registers [002016 to 003F16] cannot be accessed) 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers) ________ ________ SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Maximum No. of bytes transferred DMA request factors (Note) Falling edge of INT0 or INT1 or both edge Timer A0 to timer A4 interrupt requests Timer B0 to timer B5 interrupt requests UART0 transfer and reception interrupt requests UART1 transfer and reception interrupt requests UART2 transfer and reception interrupt requests Serial I/O3, 4 interrpt requests A-D conversion interrupt requests Software triggers Channel priority DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously Transfer unit 8 bits or 16 bits Transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) Transfer mode • Single transfer mode After the transfer counter underflows, the DMA enable bit turns to “0”, and the DMAC turns inactive • Repeat transfer mode After the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. The DMAC remains active unless a “0” is written to the DMA enable bit. DMA interrupt request generation timing When an underflow occurs in the transfer counter Active When the DMA enable bit is set to “1”, the DMAC is active. When the DMAC is active, data transfer starts every time a DMA transfer request signal occurs. Inactive • When the DMA enable bit is set to “0”, the DMAC is inactive. • After the transfer counter underflows in single transfer mode Reload timing for forward ad- At the time of starting data transfer immediately after turning the DMAC active, the value of one of source pointer and destination pointer - the one specified for the dress pointer and transfer forward direction - is reloaded to the forward direction address pointer, and the value counter of the transfer counter reload register is reloaded to the transfer counter. Writing to register Registers specified for forward direction transfer are always write enabled. Registers specified for fixed address transfer are write-enabled when the DMA enable bit is “0”. Reading the register Can be read at any time. However, when the DMA enable bit is “1”, reading the register set up as the forward register is the same as reading the value of the forward address pointer. Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level. 72 Mitsubishi microcomputers M16C / 62N Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMA0 request cause select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM0SL Address 03B816 When reset 0016 Bit symbol Bit name DMA request cause select bit b3 b2 b1 b0 Function 0 0 0 0 : Falling edge of INT0 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3 0 1 1 0 : Timer A4 (DMS=0) /two edges of INT0 pin (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) Timer B3 (DMS=1) 1 0 0 0 : Timer B1 (DMS=0) Timer B4 (DMS=1) 1 0 0 1 : Timer B2 (DMS=0) Timer B5 (DMS=1) 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 transmit R W DSEL0 DSEL1 DSEL2 DSEL3 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. DMS DSR DMA request cause expansion select bit Software DMA request bit 0 : Normal 1 : Expanded cause If software trigger is selected, a DMA request is generated by setting this bit to “1” (When read, the value of this bit is always “0”) Figure 1.14.2. DMAC register (1) 73 Mitsubishi microcomputers M16C / 62N Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMA1 request cause select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM1SL Address 03BA16 When reset 0016 Bit symbol Bit name DMA request cause select bit b3 b2 b1 b0 Function 0 0 0 0 : Falling edge of INT1 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3(DMS=0) /serial I/O3 (DMS=1) 0 1 1 0 : Timer A4 (DMS=0) /serial I/O4 (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) /two edges of INT1 (DMS=1) 1 0 0 0 : Timer B1 1 0 0 1 : Timer B2 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 receive R W DSEL0 DSEL1 DSEL2 DSEL3 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. DMS DSR DMA request cause expansion select bit Software DMA request bit 0 : Normal 1 : Expanded cause If software trigger is selected, a DMA request is generated by setting this bit to “1” (When read, the value of this bit is always “0”) DMAi control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DMiCON(i=0,1) Address 002C16, 003C16 When reset 00000X002 Bit symbol DMBIT DMASL DMAS DMAE DSD DAD Bit name Transfer unit bit select bit Repeat transfer mode select bit DMA request bit (Note 1) DMA enable bit Source address direction select bit (Note 3) 0 : 16 bits 1 : 8 bits Function R W 0 : Single transfer 1 : Repeat transfer 0 : DMA not requested 1 : DMA requested 0 : Disabled 1 : Enabled 0 : Fixed 1 : Forward (Note 2) Destination address 0 : Fixed direction select bit (Note 3) 1 : Forward Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Note 1: DMA request can be cleared by resetting the bit. Note 2: This bit can only be set to “0”. Note 3: Source address direction select bit and destination address direction select bit cannot be set to “1” simultaneously. Figure 1.14.3. DMAC register (2) 74 Mitsubishi microcomputers M16C / 62N Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAi source pointer (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol SAR0 SAR1 Address 002216 to 002016 003216 to 003016 When reset Indeterminate Indeterminate Function • Source pointer Stores the source address Transfer address specification 0000016 to FFFFF16 RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. DMAi destination pointer (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol DAR0 DAR1 Address 002616 to 002416 003616 to 003416 When reset Indeterminate Indeterminate RW Function • Destination pointer Stores the destination address Transfer address specification 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. DMAi transfer counter (i = 0, 1) (b15) b7 (b8) b0 b7 b0 Symbol TCR0 TCR1 Address 002916, 002816 003916, 003816 When reset Indeterminate Indeterminate RW Function • Transfer counter Set a value one less than the transfer count Transfer count specification 000016 to FFFF16 Figure 1.14.4. DMAC register (3) 75 Mitsubishi microcomputers M16C / 62N Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Transfer cycle The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to the SFR area (destination write). The number of read and write bus cycles depends on the source and destination addresses. In memory expansion mode and microprocessor mode, the number of read and write bus cycles also depends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted. (a) Effect of source and destination addresses When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. (b) Effect of BYTE pin level When transferring 16-bit data over an 8-bit data bus (BYTE pin = “H”) in memory expansion mode and microprocessor mode, the 16 bits of data are sent in two 8-bit blocks. Therefore, two bus cycles are required for reading the data and two are required for writing the data. Also, in contrast to when the CPU accesses internal memory, when the DMAC accesses internal memory (internal ROM, internal RAM, and SFR), these areas are accessed using the data size selected by the BYTE pin. (c) Effect of software wait When the SFR area or a memory area with a software wait is accessed, the number of cycles is increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK. Figure 1.14.5 shows the example of the transfer cycles for a source read. For convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle. For example (2) in Figure 1.14.5, if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the source read cycle and the destination write cycle. 76 Mitsubishi microcomputers M16C / 62N Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) 8-bit transfers 16-bit transfers and the source address is even. BCLK Address bus RD signal WR signal Data bus CPU use Source Destination Dummy cycle CPU use CPU use Source Destination Dummy cycle CPU use (2) 16-bit transfers and the source address is odd Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination cycles). BCLK Address bus RD signal WR signal Data bus CPU use Source Source + 1 Destination Dummy cycle CPU use CPU use Source Source + 1 Destination Dummy cycle CPU use (3) One wait is inserted into the source read under the conditions in (1) BCLK Address bus RD signal WR signal Data bus CPU use Source Destination Dummy cycle CPU use CPU use Source Destination Dummy cycle CPU use (4) One wait is inserted into the source read under the conditions in (2) (When 16-bit data is transferred on an 8-bit data bus, there are two destination cycles). BCLK Address bus RD signal WR signal Data bus CPU use Source Source + 1 Destination Dummy cycle CPU use CPU use Source Source + 1 Destination Dummy cycle CPU use Note: The same timing changes occur with the respective conditions at the destination as at the source. Figure 1.14.5. Example of the transfer cycles for a source read 77 Mitsubishi microcomputers M16C / 62N Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (2) DMAC transfer cycles Any combination of even or odd transfer read and write addresses is possible. Table 1.14.2 shows the number of DMAC transfer cycles. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k Table 1.14.2. No. of DMAC transfer cycles Transfer unit Memory expansion mode Bus width Access address Microprocessor mode No. of read No. of write No. of read No. of write cycles cycles cycles cycles 16-bit Even 1 1 1 1 (BYTE= “L”) Odd 1 1 1 1 8-bit Even — — 1 1 (BYTE = “H”) Odd — — 1 1 16-bit Even 1 1 1 1 (BYTE = “L”) Odd 2 2 2 2 8-bit Even — — 2 2 (BYTE = “H”) Odd — — 2 2 Single-chip mode 8-bit transfers (DMBIT= “1”) 16-bit transfers (DMBIT= “0”) Coefficient j, k Internal memory Internal ROM/RAM Internal ROM/RAM No wait With wait 1 2 SFR area 2 External memory Separate bus Separate bus No wait With wait 1 2 Multiplex bus 3 78 Mitsubishi microcomputers M16C / 62N Group DMAC DMA enable bit Setting the DMA enable bit to “1” makes the DMAC active. The DMAC carries out the following operations at the time data transfer starts immediately after DMAC is turned active. (1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the forward direction - to the forward direction address pointer. (2) Reloads the value of the transfer counter reload register to the transfer counter. Thus overwriting “1” to the DMA enable bit with the DMAC being active carries out the operations given above, so the DMAC operates again from the initial state at the instant “1” is overwritten to the DMA enable bit. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMA request bit The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of DMA request factors for each channel. DMA request factors include the following. * Factors effected by using the interrupt request signals from the built-in peripheral functions and software DMA factors (internal factors) effected by a program. * External factors effected by utilizing the input from external interrupt signals. For the selection of DMA request factors, see the descriptions of the DMAi factor selection register. The DMA request bit turns to “1” if the DMA transfer request signal occurs regardless of the DMAC's state (regardless of whether the DMA enable bit is set to “1” or “0”). It turns to “0” immediately before data transfer starts. In addition, it can be set to “0” by use of a program, but cannot be set to “1”. There can be instances in which a change in DMA request factor selection bit causes the DMA request bit to turn to “1”. So be sure to set the DMA request bit to “0” after the DMA request factor selection bit is changed. The DMA request bit turns to “1” if a DMA transfer request signal occurs, and turns to “0” immediately before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the DMA request bit, if read by use of a program, turns out to be “0” in most cases. To examine whether the DMAC is active, read the DMA enable bit. Here follows the timing of changes in the DMA request bit. (1) Internal factors Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to “1” due to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to turn to “1” due to several factors. Turning the DMA request bit to “0” due to an internal factor is timed to be effected immediately before the transfer starts. (2) External factors _______ An external factor is a factor caused to occur by the leading edge of input from the INTi pin (i depends on which DMAC channel is used). _______ Selecting the INTi pins as external factors using the DMA request factor selection bit causes input from these pins to become the DMA transfer request signals. The timing for the DMA request bit to turn to “1” when an external factor is selected synchronizes with the signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes _______ with the trailing edge of the input signal to each INTi pin, for example). With an external factor selected, the DMA request bit is timed to turn to “0” immediately before data transfer starts similarly to the state in which an internal factor is selected. 79 Mitsubishi microcomputers M16C / 62N Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (3) The priorities of channels and DMA transfer timing If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels concurrently turn to “1”. If the channels are active at that moment, DMA0 is given a high priority to start data transfer. When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus access, then DMA1 starts data transfer and gives the bus right to the CPU. An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer request signals due to external factors concurrently occur. Figure 1.14.6 shows the DMA transfer effected by external factors. An example in which DMA transmission is carried out in minimum cycles at the time when DMA transmission request signals due to external factors concurrently occur. BCLK DMA0 DMA1 CPU INT0 DMA0 request bit INT1 DMA1 request bit Obtainment of the bus right Figure 1.14.6. An example of DMA transfer effected by external factors 80 Mitsubishi microcomputers Timer Timer M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers B (six). All these timers function independently. Figures 1.15.1 and 1.15.2 show the block diagram of timers. Clock prescaler XIN 1/8 1/4 f1 f8 f32 fC32 f1 f8 f32 XCIN Clock prescaler reset flag (bit 7 at address 038116) set to “1” 1/32 Reset fC32 • Timer mode • One-shot timer mode • PWM mode Timer A0 interrupt TA0IN Noise filter Timer A0 • Event counter mode • Timer mode • One-shot timer mode • PWM mode Timer A1 interrupt TA1IN Noise filter Timer A1 • Event counter mode • Timer mode • One-shot timer mode • PWM mode Timer A2 interrupt TA2IN Noise filter Timer A2 • Event counter mode • Timer mode • One-shot timer mode • PWM mode Timer A3 interrupt TA3IN Noise filter Timer A3 • Event counter mode • Timer mode • One-shot timer mode • PWM mode Timer A4 interrupt TA4IN Noise filter Timer A4 • Event counter mode Timer B2 overflow Note 1: The TA0IN pin (P71) is shared with RxD2 and the TB5IN pin, so be careful. Figure 1.15.1. Timer A block diagram 81 Mitsubishi microcomputers Timer M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock prescaler XIN 1/8 1/4 f1 f8 f32 fC32 Timer A f1 f8 f32 XCIN Clock prescaler reset flag (bit 7 at address 038116) set to “1” 1/32 Reset fC32 • Timer mode • Pulse width measuring mode TB0IN Noise filter Timer B0 interrupt Timer B0 • Event counter mode • Timer mode • Pulse width measuring mode TB1IN Noise filter Timer B1 interrupt Timer B1 • Event counter mode • Timer mode • Pulse width measuring mode Timer B2 interrupt TB2IN Noise filter Timer B2 • Event counter mode • Timer mode • Pulse width measuring mode Timer B3 interrupt TB3IN Noise filter Timer B3 • Event counter mode • Timer mode • Pulse width measuring mode Timer B4 interrupt TB4IN Noise filter Timer B4 • Event counter mode • Timer mode • Pulse width measuring mode Timer B5 interrupt TB5IN Noise filter Timer B5 • Event counter mode Note 1: The TB5IN pin (P71) is shared with RxD2 and the TA0IN pin, so be careful. Figure 1.15.2. Timer B block diagram 82 Mitsubishi microcomputers Timer A Timer A M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.15.3 shows the block diagram of timer A. Figures 1.15.4 to 1.15.6 show the timer A-related registers. Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. Timer A has the four operation modes listed as follows: • Timer mode: The timer counts an internal count source. • Event counter mode: The timer counts pulses from an external source or a timer over flow. • One-shot timer mode: The timer stops counting when the count reaches “000016”. • Pulse width modulation (PWM) mode: The timer outputs pulses of a given width. Data bus high-order bits Clock source selection f1 f8 f32 fC32 Polarity selection TAiIN (i = 0 to 4) • Timer • One shot • PWM • Timer (gate function) • Event counter Data bus low-order bits Clock selection Low-order 8 bits Reload register (16) High-order 8 bits Counter (16) Clock selection Up count/down count Always down count except in event counter mode TAi Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Addresses 038716 038616 038916 038816 038B16 038A16 038D16 038C16 038F16 038E16 TAj Timer A4 Timer A0 Timer A1 Timer A2 Timer A3 TAk Timer A1 Timer A2 Timer A3 Timer A4 Timer A0 Count start flag (Address 038016) TB2 overflow TAj overflow (j = i – 1. Note, however, that j = 4 when i = 0) To external trigger circuit Down count TAk overflow (k = i + 1. Note, however, that k = 0 when i = 4) Up/down flag (Address 038416) TAiOUT (i = 0 to 4) Pulse output Toggle flip-flop Figure 1.15.3. Block diagram of timer A Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TAiMR(i=0 to 4) Address When reset 039616 to 039A16 0016 Bit symbol TMOD0 Bit name Operation mode select bit b1 b0 Function 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode RW TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 Function varies with each operation mode Count source select bit (Function varies with each operation mode) Figure 1.15.4. Timer A-related registers (1) 83 Mitsubishi microcomputers Timer A M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer Ai register (Note 1) (b15) b7 (b8) b0 b7 b0 Symbol TA0 TA1 TA2 TA3 TA4 Function Address 038716,038616 038916,038816 038B16,038A16 038D16,038C16 038F16,038E16 When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Values that can be set RW • Timer mode Counts an internal count source 000016 to FFFF16 • Event counter mode 000016 to FFFF16 Counts pulses from an external source or timer overflow • One-shot timer mode Counts a one shot width • Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator • Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 000016 to FFFF16 (Note 2,4) 000016 to FFFE16 (Note 3,4) 0016 to FE16 (High-order address) (Low-order address) 0016 to FF16 (Note 3,4) Note 1: Read and write data in 16-bit units. Note 2: When the timer Ai register is set to “000016”, the counter does not operate and the timer Ai interrupt request is not generated. When the pulse is set to output, the pulse does not output from the TAiOUT pin. Note 3: When the timer Ai register is set to “000016”, the pulse width modulator does not operate and the output level of the TAiOUT pin remains “L” level, therefore the timer Ai interrupt request is not generated. This also occurs in the 8-bit pulse width modulator mode when the significant 8 high-order bits in the timer Ai register are set to “0016”. Note 4: Use MOV instruction to write to this register. Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Address 038016 When reset 0016 Bit symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Bit name Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag Function 0 : Stops counting 1 : Starts counting RW Up/down flag (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol UDF Address 038416 When reset 0016 Bit symbol TA0UD TA1UD TA2UD TA3UD TA4UD TA2P TA3P TA4P Bit name Timer A0 up/down flag Timer A1 up/down flag Timer A2 up/down flag Timer A3 up/down flag Timer A4 up/down flag Function 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause RW Timer A2 two-phase pulse 0 : two-phase pulse signal processing disabled signal processing select bit 1 : two-phase pulse signal processing enabled (Note 2) Timer A3 two-phase pulse signal processing select bit When not using the two-phase Timer A4 two-phase pulse pulse signal processing function, signal processing select bit set the select bit to “0” Note 1: Use MOV instruction to write to this register. Note 2: Set the TAiIN and TAiOUT pins correspondent port direction registers to “0”. Figure 1.15.5. Timer A-related registers (2) 84 Mitsubishi microcomputers Timer A M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER One-shot start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol ONSF Address 038216 When reset 00X000002 Bit symbol TA0OS TA1OS TA2OS TA3OS TA4OS Bit name Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag Function 1 : Timer start When read, the value is “0” RW Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. TA0TGL TA0TGH Timer A0 event/trigger select bit b7 b6 0 0 : Input on TA0IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA4 overflow is selected 1 1 : TA1 overflow is selected Note: Set the corresponding port direction register to “0”. Trigger select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRGSR Address 038316 When reset 0016 Bit symbol TA1TGL Bit name Timer A1 event/trigger select bit Function b1 b0 RW TA1TGH TA2TGL 0 0 : Input on TA1IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected b3 b2 Timer A2 event/trigger select bit TA2TGH TA3TGL TA3TGH 0 0 : Input on TA2IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected b5 b4 Timer A3 event/trigger select bit 0 0 : Input on TA3IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected b7 b6 TA4TGL TA4TGH Timer A4 event/trigger select bit 0 0 : Input on TA4IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected Note: Set the corresponding port direction register to “0”. Clock prescaler reset flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Address 038116 When reset 0XXXXXXX2 Bit symbol Bit name Function RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) Figure 1.15.6. Timer A-related registers (3) 85 Mitsubishi microcomputers Timer A (1) Timer mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In this mode, the timer counts an internally generated count source. (See Table 1.15.1.) Figure 1.15.7 shows the timer Ai mode register in timer mode. Table 1.15.1. Specifications of timer mode Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Specification f1, f8, f32, fC32 • Down count • When the timer underflows, it reloads the reload register contents before continuing counting 1/(n+1) n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) When the timer underflows Programmable I/O port or gate input Programmable I/O port or pulse output Count value can be read out by reading timer Ai register • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter • When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) • Gate function Counting can be started and stopped by the TAiIN pin’s input signal • Pulse output function Each time the timer underflows, the TAiOUT pin’s polarity is reversed Select function Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 0 00 Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0 Address When reset 039616 to 039A16 0016 Bit name Function b1 b0 RW Operation mode select bit Pulse output function select bit 0 0 : Timer mode 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin) b4 b3 MR1 Gate function select bit 0 X (Note 2): Gate function not available (TAiIN pin is a normal port pin) MR2 1 0 : Timer counts only when TAiIN pin is held “L” (Note 3) 1 1 : Timer counts only when TAiIN pin is held “H” (Note 3) 0 (Must always be “0” in timer mode) Count source select bit b7 b6 MR3 TCK0 TCK1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: The bit can be “0” or “1”. Note 3: Set the corresponding port direction register to “0”. Figure 1.15.7. Timer Ai mode register in timer mode 86 Mitsubishi microcomputers Timer A (2) Event counter mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase external signal. Table 1.15.2 lists timer specifications when counting a single-phase external signal. Figure 1.15.8 shows the timer Ai mode register in event counter mode. Table 1.15.3 lists timer specifications when counting a two-phase external signal. Figure 1.15.9 shows the timer Ai mode register in event counter mode. Table 1.15.2. Timer specifications in event counter mode (when not processing two-phase pulse signal) Item Specification Count source • External signals input to TAiIN pin (effective edge can be selected by software) • TB2 overflow, TAj overflow Count operation • Up count or down count can be selected by external signal or software • When the timer overflows or underflows, it reloads the reload register con tents before continuing counting (Note) Divide ratio 1/ (FFFF16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer overflows or underflows TAiIN pin function Programmable I/O port or count source input TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input Read from timer Count value can be read out by reading timer Ai register Write to timer • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter • When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Select function • Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it • Pulse output function Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed Note: This does not apply when the free-run function is selected. Timer Ai mode register (When not using two-phase pulse signal processing) b7 b6 b5 b4 b3 b2 b1 b0 0 01 Symbol Address TAiMR(i = 0 to 4) 039616 to 039A16 Bit symbol TMOD0 TMOD1 MR0 Pulse output function select bit Bit name Operation mode select bit b1 b0 When reset 0016 Function RW 0 1 : Event counter mode (Note 1) 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 2) (TAiOUT pin is a pulse output pin) 0 : Counts external signal's falling edge 1 : Counts external signal's rising edge 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 4) MR1 MR2 MR3 TCK0 TCK1 Count polarity select bit (Note 3) Up/down switching cause select bit 0 (Must always be “0” in event counter mode) Count operation type select bit 0 : Reload type 1 : Free-run type Invalid when not using two-phase pulse signal processing Can be “0” or “1” Note 1: In event counter mode, the count source is selected by the event / trigger select bit (addresses 038216 and 038316). Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Valid only when counting an external signal. Note 4: When an “L” signal is input to the TAiOUT pin, the downcount is activated. When “H”, the upcount is activated. Set the corresponding port direction register to “0”. Figure 1.15.8. Timer Ai mode register in event counter mode 87 Mitsubishi microcomputers Timer A M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.15.3. Timer specifications in event counter mode (when processing two-phase pulse signal with timers A2, A3, and A4) Item Count source Count operation Specification • Two-phase pulse signals input to TAiIN or TAiOUT pin • Up count or down count can be selected by two-phase pulse signal • When the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (Note 1) 1/ (FFFF16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) Timer overflows or underflows Two-phase pulse input (Set the TAiIN pin correspondent port direction register to “0”.) Two-phase pulse input (Set the TAiOUT pin correspondent port direction register to “0”.) Count value can be read out by reading timer A2, A3, or A4 register • When counting stopped When a value is written to timer A2, A3, or A4 register, it is written to both reload register and counter • When counting in progress When a value is written to timer A2, A3, or A4 register, it is written to only reload register. (Transferred to counter at next reload time.) • Normal processing operation (timer A2 and timer A3) The timer counts up rising edges or counts down falling edges on the TAiIN pin when input signal on the TAiOUT pin is “H”. Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Select function (Note 2) TAiOUT TAiIN (i=2,3) Up count Up count Up Down count count Down count Down count • Multiply-by-4 processing operation (timer A3 and timer A4) If the phase relationship is such that the TAiIN pin goes “H” when the input signal on the TAiOUT pin is “H”, the timer counts up rising and falling edges on the TAiOUT and TAiIN pins. If the phase relationship is such that the TAiIN pin goes “L” when the input signal on the TAiOUT pin is “H”, the timer counts down rising and falling edges on the TAiOUT and TAiIN pins. TAiOUT Count up all edges Count down all edges TAiIN (i=3,4) Count up all edges Count down all edges Note 1: This does not apply when the free-run function is selected. Note 2: Timer A3 alone can be selected. Timer A2 is fixed to normal processing operation, and timer A4 is fixed to multiply-by-4 processing operation. 88 Mitsubishi microcomputers Timer A M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer Ai mode register (When using two-phase pulse signal processing) b6 b5 b4 b3 b2 b1 b0 010001 Symbol Address When reset TAiMR(i = 2 to 4) 039816 to 039A16 0016 Bit name TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 Operation mode select bit b1 b0 Function 0 1 : Event counter mode RW 0 (Must always be “0” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) 1 (Must always be “1” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) Count operation type select bit Two-phase pulse processing operation select bit (Note 1)(Note 2) 0 : Reload type 1 : Free-run type 0 : Normal processing operation 1 : Multiply-by-4 processing operation Note 1: This bit is valid for timer A3 mode register. Timer A2 is fixed to normal processing operation, and timer A4 is fixed to multiply-by-4 processing operation. Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 038416) is set to “1”. Also, always be sure to set the event/trigger select bit (addresses 038216 and 038316) to “00”. Figure 1.15.9. Timer Ai mode register in event counter mode 89 Mitsubishi microcomputers Timer A (3) One-shot timer mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In this mode, the timer operates only once. (See Table 1.15.4.) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.15.10 shows the timer Ai mode register in one-shot timer mode. Table 1.15.4. Timer specifications in one-shot timer mode Item Count source Count operation Specification f1, f8, f32, fC32 • The timer counts down • When the count reaches 000016, the timer stops counting after reloading a new count • If a trigger occurs when counting, the timer reloads a new count and restarts counting 1/n n : Set value • An external trigger is input • The timer overflows • The one-shot start flag is set (= 1) • A new count is reloaded after the count has reached 000016 • The count start flag is reset (= 0) The count reaches 000016 Programmable I/O port or trigger input Programmable I/O port or pulse output When timer Ai register is read, it indicates an indeterminate value • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter • When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 0 10 Symbol Address When reset TAiMR(i = 0 to 4) 039616 to 039A16 0016 Bit symbol TMOD0 TMOD1 MR0 Pulse output function select bit Bit name Operation mode select bit b1 b0 Function 1 0 : One-shot timer mode 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin) 0 : Falling edge of TAiIN pin's input signal (Note 3) 1 : Rising edge of TAiIN pin's input signal (Note 3) RW MR1 MR2 External trigger select bit (Note 2) Trigger select bit 0 : One-shot start flag is valid 1 : Selected by event/trigger select bits MR3 TCK0 TCK1 0 (Must always be “0” in one-shot timer mode) Count source select bit b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”. Note 3: Set the corresponding port direction register to “0”. Figure 1.15.10. Timer Ai mode register in one-shot timer mode 90 Mitsubishi microcomputers Timer A (4) Pulse width modulation (PWM) mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In this mode, the timer outputs pulses of a given width in succession. (See Table 1.15.5.) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.15.11 shows the timer Ai mode register in pulse width modulation mode. Figure 1.15.12 shows the example of how a 16-bit pulse width modulator operates. Figure 1.15.13 shows the example of how an 8bit pulse width modulator operates. Table 1.15.5. Timer specifications in pulse width modulation mode Item Count source Count operation Specification f1, f8, f32, fC32 • The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) • The timer reloads a new count at a rising edge of PWM pulse and continues counting • The timer is not affected by a trigger that occurs when counting • High level width n / fi n : Set value • Cycle time (216-1) / fi fixed • High level width n (m+1) / fi n : values set to timer Ai register’s high-order address • Cycle time (28-1) (m+1) / fi m : values set to timer Ai register’s low-order address • External trigger is input • The timer overflows • The count start flag is set (= 1) • The count start flag is reset (= 0) PWM pulse goes “L” Programmable I/O port or trigger input Pulse output When timer Ai register is read, it indicates an indeterminate value • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter • When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) 16-bit PWM 8-bit PWM Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 11 1 Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0 MR1 MR2 Address When reset 039616 to 039A16 0016 Function b1 b0 Bit name Operation mode select bit 1 1 : PWM mode RW 1 (Must always be “1” in PWM mode) External trigger select bit (Note 1) Trigger select bit 0: Falling edge of TAiIN pin's input signal (Note 2) 1: Rising edge of TAiIN pin's input signal (Note 2) 0: Count start flag is valid 1: Selected by event/trigger select bits 0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator b7 b6 MR3 16/8-bit PWM mode select bit Count source select bit TCK0 TCK1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”. Note 2: Set the corresponding port direction register to “0”. Figure 1.15.11. Timer Ai mode register in pulse width modulation mode 91 Mitsubishi microcomputers Timer A M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Condition : Reload register = 000316, when external trigger (rising edge of TAiIN pin input signal) is selected 1 / fi X (2 16 – 1) Count source TAiIN pin input signal “H” “L” Trigger is not generated by this signal 1 / fi X n PWM pulse output from TAiOUT pin Timer Ai interrupt request bit “H” “L” “1” “0” fi : Frequency of count source (f1, f8, f32, fC32) Cleared to “0” when interrupt request is accepted, or cleared by software Note: n = 000016 to FFFE16. Figure 1.15.12. Example of how a 16-bit pulse width modulator operates Condition : Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 External trigger (falling edge of TAiIN pin input signal) is selected 1 / fi X (m + 1) X (2 8 – 1) Count source (Note1) TAiIN pin input signal “H” “L” 1 / fi X (m + 1) “H” Underflow signal of 8-bit prescaler (Note2) “L” 1 / fi X (m + 1) X n PWM pulse output from TAiOUT pin Timer Ai interrupt request bit “H” “L” “1” “0” fi : Frequency of count source (f1, f8, f32, fC32) Cleared to “0” when interrupt request is accepted, or cleaerd by software Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 0016 to FF16; n = 0016 to FE16. Figure 1.15.13. Example of how an 8-bit pulse width modulator operates 92 Mitsubishi microcomputers Timer B Timer B M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.15.14 shows the block diagram of timer B. Figures 1.15.15 and 1.15.16 show the timer B-related registers. Use the timer Bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode. Timer B has three operation modes listed as follows: • Timer mode: The timer counts an internal count source. • Event counter mode: The timer counts pulses from an external source or a timer overflow. • Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or pulse width. Data bus high-order bits Data bus low-order bits Low-order 8 bits High-order 8 bits Clock source selection f1 f8 f32 fC32 TBiIN (i = 0 to 5) • Timer • Pulse period/pulse width measurement Reload register (16) Clock selection • Event counter Polarity switching and edge pulse Count start flag (address 038016) Counter reset circuit Can be selected in only event counter mode TBj overflow (j = i – 1. Note, however, j = 2 when i = 0, j = 5 when i = 3) TBi Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 Timer B5 Address 039116 039016 039316 039216 039516 039416 035116 035016 035316 035216 035516 035416 TBj Timer B2 Timer B0 Timer B1 Timer B5 Timer B3 Timer B4 Counter (16) Figure 1.15.14. Block diagram of timer B Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address TBiMR(i = 0 to 5) 039B16 to 039D16 035B16 to 035D16 When reset 00XX00002 00XX00002 Bit symbol TMOD0 TMOD1 Bit name Operation mode select bit b1 b0 Function 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/pulse width measurement mode 1 1 : Must not be set. R W MR0 MR1 MR2 Function varies with each operation mode (Note 1) (Note 2) MR3 TCK0 TCK1 Count source select bit (Function varies with each operation mode) Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5. Figure 1.15.15. Timer B-related registers (1) 93 Mitsubishi microcomputers Timer B M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer Bi register (Note) (b15) b7 (b8) b0 b7 b0 Symbol TB0 TB1 TB2 TB3 TB4 TB5 Address 039116, 039016 039316, 039216 039516, 039416 035116, 035016 035316, 035216 035516, 035416 When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Values that can be set Function • Timer mode Counts the timer's period • Event counter mode Counts external pulses input or a timer overflow • Pulse period / pulse width measurement mode Measures a pulse period or width RW 000016 to FFFF16 000016 to FFFF16 Note: Read and write data in 16-bit units. Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Address 038016 When reset 0016 Bit symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Bit name Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag Function 0 : Stops counting 1 : Starts counting RW Timer B3, 4, 5 count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TBSR Address 034016 When reset 000XXXXX2 Bit symbol Nothing is assigned. Bit name Function RW In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. TB3S TB4S TB5S Timer B3 count start flag Timer B4 count start flag Timer B5 count start flag 0 : Stops counting 1 : Starts counting Clock prescaler reset flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Address 038116 When reset 0XXXXXXX2 Bit symbol Nothing is assigned. Bit name Function RW In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) Figure 1.15.16. Timer B-related registers (2) 94 Mitsubishi microcomputers Timer B (1) Timer mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In this mode, the timer counts an internally generated count source. (See Table 1.15.6.) Figure 1.15.17 shows the timer Bi mode register in timer mode. Table 1.15.6. Timer specifications in timer mode Item Count source Count operation Specification f1, f8, f32, fC32 • Counts down • When the timer underflows, it reloads the reload register contents before continuing counting 1/(n+1) n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) The timer underflows Programmable I/O port Count value is read out by reading timer Bi register • When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter • When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) Divide ratio Count start condition Count stop condition Interrupt request generation timing TBiIN pin function Read from timer Write to timer Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol TBiMR(i=0 to 5) Address 039B16 to 039D16 035B16 to 035D16 When reset 00XX00002 00XX00002 Bit symbol TMOD0 TMOD1 MR0 MR1 MR2 Bit name Operation mode select bit b1 b0 Function 0 0 : Timer mode R W Invalid in timer mode Can be “0” or “1” 0 (Must always be “0” in timer mode ; i = 0, 3) Nothing is assiigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. (Note 1) (Note 2) MR3 Invalid in timer mode. In an attempt to write to this bit, write “0”. The value, if read in timer mode, turns out to be indeterminate. Count source select bit b7 b6 TCK0 TCK1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5. Figure 1.15.17. Timer Bi mode register in timer mode 95 Mitsubishi microcomputers Timer B (2) Event counter mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.15.7.) Figure 1.15.18 shows the timer Bi mode register in event counter mode. Table 1.15.7. Timer specifications in event counter mode Item Count source Specification • External signals input to TBiIN pin • Effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software Count operation • Counts down • When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer underflows TBiIN pin function Read from timer Write to timer Count source input Count value can be read out by reading timer Bi register • When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter • When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 01 Symbol TBiMR(i=0 to 5) Address 039B16 to 039D16 035B16 to 035D16 When reset 00XX00002 00XX00002 Bit symbol TMOD0 TMOD1 MR0 Bit name Operation mode select bit b1 b0 Function 0 1 : Event counter mode b3 b2 R W Count polarity select bit (Note 1) MR1 0 0 : Counts external signal's falling edges 0 1 : Counts external signal's rising edges 1 0 : Counts external signal's falling and rising edges 1 1 : Must not be set. (Note 2) MR2 0 (Must always be “0” in event counter mode; i = 0, 3) Nothing is assigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. Invalid in event counter mode. In an attempt to write to this bit, write “0”. The value, if read in event counter mode, turns out to be indeterminate. Invalid in event counter mode. Can be “0” or “1”. Event clock select 0 : Input from TBiIN pin (Note 4) 1 : TBj overflow (j = i – 1; however, j = 2 when i = 0, j = 5 when i = 3) (Note 3) MR3 TCK0 TCK1 Note 1: Valid only when input from the TBiIN pin is selected as the event clock. If timer's overflow is selected, this bit can be “0” or “1”. Note 2: Timer B0, timer B3. Note 3: Timer B1, timer B2, timer B4, timer B5. Note 4: Set the corresponding port direction register to “0”. Figure 1.15.18. Timer Bi mode register in event counter mode 96 Mitsubishi microcomputers Timer B (3) Pulse period/pulse width measurement mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.15.8.) Figure 1.15.19 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure 1.15.20 shows the operation timing when measuring a pulse period. Figure 1.15.21 shows the operation timing when measuring a pulse width. Table 1.15.8. Timer specifications in pulse period/pulse width measurement mode Item Count source Count operation Specification f1, f8, f32, fC32 • Up count • Counter value “000016” is transferred to reload register at measurement pulse's effective edge and the timer continues counting Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing • When measurement pulse's effective edge is input (Note 1) • When an overflow occurs. (Simultaneously, the timer Bi overflow flag changes to “1”. Assume that the count start flag condition is “1” and then the timer Bi overflow flag becomes “1”. If the timer Bi mode register has a writeaccess after next count cycle of the timer from the above condition, the timer Bi overflow flag becomes “0”.) TBiIN pin function Measurement pulse input Read from timer When timer Bi register is read, it indicates the reload register’s content (measurement result) (Note 2) Write to timer Cannot be written to Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting. Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer has started counting. Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 10 Symbol TBiMR(i=0 to 5) Address 039B16 to 039D16 035B16 to 035D16 When reset 00XX00002 00XX00002 Bit symbol TMOD0 TMOD1 MR0 Bit name Operation mode select bit Measurement mode select bit b1 b0 Function 1 0 : Pulse period / pulse width measurement mode b3 b2 R W MR1 0 0 : Pulse period measurement (Interval between measurement pulse's falling edge to falling edge) 0 1 : Pulse period measurement (Interval between measurement pulse's rising edge to rising edge) 1 0 : Pulse width measurement (Interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : Must not be set. (Note 2) MR2 0 (Must always be “0” in pulse period/pulse width measurement mode; i = 0, 3) Nothing is assigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. (Note 3) MR3 TCK0 TCK1 Timer Bi overflow flag ( Note 1) Count source select bit 0 : Timer did not overflow 1 : Timer has overflowed b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: It is indeterminate when reset. Assume that the count start flag condition is “1” and then the timer Bi overflow flag becomes “1”. If the timer Bi mode register has a write access after next count cycle of the timer from the above condition, the timer Bi overflow flag becomes “0”. This flag cannot be set to “1” by software. Note 2: Timer B0, timer B3. Note 3: Timer B1, timer B2, timer B4, timer B5. Figure 1.15.19. Timer Bi mode register in pulse period/pulse width measurement mode 97 Mitsubishi microcomputers Timer B M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER When measuring measurement pulse time interval from falling edge to falling edge Count source Measurement pulse “H” “L” Transfer (indeterminate value) Transfer (measured value) Reload register transfer timing counter (Note 1) (Note 1) (Note 2) Timing at which counter reaches “000016” Count start flag “1” “0” Timer Bi interrupt request bit “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software. Timer Bi overflow flag “1” “0” Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. Figure 1.15.20. Operation timing when measuring a pulse period Count source Measurement pulse “H” “L” Transfer (indeterminate value) Transfer (measured value) Transfer (measured value) Transfer (measured value) Reload register transfer timing counter (Note 1) (Note 1) (Note 1) (Note 1) (Note 2) Timing at which counter reaches “000016” “1” “0” Count start flag Timer Bi interrupt request bit “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software. Timer Bi overflow flag “1” “0” Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. Figure 1.15.21. Operation timing when measuring a pulse width 98 Mitsubishi microcomputers Timers’ functions for three-phase motor control M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timers’ functions for three-phase motor control Use of more than one built-in timer A and timer B provides the means of outputting three-phase motor driving waveforms. Figures 1.16.1 to 1.16.3 show registers related to timers for three-phase motor control. Three-phase PWM control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol INVC0 Address 034816 When reset 0016 R W Bit symbol INV00 Bit name Description Effective interrupt output 0: A timer B2 interrupt occurs when the timer A1 reload control signal is “1”. polarity select bit 1: A timer B2 interrupt occurs when the timer A1 reload control signal is “0”. Effective only in three-phase mode 1 Effective interrupt output 0: Not specified. 1: Selected by the effective interrupt output specification bit polarity selection bit. (Note 4) Effective only in three-phase mode 1 Mode select bit (Note 2) Output control bit Positive and negative phases concurrent L output disable function enable bit Positive and negative phases concurrent L output detect flag 0: Normal mode 1: Three-phase PWM output mode 0: Output disabled 1: Output enabled 0: Feature disabled 1: Feature enabled INV01 INV02 INV03 INV04 INV05 INV06 INV07 0: Not detected yet 1: Already detected (Note 1) Modulation mode select 0: Triangular wave modulation mode 1: Sawtooth wave modulation mode bit (Note 3) Software trigger bit 1: Trigger generated The value, when read, is “0”. Note 1: No value other than “0” can be written. Note 2: Selecting three-phase PWM output mode causes P80, P81, and P72 through P75 to output U, U, V, V, W, and W, and works the timer for setting short circuit prevention time, the U, V, W phase output control circuits, and the circuit for setting timer B2 interrupt frequency. Note 3: In triangular wave modulation mode: The short circuit prevention timer starts in synchronization with the falling edge of timer Ai output. The data transfer from the three-phase buffer register to the three-phase output shift register is made only once in synchronization with the transfer trigger signal after writing to the three-phase output buffer register. In sawtooth wave modulation mode: The short circuit prevention timer starts in synchronization with the falling edge of timer A output and with the transfer trigger signal. The data transfer from the three-phase output buffer register to the three-phase output shift register is made with respect to every transfer trigger. Note 4: To write “1” to bit 1 (INV01) of the three-phase PWM control register 0, set in advance the content of the timer B2 interrupt occurrences frequency set counter. Three-phase 0 PWM control register 1 Symbol INVC1 b7 b6 b5 b4 b3 b2 b1 b0 Address 034916 When reset 0016 R W Bit symbol INV10 Bit name Timer Ai start trigger signal select bit Timer A1-1, A2-1, A4-1 control bit Short circuit timer count source select bit Description 0: Timer B2 overflow signal 1: Timer B2 overflow signal, signal for writing to timer B2 0: Three-phase mode 0 1: Three-phase mode 1 0 : Must not be set. 1 : f1/2 (Note) INV11 INV12 Noting is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”. Reserved bit Must always be set to “0” Noting is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Note : To use three-phase PWM output mode, write “1” to INV12. Figure 1.16.1. Registers related to timers for three-phase motor control 99 Mitsubishi microcomputers Timers’ functions for three-phase motor control M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Three-phase output buffer register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol IDB0 Bit Symbol Address 034A16 When reset 0016 Bit name U phase output buffer 0 U phase output buffer 0 V phase output buffer 0 V phase output buffer 0 W phase output buffer 0 W phase output buffer 0 Function Setting in U phase output buffer 0 Setting in U phase output buffer 0 Setting in V phase output buffer 0 Setting in V phase output buffer 0 R (Note) (Note) (Note) (Note) W DU0 DUB0 DV0 DVB0 DW0 DWB0 Setting in W phase output buffer 0 (Note) Setting in W phase output buffer 0 (Note) Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Note: When executing read instruction of this register, the contents of three-phase shift register is read out. Three-phase output buffer register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol IDB1 Bit Symbol Address 034B16 When reset 0016 Bit name U phase output buffer 1 U phase output buffer 1 V phase output buffer 1 V phase output buffer 1 W phase output buffer 1 W phase output buffer 1 Function Setting in U phase output buffer 1 Setting in U phase output buffer 1 Setting in V phase output buffer 1 Setting in V phase output buffer 1 R (Note) (Note) (Note) (Note) W DU1 DUB1 DV1 DVB1 DW1 DWB1 Setting in W phase output buffer 1 (Note) Setting in W phase output buffer 1 (Note) Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Note: When executing read instruction of this register, the contents of three-phase shift register is read out. Dead time timer (Note) b7 b0 Symbol DTT Address 034C16 When reset Indeterminate Function Set dead time timer Note: Use MOV instruction to write to this register. Values that can be set 1 to 255 RW Timer B2 interrupt occurrences frequency set counter (Note 1, 2, 3) b3 b0 Symbol ICTB2 Address 034D16 When reset Indeterminate Function Set occurrence frequency of timer B2 interrupt request Values that can be set 1 to 15 R W Note 1: In setting 1 to bit 1 (INV01) - the effective interrupt output specification bit - of threephase PWM control register 0, do not change the B2 interrupt occurrences frequency set counter to deal with the timer function for three-phase motor control. Note 2: Do not write at the timing of an overflow occurrence in timer B2. Note 3: Use MOV instruction to write to this register. Figure 1.16.2. Registers related to timers for three-phase motor control 100 Mitsubishi microcomputers Timers’ functions for three-phase motor control M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer Ai register (Note 1) (b15) b7 (b8) b0 b7 b0 Symbol TA1 TA2 TA4 TB2 Function Address 038916,038816 038B16,038A16 038F16,038E16 039516,039416 When reset Indeterminate Indeterminate Indeterminate Indeterminate Values that can be set RW • Timer mode Counts an internal count source • One-shot timer mode Counts a one shot width 000016 to FFFF16 000016 to FFFF16 (Note 2, 3) Note 1: Read and write data in 16-bit units. Note 2: When the timer Ai register is set to "000016", the counter does not operate and a timer Ai interrupt does not occur. Note 3: Use MOV instruction to write to this register. Timer Ai-1 register (Note) (b15) b7 (b8) b0 b7 b0 Symbol TA11 TA21 TA41 Function Address 034316,034216 034516,034416 034716,034616 When reset Indeterminate Indeterminate Indeterminate Values that can be set RW Counts an internal count source Note: Read and write data in 16-bit units. 000016 to FFFF16 Trigger select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRGSR Bit symbol TA1TGL Address 038316 Bit name Timer A1 event/trigger select bit When reset 0016 Function b1 b0 RW TA1TGH TA2TGL 0 0 : Input on TA1IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected b3 b2 Timer A2 event/trigger select bit TA2TGH TA3TGL 0 0 : Input on TA2IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected b5 b4 Timer A3 event/trigger select bit TA3TGH 0 0 : Input on TA3IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected b7 b6 TA4TGL Timer A4 event/trigger select bit TA4TGH 0 0 : Input on TA4IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected Note: Set the corresponding port direction register to “0”. Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Bit symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Address 038016 Bit name Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag When reset 0016 Function 0 : Stops counting 1 : Starts counting RW Figure 1.16.3. Registers related to timers for three-phase motor control 101 Mitsubishi microcomputers Timers’ functions for three-phase motor control M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Three-phase motor driving waveform output mode (three-phase PWM output mode) Setting “1” in the mode select bit (bit 2 at 034816) shown in Figure 1.16.1 - causes three-phase PWM output mode that uses four timers A1, A2, A4, and B2 to be selected. As shown in Figure 1.16.4, set timers A1, A2, and A4 in one-shot timer mode, set the trigger in timer B2, and set timer B2 in timer mode using the respective timer mode registers. Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 01 010 Symbol TA1MR TA2MR TA3MR Address 039716 039816 039A16 Bit name Operation mode select bit Pulse output function select bit External trigger select bit Trigger select bit When reset 0016 0016 0016 Function b1 b0 Bit symbol TMOD0 TMOD1 MR0 RW 1 0 : One-shot timer mode 0 (Must always be “0” in three-phase PWM output mode) Invalid in three-phase PWM output mode 1 : Selected by event/trigger select register MR1 MR2 MR3 TCK0 TCK1 0 (Must always be “0” in one-shot timer mode) Count source select bit b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Timer B2 mode register b7 b6 b5 b4 b3 b2 b1 b0 0 00 Symbol TB2MR Bit symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 Address 039D16 When reset 00XX00002 RW Bit name Operation mode select bit b1 b0 Function 0 0 : Timer mode Invalid in timer mode Can be “0” or “1” 0 (Must always be “0” in timer mode) Invalid in timer mode. In an attempt to write to this bit, write "0". When read in timer mode, its content is indeterminate. Count source select bit b7 b6 TCK0 TCK1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Figure 1.16.4. Timer mode registers in three-phase PWM output mode 102 Mitsubishi microcomputers Timers’ functions for three-phase motor control M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.16.5 shows the block diagram for three-phase PWM output mode. In three-phase PWM output ___ mode, the positive-phase waveforms (U phase, V phase, and W phase) and negative waveforms (U ___ ___ phase, V phase, and W phase), six waveforms in total, are output from P80, P81, P72, P73, P74, and P75 ___ as active on the “L” level. Of the timers used in this mode, timer A4 controls the U phase and U phase, ___ ___ timer A1 controls the V phase and V phase, and timer A2 controls the W phase and W phase respectively; timer B2 controls the periods of one-shot pulse output from timers A4, A1, and A2. In outputting a waveform, dead time can be set so as to cause the “L” level of the positive waveform ___ output (U phase, V phase, and W phase) not to lap over the “L” level of the negative waveform output (U ___ ___ phase, V phase, and W phase). To set short circuit time, use three 8-bit timers sharing the reload register for setting dead time. A value from 1 through 255 can be set as the count of the timer for setting dead time. The timer for setting dead time works as a one-shot timer. If a value is written to the dead time timer (034C16), the value is written to the reload register shared by the three timers for setting dead time. Any of the timers for setting dead time takes the value of the reload register into its counter, if a start trigger comes from its corresponding timer, and performs a down count in line with the clock source selected by the dead time timer count source select bit (bit 2 at 034916). The timer can receive another trigger again before the workings due to the previous trigger are completed. In this instance, the timer performs a down count from the reload register’s content after its transfer, provoked by the trigger, to the timer for setting dead time. Since the timer for setting dead time works as a one-shot timer, it starts outputting pulses if a trigger comes; it stops outputting pulses as soon as its content becomes 0016, and waits for the next trigger to come. ___ ___ The positive waveforms (U phase, V phase, and W phase) and the negative waveforms (U phase, V ___ phase, and W phase) in three-phase PWM output mode are output from respective ports by means of setting “1” in the output control bit (bit 3 at 034816). Setting “0” in this bit causes the ports to be the state of set by port direction register. This bit can be set to “0” not only by use of the applicable instruction, but _______ by entering a falling edge in the NMI terminal or by resetting. Also, if “1” is set in the positive and negative phases concurrent L output disable function enable bit (bit 4 at 034816) causes one of the pairs of U ___ ___ ___ phase and U phase, V phase and V phase, and W phase and W phase concurrently go to “L”, as a result, the port becomes the state of set by port direction register. 103 104 INV00 1 Interrupt request bit INV05 0 f1 1/2 Trigger Trigger Dead time timer setting (8) n = 1 to 255 Bit 0 at 034B16 Bit 0 at 034A16 DQ T INV06 U phase output control circuit DU0 U phase output signal 1 n = 1 to 255 INV04 INV12 (Note) Reload register RESET NMI Interrupt occurrence frequency set counter n = 1 to 15 R INV01 INV11 INV03 D Q Circuit for interrupt occurrence frequency set counter Overflow Signal to be written to B2 INV10 INV07 Timer B2 (Timer mode) U(P80) Trigger signal for timer Ai start Control signal for timer A4 reload Trigger signal for transfer DU1 D Q D Q T T Timer A4 Reload Timer A4-1 Trigger Three-phase output shift register (U phase) Timer A4 counter DUB1 U phase output signal DUB0 (One-shot timer mode) INV11 D Q D Q T T Timers’ functions for three-phase motor control TQ DQ T U(P81) To be set to “0” when timer A4 stops Trigger Trigger Dead time timer setting (8) n = 1 to 255 V phase output signal V phase output signal INV06 V phase output control circuit DQ T V(P72) Timer A1 Reload Timer A1-1 Figure 1.16.5. Block diagram for three-phase PWM output mode V(P73) DQ T For short circuit prevention Dead time timer setting (8) n = 1 to 255 W phase output signal W phase output signal DQ T DQ T Trigger Trigger INV06 Trigger Timer A1 counter (One-shot timer mode) INV11 TQ To be set to “0” when timer A1 stops W(P74) Timer A2 Reload Timer A2-1 Trigger Timer A2 counter W phase output control circuit W(P75) (One-shot timer mode) INV11 TQ To be set to “0” when timer A2 stops Diagram for switching to P80, P81, and to P72 - P75 is not shown. M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Mitsubishi microcomputers Note: To use three-phase output mode, write "1" to INV12. Mitsubishi microcomputers Timers’ functions for three-phase motor control Triangular wave modulation M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER To generate a PWM waveform of triangular wave modulation, set “0” in the modulation mode select bit (bit 6 at 034816). Also, set “1” in the timers A4-1, A1-1, A2-1 control bit (bit 1 at 034916). In this mode, each of timers A4, A1, and A2 has two timer registers, and alternately reloads the timer register’s content to the counter every time timer B2 counter’s content becomes 000016. If “0” is set to the effective interrupt output specification bit (bit 1 at 034816), the frequency of interrupt requests that occur every time the timer B2 counter’s value becomes 000016 can be set by use of the timer B2 counter (034D16) for setting the frequency of interrupt occurrences. The frequency of occurrences is given by (setting; setting ≠ 0). Setting “1” in the effective interrupt output specification bit (bit 1 at 034816) provides the means to choose which value of the timer A1 reload control signal to use, “0” or “1”, to cause timer B2’s interrupt request to occur. To make this selection, use the effective interrupt output polarity selection bit (bit 0 at 034816). An example of U phase waveform is shown in Figure 1.16.6, and the description of waveform output workings is given below. Set “1” in DU0 (bit 0 at 034A16). And set “0” in DUB0 (bit 1 at 034A16). In addition, set “0” in DU1 (bit 0 at 034B16) and set “1” in DUB1 (bit 1 at 034B16). Also, set “0” in the effective interrupt output specification bit (bit 1 at 034816) to set a value in the timer B2 interrupt occurrence frequency set counter. By this setting, a timer B2 interrupt occurs when the timer B2 counter’s content becomes 000016 as many as (setting) times. Furthermore, set “1” in the effective interrupt output specification bit (bit 1 at 034816), set “0” in the effective interrupt output polarity select bit (bit 0 at 034816) and set "1" in the interrupt occurrence frequency set counter (034D16). These settings cause a timer B2 interrupt to occur every other interval when the U phase output goes to “H”. When the timer B2 counter’s content becomes 000016, timer A4 starts outputting one-shot pulses. In this instance, the content of DU1 (bit 0 at 034B16) and that of DU0 (bit 0 at 034A16) are set in the three-phase output shift register (U phase), the content of DUB1 (bit 1 at 034B16) and that of DUB0 (bit 1 at 034A16) ___ are set in the three-phase output shift register (U phase). After triangular wave modulation mode is selected, however, no setting is made in the shift register even though the timer B2 counter’s content becomes 000016. ___ The value of DU0 and that of DUB0 are output to the U terminal (P80) and to the U terminal (P81) respectively. When the timer A4 counter counts the value written to timer A4 (038F16, 038E16) and when timer A4 finishes outputting one-shot pulses, the three-phase shift register’s content is shifted one posi___ tion, and the value of DU1 and that of DUB1 are output to the U phase output signal and to U phase output signal respectively. At this time, one-shot pulses are output from the timer for setting dead time used for ___ setting the time over which the “L” level of the U phase waveform does not lap over the “L” level of the U phase waveform, which has the opposite phase of the former. The U phase waveform output that started from the “H” level keeps its level until the timer for setting dead time finishes outputting one-shot pulses even though the three-phase output shift register’s content changes from “1” to “0” by the effect of the one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses, "0" already shifted in the three-phase shift register goes effective, and the U phase waveform changes to the "L" level. When the timer B2 counter’s content becomes 000016, the timer A4 counter starts counting the value written to timer A4-1 (034716, 034616), and starts outputting one-shot pulses. When timer A4 finishes outputting one-shot pulses, the three-phase shift register’s content is shifted one position, but if the three-phase output shift register’s content changes from “0” to “1” as a result of the shift, the output level changes from “L” to “H” without waiting for the timer for setting dead time to finish outputting one-shot pulses. A U phase waveform is generated by these workings repeatedly. With the exception that the __ __ three-phase output shift register on the U phase side is used, the workings in generating a U phase waveform, which has the opposite phase of the U phase waveform, are the same as in generating a U 105 Mitsubishi microcomputers Timers’ functions for three-phase motor control M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER phase waveform. In this way, a waveform can be picked up from the applicable terminal in a manner in __ which the "L" level of the U phase waveform doesn’t lap over that of the U phase waveform, which has the opposite phase of the U phase waveform. The width of the “L” level too can be adjusted by varying the ___ ___ values of timer B2, timer A4, and timer A4-1. In dealing with the V and W phases, and V and W phases, the latter are of opposite phase of the former, have the corresponding timers work similarly to dealing with ___ the U and U phases to generate an intended waveform. A carrier wave of triangular waveform Carrier wave Signal wave Timer B2 Trigger signal for timer Ai start (timer B2 overflow signal) Timer A4 output m Timer B2 interrupt occurs Rewriting timer A4 and timer A4-1. Possible to set the number of overflows to generate an interrupt by use of the interrupt occurrences frequency set circuit n m n m p o Control signal for timer A4 reload The three-phase shift register shifts in synchronization with the falling edge of the timer A4 output. U phase output signal U phase output signal U phase U phase Dead time Note: Set to triangular wave modulation mode and to three-phase mode 1. Figure 1.16.6. Timing chart of operation (1) 106 Mitsubishi microcomputers Timers’ functions for three-phase motor control M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Assigning certain values to DU0 (bit 0 at 034A16) and DUB0 (bit 1 at 034A16), and to DU1 (bit 0 at 034B16) and DUB1 (bit 1 at 034B16) allows the user to output the waveforms as shown in Figure 1.16.7, that is, to ___ ___ output the U phase alone, to fix U phase to “H”, to fix the U phase to “H,” or to output the U phase alone. Carrier wave Signal wave Timer B2 Rewriting timer A4 every timer B2 interrupt occurs. Timer B2 interrupt occurs. Rewriting three-phase buffer register. Trigger signal for timer Ai start (timer B2 overflow signal) Timer A4 output m n m n m p o U phase output signal U phase output signal U phase U phase Dead time Note: Set to triangular wave modulation mode and to three-phase mode 0. Figure 1.16.7. Timing chart of operation (2) 107 Mitsubishi microcomputers Timers’ functions for three-phase motor control M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Sawtooth modulation To generate a PWM waveform of sawtooth wave modulation, set “1” in the modulation mode select bit (bit 6 at 034816). Also, set “0” in the timers A4-1, A1-1, and A2-1 control bit (bit 1 at 034916). In this mode, the timer registers of timers A4, A1, and A2 comprise conventional timers A4, A1, and A2 alone, and reload the corresponding timer register’s content to the counter every time the timer B2 counter’s content becomes 000016. The effective interrupt output specification bit (bit 1 at 034816) and the effective interrupt output polarity select bit (bit 0 at 034816) go nullified. An example of U phase waveform is shown in Figure 1.16.8, and the description of waveform output workings is given below. Set “1” in DU0 (bit 0 at 034A16), and set “0” in DUB0 (bit 1 at 034A16). In addition, set “0” in DU1 (bit 0 at 034A16) and set “1” in DUB1 (bit 1 at 034A16). When the timber B2 counter’s content becomes 000016, timer B2 generates an interrupt, and timer A4 starts outputting one-shot pulses at the same time. In this instance, the contents of the three-phase buffer registers DU1 and DU0 are set in the three-phase output shift register (U phase), and the contents of ___ DUB1 and DUB0 are set in the three-phase output shift register (U phase). After this, the three-phase buffer register’s content is set in the three-phase shift register every time the timer B2 counter’s content becomes 000016. ___ The value of DU0 and that of DUB0 are output to the U terminal (P80) and to the U terminal (P81) respectively. When the timer A4 counter counts the value written to timer A4 (038F16, 038E16) and when timer A4 finishes outputting one-shot pulses, the three-phase output shift register’s content is shifted one ___ position, and the value of DU1 and that of DUB1 are output to the U phase output signal and to the U output signal respectively. At this time, one-shot pulses are output from the timer for setting dead time used for setting the time over which the “L” level of the U phase waveform doesn’t lap over the “L” level of ___ the U phase waveform, which has the opposite phase of the former. The U phase waveform output that started from the “H” level keeps its level until the timer for setting dead time finishes outputting one-shot pulses even though the three-phase output shift register’s content changes from “1” to “0 ”by the effect of the one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses, 0 already shifted in the three-phase shift register goes effective, and the U phase waveform changes to the “L” level. When the timer B2 counter’s content becomes 000016, the contents of the three-phase buffer registers DU1 and DU0 are set in the three-phase output shift register (U phase), and the contents of ___ DUB1 and DUB0 are set in the three-phase output shift register (U phase) again. A U phase waveform is generated by these workings repeatedly. With the exception that the three-phase ___ ___ output shift register on the U phase side is used, the workings in generating a U phase waveform, which has the opposite phase of the U phase waveform, are the same as in generating a U phase waveform. In this way, a waveform can be picked up from the applicable terminal in a manner in which the “L” level of ___ the U phase waveform doesn’t lap over that of the U phase waveform, which has the opposite phase of the U phase waveform. The width of the “L” level too can be adjusted by varying the values of timer B2 ___ ___ and timer A4. In dealing with the V and W phases, and V and W phases, the latter are of opposite phase ___ of the former, have the corresponding timers work similarly to dealing with the U and U phases to generate an intended waveform. ___ Setting “1” both in DUB0 and in DUB1 provides a means to output the U phase alone and to fix the U phase output to “H” as shown in Figure 1.16.9. 108 Mitsubishi microcomputers Timers’ functions for three-phase motor control M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A carrier wave of sawtooth waveform Carrier wave Signal wave Timer B2 Trigger signal for timer Ai start (timer B2 overflow signal) Interrupt occurs. Rewriting the value of timer A4. Data transfer is made from the threephase buffer register to the threephase shift register in step with the timing of the timer B overflow. Timer A4 output m n o p U phase output signal U phase output signal U phase U phase The three-phase shift register shifts in synchronization with the falling edge of timer A4. Dead time Note: Set to sawtooth modulation mode and to three-phase mode 0. Figure 1.16.8. Timing chart of operation (3) 109 Mitsubishi microcomputers Timers’ functions for three-phase motor control M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A carrier wave of sawtooth waveform Carrier wave Signal wave Timer B2 Interrupt occurs. Rewriting the value of timer A4. Interrupt occurs. Rewriting the value of timer A4. Trigger signal for timer Ai start (timer B2 overflow signal) Rewriting three-phase output buffer register Data transfer is made from the threephase buffer register to the threephase shift register in step with the timing of the timer B overflow. Timer A4 output m n o p The three-phase shift register shifts in synchronization with the falling edge of timer A4. U phase output signal U phase output signal U phase U phase Dead time Note: Set to sawtooth modulation mode and to three-phase mode 0. Figure 1.16.9. Timing chart of operation (4) 110 Mitsubishi microcomputers Serial I/O Serial I/O M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O is configured as five channels: UART0, UART1, UART2, S I/O3 and S I/O4. UART0 to 2 UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 1.17.1 shows the block diagram of UART0, UART1 and UART2. Figures 1.17.2 and 1.17.3 show the block diagram of the transmit/receive unit. UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 03A016, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART. Although a few functions are different, UART0, UART1 and UART2 have almost the same functions. UART2, in particular, is used for the SIM interface with some extra settings added in clock-asynchronous serial I/O mode (Note). It also has the bus collision detection function that generates an interrupt request if the TxD pin and the RxD pin are different in level. Table 1.17.1 shows the comparison of functions of UART0 through UART2, and Figures 1.17.4 to 1.17.9 show the registers related to UARTi. Note: SIM : Subscriber Identity Module Table 1.17.1. Comparison of functions of UART0 through UART2 Function CLK polarity selection LSB first / MSB first selection Continuous receive mode selection Transfer clock output from multiple pins selection Serial data logic switch Sleep mode selection TxD, RxD I/O polarity switch TxD, RxD port output format Parity error signal output Bus collision detection UART0 Possible Possible Possible Impossible Impossible Possible Impossible CMOS output Impossible Impossible (Note 3) (Note 1) (Note 1) (Note 1) UART1 Possible Possible Possible Possible Impossible Possible Impossible CMOS output Impossible Impossible (Note 3) (Note 1) (Note 1) (Note 1) (Note 1) UART2 Possible Possible Possible Impossible Possible Impossible Possible N-channel open-drain output Possible Possible (Note 4) (Note 4) (Note 1) (Note 2) (Note 1) Note 1: Only when clock synchronous serial I/O mode. Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode. Note 3: Only when UART mode. Note 4: Using for SIM interface. 111 Mitsubishi microcomputers Serial I/O M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (UART0) RxD0 UART reception TxD0 1/16 Clock source selection f1 f8 f32 Bit rate generator Internal (address 03A116) Clock synchronous type 1/16 Reception control circuit Receive clock Transmit/ receive unit 1 / (n0+1) External UART transmission Clock synchronous type Transmission control circuit Transmit clock Clock synchronous type 1/2 (when internal clock is selected) Clock synchronous type (when internal clock is selected) CLK0 CLK polarity reversing circuit CTS/RTS disabled CTS/RTS selected Clock synchronous type (when external clock is selected) CTS0 / RTS0 Vcc CTS/RTS disabled RTS0 CTS0 (UART1) RxD1 Clock source selection f1 f8 f32 Bit rate generator Internal (address 03A916) 1/16 TxD1 UART reception Reception control circuit Receive clock Transmit/ receive unit Clock synchronous type UART transmission 1/16 1 / (n1+1) External Clock synchronous type Clock synchronous type 1/2 (when internal clock is selected) Transmission control circuit Transmit clock CLK1 CTS1 / RTS1/ CLKS1 CLK polarity reversing circuit Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) CTS/RTS disabled CTS/RTS selected Clock output pin select switch VCC CTS/RTS disabled RTS1 CTS1 (UART2) RxD2 RxD polarity reversing circuit UART reception 1/16 Clock source selection f1 f8 f32 Bit rate generator Internal (address 037916) Clock synchronous type UART transmission 1/16 Reception control circuit Receive clock TxD polarity reversing circuit Transmit/ receive unit TxD2 1 / (n2+1) External Clock synchronous type Clock synchronous type 1/2 Transmission control circuit Transmit clock (when internal clock is selected) CLK2 CLK polarity reversing circuit Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) CTS/RTS selected CTS/RTS disabled CTS2 / RTS2 Vcc CTS/RTS disabled RTS2 CTS2 n0 : Values set to UART0 bit rate generator (U0BRG) n1 : Values set to UART1 bit rate generator (U1BRG) n2 : Values set to UART2 bit rate generator (U2BRG) Figure 1.17.1. Block diagram of UARTi (i = 0 to 2) 112 Mitsubishi microcomputers Serial I/O M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous type UART (7 bits) UART (8 bits) 1SP PAR disabled Clock synchronous type UART (7 bits) UARTi receive register RxDi SP 2SP SP PAR PAR enabled UART UART (9 bits) Clock synchronous type UART (8 bits) UART (9 bits) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UARTi receive buffer register Address 03A616 Address 03A716 Address 03AE16 Address 03AF16 MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits MSB/LSB conversion circuit D8 D7 D6 D5 D4 D3 D2 D1 D0 UARTi transmit buffer register Address 03A216 Address 03A316 Address 03AA16 Address 03AB16 UART (8 bits) UART (9 bits) UART (9 bits) Clock synchronous type 2SP SP SP 1SP PAR PAR enabled UART TxDi PAR disabled Clock synchronous type UART (7 bits) UART (7 bits) UART (8 bits) Clock synchronous type UARTi transmit register “0” SP: Stop bit PAR: Parity bit Figure 1.17.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit 113 Mitsubishi microcomputers Serial I/O M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER No reverse RxD2 RxD data reverse circuit Reverse Clock synchronous type 1SP SP 2SP SP PAR PAR disabled Clock synchronous type UART (7 bits) UART (8 bits) UART(7 bits) UART2 receive register PAR enabled UART UART (9 bits) Clock synchronous type UART (8 bits) UART (9 bits) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UART2 receive buffer register Address 037E16 Address 037F16 Logic reverse circuit + MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits Logic reverse circuit + MSB/LSB conversion circuit D8 D7 D6 D5 D4 D3 D2 D1 D0 UART2 transmit buffer register Address 037A16 Address 037B16 UART (8 bits) UART (9 bits) PAR enabled UART (9 bits) UART Clock synchronous type 2SP SP SP 1SP PAR PAR disabled Clock synchronous type “0” UART (7 bits) UART (8 bits) Clock synchronous type UART(7 bits) UART2 transmit register Error signal output disable No reverse Error signal output circuit Error signal output enable Reverse TxD data reverse circuit TxD2 SP: Stop bit PAR: Parity bit Figure 1.17.3. Block diagram of UART2 transmit/receive unit 114 Mitsubishi microcomputers Serial I/O M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit buffer register (Note) (b15) b7 (b8) b0 b7 b0 Symbol U0TB U1TB U2TB Address 03A316, 03A216 03AB16, 03AA16 037B16, 037A16 When reset Indeterminate Indeterminate Indeterminate Function RW Transmit data Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note: Use MOV instruction to write to this register. UARTi receive buffer register (b15) b7 (b8) b0 b7 b0 Symbol U0RB U1RB U2RB Address 03A716, 03A616 03AF16, 03AE16 037F16, 037E16 When reset Indeterminate Indeterminate Indeterminate Function (During UART mode) Receive data Bit symbol Bit name Function (During clock synchronous serial I/O mode) Receive data RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. ABT OER FER PER SUM Arbitration lost detecting flag (Note 2) 0 : Not detected 1 : Detected Invalid 0 : No overrun error 1 : Overrun error found 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found Overrun error flag (Note 1) 0 : No overrun error 1 : Overrun error found Framing error flag (Note 1) Invalid Parity error flag (Note 1) Error sum flag (Note 1) Invalid Invalid Note 1: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses 03A016, 03A816 and 037816) are set to “0002” or the receive enable bit is set to “0”. (Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer register (addresses 03A616, 03AE16 and 037E16) is read out. Note 2: Arbitration lost detecting flag is allocated to U2RB and noting but “0” may be written. Nothing is assigned in bit 11 of U0RB and U1RB. When write, set “0”. The value, if read, turns out to be “0”. UARTi bit rate generator (Note 1, 2) b7 b0 Symbol U0BRG U1BRG U2BRG Address 03A116 03A916 037916 Function When reset Indeterminate Indeterminate Indeterminate Values that can be set 0016 to FF16 RW Assuming that set value = n, BRGi divides the count source by n+1 Note 1: Write a value to this register while transmit/receive halts. Note 2: Use MOV instruction to write to this register. Figure 1.17.4. Serial I/O-related registers (1) 115 Mitsubishi microcomputers Serial I/O M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiMR(i=0,1) Address 03A016, 03A816 When reset 0016 Bit symbol SMD0 SMD1 SMD2 Bit name Serial I/O mode select bit Function (During clock synchronous serial I/O mode) Must be fixed to 001 b2 b1 b0 Function (During UART mode) b2 b1 b0 RW 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set. 0 1 1 : Must not be set. 1 1 1 : Must not be set. 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set. 0 1 1 : Must not be set. 1 1 1 : Must not be set. 0 : Internal clock 1 : External clock (Note) 0 : One stop bit 1 : Two stop bits Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected CKDIR Internal/external clock select bit STPS PRY Stop bit length select bit 0 : Internal clock 1 : External clock (Note) Invalid Odd/even parity select bit Invalid PRYE SLEP Parity enable bit Sleep select bit Invalid Must always be “0” Note : Set the corresponding port direction register to “0”. UART2 transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2MR Address 037816 When reset 0016 Bit symbol SMD0 SMD1 SMD2 Bit name Serial I/O mode select bit Function (During clock synchronous serial I/O mode) Must be fixed to 001 b2 b1 b0 Function (During UART mode) b2 b1 b0 RW 0 0 0 : Serial I/O invalid 0 1 0 : (Note 1) 0 1 1 : Must not be set. 1 1 1 : Must not be set. 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set. 0 1 1 : Must not be set. 1 1 1 : Must not be set. Must always be “0” 0 : One stop bit 1 : Two stop bits Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse Usually set to “0” CKDIR Internal/external clock select bit STPS PRY Stop bit length select bit 0 : Internal clock 1 : External clock (Note 2) Invalid Odd/even parity select bit Invalid PRYE IOPOL Parity enable bit TxD, RxD I/O polarity reverse bit Invalid 0 : No reverse 1 : Reverse Usually set to “0” Note 1: Bit 2 to bit 0 are set to “0102” when I2C mode is used. Note 2: Set the corresponding port direction register to “0”. Figure 1.17.5. Serial I/O-related registers (2) 116 Mitsubishi microcomputers Serial I/O M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiC0(i=0,1) Bit symbol CLK0 CLK1 CRS Address When reset 03A416, 03AC16 0816 Function (During clock synchronous serial I/O mode) b1 b0 b1 b0 Bit name BRG count source select bit Function (During UART mode) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set. Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) RW 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set. Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) CTS/RTS function select bit TXEPT 0 : Data present in transmit 0 : Data present in transmit register Transmit register empty register (during transmission) (during transmission) flag 1 : No data present in transmit 1 : No data present in transmit register (transmission completed) register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output CRD CTS/RTS disable bit 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge NCH Data output select bit CKPOL CLK polarity select bit Must always be “0” UFORM Transfer format select bit 0 : LSB first 1 : MSB first Must always be “0” Note 1: Set the corresponding port direction register to “0”. Note 2: The settings of the corresponding port register and port direction register are invalid. UART2 transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2C0 Bit symbol CLK0 CLK1 CRS CTS/RTS function select bit Address 037C16 When reset 0816 Function (During clock synchronous serial I/O mode) Function (During UART mode) b1 b0 Bit name BRG count source select bit RW b1 b0 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set. Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set. Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) TXEPT 0 : Data present in transmit 0 : Data present in transmit register Transmit register empty register (during transmission) (during transmission) flag 1 : No data present in transmit 1 : No data present in transmit register (transmission completed) register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) 0: TXDi pin is CMOS output open-drain output CRD CTS/RTS disable bit 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) 0 : TXDi pin is CMOS output open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge Nothing is assigned. CKPOL : TXDi pin is N-channel 1: to be “0”. In an attempt to write to this bit, write1“0”. The value, if read, turns out TXDi pin is N-channel CLK polarity select bit Must always be “0” UFORM Transfer format select bit 0 : LSB first 1 : MSB first (Note 3) 0 : LSB first 1 : MSB first Note 1: Set the corresponding port direction register to “0”. Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid. Figure 1.17.6. Serial I/O-related registers (3) 117 Mitsubishi microcomputers Serial I/O M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiC1(i=0,1) Address 03A516,03AD16 When reset 0216 Bit symbol TE TI Bit name Transmit enable bit Transmit buffer empty flag Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register RW RE RI Receive enable bit Receive complete flag Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. UART2 transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2C1 Address 037D16 When reset 0216 Bit symbol TE TI Bit name Transmit enable bit Transmit buffer empty flag Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled 0 : No reverse 1 : Reverse Must be fixed to “0” Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) Must always be "0" RW RE RI Receive enable bit Receive complete flag U2IRS UART2 transmit interrupt cause select bit U2RRM UART2 continuous receive mode enable bit U2LCH Data logic select bit U2ERE Error signal output enable bit 0 : No reverse 1 : Reverse 0 : Output disabled 1 : Output enabled Figure 1.17.7. Serial I/O-related registers (4) 118 Mitsubishi microcomputers Serial I/O M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART transmit/receive control register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol UCON Address 03B016 When reset X00000002 Bit symbol U0IRS Bit name UART0 transmit interrupt cause select bit UART1 transmit interrupt cause select bit Function (During clock synchronous serial I/O mode) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) Function (During UART mode) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) RW U1IRS 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) U0RRM UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Valid when bit 5 = “1” 0 : Clock output to CLK1 1 : Clock output to CLKS1 0 : Normal mode (CLK output is CLK1 only) Must always be “0” U1RRM UART1 continuous receive mode enable bit Must always be “0” CLKMD0 CLK/CLKS select bit 0 Invalid CLKMD1 CLK/CLKS select bit 1 (Note) Must always be “0” 1 : Transfer clock output from multiple pins function selected Reserved bit Must always be set to “0” Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. Note: When using multiple pins to output the transfer clock, the following requirements must be met: • UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”. UART2 special mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR Address 037716 When reset 8016 Bit symbol IICM ABC BBS LSYN ABSCS Bit name I2C mode select bit Arbitration lost detecting flag control bit Bus busy flag SCLL sync output enable bit Bus collision detect sampling clock select bit Auto clear function select bit of transmit enable bit Transmit start condition select bit SDA digital delay select bit (Note 2) Function (During clock synchronous serial I/O mode) 0 : Normal mode 1 : I2C mode 0 : Update per bit 1 : Update per byte 0 : STOP condition detected 1 : START condition detected Function (During UART mode) Must always be “0” Must always be “0” Must always be “0” RW (Note1) 0 : Disabled 1 : Enabled Must always be “0” Must always be “0” 0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 0 : No auto clear function 1 : Auto clear at occurrence of bus collision 0 : Ordinary 1 : Falling edge of RXD2 ACSE Must always be “0” SSS Must always be “0” SDDS 0 : Must always be “0” Must always be “0” when not using I2C mode 1 : Digital delay output is selected Note 1: Nothing but “0” may be written. Note 2: When not in I2C mode, do not set this bit by writing a “1”. During normal mode, fix it to “0”. When this bit = “0”, UART2 special mode register 3 (U2SMR3 at address 037516) bits 7 to 5 (DL2 to DL0 = SDA digital delay setup bits) are initialized to “000”. Also, when SDDS = “0”, the U2SMR3 register cannot be read or written to. Figure 1.17.8. Serial I/O-related registers (5) 119 Mitsubishi microcomputers Serial I/O M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART2 special mode register 2 (I 2 C bus exclusive use register) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR2 Address 037616 When reset 0016 Bit symbol IICM2 CSC SWC ALS STAC SWC2 SDHI SHTC Bit name I 2C mode select bit 2 Clock-synchronous bit SCL wait output bit SDA output stop bit UART2 initialization bit SCL wait output bit 2 SDA output disable bit Start/stop condition control bit Function (I2C bus exclusive use) Refer to Table 1.17.11 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0: UART2 clock 1: 0 output 0: Enabled 1: Disabled (high impedance) Set this bit to “1” in I2C mode (refer to Table 1.17.12) RW UART2 special mode register 3 (I 2 C bus exclusive use register) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR3 Bit symbol Address 037516 When reset 0016 Function (I 2 C bus exclusive use register) Bit name RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. However, when SDDS = “1”, the value “0” is read out (Note 1) DL0 SDA digital delay setup bit (Note 1, Note 2, Note 3) b7 b6 b5 DL1 DL2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : Must not be set when using I2C mode 1 : 1 to 2 cycle(s) of 1/f(XIN) 0 : 2 to 3 cycles of 1/f(XIN) 1 : 3 to 4 cycles of 1/f(XIN) Digital delay 0 : 4 to 5 cycles of 1/f(XIN) is selected 1 : 5 to 6 cycles of 1/f(XIN) 0 : 6 to 7 cycles of 1/f(XIN) 1 : 7 to 8 cycles of 1/f(XIN) Note 1: This bit can be read or written to when UART2 special mode register (U2SMR at address 037716) bit 7 (SDDS: SDA digital delay select bit) = “1”. When the initial value of UART2 special mode register 3 (U2SMR3) is read after setting SDDS = “1”, the value is “0016”. When writing to UART2 special mode register 3 (U2SMR3) after setting SDDS = “1”, be sure to write 0's to bits 0–4. When SDDS = “0”, this register cannot be written to; when read, the value is indeterminate. Note 2: These bits are initialized to “000” when SDDS = “0”. After a reset, these bits are set to “000”. However, because these bits can be read only when SDDS = “1”, the value read from these bits when SDDS = “0” is indeterminate. Note 3: The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the amount of delay increases by about 200 ns, so be sure to take this into account when using the device. Figure 1.17.9. Serial I/O-related registers (6) 120 Mitsubishi microcomputers Clock synchronous serial I/O mode (1) Clock synchronous serial I/O mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.17.2 and 1.17.3 list the specifications of the clock synchronous serial I/O mode. Figure 1.17.10 shows the UARTi transmit/receive mode register. Table 1.17.2. Specifications of clock synchronous serial I/O mode (1) Specification • Transfer data length: 8 bits • When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”) : fi/ 2(n+1) (Note 1) fi = f1, f8, f32 • When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “1”) : Input from CLKi pin _______ _______ _______ _______ Transmission/reception control • CTS function, RTS function, CTS and RTS function invalid: selectable Transmission start condition • To start transmission, the following requirements must be met: _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1” _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0” _______ _______ _ When CTS function selected, CTS input level = “L” • Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”: CLKi input level = “H” _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”: CLKi input level = “L” Reception start condition • To start reception, the following requirements must be met: _ Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1” _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1” _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0” • Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”: CLKi input level = “H” _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”: CLKi input level = “L” • When transmitting Interrupt request _ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at generation timing address 037D16) = “0”: Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed _ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at address 037D16) = “1”: Interrupts requested when data transmission from UARTi transfer register is completed • When receiving _ Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Error detection • Overrun error (Note 2) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit does not change. Item Transfer data format Transfer clock 121 Mitsubishi microcomputers Clock synchronous serial I/O mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.17.3. Specifications of clock synchronous serial I/O mode (2) Item Select function Specification • CLK polarity selection Whether transmit data is output/input timing at the rising edge or falling edge of the transfer clock can be selected • LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected • Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register • Transfer clock output from multiple pins selection (UART1) UART1 transfer clock can be chosen by software to be output from one of the two pins set • Switching serial data logic (UART2) Whether to reverse data in writing to the transmission buffer register or reading the reception buffer register can be selected. • TxD, RxD I/O polarity reverse (UART2) This function is reversing TxD port output and RxD port input. All I/O data level is reversed. 122 Mitsubishi microcomputers Clock synchronous serial I/O mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive mode registers b7 b6 b5 b4 b3 b2 b1 b0 0 001 Symbol UiMR(i=0,1) Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE SLEP Address 03A016, 03A816 Bit name When reset 0016 Function b2 b1 b0 RW Serial I/O mode select bit 0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock 1 : External clock (Note) Internal/external clock select bit Invalid in clock synchronous serial I/O mode 0 (Must always be “0” in clock synchronous serial I/O mode) Note : Set the corresponding port direction register to “0”. UART2 transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 0 001 Symbol U2MR Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE IOPOL Address 037816 Bit name When reset 0016 Function b2 b1 b0 RW Serial I/O mode select bit 0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock 1 : External clock (Note 2) Internal/external clock select bit Invalid in clock synchronous serial I/O mode TxD, RxD I/O polarity reverse bit (Note 1) 0 : No reverse 1 : Reverse Note 1: Usually set to “0”. Note 2: Set the corresponding port direction register to “0”. Figure 1.17.10. UARTi transmit/receive mode register in clock synchronous serial I/O mode 123 Mitsubishi microcomputers Clock synchronous serial I/O mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.17.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table shows the pin functions when the transfer clock output from multiple pins function is not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain is selected, this pin is in floating state.) Table 1.17.4. Input/output pin functions in clock synchronous serial I/O mode (when transfer clock output from multiple pins is not selected) Pin name Function Method of selection (Outputs dummy data when performing reception only) Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16, bit 1 at address 03EF16)= “0” (Can be used as an input port when performing transmission only) Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “0” Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “1” Port P61, P65 and P72 direction register (bits 1 and 5 at address 03EE16, bit 2 at address 03EF16) = “0” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) =“0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “0” Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16, bit 3 at address 03EF16) = “0” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “1” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “1” TxDi Serial data output (P63, P67, P70) Serial data input RxDi (P62, P66, P71) CLKi Transfer clock output (P61, P65, P72) Transfer clock input CTSi/RTSi CTS input (P60, P64, P73) RTS output Programmable I/O port 124 Mitsubishi microcomputers Clock synchronous serial I/O mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER • Example of transmit timing (when internal clock is selected) Tc Transfer clock “1” “0” “1” “0” Transferred from UARTi transmit buffer register to UARTi transmit register “H” Data is set in UARTi transmit buffer register Transmit enable bit (TE) Transmit buffer empty flag (Tl) CTSi “L” TCLK Stopped pulsing because CTS = “H” Stopped pulsing because transfer enable bit = “0” CLKi TxDi Transmit register empty flag (TXEPT) “1” “0” D0 D 1 D2 D3 D4 D5 D6 D7 D0 D 1 D2 D3 D4 D5 D 6 D7 D 0 D1 D2 D 3 D 4 D 5 D6 D7 Transmit interrupt “1” request bit (IR) “0” Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: • Internal clock is selected. • CTS function is selected. • CLK polarity select bit = “0”. • Transmit interrupt cause select bit = “0”. Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f1, f8, f32) n: value set to BRGi • Example of receive timing (when external clock is selected) Receive enable bit (RE) Transmit enable bit (TE) Transmit buffer empty flag (Tl) RTSi “1” “0” “1” “0” “1” “0” “H” “L” Dummy data is set in UARTi transmit buffer register Transferred from UARTi transmit buffer register to UARTi transmit register 1 / fEXT Receive data is taken in CLKi RxDi Receive complete “1” flag (Rl) “0” Receive interrupt request bit (IR) “1” “0” D 0 D1 D 2 D3 D 4 D5 D6 D 7 Transferred from UARTi receive register to UARTi receive buffer register D0 D 1 D 2 D3 D4 D5 Read out from UARTi receive buffer register Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: • External clock is selected. • RTS function is selected. • CLK polarity select bit = “0”. fEXT: frequency of external clock Meet the following conditions are met when the CLK input before data reception = “H” • Transmit enable bit “1” • Receive enable bit “1” • Dummy data write to UARTi transmit buffer register Figure 1.17.11. Typical transmit/receive timings in clock synchronous serial I/O mode 125 Mitsubishi microcomputers Clock synchronous serial I/O mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (a) Polarity select function As shown in Figure 1.17.12, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) allows selection of the polarity of the transfer clock. • When CLK polarity select bit = “0” CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Note 1: The CLKi pin level when not transferring data is “H”. • When CLK polarity select bit = “1” CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Note 2: The CLKi pin level when not transferring data is “L”. Figure 1.17.12. Polarity of transfer clock (b) LSB first/MSB first select function As shown in Figure 1.17.13, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16, 037C16) = “0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”. • When transfer format select bit = “0” CLKi TXDi R XD i D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 LSB first D7 • When transfer format select bit = “1” CLKi TXDi R XD i D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 MSB first D0 Note: This applies when the CLK polarity select bit = “0”. Figure 1.17.13. Transfer format 126 Mitsubishi microcomputers Clock synchronous serial I/O mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (c) Transfer clock output from multiple pins function (UART1) This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.17.14.) The multiple pins function is valid only when the internal clock is selected for UART1. Microcomputer TXD1 (P67) CLKS1 (P64) CLK1 (P65) IN CLK IN CLK Note: This applies when the internal clock is selected and transmission is performed only in clock synchronous serial I/O mode. Figure 1.17.14. The transfer clock output from the multiple pins function usage (d) Continuous receive mode If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) is set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. (e) Serial data logic switch function (UART2) When the data logic select bit (bit6 at address 037D16) = “1”, and writing to transmit buffer register or reading from receive buffer register, data is reversed. Figure 1.17.15 shows the example of serial data logic switch timing. •When LSB first Transfer clock TxD2 “H” “L” “H” (no reverse) “L” D0 D1 D2 D3 D4 D5 D6 D7 TxD2 “H” (reverse) “L” D0 D1 D2 D3 D4 D5 D6 D7 Figure 1.17.15. Serial data logic switch timing 127 Mitsubishi microcomputers M16C / 62N Group Clock asynchronous serial I/O (UART) mode (2) Clock asynchronous serial I/O (UART) mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables 1.17.5 and 1.17.6 list the specifications of the UART mode. Figure 1.17.16 shows the UARTi transmit/receive mode register. Table 1.17.5. Specifications of UART Mode (1) Item Transfer data format Specification • Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected • Start bit: 1 bit • Parity bit: Odd, even, or nothing as selected • Stop bit: 1 bit or 2 bits as selected • When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”) : fi/16(n+1) (Note 1) fi = f1, f8, f32 • When external clock is selected (bit 3 at addresses 03A016, 03A816 =“1”) : fEXT/16(n+1) (Note 1) (Note 2) (Do not set external clock for UART2) _______ _______ _______ _______ SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Transfer clock Transmission/reception control • CTS function, RTS function, CTS and RTS function invalid: selectable Transmission start condition • To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1” - Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0” _______ _______ - When CTS function selected, CTS input level = “L” Reception start condition • To start reception, the following requirements must be met: - Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1” - Start bit detection Interrupt request • When transmitting generation timing - Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at address 037D16) = “0”: Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed - Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at address 037D16) = “1”: Interrupts requested when data transmission from UARTi transfer register is completed • When receiving - Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Error detection • Overrun error (Note 3) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out • Framing error This error occurs when the number of stop bits set is not detected • Parity error This error occurs when if parity is enabled, the number of 1’s in parity and character bits does not match the number of 1’s set • Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: fEXT is input from the CLKi pin. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit does not change. 128 Mitsubishi microcomputers M16C / 62N Group Clock asynchronous serial I/O (UART) mode Table 1.17.6. Specifications of UART Mode (2) Item Select function Specification • Sleep mode selection (UART0, UART1) This mode is used to transfer data to and from one of multiple slave microcomputers • Serial data logic switch (UART2) This function is reversing logic value of transferring data. Start bit, parity bit and stop bit are not reversed. • TXD, RXD I/O polarity switch (UART2) This function is reversing TXD port output and RXD port input. All I/O data level is reversed. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 129 Mitsubishi microcomputers M16C / 62N Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit / receive mode registers b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiMR(i=0,1) Address 03A016, 03A816 When reset 0016 Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY Bit name Serial I/O mode select bit b2 b1 b0 Function 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 : Internal clock 1 : External clock (Note) 0 : One stop bit 1 : Two stop bits Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected RW Internal / external clock select bit Stop bit length select bit Odd / even parity select bit Parity enable bit Sleep select bit PRYE SLEP Note : Set the corresponding port direction register to “0”. UART2 transmit / receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2MR Address 037816 When reset 0016 Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY Bit name Serial I/O mode select bit b2 b1 b0 Function 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long Must always be “0” 0 : One stop bit 1 : Two stop bits Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse RW Internal / external clock select bit Stop bit length select bit Odd / even parity select bit Parity enable bit TxD, RxD I/O polarity reverse bit (Note) PRYE IOPOL Note: Usually set to “0”. Figure 1.17.16. UARTi transmit/receive mode register in UART mode 130 Mitsubishi microcomputers M16C / 62N Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.17.7 lists the functions of the input/output pins during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”. (If the Nchannel open-drain is selected, this pin is in floating state.) Table 1.17.7. Input/output pin functions in UART mode Pin name Function TxDi Serial data output (P63, P67, P70) RxDi Serial data input (P62, P66, P71) CLKi Programmable I/O port (P61, P65, P72) Transfer clock input Method of selection Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16, bit 1 at address 03EF16)= “0” (Can be used as an input port when performing transmission only) Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “0” Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “1” Port P61, P65 direction register (bits 1 and 5 at address 03EE16) = “0” (Do not set external clock for UART2) CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) =“0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “0” Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16, bit 3 at address 03EF16) = “0” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “1” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “1” CTSi/RTSi CTS input (P60, P64, P73) RTS output Programmable I/O port 131 Mitsubishi microcomputers M16C / 62N Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) The transfer clock stops momentarily as CTS is “H” when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTS changes to “L”. Tc Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI) “1” “0” “1” “0” Data is set in UARTi transmit buffer register. Transferred from UARTi transmit buffer register to UARTi transmit register “H” CTSi “L” Start bit TxDi “1” Transmit register empty flag (TXEPT) “0” “1” “0” Parity bit P Stop bit SP Stopped pulsing because transmit enable bit = “0” ST D0 D1 ST D0 D1 D2 D3 D4 D5 D6 D7 ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Transmit interrupt request bit (IR) Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is enabled. • One stop bit. • CTS function is selected. • Transmit interrupt cause select bit = “1”. Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi • Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) Tc Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI) “1” “0” “1” “0” Data is set in UARTi transmit buffer register Transferred from UARTi transmit buffer register to UARTi transmit register Start bit TxDi “1” Transmit register empty flag (TXEPT) “0” “1” “0” Stop bit Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP ST D0 D1 ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP Transmit interrupt request bit (IR) Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is disabled. • Two stop bits. • CTS function is disabled. • Transmit interrupt cause select bit = “0”. Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Figure 1.17.17. Typical transmit timings in UART mode(UART0,UART1) 132 Mitsubishi microcomputers M16C / 62N Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) Tc Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI) “1” “0” “1” “0” Data is set in UART2 transmit buffer register Note Transferred from UART2 transmit buffer register to UARTi transmit register Start bit ST D0 D1 TxD2 Parity bit D 2 D 3 D4 D 5 D 6 D 7 P Stop bit SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP “1” Transmit register empty flag (TXEPT) “0” Transmit interrupt request bit (IR) “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is enabled. • One stop bit. • Transmit interrupt cause select bit = “1”. Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2 Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing. Figure 1.17.18. Typical transmit timings in UART mode(UART2) 133 Mitsubishi microcomputers M16C / 62N Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) BRGi count source Receive enable bit RxDi “1” “0” Start bit Sampled “L” Receive data taken in Transfer clock Receive complete flag RTSi Receive interrupt request bit Reception triggered when transfer clock “1” is generated by falling edge of start bit “0” “H” “L” “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software The above timing applies to the following settings : •Parity is disabled. •One stop bit. •RTS function is selected. Transferred from UARTi receive register to UARTi receive buffer register Stop bit D0 D1 D7 Figure 1.17.19. Typical receive timing in UART mode (a) Sleep mode (UART0, UART1) This mode is used to transfer data between specific microcomputers among multiple microcomputers connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”. (b) Function for switching serial data logic (UART2) When the data logic select bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. Figure 1.17.20 shows the example of timing for switching serial data logic. • When LSB first, parity enabled, one stop bit Transfer clock TxD2 (no reverse) “H” “L” “H” “L” “H” “L” ST D0 D1 D2 D3 D4 D5 D6 D7 P SP TxD2 (reverse) ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST : Start bit P : Even parity SP : Stop bit Figure 1.17.20. Timing for switching serial data logic 134 Mitsubishi microcomputers M16C / 62N Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (c) TxD, RxD I/O polarity reverse function (UART2) This function is to reverse TXD pin output and RXD pin input. The level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for usual use. (d) Bus collision detection function (UART2) This function is to sample the output level of the TXD pin and the input level of the RXD pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.17.21 shows the example of detection timing of a bus collision (in UART mode). Transfer clock “H” “L” TxD2 “H” “L” ST SP RxD2 Bus collision detection interrupt request signal Bus collision detection interrupt request bit “H” “L” “1” “0” “1” “0” ST SP ST : Start bit SP : Stop bit Figure 1.17.21. Detection timing of a bus collision (in UART mode) 135 Mitsubishi microcomputers M16C / 62N Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (3) Clock-asynchronous serial I/O mode (used for the SIM interface) The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table 1.17.8 shows the specifications of clock-asynchronous serial I/O mode (used for the SIM interface). Table 1.17.8. Specifications of clock-asynchronous serial I/O mode (used for the SIM interface) Item Transfer data format Specification • Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = “1012”) • One stop bit (bit 4 of address 037816 = “0”) • With the direct format chosen Set parity to “even” (bit 5 and bit 6 of address 037816 = “1” and “1” respectively) Set data logic to “direct” (bit 6 of address 037D16 = “0”). Set transfer format to LSB (bit 7 of address 037C16 = “0”). • With the inverse format chosen Set parity to “odd” (bit 5 and bit 6 of address 037816 = “0” and “1” respectively) Set data logic to “inverse” (bit 6 of address 037D16 = “1”) Set transfer format to MSB (bit 7 of address 037C16 = “1”) • With the internal clock chosen (bit 3 of address 037816 = “0”) : fi / 16 (n + 1) (Note 1) : fi=f1, f8, f32 (Do not set external clock) _______ _______ Transfer clock Transmission / reception control • Disable the CTS and RTS function (bit 4 of address 037C16 = “1”) Other settings • The sleep mode select function is not available for UART2 • Set transmission interrupt factor to “transmission completed” (bit 4 of address 037D16 = “1”) Transmission start condition • To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 of address 037D16) = “1” - Transmit buffer empty flag (bit 1 of address 037D16) = “0” Reception start condition • To start reception, the following requirements must be met: - Reception enable bit (bit 2 of address 037D16) = “1” - Detection of a start bit Interrupt request • When transmitting generation timing When data transmission from the UART2 transmit register is completed (bit 4 of address 037D16 = “1”) • When receiving When data transfer from the UART2 receive register to the UART2 receive buffer register is completed Error detection • Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2) • Framing error (see the specifications of clock-asynchronous serial I/O) • Parity error (see the specifications of clock-asynchronous serial I/O) - On the reception side, an “L” level is output from the TXD2 pin by use of the parity error signal output function (bit 7 of address 037D16 = “1”) when a parity error is detected - On the transmission side, a parity error is detected by the level of input to the RXD2 pin when a transmission interrupt occurs • The error sum flag (see the specifications of clock-asynchronous serial I/O) Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UART2 bit rate generator. Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also that the UART2 receive interrupt request bit does not change. 136 Mitsubishi microcomputers M16C / 62N Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Tc Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI) “1” “0” “1” “0” Data is set in UART2 transmit buffer register Note 1 Transferred from UART2 transmit buffer register to UART2 transmit register Start bit Parity bit D 1 D2 D3 D4 D5 D 6 D 7 P Stop bit SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP TxD2 RxD2 ST D0 An “L” level returns from TxD2 due to the occurrence of a parity error. Signal conductor level (Note 2) “1” Transmit register empty flag (TXEPT) “0” “1” “0” ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 The level is detected by the interrupt routine. P SP The level is detected by the interrupt routine. Transmit interrupt request bit (IR) Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is enabled. • One stop bit. • Transmit interrupt cause select bit = “1”. Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2 Note 1: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing. Tc Transfer clock Receive enable bit (RE) “1” “0” Start bit Parity bit P Stop bit SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP RxD2 TxD2 ST D0 D1 D2 D3 D4 D5 D6 D7 An “L” level returns from TxD2 due to the occurrence of a parity error. Signal conductor level (Note 2) Receive complete flag (RI) Receive interrupt request bit (IR) “1” “0” “1” “0” ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Read to receive buffer Read to receive buffer Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is enabled. • One stop bit. • Transmit interrupt cause select bit = “0”. Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2 Note 2: Equal in waveform because TxD2 and RxD2 are connected. Figure 1.17.22. Typical transmit/receive timing in UART mode (used for the SIM interface) 137 Mitsubishi microcomputers M16C / 62N Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (a) Function for outputting a parity error signal During reception, with the error signal output enable bit (bit 7 of address 037D16) assigned “1”, you can output an “L” level from the TXD2 pin when a parity error is detected. And during transmission, comparing with the case in which the error signal output enable bit (bit 7 of address 037D16) is assigned “0”, the transmission completion interrupt occurs in the half cycle later of the transfer clock. Therefore parity error signals can be detected by a transmission completion interrupt program. Figure 1.17.23 shows the output timing of the parity error signal. • LSB first Transfer clock RxD2 TxD2 Receive complete flag “H” “L” “H” “L” “H” “L” “1” “0” ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Hi-Z ST : Start bit P : Even Parity SP : Stop bit Figure 1.17.23. Output timing of the parity error signal (b) Direct format/inverse format Connecting the SIM card allows you to switch between direct format and inverse format. If you choose the direct format, D0 data is output from TxD2. If you choose the inverse format, D7 data is inverted and output from TxD2. Figure 1.17.24 shows the SIM interface format. Transfer clcck TxD2 (direct) TxD2 (inverse) D0 D1 D2 D3 D4 D5 D6 D7 P D7 D6 D5 D4 D3 D2 D1 D0 P P : Even parity Figure 1.17.24. SIM interface format 138 Mitsubishi microcomputers M16C / 62N Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.17.25 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pull-up. Microcomputer SIM card TxD2 RxD2 Figure 1.17.25. Connecting the SIM interface 139 Mitsubishi microcomputers UART2 Special Mode Register UART2 Special Mode Register M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The UART2 special mode register (address 037716) is used to control UART2 in various ways. Figure 1.17.26 shows the UART2 special mode register. Bit 0 of the UART2 special mode register (037716) is used as the I2C mode select bit. Setting “1” in the I2C mode select bit (bit 0) goes the circuit to achieve the I2C bus (simplified I2C bus) interface effective. Table 1.17.9 shows the relation between the I2C mode select bit and respective control workings. Since this function uses clock-synchronous serial I/O mode, set this bit to “0” in UART mode. UART2 special mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR Address 037716 When reset 8016 Bit symbol IICM ABC BBS LSYN ABSCS Bit name I2C mode select bit Arbitration lost detecting flag control bit Bus busy flag SCL L sync output enable bit Bus collision detect sampling clock select bit Function (During clock synchronous serial I/O mode) 0 : Normal mode 1 : I2C mode 0 : Update per bit 1 : Update per byte 0 : STOP condition detected 1 : START condition detected Function (During UART mode) Must always be “0” Must always be “0” Must always be “0” RW (Note1) 0 : Disabled 1 : Enabled Must always be “0” Must always be “0” 0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 0 : No auto clear function 1 : Auto clear at occurrence of bus collision 0 : Ordinary 1 : Falling edge of RxD2 ACSE Auto clear function select bit of transmit enable bit Transmit start condition select bit SDA digital delay select bit (Note 2) Must always be “0” SSS Must always be “0” SDDS 0 : Must always be “0” Must always be “0” when not using I2C mode 1 : Digital delay output is selected Note 1: Nothing but “0” may be written. Note 2: When not in I2C mode, do not set this bit by writing a “1”. During normal mode, fix it to “0”. When this bit = “0”, UART2 special mode register 3 (U2SMR3 at address 037516) bits 7 to 5 (DL2 to DL0 = SDA digital delay setup bits) are initialized to “000”. Also, when SDDS = “0”, the U2SMR3 register cannot be read or written to. UART2 special mode register 3 (I 2 C bus exclusive use register) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR3 Address 037516 When reset 0016 Function (I 2 C bus exclusive use register) Bit symbol Bit name RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. However, when SDDS = “1”, the value “0” is read out (Note 1) DL0 SDA digital delay setup bit (Note 1, Note 2, Note 3) b7 b6 b5 DL1 DL2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : Must not be set when using I2C mode 1 : 1 to 2 cycle(s) of 1/f(XIN) 0 : 2 to 3 cycles of 1/f(XIN) 1 : 3 to 4 cycles of 1/f(XIN) Digital delay 0 : 4 to 5 cycles of 1/f(XIN) is selected 1 : 5 to 6 cycles of 1/f(XIN) 0 : 6 to 7 cycles of 1/f(XIN) 1 : 7 to 8 cycles of 1/f(XIN) Note 1: This bit can be read or written to when UART2 special mode register (U2SMR at address 037716) bit 7 (SDDS: SDA digital delay select bit) = “1”. When the initial value of UART2 special mode register 3 (U2SMR3) is read after setting SDDS = “1”, the value is “0016”. When writing to UART2 special mode register 3 (U2SMR3) after setting SDDS = “1”, be sure to write 0's to bits 0–4. When SDDS = “0”, this register cannot be written to; when read, the value is indeterminate. Note 2: These bits are initialized to “000” when SDDS = “0”. After a reset, these bits are set to “000”. However, because these bits can be read only when SDDS = “1”, the value read from these bits when SDDS = “0” is indeterminate. Note 3: The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the amount of delay increases by about 200 ns, so be sure to take this into account when using the device. Figure 1.17.26. UART2 special mode register 140 Mitsubishi microcomputers UART2 Special Mode Register M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER P70 through P72 conforming to the simplified I 2C bus P70/TxD2/SDA Timer I/O Selector UART2 To DMA0, DMA1 UART2 SDDS=0 or DL=000 Transmission register IICM=0 or IICM2=1 IICM=1 and IICM2=0 UART2 transmission/ NACK interrupt request Digital delay (Divider) SDDS=1 and DL≠000 DQ T SDHI ALS Arbitration To DMA0 IICM=1 Reception register IICM=0 UART2 IICM=1 and IICM2=0 S Q Noize Filter Timer IICM=0 or IICM2=1 UART2 reception/ACK interrupt request, DMA1 request Start condition detection Stop condition detection Falling edge detection P71/RxD2/SCL I/O Q R R Bus busy NACK D T DQ T Q L-synchronous output enabling bit ACK Data bus Selector UART2 IICM=1 Noize Filter Noize Filter (Port P7 1 output data latch) Internal clock SWC2 9th pulse IICM=1 Bus collision/start, stop condition detection interrupt request IICM=1 CLK control detection UART2 External clock Bus collision IICM=0 IICM=0 Falling edge of 9 bit SWC UART2 Port reading * With IICM set to 1, the port terminal is to be readable P72/CLK2 IICM=0 Selector even if 1 is assigned to P7 1 of the direction register. I/O Timer Figure 1.17.27. Functional block diagram for I2C mode Table 1.17.9. Features in I2C mode Function 1 2 3 4 5 6 7 8 9 Factor of interrupt number 10 (Note 2) Factor of interrupt number 15 (Note 2) Factor of interrupt number 16 (Note 2) UART2 transmission output delay P70 at the time when UART2 is in use P71 at the time when UART2 is in use P72 at the time when UART2 is in use DMA1 factor at the time when 1 1 0 1 is assigned to the DMA request factor selection bits Noise filter width Normal mode Bus collision detection UART2 transmission UART2 reception Not delayed TxD2 (output) RxD2 (input) CLK2 UART2 reception 15ns Reading the terminal when 0 is assigned to the direction register H level (when 0 is assigned to the CLK polarity select bit) I2C mode (Note 1) Start condition detection or stop condition detection No acknowledgment detection (NACK) Acknowledgment detection (ACK) Delayed (digital delay) SDA (input/output) (Note 3) SCL (input/output) P72 Acknowledgment detection (ACK) 200ns Reading the terminal regardless of the value of the direction register The value set in latch P70 when the port is selected 10 Reading P71 11 Initial value of UART2 output Note 1: Make the settings given below when I2C mode is in use. Set 0 1 0 in bits 2, 1, 0 of the UART2 transmission/reception mode register. Disable the RTS/CTS function. Choose the MSB First function. Note 2: Follow the steps given below to switch from a factor to another. 1. Disable the interrupt of the corresponding number. 2. Switch from a factor to another. 3. Reset the interrupt request flag of the corresponding number. 4. Set an interrupt level of the corresponding number. Note 3: Set an initial value of SDA transmission output when serial I/O is invalid. 141 Mitsubishi microcomputers UART2 Special Mode Register M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.17.27 shows the functional block diagram for I2C mode. Setting “1” in the I2C mode select bit (IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock inputoutput terminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission output, so the SDA output changes after SCL fully goes to “L”. When digital delay is selected, the amount of delay can be selected in the range of 2 cycles to 8 cycles of f1 using UART2 special mode register 3 (at address 037516). Delay circuit select conditions are shown in Table 1.17.10. Table 1.17.10. Delay circuit select conditions Register value Contents IICM Digital delay is selected No delay SDDS 1 0 1 0 DL 001 to 111 (000) Digital delay is added When IICM = “0”, no delay circuit is selected. When IICM = “0”, however, always make sure SDDS = “0”. An attempt to read Port P71 (SCL) results in getting the terminal’s level regardless of the content of the port direction register. The initial value of SDA transmission output in this mode goes to the value set in port P70. The interrupt factors of the bus collision detection interrupt, UART2 transmission interrupt, and of UART2 reception interrupt turn to the start/stop condition detection interrupt, acknowledgment nondetection interrupt, and acknowledgment detection interrupt respectively. The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA terminal (P70) is detected with the SCL terminal (P71) staying “H”. The stop condition detection interrupt refers to the interrupt that occurs when the rising edge of the SDA terminal (P70) is detected with the SCL terminal (P71) staying “H”. The bus busy flag (bit 2 of the UART2 special mode register) is set to “1” by the start condition detection, and set to “0” by the stop condition detection. The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA terminal level is detected still staying “H” at the rising edge of the 9th transmission clock. The acknowledgment detection interrupt refers to the interrupt that occurs when SDA terminal’s level is detected already went to “L” at the 9th transmission clock. Also, assigning 1 1 0 1 (UART2 reception) to the DMA1 request factor select bits provides the means to start up the DMA transfer by the effect of acknowledgment detection. Bit 1 of the UART2 special mode register (037716) is used as the arbitration lost detecting flag control bit. Arbitration means the act of detecting the nonconformity between transmission data and SDA terminal data at the timing of the SCL rising edge. This detecting flag is located at bit 11 of the UART2 reception buffer register (037F16, 037E16), and “1” is set in this flag when nonconformity is detected. Use the arbitration lost detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by byte. When setting this bit to “1” and updated the flag byte by byte if nonconformity is detected, the arbitration lost detecting flag is set to “1” at the falling edge of the 9th transmission clock. If update the flag byte by byte, must judge and clear (“0”) the arbitration lost detecting flag after completing the first byte acknowledge detect and before starting the next one byte transmission. Bit 3 of the UART2 special mode register is used as SCL- and L-synchronous output enable bit. Setting this bit to “1” goes the P71 data register to “0” in synchronization with the SCL terminal level going to “L”. 142 Mitsubishi microcomputers UART2 Special Mode Register M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Some other functions added are explained here. Figure 1.17.28 shows their workings. Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit. The bus collision detect interrupt occurs when the RXD2 level and TXD2 level do not match, but the nonconformity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to “0”. If this bit is set to “1”, the nonconformity is detected at the timing of the overflow of timer A0 rather than at the rising edge of the transfer clock. Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enable bit. Setting this bit to “1” automatically resets the transmit enable bit to “0” when “1” is set in the bus collision detect interrupt request bit (nonconformity). Bit 6 of the UART2 special mode register is used as the transmit start condition select bit. Setting this bit to “1” starts the TxD transmission in synchronization with the falling edge of the RxD terminal. 1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register) 0: Rising edges of the transfer clock CLK TxD/RxD 1: Timer A0 overflow Timer A0 2. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register) CLK TxD/RxD Bus collision detect interrupt request bit Transmit enable bit 3. Transmit start condition select bit (Bit 6 of the UART2 special mode register) 0: In normal state CLK TxD Enabling transmission With "1: falling edge of RxD2" selected CLK TxD RxD Figure 1.17.28. Some other functions added 143 Mitsubishi microcomputers UART2 Special Mode Register 2 UART2 Special Mode Register 2 M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART2 special mode register 2 (address 037616) is used to further control UART2 in I2C mode. Figure 1.17.29 shows the UART2 special mode register 2. UART2 special mode register 2 (I 2 C bus exclusive use register) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR2 Address 037616 When reset 0016 Bit symbol IICM2 CSC SWC ALS STAC SWC2 SDHI SHTC Bit name I 2C mode select bit 2 Clock-synchronous bit SCL wait output bit SDA output stop bit UART2 initialization bit SCL wait output bit 2 SDA output disable bit Start/stop condition control bit Function Refer to Table 1.17.11 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0: UART2 clock 1: 0 output 0: Enabled 1: Disabled (high impedance) Set this bit to “1” in I2C mode (refer to Table 1.17.12) RW Figure 1.17.29. UART2 special mode register 2 144 Mitsubishi microcomputers UART2 Special Mode Register 2 M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Bit 0 of the UART2 special mode register 2 (address 037616) is used as the I2C mode select bit 2. Table 1.17.11 shows the types of control to be changed by I2C mode select bit 2 when the I2C mode select bit is set to “1”. Table 1.17.12 shows the timing characteristics of detecting the start condition and the stop condition. Set the start/stop condition control bit (bit 7 of UART2 special mode register 2) to “1” in I2C mode. Table 1.17.11. Functions changed by I2C mode select bit 2 Function 1 Factor of interrupt number 15 2 Factor of interrupt number 16 IICM2 = 0 No acknowledgment detection (NACK) Acknowledgment detection (ACK) IICM2 = 1 UART2 transmission (the rising edge of the final bit of the clock) UART2 reception (the falling edge of the final bit of the clock) UART2 reception (the falling edge of the final bit of the clock) The falling edge of the final bit of the reception clock The falling edge of the final bit of the reception clock 3 DMA1 factor at the time when 1 1 0 1 Acknowledgment detection (ACK) is assigned to the DMA request factor selection bits 4 Timing for transferring data from the UART2 reception shift register to the reception buffer. 5 Timing for generating a UART2 reception/ACK interrupt request The rising edge of the final bit of the reception clock The rising edge of the final bit of the reception clock Table 1.17.12. Timing characteristics of detecting the start condition and the stop condition (Note 1) 3 to 6 cycles < duration for setting-up (Note 2) 3 to 6 cycles < duration for holding (Note 2) Note 1 : When the start/stop condition control bit SHTC is “1” . Note 2 : “Cycles” is in terms of the input oscillation frequency f(XIN) of the main clock. Duration for setting up SCL SDA Duration for holding (Start condition) SDA (Stop condition) 145 Mitsubishi microcomputers UART2 Special Mode Register 2 M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER P70 through P7 2 conforming to the simplified I 2C bus P70/TxD2/SDA Timer I/O Selector UART2 To DMA0, DMA1 UART2 SDDS=0 or DL=000 Transmission register IICM=0 or IICM2=1 IICM=1 and IICM2=0 UART2 transmission/ NACK interrupt request Digital delay (Divider) SDDS=1 and DL≠000 DQ T SDHI ALS Arbitration To DMA0 IICM=1 Reception register IICM=0 UART2 IICM=1 and IICM2=0 S Q Noize Filter Timer IICM=0 or IICM2=1 UART2 reception/ACK interrupt request, DMA1 request Start condition detection Stop condition detection Falling edge detection P71/RxD2/SCL I/O Q R R Bus busy NACK D T D T Q L-synchronous output enabling bit Q ACK Data bus Selector (Port P7 1 output data latch) Internal clock UART2 IICM=1 SWC2 9th pulse IICM=1 Bus collision/start, stop condition detection interrupt request Noize Filter Noize Filter IICM=1 Bus collision CLK control detection UART2 Falling edge of 9 bit SWC IICM=0 External clock IICM=0 UART2 Port reading * With IICM set to 1, the port terminal is to be readable P72/CLK2 IICM=0 Selector even if 1 is assigned to P7 1 of the direction register. I/O Timer Figure 1.17.30. Functional block diagram for I2C mode Functions available in I2C mode are shown in Figure 1.17.30 — a functional block diagram. Bit 3 of the UART2 special mode register 2 (address 037616) is used as the SDA output stop bit. Setting this bit to “1” causes an arbitration loss to occur, and the SDA pin turns to high-impedance state at the instant when the arbitration lost detecting flag is set to “1”. Bit 1 of the UART2 special mode register 2 (address 037616) is used as the clock synchronization bit. With this bit set to “1” at the time when the internal SCL is set to “H”, the internal SCL turns to “L” if the falling edge is found in the SCL pin; and the baud rate generator reloads the set value, and start counting within the “L” interval. When the internal SCL changes from “L” to “H” with the SCL pin set to “L”, stops counting the baud rate generator, and starts counting it again when the SCL pin turns to “H”. Due to this function, the UART2 transmission-reception clock becomes the logical product of the signal flowing through the internal SCL and that flowing through the SCL pin. This function operates over the period from the moment earlier by a half cycle than falling edge of the UART2 first clock to the rising edge of the ninth bit. To use this function, choose the internal clock for the transfer clock. Bit 2 of the UART2 special mode register 2 (037616) is used as the SCL wait output bit. Setting this bit to “1” causes the SCL pin to be fixed to “L” at the falling edge of the ninth bit of the clock. Setting this bit to “0” frees the output fixed to “L”. 146 Mitsubishi microcomputers UART2 Special Mode Register 2 M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Bit 4 of the UART2 special mode register 2 (address 037616) is used as the UART2 initialization bit. Setting this bit to “1”, and when the start condition is detected, the microcomputer operates as follows. (1) The transmission shift register is initialized, and the content of the transmission register is transferred to the transmission shift register. This starts transmission by dealing with the clock entered next as the first bit. The UART2 output value, however, doesn’t change until the first bit data is output after the entrance of the clock, and remains unchanged from the value at the moment when the microcomputer detected the start condition. (2) The reception shift register is initialized, and the microcomputer starts reception by dealing with the clock entered next as the first bit. (3) The SCL wait output bit turns to “1”. This turns the SCL pin to “L” at the falling edge of the ninth bit of the clock. Starting to transmit/receive signals to/from UART2 using this function doesn’t change the value of the transmission buffer empty flag. To use this function, choose the external clock for the transfer clock. Bit 5 of the UART2 special mode register 2 (037616) is used as the SCL pin wait output bit 2. Setting this bit to “1” with the serial I/O specified allows the user to forcibly output an “1” from the SCL pin even if UART2 is in operation. Setting this bit to “0” frees the “L” output from the SCL pin, and the UART2 clock is input/output. Bit 6 of the UART2 special mode register 2 (037616) is used as the SDA output disable bit. Setting this bit to “1” forces the SDA pin to turn to the high-impedance state. Refrain from changing the value of this bit at the rising edge of the UART2 transfer clock. There can be instances in which arbitration lost detecting flag is turned on. 147 Mitsubishi microcomputers M16C / 62N Group S I/O3, 4 S I/O3, 4 S I/O3 and S I/O4 are exclusive clock-synchronous serial I/Os. Figure 1.17.31 shows the S I/O3, 4 block diagram, and Figure 1.17.32 shows the S I/O3, 4 related register. Table 1.17.13 shows the specifications of S I/O3, 4. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER f1 f8 f32 SMi1 SMi0 Data bus Synchronous circuit SMi3 SMi6 SMi6 1/2 1/(ni+1) Bit rate generator (8) S I/O counter i (3) P90/CLK3 (P95/CLK4) SMi2 SMi3 S I/Oi interrupt request P92/SOUT3 (P96/SOUT4) P91/SIN3 (P97/SIN4) SMi5 LSB MSB S I/Oi transmission/reception register (8) 8 Note: i = 3, 4. ni = A value set in the S I/O i bit rate generator (036316, 036716). Figure 1.17.31. S I/O3, 4 block diagram 148 Mitsubishi microcomputers M16C / 62N Group S I/O3, 4 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER S I/Oi control register (i = 3, 4) (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol SiC Bit symbol SMi0 SMi1 SMi2 SMi3 Address 036216, 036616 Bit name When reset 4016 Description b1 b0 RW Internal synchronous clock select bit 0 0 : Selecting f1 0 1 : Selecting f8 1 0 : Selecting f32 1 1 : Must not be set. 0 : SOUTi output 1 : SOUTi output disable(high impedance) 0 : Input-output port 1 : SOUTi output, CLK function SOUTi output disable bit S I/Oi port select bit (Note 2) Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”. SMi5 SMi6 SMi7 Transfer direction select bit Synchronous clock select bit (Note 2) SOUTi initial value set bit 0 : LSB first 1 : MSB first 0 : External clock 1 : Internal clock Effective when SMi3 = 0 0 : L output 1 : H output Note 1: Set “1” in bit 2 of the protection register (000A16) in advance to write to the S I/Oi control register (i = 3, 4). Note 2: When using the port as an input/output port by setting the SI/Oi port select bit (i = 3, 4) to “0”, be sure to set the sync clock select bit to “1”. SI/Oi bit rate generator (Note 1, 2) b7 b0 Symbol S3BRG S4BRG Address 036316 036716 When reset Indeterminate Indeterminate Values that can be set 0016 to FF16 RW Indeterminate Assuming that set value = n, BRGi divides the count source by n + 1 Note 1: Write a value to this register while transmit/receive halts. Note 2: Use MOV instruction to write to this register. SI/Oi transmit/receive register (Note) b7 b0 Symbol S3TRR S4TRR Address 036016 036416 Indeterminate When reset Indeterminate Indeterminate RW Transmission/reception starts by writing data to this register. After transmission/reception finishes, reception data is input. Note: Write a value to this register while transmit/receive halts. Figure 1.17.32. S I/O3, 4 related register 149 Mitsubishi microcomputers M16C / 62N Group S I/O3, 4 Table 1.17.13. Specifications of S I/O3, 4 Item Transfer data format Transfer clock Specifications • Transfer data length: 8 bits • With the internal clock selected (bit 6 of 036216, 036616 = “1”): f1/2(ni+1), f8/2(ni+1), f32/2(ni+1) (Note 1) • With the external clock selected (bit 6 of 036216, 036616 = 0):Input from the CLKi terminal (Note 2) • To start transmit/reception, the following requirements must be met: - Select the synchronous clock (use bit 6 of 036216, 036616). Select a frequency dividing ratio if the internal clock has been selected (use bits 0 and 1 of 036216, 036616). - SOUTi initial value set bit (use bit 7 of 036216, 036616)= 1. - S I/Oi port select bit (bit 3 of 036216, 036616) = 1. - Select the transfer direction (use bit 5 of 036216, 036616) -Write transfer data to SI/Oi transmit/receive register (036016, 036416) • To use S I/Oi interrupts, the following requirements must be met: - Clear the SI/Oi interrupt request bit before writing transfer data to the SI/Oi transmit/receive register (bit 3 of 004916, 004816) = 0. • Rising edge of the last transfer clock. (Note 3) • LSB first or MSB first selection Whether transmission/reception begins with bit 0 (LSB) or bit 7 (MSB) can be selected. • Function for setting an SOUTi initial value selection When using an external clock for the transfer clock, the user can choose the SOUTi pin output level during a non-transfer time. For details on how to set, see Figure 1.17.33. • Unlike UART0–2, SI/Oi (i = 3, 4) is not divided for transfer register and buffer. Therefore, do not write the next transfer data to the SI/Oi transmit/receive register (addresses 036016, 036416) during a transfer. • When the internal clock is selected for the transfer clock, SOUTi holds the last data for a 1/2 transfer clock period after it finished transferring and then goes to a highimpedance state. However, if the transfer data is written to the SI/Oi transmit/ receive register (addresses 036016, 036416) during this time, SOUTi is placed in the high-impedance state immediately upon writing and the data hold time is thereby reduced. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Conditions for transmission/ reception start Interrupt request generation timing Select function Precaution Note 1: n is a value from 0016 through FF16 set in the S I/Oi bit rate generator (i = 3, 4). Note 2: With the external clock selected: • Before data can be written to the SI/Oi transmit/receive register (addresses 036016, 036416), the CLKi pin input must be in the high state. Also, before rewriting the SI/Oi Control Register (addresses 036216, 036616)’s bit 7 (SOUTi initial value set bit), make sure the CLKi pin input is held high. • The S I/Oi circuit keeps on with the shift operation as long as the synchronous clock is entered in it, so stop the synchronous clock at the instant when it counts to eight. The internal clock, if selected, automatically stops. Note 3: If the internal clock is used for the synchronous clock, the transfer clock signal stops at the “H” state. 150 Mitsubishi microcomputers M16C / 62N Group S I/O3, 4 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Functions for setting an SOUTi initial value When using an external clock for the transfer clock, the SOUTi pin output level during a non-transfer time can be set to the high or the low state. Figure 1.17.33 shows the timing chart for setting an SOUTi initial value and how to set it. (Example) With “H” selected for SOUTi: S I/Oi port select bit SMi3 = 0 Signal written to the S I/Oi transmit/receive register SOUTi's initial value set bit (SMi7) SOUTi initial value select bit SMi7 = 1 (SOUTi: Internal “H” level) S I/Oi port select bit (SMi3) S I/Oi port select bit SMi3 = 0 1 (Port select: Normal port SOUTi) D0 SOUTi (internal) SOUTi terminal = “H” output Port output SOUTi terminal output Initial value = “H” (Note) (i = 3, 4) Setting the SOUTi initial value to H Port selection (normal port SOUTi) D0 Signal written to the S I/Oi register =“L” “H” “L” (Falling edge) Note: The set value is output only when the external clock has been selected. When initializing SOUTi, make sure the CLKi pin input is held “H” level. If the internal clock has been selected or if SOUT output disable has been set, this output goes to the high-impedance state. SOUTi terminal = Outputting stored data in the S I/Oi transmission/ reception register Figure 1.17.33. Timing chart for setting SOUTi’s initial value and how to set it S I/Oi operation timing Figure 1.17.34 shows the S I/Oi operation timing 1.5 cycle (max) SI/Oi internal clock Transfer clock (Note 1) Signal written to the S I/Oi transmit/receive register S I/Oi output SOUTi (i= 3, 4) "H" "L" "H" "L" "H" "L" Note2 "H" "L" "H" "L" Hiz D0 D1 D2 D3 D4 D5 D6 D7 Hiz S I/Oi input SINi (i= 3, 4) SI/Oi interrupt request (i= 3, 4) bit "1" "0" Note 1: With the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using bits 0 and 1 of the S I/Oi control register. (i=3,4) (No frequency division, 8-division frequency, 32-division frequency.) Note 2: With the internal clock selected for the transfer clock, the SOUTi (i = 3, 4) pin becomes to the high-impedance state after the transfer finishes. Note 3: Shown above is the case where the SOUTi (i = 3, 4) port select bit =“1”. Figure 1.17.34. S I/Oi operation timing chart 151 Mitsubishi microcomputers A-D Converter A-D Converter M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P100 to P107, P95, P96 and P00 to P07 also function as the analog signal input pins. The direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF. The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Table 1.18.1 shows the performance of the A-D converter. Figure 1.18.1 shows the block diagram of the A-D converter, and Figures 1.18.2 and 1.18.3 show the A-D converter-related registers. Table 1.18.1. Performance of A-D converter Item Performance Method of A-D conversion Successive approximation (capacitive coupling amplifier) 0V to AVCC (VCC) VCC = 3.3V fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN) 8-bit or 10-bit (selectable) VCC = 3.3V • Without sample and hold function ±5LSB • With sample and hold function (8-bit resolution) ±2LSB • With sample and hold function (10-bit resolution) AN0 to AN7 input : ±5LSB ANEX0 and ANEX1 input (including mode in which external operation amp is connected) : ±7LSB AN00 to AN07 input : ±7LSB Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 Analog input pins 8pins (AN0 to AN7) + 2pins (ANEX0 and ANEX1) + 8pins (AN00 to AN07) A-D conversion start condition • Software trigger A-D conversion starts when the A-D conversion start flag changes to “1” • External trigger (can be retriggered) A-D conversion starts when the A-D conversion start flag is “1” and the ___________ ADTRG/P97 input changes from “H” to “L” Conversion speed per pin • Without sample and hold function 8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles • With sample and hold function 8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles Note 1: Does not depend on use of sample and hold function. Note 2: Divide the fAD if f(XIN) exceeds 10MHZ, and make φAD frequency equal to or less than 10MHz. And divide the fAD if VCC is less than 3.0V, and make φAD frequency equal to or lower than fAD/2. Without sample and hold function, set the φAD frequency to 250kHZ min. With the sample and hold function, set the φAD frequency to 1MHZ min. Analog input voltage (Note 1) Operating clock φAD (Note 2) Resolution Absolute precision 152 Mitsubishi microcomputers A-D Converter M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D conversion rate selection CKS1 = 1 fAD VREF VCUT = 0 1/2 Resistor ladder 1/2 CKS0 = 1 CKS0 = 0 φAD CKS1 = 0 AVSS VCUT = 1 Successive conversion register A-D control register 1 (address 03D716) A-D control register 0 (address 03D616) Addresses (03C116, 03C016) (03C316, 03C216) (03C516, 03C416) (03C716, 03C616) (03C916, 03C816) (03CB16, 03CA16) (03CD16, 03CC16) (03CF16, 03CE16) A-D register 0 (16) A-D register 1 (16) A-D register 2 (16) A-D register 3 (16) A-D register 4 (16) A-D register 5 (16) A-D register 6 (16) A-D register 7 (16) Data bus high-order Data bus low-order Decoder for A-D register A-D control register 2 (address 03D416) Vref Decoder for channel selection Comparator VIN PM00 PM01 Port P10 group Port P0 group P00/AN00 P01/AN01 P02/AN02 P03/AN03 P04/AN04 P05/AN05 P06/AN06 P07/AN07 PM01,PM00,CH2,CH1,CH0 = 00000 = 00001 = 00010 = 00011 = 00100 = 00101 = 00110 = 00111 P100/AN0 P101/AN1 P102/AN2 P103/AN3 P104/AN4 P105/AN5 P106/AN6 P107/AN7 CH2,CH1,CH0 = 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111 ADGSEL1,ADGSEL0 = 00 OPA1,OPA0 = 00 PM01,PM00 = 00 ADGSEL1,ADGSEL0 = 10 OPA1,OPA0 = 00 ADGSEL1,ADGSEL0 = 00 OPA1,OPA0 = 11 PM01,PM00 = 00 ADGSEL1,ADGSEL0 = 10 OPA1,OPA0 = 11 ANEX0 ANEX1 OPA0 = 1 OPA1 = 1 OPA1,OPA0 = 01 OPA1 = 1 Figure 1.18.1. Block diagram of A-D converter 153 Mitsubishi microcomputers A-D Converter M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON0 Bit symbol CH0 Address 03D616 Bit name When reset 00000XXX2 Function b2 b1 b0 RW Analog input pin select bit CH1 CH2 MD0 MD1 TRG ADST CKS0 Trigger select bit A-D conversion start flag Frequency select bit 0 A-D operation mode select bit 0 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b4 b3 (Note 2) (Note 3) 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected (Note 3) Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN00 to AN07 can be used the same as AN0 to AN7. Note 3: When changing A-D operation mode, set analog input pin again. A-D control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON1 Bit symbol SCAN0 Address 03D716 Bit name When reset 0016 Function When single sweep and repeat sweep mode 0 are selected b1 b0 RW A-D sweep pin select bit 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) SCAN1 When repeat sweep mode 1 is selected b1 b0 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) MD2 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit External op-amp connection mode bit (Note 2) 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 0 : Vref not connected 1 : Vref connected b7 b6 BITS CKS1 VCUT OPA0 OPA1 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN00 to AN07 can be used the same as AN0 to AN7. Figure 1.18.2. A-D converter-related registers (1) 154 Mitsubishi microcomputers A-D Converter M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D control register 2 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON2 Address 03D416 When reset 0000XXX02 0 Bit symbol SMP Bit name A-D conversion method select bit Function 0 : Without sample and hold 1 : With sample and hold b2 b1 RW ADGSEL0 ADGSEL1 Reserved bit Analog input group select bit 0 0 : Port10 group is selected 0 1 : Must not be set. 1 0 : Port0 group is selected (Note 2) 1 1 : Must not be set. Must always be set to “0” Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: In selecting port P0 group, P104 to P107 can not be used as a key-input interrupt function input pin. A-D register i (b15) b7 (b8) b0 b7 Symbol ADi(i=0 to 7) Address When reset 03C016 to 03CF16 Indeterminate b0 Function Eight low-order bits of A-D conversion result • During 10-bit mode Two high-order bits of A-D conversion result • During 8-bit mode When read, the content is indeterminate Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. RW Figure 1.18.3. A-D converter-related registers (2) 155 Mitsubishi microcomputers A-D Converter (1) One-shot mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conversion. Table 1.18.2 shows the specifications of one-shot mode. Figure 1.18.4 shows the A-D control register in one-shot mode. Table 1.18.2. One-shot mode specifications Specification Function The pin selected by the analog input pin select bit is used for one A-D conversion Start condition Writing “1” to A-D conversion start flag Stop condition • End of A-D conversion (A-D conversion start flag changes to “0”, except when external trigger is selected) • Writing “0” to A-D conversion start flag Interrupt request generation timing End of A-D conversion Input pin One of AN0 to AN7, as selected (Note) Reading of result of A-D converter Read A-D register corresponding to selected pin Note : AN00 to AN07 can be used the same as AN0 to AN7. A-D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Item 00 Symbol ADCON0 Bit symbol CH0 Address 03D616 Bit name When reset 00000XXX2 Function b2 b1 b0 RW Analog input pin select bit CH1 CH2 MD0 MD1 TRG ADST CKS0 A-D operation mode select bit 0 Trigger select bit 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b4 b3 (Note 2) (Note 3) (Note 3) 0 0 : One-shot mode 0 : Software trigger 1 : ADTRG trigger A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0: fAD/4 is selected 1: fAD/2 is selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN00 to AN07 can be used the same as AN0 to AN7. Note 3: When changing A-D operation mode, set analog input pin again. A-D control register 1 (Note) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit symbol SCAN0 SCAN1 MD2 BITS CKS1 VCUT OPA0 OPA1 Address 03D716 Bit name When reset 0016 Function Invalid in one-shot mode RW A-D sweep pin select bit A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit1 Vref connect bit External op-amp connection mode bit Set to “0” when this mode is selected 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected b7 b6 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Figure 1.18.4. A-D conversion register in one-shot mode 156 Mitsubishi microcomputers A-D Converter (2) Repeat mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. Table 1.18.3 shows the specifications of repeat mode. Figure 1.18.5 shows the A-D control register in repeat mode. Table 1.18.3. Repeat mode specifications Item Function Star condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter Specification The pin selected by the analog input pin select bit is used for repeated A-D conversion Writing “1” to A-D conversion start flag Writing “0” to A-D conversion start flag None generated One of AN0 to AN7, as selected (Note) Read A-D register corresponding to selected pin (at any time) Note : AN00 to AN07 can be used the same as AN0 to AN7. A-D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 01 Symbol ADCON0 Bit symbol CH0 CH1 Address 03D616 Bit name When reset 00000XXX2 Function b2 b1 b0 RW Analog input pin select bit CH2 MD0 MD1 TRG ADST CKS0 A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b4 b3 (Note 2) (Note 3) (Note 3) 0 1 : Repeat mode 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN00 to AN07 can be used the same as AN0 to AN7. Note 3: When changing A-D operation mode, set analog input pin again. A-D control register 1 (Note) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit symbol SCAN0 SCAN1 MD2 BITS CKS1 VCUT OPA0 OPA1 Address 03D716 Bit name When reset 0016 Function Invalid in repeat mode RW A-D sweep pin select bit A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit External op-amp connection mode bit Set to “0” when this mode is selected 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected b7 b6 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Figure 1.18.5. A-D conversion register in repeat mode 157 Mitsubishi microcomputers A-D Converter (3) Single sweep mode M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D conversion. Table 1.18.4 shows the specifications of single sweep mode. Figure 1.18.6 shows the A-D control register in single sweep mode. Table 1.18.4. Single sweep mode specifications Item Specification Function The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion Start condition Writing “1” to A-D converter start flag Stop condition • End of A-D conversion (A-D conversion start flag changes to “0”, except when external trigger is selected) • Writing “0” to A-D conversion start flag Interrupt request generation timing End of A-D conversion Input pin AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) (Note) Reading of result of A-D converter Read A-D register corresponding to selected pin Note : AN00 to AN07 can be used the same as AN0 to AN7. A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 10 Symbol ADCON0 Bit symbol CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 Address 03D616 Bit name When reset 00000XXX2 Function Invalid in single sweep mode RW Analog input pin select bit A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0 b4 b3 1 0 : Single sweep mode 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit symbol SCAN0 Address 03D716 Bit name When reset 0016 Function When single sweep and repeat sweep mode 0 are selected b1 b0 RW A-D sweep pin select bit SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit External op-amp connection mode bit (Note 3) 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) (Note 2) MD2 BITS CKS1 VCUT OPA0 OPA1 Set to “0” when this mode is selected 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected b7 b6 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN00 to AN07 can be used the same as AN0 to AN7. Note 3: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit. Figure 1.18.6. A-D conversion register in single sweep mode 158 Mitsubishi microcomputers A-D Converter (4) Repeat sweep mode 0 M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep A-D conversion. Table 1.18.5 shows the specifications of repeat sweep mode 0. Figure 1.18.7 shows the A-D control register in repeat sweep mode 0. Table 1.18.5. Repeat sweep mode 0 specifications Item Function Start condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter Specification The pins selected by the A-D sweep pin select bit are used for repeat A-D conversion Writing “1” to A-D conversion start flag Writing “0” to A-D conversion start flag None generated AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) (Note) Read A-D register corresponding to selected pin (at any time) Note : AN00 to AN07 can be used the same as AN0 to AN7. A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 11 Symbol ADCON0 Bit symbol CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 Address 03D616 Bit name When reset 00000XXX2 Function Invalid in repeat sweep mode 0 RW Analog input pin select bit A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0 b4 b3 1 1 : Repeat sweep mode 0 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit symbol SCAN0 Address 03D716 Bit name When reset 0016 Function When single sweep and repeat sweep mode 0 are selected b1 b0 RW A-D sweep pin select bit SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit External op-amp connection mode bit (Note 3) 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) (Note 2) MD2 BITS CKS1 VCUT OPA0 OPA1 Set to “0” when this mode is selected 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected b7 b6 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN00 to AN07 can be used the same as AN0 to AN7. Note 3: Neither “01” nor “10” can be selected with the external op-amp connection mode bit. Figure 1.18.7. A-D conversion register in repeat sweep mode 0 159 Mitsubishi microcomputers A-D Converter (5) Repeat sweep mode 1 M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the A-D sweep pin select bit. Table 1.18.6 shows the specifications of repeat sweep mode 1. Figure 1.18.8 shows the A-D control register in repeat sweep mode 1. Table 1.18.6. Repeat sweep mode 1 specifications Specification All pins perform repeat A-D conversion, with emphasis on the pin or pins selected by the A-D sweep pin select bit Example : AN0 selected AN0 AN1 AN0 AN2 AN0 AN3, etc Start condition Writing “1” to A-D conversion start flag Stop condition Writing “0” to A-D conversion start flag Interrupt request generation timing None generated Input pin With emphasis on these pins ; AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins) (Note) Reading of result of A-D converter Read A-D register corresponding to selected pin (at any time) Note : AN00 to AN07 can be used the same as AN0 to AN7. Function A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 Item 11 Symbol ADCON0 Bit symbol CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 Address 03D616 Bit name When reset 00000XXX2 Function Invalid in repeat sweep mode 1 RW Analog input pin select bit A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0 b4 b3 1 1 : Repeat sweep mode 1 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol ADCON1 Bit symbol SCAN0 Address 03D716 Bit name When reset 0016 Function When repeat sweep mode 1 is selected b1 b0 RW A-D sweep pin select bit SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit External op-amp connection mode bit (Note 3) 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) Set to “1” when this mode is selected 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected b7 b6 (Note 2) MD2 BITS CKS1 VCUT OPA0 OPA1 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN00 to AN07 can be used the same as AN0 to AN7. Note 3: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit. Figure 1.18.8. A-D conversion register in repeat sweep mode 1 160 Mitsubishi microcomputers A-D Converter (a) Sample and hold M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 φAD cycle is achieved with 8-bit resolution and 33 φAD with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold is to be used. (b) Extended analog input pins In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can also be converted from analog to digital. When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “0”, input via ANEX0 is converted from analog to digital. The result of conversion is stored in A-D register 0. When bit 6 of the A-D control register 1 (address 03D716) is “0” and bit 7 is “1”, input via ANEX1 is converted from analog to digital. The result of conversion is stored in A-D register 1. Furthermore, the input via 8 pins of the extended analog input pins AN00 to AN07 can be converted from analog to digital. These pins can be used the same as AN0 to AN7. Use the A-D control register 2 (address 03D416) bit 1 and bit 2 to select the pin group AN0 to AN7, AN00 to AN07. (c) External operation amp connection mode In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can be amplified together by just one operation amp and used as the input for A-D conversion. When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “1”, input via AN0 to AN7 (Note) is output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in the corresponding A-D register. The speed of A-D conversion depends on the response of the external operation amp. Do not connect the ANEX0 and ANEX1 pins directly. Figure 1.18.9 is an example of how to connect the pins in external operation amp mode. Note : AN00 to AN07 can be used the same as AN0 to AN7. ADGSEL1,ADGSEL0 = 0,0 Port P10 group Analog input pins AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADGSEL1,ADGSEL0 = 1,0 Resistor ladder Successive conversion register Port P0 group Analog input pins AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 ANEX0 ANEX1 External op-amp Comparator Figure 1.18.9. Example of external op-amp connection mode 161 Mitsubishi microcomputers D-A Converter D-A Converter M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of this type. D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the target port to output mode if D-A conversion is to be performed. When the D-A output is enabled, the pullup function of the corresponding port is automatically disabled. Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register. V = VREF X n/ 256 (n = 0 to 255) VREF : reference voltage Table 1.19.1 lists the performance of the D-A converter. Figure 1.19.1 shows the block diagram of the D-A converter. Figure 1.19.2 shows the D-A control register. Figure 1.19.3 shows the D-A converter equivalent circuit. Table 1.19.1. Performance of D-A converter Item Conversion method Resolution Analog output pin Performance R-2R method 8 bits 2 channels Data bus low-order bits D-A register 0 (8) (Address 03D816) D-A0 output enable bit R-2R resistor ladder P93/DA0 D-A register 1 (8) (Address 03DA16) D-A1 output enable bit R-2R resistor ladder P94/DA1 Figure 1.19.1. Block diagram of D-A converter 162 Mitsubishi microcomputers D-A Converter M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER D-A control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DACON Bit symbol DA0E DA1E Address 03DC16 Bit name D-A0 output enable bit D-A1 output enable bit When reset 0016 Function 0 : Output disabled 1 : Output enabled 0 : Output disabled 1 : Output enabled RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0” D-A register b7 b0 Symbol DAi (i = 0,1) Address 03D816, 03DA16 When reset Indeterminate Function Output value of D-A conversion RW RW Figure 1.19.2. D-A control register D-A0 output enable bit “0” DA0 “1” 2R MSB D-A register 0 2R 2R 2R 2R 2R 2R 2R LSB R R R R R R R 2R “0” “1” AVSS VREF Note 1: The above diagram shows an instance in which the D-A register is assigned 2A16. Note 2: The same circuit as this is also used for D-A1. Note 3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to 0 and set the D-A register to 0016 so that no current flows in the resistors Rs and 2Rs. Figure 1.19.3. D-A converter equivalent circuit 163 Mitsubishi microcomputers CRC M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CRC Calculation Circuit The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcomputer uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code. The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC code is set in a CRC data register each time one byte of data is transferred to a CRC input register after writing an initial value into the CRC data register. Generation of CRC code for one byte of data is completed in two machine cycles. Figure 1.20.1 shows the block diagram of the CRC circuit. Figure 1.20.2 shows the CRC-related registers. Figure 1.20.3 shows the calculation example using the CRC calculation circuit. Data bus high-order bits Data bus low-order bits Eight low-order bits CRC data register (16) Eight high-order bits (Addresses 03BD16, 03BC16) CRC code generating circuit x16 + x12 + x5 + 1 CRC input register (8) (Address 03BE16) Figure 1.20.1. Block diagram of CRC circuit CRC data register (b15) b7 (b8) b0 b7 b0 Symbol CRCD Address 03BD16, 03BC16 When reset Indeterminate Values that can be set 000016 to FFFF16 Function CRC calculation result output register RW CRC input register b7 b0 Symbo CRCIN Function Data input register Address 03BE16 When reset Indeterminate Values that can be set 0016 to FF16 RW Figure 1.20.2. CRC-related registers 164 Mitsubishi microcomputers CRC M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER b15 b0 (1) Setting 000016 CRC data register CRCD [03BD16, 03BC16] b7 b0 (2) Setting 0116 CRC input register CRCIN [03BE16] 2 cycles After CRC calculation is complete b15 b0 118916 CRC data register CRCD [03BD16, 03BC16] Stores CRC code The code resulting from sending 0116 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial, (X16 + X12 + X5 + 1), becomes the remainder resulting from dividing (1000 0000) X16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. LSB 1000 1000 1 0001 0000 0010 0001 1000 0000 0000 1000 1000 0001 1000 0001 1000 1000 1001 LSB 8 1 0000 0000 0000 0001 0001 1 0000 1 1000 0000 1000 0000 0 1 1000 MSB MSB Modulo-2 operation is operation that complies with the law given below. 0+0=0 0+1=1 1+0=1 1+1=0 -1 = 1 9 Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000) corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC operation. Also switch between the MSB and LSB of the result as stored in CRC data. b7 b0 (3) Setting 2316 CRC input register CRCIN [03BE16] After CRC calculation is complete b15 b0 0A4116 CRC data register CRCD [03BD16, 03BC16] Stores CRC code Figure 1.20.3. Calculation example using the CRC calculation circuit 165 Mitsubishi microcomputers Programmable I/O Port M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Ports There are 87 programmable I/O ports: P0 to P10 (excluding P85). Each port can be set independently for input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P85 is an input-only port and has no built-in pull-up resistance. Figures 1.21.1 to 1.21.4 show the programmable I/O ports. Figure 1.21.5 shows the I/O pins. Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices. To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A converter), they function as outputs regardless of the contents of the direction registers. When pins are to be used as the outputs for the D-A converter, do not set the direction registers to output mode. See the descriptions of the respective functions for how to set up the built-in peripheral devices. (1) Direction registers Figure 1.21.6 shows the direction registers. These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin. In memory expansion and microprocessor mode, the contents of corresponding direction register of pins _______ _______ _____ ________ ______ ________ _______ _______ __________ _________ A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot be modified. Note: There is no direction register bit for P85. (2) Port registers Figure 1.21.7 shows the port registers. These registers are used to write and read data for input and output to and from an external device. A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port registers corresponds one for one to each I/O pin. In memory expansion and microprocessor mode, the contents of corresponding port register of pins A0 to _______ ________ _____ ________ ______ ________ ________ _______ __________ _________ A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot be modified. (3) Pull-up control registers Figure 1.21.8 shows the pull-up control registers. The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. However, in memory expansion mode and microprocessor mode, the pull-up control register of P0 to P3, P40 to P43, and P5 is invalid. The contents of register can be changed, but the pull-up resistance is not connected. (4) Port control register Figure 1.21.9 shows the port control register. The bit 0 of port control register is used to read port P1 as follows: 0 : When port P1 is input port, port input level is read. When port P1 is output port , the contents of port P1 register is read. 1 : The contents of port P1 register is read always. This register is valid in the following: • External bus width is 8 bits in microprocessor mode or memory expansion mode. • Port P1 can be used as a port in multiplexed bus for the entire space. 166 Mitsubishi microcomputers M16C / 62N Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up selection Direction register P00 to P07 P20 to P27, P30 to P37, P40 to P47, P50 to P54, P56 Inside dotted-line included Inside dotted-line not included Data bus Port latch (Note) Analog input Pull-up selection P10 to P14 Direction register Port P1 control register Data bus Port latch (Note) Pull-up selection P15 to P17 Direction register Port P1 control register Data bus Port latch (Note) Input to respective peripheral functions Pull-up selection P57, P60, P61, P64, P65, P72 to P76, P80, P81, P90, P92 Data bus Direction register "1" Output Port latch (Note) Input to respective peripheral functions Note :1 symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. Figure 1.21.1. Programmable I/O ports (1) 167 Mitsubishi microcomputers Programmable I/O Port M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up selection P82 to P84 Direction register Data bus Port latch (Note1) Input to respective peripheral functions Pull-up selection Direction register P55, P62, P66, P77, P91, P97 Data bus Port latch (Note1) Input to respective peripheral functions Pull-up selection P63, P67 Direction register "1" Data bus Port latch Output (Note1) P85 Data bus NMI interrupt input (Note1) P70, P71 Direction register "1" Port latch Output (Note2) Data bus Input to respective peripheral functions Note :1 Note :2 symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. symbolizes a parasitic diode. Figure 1.21.2. Programmable I/O ports (2) 168 Mitsubishi microcomputers M16C / 62N Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER P100 to P103 (inside dotted-line not included) P104 to P107 (inside dotted-line included) Pull-up selection Direction register Data bus Port latch (Note) Analog input Input to respective peripheral functions Pull-up selection D-A output enabled P93, P94 Direction register Data bus Port latch (Note) Input to respective peripheral functions Analog output D-A output enabled Pull-up selection Direction register P96 "1" Data bus Port latch Output (Note) Analog input Pull-up selection Direction register P95 "1" Data bus Port latch Output (Note) Input to respective peripheral functions Analog input Note : symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. Figure 1.21.3. Programmable I/O ports (3) 169 Mitsubishi microcomputers Programmable I/O Port M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up selection Direction register P87 Data bus Port latch (Note) fc Rf Pull-up selection P86 Direction register "1" Data bus Port latch Output (Note) Rd Note : symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. Figure 1.21.4. Programmable I/O ports (4) BYTE BYTE signal input (Note 2) (Note 1) CNVSS CNVSS signal input (Note 2) (Note 1) RESET RESET signal input (Note 1) Note 1: symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each pin. Note 2: A parasitic diode on the VCC side is added to the mask ROM version. Do not apply a voltage higher than Vcc to each pin. Figure 1.21.5. I/O pins 170 Mitsubishi microcomputers M16C / 62N Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Port Pi direction register (Note 1, 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PDi (i = 0 to 10, except 8) Bit symbol PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7 Address 03E216, 03E316, 03E616, 03E716, 03EA16 03EB16, 03EE16, 03EF16, 03F316, 03F616 Function 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 0 to 10 except 8) When reset 0016 Bit name Port Pi0 direction register Port Pi1 direction register Port Pi2 direction register Port Pi3 direction register Port Pi4 direction register Port Pi5 direction register Port Pi6 direction register Port Pi7 direction register RW Note 1: Set bit 2 of protect register (address 000A16) to “1” before rewriting to the port P9 direction register. Note 2: In memory expansion and microprocessor mode, the contents of corresponding port Pi direction register of pins A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot be modified. Port P8 direction register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PD8 Address 03F216 Bit name Port P80 direction register Port P81 direction register Port P82 direction register Port P83 direction register When reset 00X000002 Function 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Bit symbol PD8_0 PD8_1 PD8_2 PD8_3 RW PD8_4 Port P84 direction register Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. PD8_6 PD8_7 Port P86 direction register Port P87 direction register 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Figure 1.21.6. Direction register 171 Mitsubishi microcomputers Programmable I/O Port M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Port Pi register (Note 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Pi (i = 0 to 10, except 8) Address 03E016, 03E116, 03E416, 03E516, 03E816 03E916, 03EC16, 03ED16, 03F116, 03F416 Function Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : “L” level data 1 : “H” level data (Note 1) (i = 0 to 10 except 8) When reset Indeterminate Indeterminate RW Bit symbol Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7 Bit name Port Pi0 register Port Pi1 register Port Pi2 register Port Pi3 register Port Pi4 register Port Pi5 register Port Pi6 register Port Pi7 register Note 1: Since P70 and P71 are N-channel open drain ports, the data is high-impedance. Note 2: In memory expansion and microprocessor mode, the contents of corresponding port Pi register of pins A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot be modified. Port P8 register b7 b6 b5 b4 b3 b2 b1 b0 Symbol P8 Bit symbol P8_0 P8_1 P8_2 P8_3 P8_4 P8_5 P8_6 P8_7 Address 03F016 Bit name Port P80 register Port P81 register Port P82 register Port P83 register Port P84 register Port P85 register Port P86 register Port P87 register When reset Indeterminate Function Data is input and output to and from each pin by reading and writing to and from each corresponding bit (except for P85) 0 : “L” level data 1 : “H” level data RW Figure 1.21.7. Port register 172 Mitsubishi microcomputers M16C / 62N Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR0 Bit symbol PU00 PU01 PU02 PU03 PU04 PU05 PU06 PU07 Address 03FC16 Bit name P00 to P03 pull-up P04 to P07 pull-up P10 to P13 pull-up P14 to P17 pull-up P20 to P23 pull-up P24 to P27 pull-up P30 to P33 pull-up P34 to P37 pull-up When reset 0016 Function The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high RW Note : In memory expansion and microprocessor mode, the content of this register can be changed, but the pull-up resistance is not connected. Pull-up control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR1 Bit symbol PU10 PU11 PU12 PU13 PU14 PU15 PU16 Address 03FD16 Bit name When reset 0016 (Note 2) Function RW P40 to P43 pull-up (Note 3) The corresponding port is pulled high with a pull-up resistor P44 to P47 pull-up 0 : Not pulled high P50 to P53 pull-up (Note 3) 1 : Pulled high P54 to P57 pull-up (Note 3) P60 to P63 pull-up P64 to P67 pull-up P72 to P73 pull-up (Note 1) PU17 P74 to P77 pull-up Note 1: Since P70 and P71 are N-channel open drain ports, pull-up is not available for them. Note 2: When the VCC level is being impressed to the CNVSS terminal, this register becomes to 0216 when reset (PU11 becomes to “1”). Note 3: In memory expansion and microprocessor mode, the content of these bits can be changed, but the pull-up resistance is not connected. Pull-up control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR2 Bit symbol PU20 PU21 PU22 PU23 PU24 PU25 Address 03FE16 Bit name P80 to P83 pull-up P84 to P87 pull-up (Except P85) P90 to P93 pull-up P94 to P97 pull-up P100 to P103 pull-up P104 to P107 pull-up When reset 0016 Function The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Figure 1.21.8. Pull-up control register 173 Mitsubishi microcomputers Programmable I/O Port M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Port control register b7 b6 b5 b4 b3 b2 b1 b0 Symbpl PCR Address 03FF16 When reset 0016 Bit symbol PCR0 Bit name Port P1 control register Function 0 : When input port, read port input level. When output port, read the contents of port P1 register. 1 : Read the contents of port P1 register though input/output port. RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Figure 1.21.9. Port control register 174 Mitsubishi microcomputers M16C / 62N Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.21.1. Example connection of unused pins in single-chip mode Pin name Ports P0 to P10 (excluding P85) XOUT (Note) NMI AVCC AVSS, VREF, BYTE Connection After setting for input mode, connect every pin to VSS via a resistor (pull-down); or after setting for output mode, leave these pins open. Open Connect via resistor to VCC (pull-up) Connect to VCC Connect to VSS Note: With external clock input to XIN pin. Table 1.21.2. Example connection of unused pins in memory expansion mode and microprocessor mode Pin name Ports P6 to P10 (excluding P85) P45 / CS1 to P47 / CS3 Connection After setting for input mode, connect every pin to VSS via a resistor (pull-down); or after setting for output mode, leave these pins open. Set ports to input mode, set output enable bits of CS1 through CS3 to 0, and connect to Vcc via resistors (pull-up). Open BHE, ALE, HLDA, XOUT (Note 1), BCLK (Note 2) HOLD, RDY, NMI AVCC AVSS, VREF Connect via resistor to VCC (pull-up) Connect to VCC Connect to VSS Note 1: With external clock input to XIN pin. Note 2: When the BCLK output disable bit (bit 7 at address 000416) is set to “1”, connect to VCC via a resistor (pull-up). Microcomputer Port P0 to P10 (except for P85) (Input mode) · · · (Input mode) (Output mode) · · · Microcomputer Port P6 to P10 (except for P85) (Input mode) · · · (Input mode) (Output mode) · · · Open Open NMI XOUT AVCC BYTE AVSS VREF Open VCC Port P45 / CS1 to P47 / CS3 NMI BHE HLDA ALE XOUT BCLK (Note) HOLD RDY AVCC AVSS VREF Open VCC VSS VSS In single-chip mode In memory expansion mode or in microprocessor mode Note : When the BCLK output disable bit (bit 7 at address 000416) is set to “1”, connect to VCC via a resistor (pull-up). Figure 1.21.10. Example connection of unused pins 175 Mitsubishi microcomputers Electrical characteristics M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Electrical characteristics Table 1.26.1. Absolute maximum ratings Symbol Vcc AVcc Supply voltage Parameter Analog supply voltage Input voltage RESET, CNVSS, BYTE, P00 to P07, P10 to P17, P20 to P27, P30 to P37,P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P87, P90 to P97, P100 to P107, VREF, XIN P70, P71 Output voltage P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107, XOUT Condition VCC=AVCC VCC=AVCC Rated value - 0.3 to 4.2 - 0.3 to 4.2 Unit V V VI - 0.3 to Vcc + 0.3 V - 0.3 to 4.2 V VO - 0.3 to Vcc + 0.3 V Pd P70, P71 Power dissipation Topr=25 C - 0.3 to 4.2 300 - 20 to 85 / -40 to 85 (Note) - 65 to 150 Operating ambient temperature Topr Storage temperature Tstg Note: Specify a product of -40°C to 85°C to use it. V mW C C 176 Mitsubishi microcomputers Electrical characteristics M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.26.2. Recommended operating conditions (referenced to VCC = 2.4V (Mask ROM version is 2.2V) to 3.6V at Topr = –20°C to 85oC / – 40°C to 85oC(Note 3) unless otherwise specified) Symbol Vcc AVcc Vss AVss Parameter Supply voltage Analog supply voltage Supply voltage Analog supply voltage HIGH input voltage P31 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVSS, BYTE P70, P71 P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode) P00 to P07, P10 to P17, P20 to P27, P30 (data input function during memory expansion and microprocessor modes) Min. 2.4 (Note 4) Standard Typ. 3.3 Vcc 0 0 Max. 3.6 Unit V V V V 0.8Vcc 0.8Vcc 0.8Vcc 0.5Vcc 0 0 0 V cc 4.2 V cc V cc 0.2Vcc 0.2Vcc 0.16Vcc - 10.0 V V V V V V V mA VIH LOW input voltage VIL P31 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVSS, BYTE P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode) P00 to P07, P10 to P17, P20 to P27, P30 (data input function during memory expansion and microprocessor modes) HIGH peak output I OH (peak) current I OH (avg) I OL (peak) I OL (avg) P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 HIGH average output P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, current P80 to P84, P86, P87, P90 to P97, P100 to P107 P00 to P07, P10 to P17, P20 to P27, P30 to P37, LOW peak output P40 to P47, P50 to P57, P60 to P67, P70 to P77, current P80 to P84, P86, P87, P90 to P97, P100 to P107 P00 to P07, P10 to P17, P20 to P27, P30 to P37, LOW average P40 to P47, P50 to P57, P60 to P67, P70 to P77, output current P80 to P84, P86, P87, P90 to P97, P100 to P107 - 5.0 mA 10.0 mA 5.0 0 0 0 0 0 0 32.768 16 15 X Vcc - 29 17.5 X Vcc - 35 16 11.25 X Vcc - 17.75 11.25 X Vcc - 17.75 50 mA MHz MHz MHz MHz MHz MHz kHz f (XIN) Main clock input oscillation frequency (Note 5, Note 6) No wait With wait Vcc=3.0V to 3.6V Mask ROM version Flash memory version Vcc=2.4V to 3.0V Mask ROM version Vcc=2.2V to 2.4V Vcc=3.0V to 3.6V Mask ROM version Flash memory version Vcc=2.4V to 3.0V Mask ROM version f (XcIN) Vcc=2.2V to 2.4V Subclock oscillation frequency Note 1: The mean output current is the mean value within 100ms. Note 2: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, and P10 must be 80mA max. The total IOH (peak) for ports P0, P1, P2, P86, P87, P9, and P10 must be 80mA max. The total IOL (peak) for ports P3, P4, P5, P6, P7, and P80 to P84 must be 80mA max. The total IOH (peak) for ports P3, P4, P5, P6, P72 to P77, and P80 to P84 must be 80mA max. Note 3: Specify a product of -40°C to 85°C to use it. Note 4: 2.2V is minimum supply voltage of mask ROM version. Note 5: Relationship between main clock oscillation frequency and supply voltage. Main clock input oscillation frequency (No wait) Mask ROM version Main clock input oscillation frequency (With wait) Mask ROM version Flash memory version program voltage and read operation voltage characteristics Operating maximum frequency [MHZ] Mask ROM and flash memory versions Operating maximum frequency [MHZ] Mask ROM and flash memory versions 11.25 X VCC –17.75MHZ Flash program voltage VCC=3.0V to 3.6V Flash read operation voltage VCC=2.4V to 3.6V 16.0 15 X VCC –29MHZ 17.5 X VCC–35MHZ 16.0 9.25 7.0 7.0 3.5 0.0 2.2 2.4 3.0 3.6 0.0 2.2 2.4 3.0 3.6 Supply voltage[V] Supply voltage[V] (BCLK: no division) (BCLK: no division) Note 6: Execute case without wait, program / erase of flash memory by VCC=3.0V to 3.6V and f(BCLK) ≤ 6.25 MHz. Execute case with wait, program / erase of flash memory by VCC=3.0V to 3.6V and f(BCLK) ≤ 10.0 MHz. 177 Mitsubishi microcomputers Electrical characteristics M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.26.3. Electrical characteristics (referenced to VCC = 3.0V to 3.6V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 1), f(XIN) = 16MHZ unless otherwise specified) Symbol VOH Parameter Measuring condition Standard Min Typ. Max. 2 .8 Unit V HIGH output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37, P40 to P47, P50 to P57, IOH = -1mA P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 VCC = 3.3V HIGH output voltage XOUT HIGHPOWER LOWPOWER IOH = -0.1mA, VCC = 3.3V IOH = -50µA, VCC = 3.3V With no load applied, VCC = 3.3V With no load applied, VCC = 3.3V 2.8 2 .8 2 .8 1 .6 V V VOH HIGH output voltage XCOUT HIGHPOWER LOWPOWER VOL LOW output P00 to P07 ,P10 to P17, P20 to P27, voltage P30 to P37, P40 to P47, P50 to P57, IO L = 1 m A P60 to P67, P70 to P77, P80 to P84, VCC = 3.3V P86, P87, P90 to P97, P100 to P107 HIGHPOWER 0 .5 V VOL LOW output voltage XOUT LOW output voltage XCOUT Hysteresis IOL = 0.1mA, VCC = 3.3V IOL = 50µA, VCC = 3.3V With no load applied, VCC = 3.3V With no load applied, VCC = 3.3V 0 0 0 .5 0 .5 V V LOWPOWER HIGHPOWER LOWPOWER VT+-VT- HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, SCL, SDA CLK0 to CLK4,TA2OUT to TA4OUT, KI0 to KI3, RxD0 to RxD2, SIN3, SIN4 VCC = 3.3V RESET VCC = 3.3V 0.2 0.8 V VT+-VT- Hysteresis 0 .2 1 .8 V II H HIGH input P00 to P07, P10 to P17, P20 to P27, current P30 to P37, P40 to P47 ,P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVss, BYTE LOW input current P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVss, BYTE P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97 ,P100 to P107 VI = 3 V VCC = 3.3V 4 .0 µA I IL VI = 0 V VCC = 3.3V -4.0 µA R PULLUP Pull-up resistance VI = 0 V VCC = 3.3V 20.0 100.0 500.0 kΩ MΩ MΩ V mA mA µA µA µA mA mA R fXIN R fXCIN V RAM Feedback resistance XIN Feedback resistance XCIN RAM retention voltage In single-chip mode, the output pins are open and other pins are VSS When clock is stopped Mask ROM version Flash memory version Mask ROM version 3.0 10.0 2.0 12.5 20.0 40.0 45 225 19.0 21.0 25.0 32.0 f(XIN) = 16MHz, Square wave, no division f(XIN) = 16MHz Square wave, no division f(XCIN) = 32kHz, VCC = 3.3V Square wave Flash memory version f(XCIN) = 32kHz, VCC = 3.3V Square wave, in RAM Flash memory version f(XCIN) = 32kHz, VCC = 3.3V Square wave, in flash memory Flash memory version program Flash memory version erase f(XIN) = 16MHz, VCC = 3.3V Division by 2 f(XIN) = 16MHz, VCC = 3.3V Division by 2 Icc Power supply current f(XCIN) = 32kHz, VCC = 3.3V When a WAITinstruction is executed. Oscillation capacity High (Note 2) 5 .8 µA Mask ROM version f(XCIN) = 32kHz, VCC = 3.3V When a WAIT instruction is executed. Oscillation capacity Low (Note 2) 2.7 µA f(XCIN) = 32kHz, VCC = 3.3V When a WAITinstruction is executed. Oscillation capacity High (Note 2) 7 .0 µA Flash memory version f(XCIN) = 32kHz, VCC = 3.3V When a WAIT instruction is executed. Oscillation capacity Low (Note 2) 3 .0 µA Flash memory version and mask ROM version Topr = 25°C, VCC = 3.3V when clock is stopped Topr = 85°C, VCC = 3.3V when clock is stopped 0.1 0 .4 2.0 µA 100 Note 1: Specify a product of -40°C to 85°C to use it. Note 2: With one timer operated using fC32. 178 Mitsubishi microcomputers Electrical characteristics M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.26.4. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 2.4V to 3.6V, VSS = AVSS = 0V, at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 4), f(XIN) =16MHZ unless otherwise specified) Symbol Resolution Absolute accuracy Sample & hold function not available Sample & hold function available(10bit) Paramete Measuring condition VREF = VCC VREF = VCC = 3.3V AN0 to AN7 input VREF=VCC ANEX0, ANEX1 input, = 3.3V AN00 to AN07 input VREF = VCC = 3.3V Standard Min. Typ. Max. 10 ±2 ±2 ±5 ±5 ±7 ±2 40 Unit Bits LSB LSB LSB LSB kΩ µs µs µs V V Sample & hold function available(8bit) RLADDER tCONV tCONV tSAMP VREF VI A Ladder resistance Conversion time(10bit) Conversion time(8bit) Sampling time Reference voltage Analog input voltage VREF = VCC 10 3.3 2.8 0.3 2.4 0 VCC VREF Note 1: Do f(XIN) in range of main clock input oscillation frequency prescribed with recommended operating conditions of table 1.26.2. Divide the fAD if f(XIN) exceeds 10MHz, and make AD operation clock frequency (ØAD) equal to or lower than 10MHz. And divide the fAD if VCC is less than 3.0V, and make AD operation clock frequency (ØAD) equal to or lower than fAD/2. Note 2: A case without sample & hold function turn AD operation clock frequency (ØAD) into 250 kHz or more in addition to a limit of Note 1. A case with sample & hold function turn AD operation clock frequency (ØAD) into 1MHz or more in addition to a limit of Note 1. Note 3: Connect AVCC pin to VCC pin and apply the same electric potential. Note 4: Specify a product of -40°C to 85°C to use it. Table 1.26.5. D-A conversion characteristics (referenced to VCC = VREF = 2.4V to 3.6V, VSS = AVSS = 0V, at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 2), f(XIN) =16MHZ unless otherwise specified) Symbol – – tsu RO IVREF Parameter Resolution Absolute accuracy, VREF = VCC = 3.3V Setup time Output resistance Reference power supply input current Measuring condition Standard Min. Typ. Max 8 1.0 3 25 1.0 Unit Bits % µs kΩ mA 4 (Note1) 15 Note 1: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “0016”. The A-D converter's ladder resistance is not included. Also, when D-A register contents are not “0016”, the current IVREF always flows even though Vref may have been set to be unconnected by the A-D control register. Note 2: Specify a product of -40°C to 85°C to use it. Table 1.26.6. Flash memory version electrical characteristics (referenced to VCC = 3.0V to 3.6V, at Topr = 0oC to 60oC unless otherwise specified) Parameter Word program time 4K block erase time 64K block erase time Erase all unlocked blocks time Lock bit program time Min. Standard Typ. 15 0.3 0.5 0.5 X n 0.02 Max 150 8 8 8Xn 0.4 Unit µs s s s ms Note : n denotes the number of block erases. Table 1.26.7. Flash memory version program voltage and read operation voltage characteristics (at Topr = 0oC to 60oC) Flash program voltage VCC=3.0V to 3.6V Flash read operation voltage VCC=2.4V to 3.6V 179 Mitsubishi microcomputers Electrical characteristics M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing requirements (referenced to VCC = 3.3V, VSS = 0V, at Topr = – 20oC to 85oC / – 40oC to 85oC (*) unless otherwise specified) * : Specify a product of -40°C to 85°C to use it. Table 1.26.8. External clock input Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Standard Min. Max. 62.5 25 25 15 15 Unit ns ns ns ns ns Table 1.26.9. Memory expansion and microprocessor modes Symbol tac1(RD-DB) tac2(RD-DB) tac3(RD-DB) tsu(DB-RD) tsu(RDY-BCLK ) tsu(HOLD-BCLK ) th(RD-DB) th(BCLK -RDY) th(BCLK-HOLD ) td(BCLK-HLDA ) Parameter Data input access time (no wait) Data input access time (with wait) Data input access time (when accessing multiplex bus area) Data input setup time RDY input setup time HOLD input setup time Data input hold time RDY input hold time HOLD input hold time HLDA output delay time Standard Max. Min. (Note) (Note) (Note) 50 50 100 0 0 0 40 Unit ns ns ns ns ns ns ns ns ns ns Note: Calculated according to the BCLK frequency as follows: tac1(RD – DB) = tac2(RD – DB) = tac3(RD – DB) = 10 9 – 90 f(BCLK) X 2 3 X 10 – 90 f(BCLK) X 2 3 X 10 – 90 f(BCLK) X 2 9 9 [ns] [ns] [ns] 180 Mitsubishi microcomputers Electrical characteristics M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing requirements (referenced to VCC = 3.3V, VSS = 0V, at Topr = – 20oC to 85oC / – 40oC to 85oC (*) unless otherwise specified) * : Specify a product of –40°C to 85°C to use it. Table 1.26.10. Timer A input (counter input in event counter mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 100 40 40 Unit ns ns ns Table 1.26.11. Timer A input (gating input in timer mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 400 200 200 Unit ns ns ns Table 1.26.12. Timer A input (external trigger input in one-shot timer mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Min. Standard Max. Unit ns ns ns 200 100 100 Table 1.26.13. Timer A input (external trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Max. Min. 100 100 Unit ns ns Table 1.26.14. Timer A input (up/down input in event counter mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time Parameter Standard Min. Max. 2000 1000 1000 400 400 Unit ns ns ns ns ns 181 Mitsubishi microcomputers Electrical characteristics M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing requirements (referenced to VCC = 3.3V, VSS = 0V, at Topr = – 20oC to 85oC / – 40oC to 85oC (*) unless otherwise specified) * : Specify a product of –40°C to 85°C to use it. Table 1.26.15. Timer B input (counter input in event counter mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) Standard Min. 100 40 40 200 80 80 Max. Unit ns ns ns ns ns ns Table 1.26.16. Timer B input (pulse period measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 400 200 200 Max. Unit ns ns ns Table 1.26.17. Timer B input (pulse width measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 400 200 200 Max. Unit ns ns ns Table 1.26.18. A-D trigger input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (trigger able minimum) ADTRG input LOW pulse width Standard Min. 1000 125 Max. Unit ns ns Table 1.26.19. Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time _______ Parameter Standard Min. 300 150 150 100 0 50 90 Max. Unit ns ns ns ns ns ns ns Table 1.26.20. External interrupt INTi inputs Symbol tw(INH) tw(INL) INTi input HIGH pulse width INTi input LOW pulse width Parameter Standard Min. 250 250 Max. Unit ns ns 182 Mitsubishi microcomputers Electrical characteristics M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Switching characteristics (referenced to VCC = 3.3V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 3), CM15 = “1” unless otherwise specified) Table 1.26.21. Memory expansion and microprocessor modes (with no wait) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard)(Note2) 10 9 – 50 f(BCLK) X 2 Measuring condition Standard Min. Max. 50 4 0 0 50 4 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 1.26.1 –4 40 0 40 0 50 4 (Note1) 0 Note 1: Calculated according to the BCLK frequency as follows: td(DB – WR) = [ns] Note 2: This is standard value shows the timing when the output is off, and doesn't show hold time of data bus. Hold time of data bus is different by capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = –CR X ln (1 – VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time of output “L” level is t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC) = 6.7ns. Note 3: Specify a product of -40°C to 85°C to use it. R DBi C P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 30pF Figure 1.26.1. Port P0 to P10 measurement circuit 183 Mitsubishi microcomputers Electrical characteristics M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Switching characteristics (referenced to VCC = 3.3V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 3), CM15 = “1” unless otherwise specified) Table 1.26.22. Memory expansion and microprocessor modes (when accessing external memory area with wait) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard)(Note2) 10 9 f(BCLK) Measuring condition Standard Min. Max. 50 4 0 0 50 4 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 1.26.1 –4 40 0 40 0 50 4 (Note1) 0 Note 1: Calculated according to the BCLK frequency as follows: td(DB – WR) = – 50 [ns] Note 2: This is standard value shows the timing when the output is off, and doesn't show hold time of data bus. Hold time of data bus is different by capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = –CR X ln (1 – VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time of output “L” level is t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC) = 6.7ns. Note 3: Specify a product of -40°C to 85°C to use it. R DBi C 184 Mitsubishi microcomputers Electrical characteristics M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Switching characteristics (referenced to VCC = 3.3V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 2), CM15 = “1” unless otherwise specified) Table 1.26.23. Memory expansion and microprocessor modes (when accessing external memory area with wait, and select multiplexed bus) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) td(AD-RD) td(AD-WR) tdZ(RD-AD) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) Chip select output hold time (RD standard) Chip select output hold time (WR standard) RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard) ALE signal output delay time (BCLK standard) ALE signal output hold time (BCLK standard) ALE signal output delay time (Address standard) ALE signal output hold time (Adderss standard) Post-address RD signal output delay time Post-address WR signal output delay time Address output floating start time 10 9 +0 f(BCLK) X 2 10 +0 f(BCLK) X 2 10 9 +0 f(BCLK) X 2 10 +0 f(BCLK) X 2 10 X 3 – 50 f(BCLK) X 2 10 +0 f(BCLK) X 2 10 9 – 40 f(BCLK) X 2 9 9 9 9 Measuring condition Standard Min. Max. 50 4 (Note1) (Note1) Unit ns ns ns ns 50 4 (Note1) (Note1) ns ns ns ns ns ns ns ns ns ns ns 40 Figure 1.26.1 0 40 0 50 4 (Note1) (Note1) 40 –4 (Note1) ns ns ns ns ns ns 30 0 0 8 ns ns Note 1: Calculated according to the BCLK frequency as follows: th(RD – AD) = [ns] th(WR – AD) = [ns] th(RD – CS) = [ns] th(WR – CS) = [ns] td(DB – WR) = [ns] th(WR – DB) = [ns] td(AD – ALE) = [ns] Note 2: Specify a product of -40°C to 85°C to use it. 185 Mitsubishi microcomputers M16C / 62N Group Timing SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) th(TIN–UP) tsu(UP–TIN) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) th(C–Q) TxDi td(C–Q) RxDi tw(INL) INTi input tw(INH) tsu(D–C) th(C–D) Figure 1.26.2. Timing diagram (1) 186 Mitsubishi microcomputers M16C / 62N Group Timing SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Expansion Mode and Microprocessor Mode (Valid only with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY–BCLK) th(BCLK–RDY) (Valid with or without wait) BCLK tsu(HOLD–BCLK) HOLD input th(BCLK–HOLD) HLDA output td(BCLK–HLDA) P0, P1, P2, P3, P4, P50 to P52 Hi–Z td(BCLK–HLDA) Note: The above pins are set to high-impedance regardless of the input level of the BYTE pin and bit (PM06) of processor mode register 0 selects the function of ports P40 to P43. Measuring conditions : • VCC=3.3V • Input timing voltage : Determined with VIL=0.66V, VIH=2.64V • Output timing voltage : Determined with VOL=1.65V, VOH=1.65V Figure 1.26.3. Timing diagram (2) 187 Mitsubishi microcomputers M16C / 62N Group Timing SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Expansion Mode and Microprocessor Mode (With no wait) Read timing BCLK td(BCLK–CS) 50ns.max th(BCLK–CS) 4ns.min CSi tcyc th(RD–CS) 0ns.min td(BCLK–AD) 50ns.max th(BCLK–AD) 4ns.min ADi BHE ALE RD td(BCLK–ALE) th(BCLK–ALE) 40ns.max –4ns.min th(RD–AD) 0ns.min td(BCLK–RD) 40ns.max th(BCLK–RD) 0ns.min tac1(RD–DB) DB Hi–Z tSU(DB–RD) 50ns.min th(RD–DB) 0ns.min Write timing BCLK td(BCLK–CS) 50ns.max th(BCLK–CS) 4ns.min CSi tcyc th(WR–CS) 0ns.min td(BCLK–AD) 50ns.max th(BCLK-AD) 4ns.min ADi BHE ALE td(BCLK–ALE) th(BCLK–ALE) 40ns.max th(WR–AD) 0ns.min th(BCLK–WR) 0ns.min –4ns.min td(BCLK–WR) WR,WRL, WRH DB 40ns.max td(BCLK–DB) 50ns.max Hi-Z td(DB–WR) th(BCLK–DB) 4ns.min th(WR–DB) 0ns.min (tcyc/2–50)ns.min Figure 1.26.4. Timing diagram (3) 188 Mitsubishi microcomputers M16C / 62N Group Timing SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Expansion Mode and Microprocessor Mode (When accessing external memory area with wait) Read timing BCLK td(BCLK–CS) 50ns.max th(BCLK–CS) 4ns.min CSi tcyc th(RD–CS) 0ns.min td(BCLK–AD) 50ns.max th(BCLK–AD) 4ns.min ADi BHE ALE td(BCLK–ALE) 40ns.max th(RD–AD) 0ns.min th(BCLK–ALE) –4ns.min td(BCLK–RD) RD DB 40ns.max th(BCLK–RD) 0ns.min tac2(RD–DB) Hi–Z tSU(DB–RD) 50ns.min th(RD–DB) 0ns.min Write timing BCLK td(BCLK–CS) 50ns.max th(BCLK–CS) 4ns.min CSi tcyc th(WR–CS) 0ns.min td(BCLK–AD) 50ns.max th(BCLK–AD) 4ns.min ADi BHE ALE td(BCLK–ALE) 40ns.max th(WR–AD) 0ns.min th(BCLK–ALE) –4ns.min td(BCLK–WR) WR,WRL, WRH DBi td(DB–WR) (tcyc–50)ns.min 40ns.max th(BCLK–WR) 0ns.min td(BCLK–DB) 50ns.max th(BCLK–DB) 4ns.min th(WR–DB) 0ns.min Measuring conditions : • VCC=3.3V • Input timing voltage : Determined with: VIL=0.52V, VIH=1.65V • Output timing voltage : Determined with: VOL=1.65V, VOH=1.65V Figure 1.26.5. Timing diagram (4) 189 Mitsubishi microcomputers M16C / 62N Group Timing SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Expansion Mode and Microprocessor Mode (When accessing external memory area with wait, and select multiplexed bus) Read timing BCLK td(BCLK–CS) 50ns.max tcyc th(RD–CS) (tcyc/2)ns.min th(BCLK–CS) 4ns.min CSi ADi /DBi td(AD–ALE) (tcyc/2-40)ns.min Address th(ALE–AD) 30ns.min Data input Address tdz(RD–AD) 8ns.max tac3(RD–DB) td(AD–RD) 0ns.min th(RD–DB) tSU(DB–RD) 50ns.min 0ns.min td(BCLK–AD) 50ns.max th(BCLK–AD) 4ns.min ADi BHE ALE RD td(BCLK–ALE) 40ns.max th(BCLK–ALE) –4ns.min th(RD–AD) (tcyc/2)ns.min th(BCLK–RD) 0ns.min 40ns.max td(BCLK–RD) Write timing BCLK td(BCLK–CS) 50ns.max tcyc th(BCLK–CS) th(WR–CS) (tcyc/2)ns.min 4ns.min CSi td(BCLK–DB) 50ns.max th(BCLK–DB) 4ns.min Data output Address ADi /DBi Address td(AD–ALE) (tcyc/2–40)ns.min td(DB–WR) (tcyc*3/2–50)ns.min th(WR–DB) (tcyc/2)ns.min th(BCLK–AD) 4ns.min td(BCLK–AD) 50ns.max ADi BHE ALE td(BCLK–ALE) 40ns.max th(BCLK–ALE) –4ns.min td(AD–WR) 0ns.min th(WR–AD) (tcyc/2)ns.min th(BCLK–WR) 0ns.min td(BCLK–WR) WR,WRL, WRH 40ns.max Measuring conditions : • VCC=3.3V • Input timing voltage : Determined with VIL=0.52V, VIH=1.65V • Output timing voltage : Determined with VOL=1.65V, VOH=1.65V Figure 1.26.6. Timing diagram (5) 190 Mitsubishi microcomputers M16C / 62N Group Description (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Outline Performance (Flash Memory Version) Table 1.28.1 shows the outline performance of the M16C/62N (flash memory version). Table 1.28.1. Outline performance of the M16C/62N (flash memory version) Item Flash memory operation mode Erase block division User ROM area Boot ROM area Performance Three modes (parallel I/O, standard serial I/O, CPU rewrite) See Figure 1.28.1 One division (4 Kbytes) (Note 1) In units of word/byte (Note 2) Collective erase/block erase Program/erase control by software command Protected for each block by lock bit 8 commands 100 times 10 years Parallel I/O and standard serial I/O modes are supported. Program method Erase method Program/erase control method Protect method Number of commands Program/erase count Data Retention ROM code protect Note 1: The boot ROM area contains a standard serial I/O mode control program which is stored in it when shipped from the factory. This area can be erased and programmed in only parallel I/O mode. Note 2: Can be programmed in byte unit only when using parallel I/O mode. 191 Mitsubishi microcomputers M16C / 62N Group Description (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Flash Memory The M16C/62N (flash memory version) contains the flash memory that can be rewritten with a single voltage. For this flash memory, three flash memory modes are available in which to read, program, and erase: parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). Each mode is detailed in the pages to follow. The flash memory is divided into several blocks as shown in Figure 1.28.1, so that memory can be erased one block at a time. Each block has a lock bit to enable or disable execution of an erase or program operation, allowing for data in each block to be protected. In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user’s application system. This boot ROM area can be rewritten in only parallel I/O mode. 0C000016 Block 6 : 64K byte 0D000016 Block 5 : 64K byte 0E000016 Block 4 : 64K byte Note 1: The boot ROM area can be rewritten in only parallel input/output mode. (Access to any other areas is inhibited.) Note 2: To specify a block, use an even address in the block. 0F000016 Flash memory size 256Kbytes 128Kbytes Flash memory start address 0C000016 0E000016 0FE00016 0FF00016 0FFFFF16 0F800016 Block 3 : 32K byte Block 2 :24K byte Block 1 : 4K byte Block 0 : 4K byte User ROM area 0FF00016 0FFFFF16 4K byte Boot ROM area Figure 1.28.1. Block diagram of flash memory version 192 Mitsubishi microcomputers CPU Rewrite Mode (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, only the user ROM area shown in Figure 1.28.1 can be rewritten; the boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the user ROM area and each block area. The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to any area other than the internal flash memory before it can be executed. Microcomputer Mode and Boot Mode The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 1.28.1 for details about the boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low. In this case, the CPU starts operating using the control program in the user ROM area. When the microcomputer is reset by pulling the P55 pin low, the CNVSS pin high, and the P50 pin high, the CPU starts operating using the control program in the boot ROM area. This mode is called the “boot” mode. The control program in the boot ROM area can also be used to rewrite the user ROM area (When rewriting the user ROM area in boot mode, bit 5 of the flash memory control register 0 must be set to “1”. Write to this bit only when executing out of an area other than the internal flash memory). Block Address Block addresses refer to an even address of each block. These addresses are used in the block erase command, lock bit program command, and read lock status command. 193 Mitsubishi microcomputers CPU Rewrite Mode (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Outline Performance (CPU Rewrite Mode) In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by software commands. Operations must be executed from a memory other than the internal flash memory, such as the internal RAM. When the CPU rewrite mode select bit (bit 1 at address 03B716) is set to “1”, transition to CPU rewrite mode occurs and software commands can be accepted. In the CPU rewrite mode, write to and read from software commands and data into even-numbered address (“0” for byte address A0) in 16-bit units. Write data into even address in 16-bit units. Do not write 16bit data into odd address or data in 8-bit units. Always write 8-bit software commands into even-numbered address. Commands are ignored with odd-numbered addresses. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. Read data from an even address in the user ROM area when reading the status register. Figure 1.29.1 shows the flash identification register and flash memory control register 0. _____ Bit 0 of the flash memory control register 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming, erase and lock-bit programming operations, it is “0”. Otherwise, it is “1”. Bit 1 of the flash memory control register 0 is the CPU rewrite mode select bit. The CPU rewrite mode is entered by setting this bit to “1”, so that software commands become acceptable. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly. Therefore, Write to this bit only when _______ executing out of an area other than the internal flash memory. Also only when NMI pin is "H" level. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession. To set this bit to “0” by only writing a “0” . Bit 2 of the flash memory control register 0 is a lock bit disable select bit. By setting this bit to “1”, it is possible to disable erase and write protect (block lock) effectuated by the lock bit data. The lock bit disable select bit only disables the lock bit function; it does not change the lock data bit value. However, if an erase operation is performed when this bit =“1”, the lock bit data that is “0” (locked) is set to “1” (unlocked) after erasure. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession. This bit can be manipulated only when the CPU rewrite mode select bit = “1”. Bit 3 of the flash memory control register is the flash memory reset bit used to reset the control circuit of the internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU rewrite mode select bit is “1”, writing “1” for this bit resets the control circuit. To _____ release the reset, it is necessary to set this bit to “0” when RY/BY status flag is “1”. Also when this bit is set to “1”, power is not supplied to the internal flash memory, thus power consumption can be reduced. However, in this state, the internal flash memory cannot be accessed. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession when the CPU rewrite mode select bit is “1”. Use this bit mainly in the low speed mode (when XCIN is the count source of BCLK). When the CPU is shifted to the stop or wait modes, power to the internal flash memory is automatically shut off. It is reconnected automatically when CPU operation is restored. Therefore, it is not particularly necessary to set flash memory control register 0. Figure 1.29.2b shows a flowchart for shifting to the low power dissipation mode. Always perform operation as indicated in these flowcharts. 194 Mitsubishi microcomputers CPU Rewrite Mode (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Bit 5 of the flash memory control register 0 is a user ROM area select bit which is effective in only boot mode. If this bit is set to “1” in boot mode, the area to be accessed is switched from the boot ROM area to the user ROM area. When the CPU rewrite mode needs to be used in boot mode, set this bit to “1”. Note that if the microcomputer is booted from the user ROM area, it is always the user ROM area that can be accessed and this bit has no effect. When in boot mode, the function of this bit is effective regardless of whether the CPU rewrite mode is on or off. Write to this bit only when executing out of an area other than the internal flash memory. Bit 6 of the flash memory control register 0 is the program status flag used exclusively to read the operating status of the auto program operation. If a program error occurs, it is set to “1”. Otherwise, it is “0”. Bit 7 of the flash memory control register 0 is the erase status flag used exclusively to read the operating status of the auto erase operation. If an erase error occurs, it is set to “1”. Otherwise, it is “0”. Flash identification register b7 b6 b5 b4 b3 b2 b1 b0 Symbol FIDR Bit symbol Address 03B416 When reset 0016 Bit name Function RW RW FIDR0 Procedure Flash identification value Flash value output HND: 0016 (1) Write FF16 to the address 03B416 (2) Read address 03B416 Read value = FF16 ••• DINOR flash memory Read value = 0016 ••• HND flash memory Flash memory control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol FMR0 Bit symbol Address 03B716 When reset XX0000012 0 Bit name RY/BY status flag CPU rewrite mode select bit (Note 1) Function 0: Busy (being written or erased) 1: Ready 0: Normal mode (Software commands invalid) 1: CPU rewrite mode (Software commands acceptable) 0: Block lock by lock bit data is enabled 1: Block lock by lock bit data is disabled 0: Normal operation 1: Reset Must always be set to “0” 0: Boot ROM area is accessed 1: User ROM area is accessed 0: Pass 1: Error 0: Pass 1: Error RW RW FMR00 FMR01 FMR02 Lock bit disable select bit (Note 2) FMR03 Flash memory reset bit (Note 3) Reserved bit FMR05 User ROM area select bit (Note 4) (Effective in only boot mode) Program status flag Erase status flag FMR06 FMR07 Note 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Write to this bit only when executing out of an area other than the internal flash memory. Also only when NMI pin is “H” level. Clear this bit to “0” after read array command. Note 2: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession when the CPU rewrite mode select bit = “1”. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Note 3: Effective only when the CPU rewrite mode select bit = 1. After write “1”, write “0” when RY/BY status flag is “1”. Note 4: Write to this bit only when executing out of an area other than the internal flash memory. Figure 1.29.1. Flash identification register and flash memory control register 0 195 Mitsubishi microcomputers CPU Rewrite Mode (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Program in ROM Start Program in RAM *1 Single-chip mode, memory expansion mode, or boot mode (Boot mode only) Set user ROM area select bit to “1” Set processor mode register (Note 1) Set CPU rewrite mode select bit to “1” (by writing “0” and then “1” in succession)(Note 2) Transfer CPU rewrite mode control program to internal RAM Using software command execute erase, program, or other operation (Set lock bit disable bit as required) Jump to transferred control program in RAM (Subsequent operations are executed by control program in this RAM) Execute read array command or reset flash memory by setting flash memory reset bit (by writing “1” and then “0” in succession) (Note 3) *1 Write “0” to CPU rewrite mode select bit (Boot mode only) Write “0” to user ROM area select bit (Note 4) End Note 1: During CPU rewrite mode, set the BCLK as shown below using the main clock divide ratio select bit (bit 6 at address 000616 and bits 6 and 7 at address 000716): 6.25 MHz or less when wait bit (bit 7 at address 000516) = “0” (without internal access wait state) 10.0 MHz or less when wait bit (bit 7 at address 000516) = “1” (with internal access wait state) Note 2: For CPU rewrite mode select bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Write to this bit only when executing out of an area other than the internal flash memory. Also only when NMI pin is “H” level. Note 3: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute a read array command or reset the flash memory. Note 4: “1” can be set. However, when this bit is “1”, user ROM area is accessed. Figure 1.29.2. CPU rewrite mode set/reset flowchart Program in ROM Start Program in RAM *1 Transfer the program to be executed in the low power dissipation mode, to the internal RAM. Set CPU rewrite mode select bit to “1” (by writing “0” and then “1” in succession) Jump to transferred control program in RAM (Subsequent operations are executed by control program in this RAM) Set flash memory reset bit to “1” (by writing “0” and then “1” in succession)(Note 1) *1 Switch the count source of BCLK. XIN stop. (Note 2) Process of low power dissipation mode XIN oscillating Wait until the XIN has stabilized Switch the count source of BCLK (Note 2) Set flash memory reset bit to “0” Set CPU rewrite mode select bit to “0” Wait time until the internal circuit stabilizes (10 µs) (Note 3) End Note 1: For flash memory reset bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Note 2: Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Note 3: Make a waiting time for 10 µs by software. In this waiting time, do not access flash memory. Figure 1.29.2b. Shifting to the low power dissipation mode flowchart 196 Mitsubishi microcomputers CPU Rewrite Mode (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the BCLK as shown below using the main clock divide ratio select bit (bit 6 at address 000616 and bits 6 and 7 at address 000716): 6.25 MHz or less when wait bit (bit 7 at address 000516) = 0 (without internal access wait state) 10.0 MHz or less when wait bit (bit 7 at address 000516) = 1 (with internal access wait state) (2) Instructions inhibited against use The instructions listed below cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction (3) Interrupts inhibited against use The address match interrupt cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. If interrupts have their vector in the variable vector table, they can be _______ used by transferring the vector into the RAM area. The NMI and watchdog timer interrupts can be used to automatically initialize the flash identification register and flash memory control register 0 to “0”, then return to normal operation. However, these two interrupts' jump addresses are located in the fixed vector table and there must exsist a routine to be executed. Since the rewrite operation is halted _______ when an NMI or watchdog timer interrupts occurs, you must reset the CPU rewite mode select bit to “1” and the perform the erase/program operation again. (4) Access disable Write to CPU rewrite mode select bit and user ROM area select bit only when executing out of an area other than the internal flash memory. (5) How to access For CPU rewrite mode select bit and lock bit disable select bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Write to CPU rewrite mode select bit and user ROM area select bit only when executing out of an area other _______ than the internal flash memory.Also only when NMI pin is “H” level. (6)Writing in the user ROM area If power is lost while rewriting blocks that contain the flash rewrite program with the CPU rewrite mode, those blocks may not be correctly rewritten and it is possible that the flash memory can no longer be rewritten after that. Therefore, it is recommended to use the standard serial I/O mode or parallel I/O mode to rewrite these blocks. (7)Using the lock bit To use the CPU rewrite mode, use a boot program that can set and cancel the lock command. (8) Internal reserved area expansion bit (Bit 3 at address 000516) To use the products which RAM size is over 15 Kbytes or flash memory size is over 192 Kbytes, change into the CPU rewrite mode after setting the internal reserved area expansion bit (bit 3 at address 000516) to “1”. Even if the CPU rewrite mode select bit (bit 1 at address 03B716) is set to “1”, the internal reserved area expansion bit (bit 3 at address 000516) is not set to “1” automatically. 197 Mitsubishi microcomputers CPU Rewrite Mode (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Software Commands Table 1.29.1 lists the software commands available with the M16C/62N (flash memory version). After setting the CPU rewrite mode select bit to 1, write a software command to specify an erase or program operation. Note that when entering a software command, the upper byte (D8 to D15) is ignored. The content of each software command is explained below. Table 1.29.1. List of software commands (CPU rewrite mode) First bus cycle Command Read array Read status register Clear status register Program Block erase Erase all unlock block Lock bit program Read lock bit status (Note 3) Second bus cycle Data (D0 to D7) FF16 7016 5016 4016 2016 A716 7716 7116 Write Write Write Write Read WA BA (Note 3) (Note 4) Mode Write Write Write Write Write Write Write Write Address X X X WA X X BA X Mode Address Data (D0 to D7) Read X SRD (Note 2) WD (Note 3) D016 D016 D016 D6 (Note 5) X BA BA Note 1: When a software command is input, the high-order byte of data (D8 to D15) is ignored. Note 2: SRD = Status Register Data (Set an address to even address in the user ROM area) Note 3: WA = Write Address (even address), WD = Write Data (16-bit data) Note 4: BA = Block Address (Enter the maximum address of each block that is an even address.) Note 5: D6 corresponds to the block lock status. Block not locked when D6 = 1, block locked when D6 = 0. Note 6: X denotes a given address in the user ROM area (that is an even address). Read Array Command (FF16) The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an even address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (D0–D15), 16 bits at a time. The read array mode is retained intact until another command is written. However, please begin to read data in the following procedures when a user uses read array command after program command. (1) Set FF16, FF16, FF16, FF16 to arbitrary continuing four address beforehand (2) Input the top address which FF16 was set at (in read array mode) (3) Input the top address till FFFF16 agrees with the value that begins to have been read (4) Input top address +2 (5) Input top address +2 till FFFF16 agrees with the value that begins to have been read (6) Input an arbitrary address Read Status Register Command (7016) When the command code “7016” is written in the first bus cycle, the content of the status register is read out at the data bus (D0–D7) by a read in the second bus cycle (Set an address to even address in the user ROM area). The status register is explained in the next section. Clear Status Register Command (5016) This command is used to clear the bits SR4 and SR5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code “5016” in the first bus cycle. 198 Mitsubishi microcomputers CPU Rewrite Mode (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Program Command (4016) Program operation starts when the command code “4016” is written in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and verification) will start. Make an address in the first bus cycle same as an address to program by the second bus cycle. Whether the write operation is completed can be confirmed by reading the status register or the RY/ _____ BY status flag. When the program starts, the read status register mode is accessed automatically and the content of the status register is read into the data bus (D0 - D7). The status register bit 7 (SR7) is set to 0 at the same time the write operation starts and is returned to 1 upon completion of the write operation. In this case, the read status register mode remains active until the Read Array command (FF16) is written. ____ The RY/BY status flag is 0 during write operation and 1 when the write operation is completed as is the status register bit 7. At program end, program results can be checked by reading the status register. Figure 1.29.3 shows an example of a program flowchart. Each block of the flash memory can be write protected by using a lock bit. For details, refer to the section where the data protect function is detailed. Additional writes to the already programmed pages are prohibited. Do a command to use in right after of program command as follows Make an address in the first bus cycle same as an address to program by the second bus cycle of program command. Start Write 4016 Write Write address Write data (Set an address to even address in the user ROM area when reading the status register) Status register read SR7=1? or RY/BY=1? YES NO NO SR4=0? YES Program completed Program error Figure 1.29.3. Program flowchart 199 Mitsubishi microcomputers CPU Rewrite Mode (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Block Erase Command (2016/D016) By writing the command code “2016” in the first bus cycle and the confirmation command code “D016” in the second bus cycle that follows to the block address of a flash memory block, the system initiates an auto erase (erase and erase verify) operation. Whether the auto erase operation is completed can be confirmed by reading the status register or the flash memory control register 0. At the same time the auto erase operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. The status register bit 7 (SR7) is set to 0 at the same time the auto erase operation starts and is returned to 1 upon completion of the auto erase operation. In this case, the read status register mode remains active until the Read Array command (FF16) or Read Lock Bit Status command (7116) is written or the flash memory is reset using its reset bit. ____ The RY/BY status flag of the flash memory control register 0 is 0 during auto erase operation and 1 when the auto erase operation is completed as is the status register bit 7. After the auto erase operation is completed, the status register can be read out to know the result of the auto erase operation. For details, refer to the section where the status register is detailed. Figure 1.29.4 shows an example of a block erase flowchart. Each block of the flash memory can be protected against erasure by using a lock bit. For details, refer to the section where the data protect function is detailed. Start Write 2016 Write D016 Block address Status register read (Set an address to even address in the user ROM area when reading the status register) SR7=1? or RY/BY=1? NO YES Check full status check (Note) Block erase completed Error Erase error Note: Refer to Figure 1.29.7 . Figure 1.29.4. Block erase flowchart 200 Mitsubishi microcomputers CPU Rewrite Mode (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Erase All Unlock Blocks Command (A716/D016) By writing the command code “A716” in the first bus cycle and the confirmation command code “D016” in the second bus cycle that follows, the system starts erasing blocks successively. Whether the erase all unlock blocks command is terminated can be confirmed by reading the status register or the flash memory control register 0, in the same way as for block erase. Also, the status register can be read out to know the result of the auto erase operation. When the lock bit disable select bit of the flash memory control register 0 = 1, all blocks are erased no matter how the lock bit is set. On the other hand, when the lock bit disable select bit = 0, the function of the lock bit is effective and only nonlocked blocks (where lock bit data = 1) are erased. Lock Bit Program Command (7716/D016) By writing the command code “7716” in the first bus cycle and the confirmation command code “D016” in the second bus cycle that follows to the block address of a flash memory block, the system sets the lock bit for the specified block to 0 (locked). Make an address in the first bus cycle same as an address to block by the second bus cycle. Figure 1.29.5 shows an example of a lock bit program flowchart. The status of the lock bit (lock bit data) can be read out by a read lock bit status command. Whether the lock bit program command is terminated can be confirmed by reading the status register or the flash memory control register 0, in the same way as for page program. For details about the function of the lock bit and how to reset the lock bit, refer to the section where the data protect function is detailed. Start Write 7716 Write D016 block address Status register read (Set an address to even address in the user ROM area when reading the status register) SR7=1? or RY/BY=1? NO YES SR4 = 0? NO Lock bit program in error YES Lock bit program completed Figure 1.29.5. Lock bit program flowchart 201 Mitsubishi microcomputers CPU Rewrite Mode (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Read Lock Bit Status Command (7116) By writing the command code “7116” in the first bus cycle and then the block address of a flash memory block in the second bus cycle that follows, the system reads out the status of the lock bit of the specified block on to the data bus(D6). Figure 1.29.6 shows an example of a read lock bit program flowchart. Start Write 7116 Enter block address (Note) NO D6 = 0? YES Blocks locked Blocks not locked Note: Data bus bit 6. Figure 1.29.6. Read lock bit status flowchart 202 Mitsubishi microcomputers CPU Rewrite Mode (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Data Protect Function (Block Lock) Each block in Figure 1.28.1 has a nonvolatile lock bit to specify that the block be protected (locked) against erase/write. The lock bit program command is used to set the lock bit to 0 (locked). The lock bit of each block can be read out using the read lock bit status command. Whether block lock is enabled or disabled is determined by the status of the lock bit and how the flash memory control register 0’s lock bit disable select bit is set. (1) When the lock bit disable select bit = “0”, a specified block can be locked or unlocked by the lock bit status (lock bit data). Blocks whose lock bit data = 0 are locked, so they are disabled against erase/ write. On the other hand, the blocks whose lock bit data = “1” are not locked, so they are enabled for erase/write. (2) When the lock bit disable select bit = 1, all blocks are nonlocked regardless of the lock bit data, so they are enabled for erase/write. In this case, the lock bit data that is “0” (locked) is set to “1” (nonlocked) after erasure, so that the lock bit-actuated lock is removed. Status Register The status register shows the operating state of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways. (1) By reading an arbitrary even address from the user ROM area after writing the read status register command (7016) (2) By reading an arbitrary even address from the user ROM area in the period from when the program starts or erase operation starts to when the read array command (FF16) is input Table 1.29.2 shows the status register. Also, the status register can be cleared in the following way. (1) By writing the clear status register command (5016) After a reset, the status register is set to “8016”. Each bit in this register is explained below. Sequencer status (SR7) After power-on, the sequencer status is set to 1(ready). The sequencer status indicates the operating status of the device. This status bit is set to “0” (busy) during write or erase operation and is set to “1” upon completion of these operations. Erase status (SR5) The erase status informs the operating status of erase operation to the CPU. When an erase error occurs, it is set to “1”. The erase status is reset to “0” when cleared. 203 Mitsubishi microcomputers CPU Rewrite Mode (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Program status (SR4) The program status informs the operating status of write operation to the CPU. When a write error occurs, it is set to “1”. The program status is reset to “0” when cleared. When an erase command is in error (which occurs if the command entered after the block erase command (2016) is not the confirmation command (D016), both the program status and erase status (SR5) are set to “1”. When the program status or erase status =“1”, only the following flash commands will be accepted: Read Array, Read Status Register, and Clear Status Register. Also, in one of the following cases, both SR4 and SR5 are set to 1 (command sequence error): (1) When the valid command is not entered correctly (2) When the data entered in the second bus cycle of lock bit program (7716/D016), block erase (2016/D016), or erase all unlock blocks (A716/D016) is not the D016 or FF16. However, if FF16 is entered, read array is assumed and the command that has been set up in the first bus cycle is canceled. Table 1.29.2. Definition of each bit in status register Each bit of SRD SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Definition Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved "1" Ready Terminated in error Terminated in error "0" Busy Terminated normally Terminated normally - 204 Mitsubishi microcomputers CPU Rewrite Mode (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Full Status Check By performing full status check, it is possible to know the execution results of erase and program operations. Figure 1.29.7 shows a full status check flowchart and the action to be taken when each error occurs. Read status register (Set an address to even when reading the status register) Command sequence error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used. SR4=1 and SR5 =1 ? NO SR5=0? YES SR4=0? YES YES NO Block erase error NO Program error End (block erase, program) Execute the read lock bit status command (7116) to see if the block is locked. After removing lock, execute write operation in the same way. If the error still occurs, the page in error cannot be used. Note: When one of SR5 to SR4 is set to 1, none of the program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands. Figure 1.29.7. Full status check flowchart and remedial procedure for errors 205 Mitsubishi microcomputers M16C / 62N Group Functions To Inhibit Rewriting Flash Memory Version (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of the flash memory version from being read out or rewritten easily, the device incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode. ROM code protect function The ROM code protect function is used to prohibit reading out or modifying the contents of the flash memory during parallel I/O mode and is set by using the ROM code protect control address register (0FFFFF16). Figure 1.30.1 shows the ROM code protect control address (0FFFFF16). (This address exists in the user ROM area.) If one of the pair of ROM code protect bits is set to 0, ROM code protect is turned on, so that the contents of the flash memory version are protected against readout and modification. If both of the two ROM code protect reset bits are set to “00,” ROM code protect is turned off, so that the contents of the flash memory version can be read out or modified. Once ROM code protect is turned on, the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/ O or some other mode to rewrite the contents of the ROM code protect reset bits. ROM code protect control address b7 b6 b5 b4 b3 b2 b1 b0 1 1 11 Symbol ROMCP Address 0FFFFF16 When reset FF16 Bit symbol Bit name Function Always set this bit to 1. b5 b4 Reserved bit ROMCR ROM code protect reset bit (Note 2) 0 0: Protect removed 0 1: Protect set bit effective 1 0: Protect set bit effective 1 1: Protect set bit effective b7 b6 ROMCP1 ROM code protect level 1 set bit (Note 1) 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled Note 1: When ROM code protect is turned on, the on-chip flash memory is protected against readout or modification in parallel input/output mode. Note 2: The ROM code protect reset bits can be used to turn off ROM code protect level 1. However, since these bits cannot be changed in parallel input/output mode, they need to be rewritten in serial input/output or some other mode. Figure 1.30.1. ROM code protect control address 206 Mitsubishi microcomputers M16C / 62N Group Functions To Inhibit Rewriting Flash Memory Version (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ID Code Check Function Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the peripheral unit is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the peripheral unit are not accepted. The ID code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. Write a program which has had the ID code preset at these addresses to the flash memory. Address 0FFFDC16 to 0FFFDF16 0FFFE016 to 0FFFE316 0FFFE416 to 0FFFE716 0FFFE816 to 0FFFEB16 0FFFEC16 to 0FFFEF16 0FFFF016 to 0FFFF316 0FFFF416 to 0FFFF716 0FFFF816 to 0FFFFB16 0FFFFC16 to 0FFFFF16 ID1 Undefined instruction vector ID2 Overflow vector BRK instruction vector ID3 Address match vector ID4 Single step vector ID5 Watchdog timer vector ID6 DBC vector ID7 NMI vector Reset vector 4 bytes Figure 1.30.2. ID code store addresses 207 Mitsubishi microcomputers Appendix Parallel I/O Mode (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Parallel I/O Mode The parallel I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is parallel. Use an exclusive programer supporting M16C/62N (flash memory version). Refer to the instruction manual of each programer maker for the details of use. User ROM and Boot ROM Areas In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 1.28.1 can be rewritten. Both areas of flash memory can be operated on in the same way. Program and block erase operations can be performed in the user ROM area. The user ROM area and its blocks are shown in Figure 1.28.1. The boot ROM area is 4 Kbytes in size. In parallel I/O mode, it is located at addresses 0FF00016 through 0FFFFF16. Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the boot ROM area, an erase block operation is applied to only one 4 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory. Therefore, using the device in standard serial input/output mode, you do not need to write to the boot ROM area. 208 Mitsubishi microcomputers Appendix Standard Serial I/O Mode (Flash Memory Version) Pin functions (Flash memory standard serial I/O mode) Pin VCC,VSS CNVSS RESET XIN XOUT BYTE AVCC, AVSS VREF P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P51 to P54, P56, P57 P50 P55 P60 to P63 P64 Name Power input CNVSS Reset input I I I/O M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description Apply program/erase protection voltage to Vcc pin and 0 V to Vss pin. Connect to Vcc pin. Reset input pin. While reset is "L" level, a 20 cycle or longer clock must be input to XIN pin. Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin. Connect this pin to Vcc or Vss. Connect AVss to Vss and AVcc to Vcc, respectively. Clock input Clock output BYTE Analog power supply input Reference voltage input Input port P0 Input port P1 Input port P2 Input port P3 Input port P4 Input port P5 CE input EPM input Input port P6 BUSY output I O I I I I I I I I I I I O Enter the reference voltage for AD from this pin. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" level signal. Input "L" level signal. Input "H" or "L" level signal or open. Standard serial I/O mode 1: BUSY signal output pin Standard serial I/O mode 2: Monitors the boot program operation check signal output pin. Standard serial I/O mode 1: Serial clock input pin Standard serial I/O mode 2: Input "L". Serial data input pin Serial data output pin Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Connect this pin to Vcc. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. P65 P66 P67 P70 to P77 P80 to P84, P86, P87 P85 P90 to P97 P100 to P107 SCLK input RxD input TxD output Input port P7 Input port P8 NMI input Input port P9 Input port P10 I I O I I I I I 209 Mitsubishi microcomputers Appendix Standard Serial I/O Mode (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P10/D8 P11/D9 P12/D10 P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P20/A0(/D0/-) P21/A1(/D1/D0) P22/A2(/D2/D1) P23/A3(/D3/D2) P24/A4(/D4/D3) P25/A5(/D5/D4) P26/A6(/D6/D5) P27/A7(/D7/D6) Vss P30/A8(/-/D7) Vcc P31/A9 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 P42/A18 P43/A19 P07/AN07/D7 P06/AN06/D6 P05/AN05/D5 P04/AN04/D4 P03/AN03/D3 P02/AN02/D2 P01/AN01/D1 P00/AN00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/SIN4 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 1 2345 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 44 M16C/62N Group (Flash memory version) 43 42 41 40 39 38 37 36 35 34 33 32 31 P44/CS0 P45/CS1 P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE P52/RD P53/BCLK P54/HLDA P55/HOLD P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 CE EPM BUSY SCLK RxD TxD Vss P96/ANEX1/SOUT4 P95/ANEX0/CLK4 P94/DA1/TB4IN P93/DA0/TB3IN P92/TB2IN/SOUT3 P91/TB1IN/SIN3 P90/TB0IN/CLK3 BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V P72/CLK2/TA1OUT/V P71/RxD2/SCL/TA0IN/TB5IN P70/TXD2/SDA/TA0OUT Vcc Mode setup method Value Signal CNVss Vcc EPM Vss RESET Vss to Vcc CE Vcc RESET CNVss Connect oscillator circuit. Package: 100P6S-A Figure 1.32.1. Pin connections for serial I/O mode 210 Mitsubishi microcomputers Appendix Standard Serial I/O Mode (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER P12/D10 P11/D9 P10/D8 P07/AN07/D7 P06/AN06/D6 P05/AN05/D5 P04/AN04/D4 P03/AN03/D3 P02/AN02/D2 P01/AN01/D1 P00/AN00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/SIN4 P96/ANEX1/SOUT4 P95/ANEX0/CLK4 P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P20/A0(/D0/-) P21/A1(/D1/D0) P22/A2(/D2/D1) P23/A3(/D3/D2) P24/A4(/D4/D3) P25/A5(/D5/D4) P26/A6(/D6/D5) P27/A7(/D7/D6) Vss P30/A8(/-/D7) Vcc P31/A9 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 M16C/62N Group (Flash memory version) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P42/A18 P43/A19 P44/CS0 P45/CS1 P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE P52/RD P53/BCLK P54/HLDA P55/HOLD P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CTS0/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 P70/TXD2/SDA/TA0OUT P71/RxD2/SCL/TA0IN/TB5IN P72/CLK2/TA1OUT/V CE EPM BUSY SCLK RX D TX D 12345678 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V P94/DA1/TB4IN P93/DA0/TB3IN P92/TB2IN/SOUT3 P91/TB1IN/SIN3 P90/TB0IN/CLK3 BYTE CNVss P87/XCIN P86/XCOUT VSS VCC Mode setup method Signal Value CNVss Vcc EPM Vss RESET Vss to Vcc CE Vcc RESET CNVSS Connect oscillator circuit. Package: 100P6Q-A Figure 1.32.1. Pin connections for serial I/O mode (2) 211 Mitsubishi microcomputers Appendix Standard Serial I/O Mode (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Standard serial I/O mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is serial. There are actually two standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Both modes require a purpose-specific peripheral unit. The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU's rewrite mode), rewrite data input and so forth. It is started when the reset is re_____ ________ leased, which is done when the P50 (CE) pin is "H" level, the P55 (EPM) pin "L" level and the CNVss pin "H" level. (In the ordinary command mode, set CNVss pin to "L" level.) This control program is written in the boot ROM area when the product is shipped from Mitsubishi. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the boot ROM area is rewritten in the parallel I/O mode. Figure 1.32.1 shows the pin connections for the standard serial I/O mode. Serial data I/O uses UART1 and transfers the data serially in 8-bit units. Standard serial I/O switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level of CLK1 pin when the reset is released. To use standard serial I/O mode 1 (clock synchronized), set the CLK1 pin to "H" level and release the reset. The operation uses the four UART1 pins CLK1, RxD1, TxD1 and RTS1 (BUSY). The CLK1 pin is the transfer clock input pin through which an external transfer clock is input. The TxD1 pin is for CMOS output. The RTS1 (BUSY) pin outputs an "L" level when ready for reception and an "H" level when reception starts. To use standard serial I/O mode 2 (clock asynchronized), set the CLK1 pin to "L" level and release the reset. The operation uses the two UART1 pins RxD1 and TxD1. In the standard serial I/O mode, only the user ROM area indicated in Figure 1.32.18 can be rewritten. The boot ROM cannot. In the standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, commands sent from the peripheral unit are not accepted unless the ID code matches. 212 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 1 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Overview of standard serial I/O mode 1 (clock synchronized) In standard serial I/O mode 1, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial I/O (UART1). Standard serial I/O mode 1 is engaged by releasing the reset with the P65 (CLK1) pin "H" level. In reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the CLK1 pin, and are then input to the MCU via the RxD1 pin. In transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the TxD1 pin. The TxD1 pin is for CMOS output. Transfer is in 8-bit units with LSB first. When busy, such as during transmission, reception, erasing or program execution, the RTS1 (BUSY) pin is "H" level. Accordingly, always start the next transfer after the RTS1 (BUSY) pin is "L" level. Also, data and status registers in memory can be read after inputting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained software commands, status registers, etc. 213 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 1 (Flash Memory Version) Software Commands M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.32.1 lists software commands. In the standard serial I/O mode 1, erase operations, programs and reading are controlled by transferring software commands via the RxD1 pin. Software commands are explained here below. Table 1.32.1. Software commands (Standard serial I/O mode 1) Control command 1 Page read 1st byte transfer 2nd byte Address (middle) Address (middle) Address (middle) D016 SRD output Address (middle) Address (middle) 3rd byte Address (high) Address (high) Address (high) SRD1 output Address (high) Address (high) 4th byte 5th byte 6th byte Data output Data input D016 Data output Data input Data output Data input Data output to 259th byte Data input to 259th byte FF16 When ID is not verified Not acceptable Not acceptable Not acceptable Not acceptable Acceptable Not acceptable Not acceptable Not acceptable Not acceptable Not acceptable 2 Page program 4116 3 4 5 6 7 Block erase Erase all unlocked blocks Read status register Clear status register Read lock bit status 2016 A716 7016 5016 7116 Lock bit data output D016 8 9 Lock bit program Lock bit enable 7716 7A16 7516 10 Lock bit disable 11 ID check function 12 Download function Address (middle) Size FA16 Size (low) (high) F516 Version data output Address (middle) Version data output Address (high) Check data (high) Address (low) Address (high) Checksum Version data output Data output 13 Version data output function FB16 ID1 To Data required input number of times Version Version data data output output Data output Data output ID size To ID7 Acceptable Not acceptable 14 Boot ROM area output function 15 Read check data FC16 Version data output to 9th byte Data output to 259th byte Acceptable Not acceptable Not acceptable Check FD16 data (low) Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is transferred from the peripheral unit to the flash memory microcomputer. Note 2: SRD refers to status register data. SRD1 refers to status register 1 data. Note 3: All commands can be accepted when the flash memory is totally blank. 214 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 1 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the “FF16” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first in sync with the fall of the clock. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) FF16 A8 to A15 A16 to A23 data0 data255 Figure 1.32.2. Timing for page read Read Status Register Command This command reads status information. When the “7016” command code is sent with the 1st byte, the contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1 (SRD1) specified with the 3rd byte are read. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 7016 SRD output SRD1 output Figure 1.32.3. Timing for reading the status register 215 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 1 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clear Status Register Command This command clears the bits (SR4, SR5) which are set when the status register operation ends in error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared. When the clear status register operation ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 5016 Figure 1.32.4. Timing for clearing the status register Page Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the “4116” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (D0–D7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. When reception setup for the next 256 bytes ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. The result of the page program can be known by reading the status register. For more information, see the section on the status register. Each block can be write-protected with the lock bit. For more information, see the section on the data protection function. Additional writing is not allowed with already programmed pages. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 4116 A8 to A15 A16 to A23 data0 data255 Figure 1.32.5. Timing for the page program 216 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 1 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Block Erase Command This command erases the data in the specified block. Execute the block erase command as explained here following. (1) Transfer the “2016” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, the erase operation will start for the specified block in the flash memory. Write the highest address of the specified block for addresses A8 to A23. When block erasing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. After block erase ends, the result of the block erase operation can be known by reading the status register. For more information, see the section on the status register. Each block can be erase-protected with the lock bit. For more information, see the section on the data protection function. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 2016 A8 to A15 A16 to A23 D016 Figure 1.32.6. Timing for block erasing 217 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 1 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Erase All Unlocked Blocks Command This command erases the content of all blocks. Execute the erase all unlocked blocks command as explained here following. (1) Transfer the “A716” command code with the 1st byte. (2) Transfer the verify command code “D016” with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. When block erasing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. The result of the erase operation can be known by reading the status register. Each block can be erase-protected with the lock bit. For more information, see the section on the data protection function. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) A716 D016 Figure 1.32.7. Timing for erasing all unlocked blocks Lock Bit Program Command This command writes “0” (lock) for the lock bit of the specified block. Execute the lock bit program command as explained here following. (1) Transfer the “7716” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, “0” is written for the lock bit of the specified block. Write the highest address of the specified block for addresses A8 to A23. When writing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. Lock bit status can be read with the read lock bit status command. For information on the lock bit function, reset procedure and so on, see the section on the data protection function. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 7716 A8 to A15 A16 to A23 D016 Figure 1.32.8 Timing for the lock bit program 218 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 1 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Read Lock Bit Status Command This command reads the lock bit status of the specified block. Execute the read lock bit status command as explained here following. (1) Transfer the “7116” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) The lock bit data of the specified block is output with the 4th byte. The lock bit data is the 6th bit(D6) of the output data. Write the highest address of the specified block for addresses A8 to A23. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 7116 A8 to A15 A16 to A23 D6 Figure 1.32.9. Timing for reading lock bit status Lock Bit Enable Command This command enables the lock bit in blocks whose bit was disabled with the lock bit disable command. The command code “7A16” is sent with the 1st byte of the serial transmission. This command only enables the lock bit function; it does not set the lock bit itself. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 7A16 Figure 1.32.10. Timing for enabling the lock bit 219 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 1 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Lock Bit Disable Command This command disables the lock bit. The command code “7516” is sent with the 1st byte of the serial transmission. This command only disables the lock bit function; it does not set the lock bit itself. However, if an erase command is executed after executing the lock bit disable command, “0” (locked) lock bit data is set to “1” (unlocked) after the erase operation ends. In any case, after the reset is cancelled, the lock bit is enabled. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 7516 Figure 1.32.11. Timing for disabling the lock bit Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the “FA16” command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) FA16 Data size (low) Check sum Program data Program data Data size (high) Figure 1.32.12. Timing for download 220 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 1 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Version Information Output Command This command outputs the version information of the control program stored in the boot area. Execute the version information output command as explained here following. (1) Transfer the “FB16” command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) FB16 'V' 'E' 'R' 'X' Figure 1.32.13. Timing for version information output Boot ROM Area Output Command This command outputs the control program stored in the boot ROM area in one page blocks (256 bytes). Execute the boot ROM area output command as explained here following. (1) Transfer the “FC16” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first, in sync with the fall of the clock. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) FC16 A8 to A15 A16 to A23 data0 data255 Figure 1.32.14. Timing for boot ROM area output 221 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 1 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ID Check This command checks the ID code. Execute the boot ID check command as explained here following. (1) Transfer the “F516” command code with the 1st byte. (2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd, 3rd and 4th bytes respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) F516 DF16 FF16 0F16 ID size ID1 ID7 Figure 1.32.15. Timing for the ID check ID Code When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write a program into the flash memory, which already has the ID code set for these addresses. Address 0FFFDC16 to 0FFFDF16 0FFFE016 to 0FFFE316 0FFFE416 to 0FFFE716 0FFFE816 to 0FFFEB16 0FFFEC16 to 0FFFEF16 0FFFF016 to 0FFFF316 0FFFF416 to 0FFFF716 0FFFF816 to 0FFFFB16 0FFFFC16 to 0FFFFF16 ID1 Undefined instruction vector ID2 Overflow vector BRK instruction vector ID3 Address match vector ID4 Single step vector ID5 Watchdog timer vector ID6 DBC vector ID7 NMI vector Reset vector 4 bytes Figure 1.32.16. ID code storage addresses 222 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 1 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Read Check Data This command reads the check data that confirms that the write data, which was sent with the page program command, was successfully received. (1) Transfer the "FD16" command code with the 1st byte. (2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd. To use this read check data command, first execute the command and then initialize the check data. Next, execute the page program command the required number of times. After that, when the read check command is executed again, the check data for all of the read data that was sent with the page program command during this time is read. The check data is the result of CRC operation of write data. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) FD16 Check data (low) RTS1(BUSY) Check data (high) Figure 1.32.17. Timing for the read check data 223 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 1 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Data Protection (Block Lock) Each of the blocks in Figure 1.32.18 have a nonvolatile lock bit that specifies protection (block lock) against erasing/writing. A block is locked (writing “0” for the lock bit) with the lock bit program command. Also, the lock bit of any block can be read with the read lock bit status command. Block lock disable/enable is determined by the status of the lock bit itself and execution status of the lock bit disable and lock enable bit commands. (1) After the reset has been cancelled and the lock bit enable command executed, the specified block can be locked/unlocked using the lock bit (lock bit data). Blocks with a “0” lock bit data are locked and cannot be erased or written in. On the other hand, blocks with a “1” lock bit data are unlocked and can be erased or written in. (2) After the lock bit disable command has been executed, all blocks are unlocked regardless of lock bit data status and can be erased or written in. In this case, lock bit data that was “0” before the block was erased is set to “1” (unlocked) after erasing, therefore the block is actually unlocked with the lock bit. 0C000016 Block 6 : 64K byte 0D000016 Block 5 : 64K byte 0E000016 Block 4 : 64K byte 0F000016 Flash memory size 256Kbytes 128Kbytes Flash memory start address 0C000016 0E000016 0FE00016 0FF00016 0FFFFF16 0F800016 Block 3 : 32K byte Block 2 :24K byte Block 1 : 4K byte Block 0 : 4K byte User ROM area Figure 1.32.18. Blocks in the user area 224 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 1 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Status Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status register command (7016). Also, the status register is cleared by writing the clear status register command (5016). Table 1.32.2 gives the definition of each status register bit. After clearing the reset, the status register outputs “8016”. Table 1.32.2. Status register (SRD) SRD0 bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved Definition “1” Ready Terminated in error Terminated in error “0” Busy Terminated normally Terminated normally - Sequencer status (SR7) After power-on, the sequencer status is set to 1(ready). The sequencer status indicates the operating status of the device. This status bit is set to “0” (busy) during write or erase operation and is set to 1 upon completion of these operations. Erase Status (SR5) The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”. Program Status (SR4) The program status reports the operating status of the auto write operation. If a write error occurs, it is set to “1”. When the program status is cleared, it is set to “0”. 225 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 1 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Status Register 1 (SRD1) Status register 1 indicates the status of serial communications, results from ID checks and results from check sum comparisons. It can be read after the SRD by writing the read status register command (7016). Also, status register 1 is cleared by writing the clear status register command (5016). Table 1.32.3 gives the definition of each status register 1 bit. “0016” is output when power is turned ON and the flag status is maintained even after the reset. Table 1.32.3. Status register 1 (SRD1) SRD1 bits SR15 (bit7) SR14 (bit6) SR13 (bit5) SR12 (bit4) SR11 (bit3) SR10 (bit2) Status name Boot update completed bit Flash identification value Reserved Check sum match bit ID check completed bits Definition "1" Update completed "0" Not update DINOR Mismatch Not verified Verification mismatch Reserved Verified Normal operation - HND Match 00 01 10 11 Time out - SR9 (bit1) SR8 (bit0) Data receive time out Reserved Boot Update Completed Bit (SR15) This flag indicates whether the control program was downloaded to the RAM or not, using the download function. Flash Identification Value (SR14) This flag indicates whether the flash memor type is HND or DINOR. Check Sum Match Bit (SR12) This flag indicates whether the check sum matches or not when a program, is downloaded for execution using the download function. ID Check Completed Bits (SR11 and SR10) These flags indicate the result of ID checks. Some commands cannot be accepted without an ID check. Data Receive Time Out (SR9) This flag indicates when a time out error is generated during data reception. If this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state. 226 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 1 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Full Status Check Results from executed erase and program operations can be known by running a full status check. Figure 1.32.19 shows a flowchart of the full status check and explains how to remedy errors which occur. Read status register SR4=1 and SR5 =1 ? NO SR5=0? YES SR4=0? YES YES Command sequence error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used. NO Block erase error NO Program error End (block erase, program) Execute the read lock bit status command (7116) to see if the block is locked. After removing lock, execute write operation in the same way. If the error still occurs, the page in error cannot be used. Note: When one of SR5 to SR4 is set to 1, none of the program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands. Figure 1.32.19. Full status check flowchart and remedial procedure for errors 227 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 1 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Example Circuit Application for The Standard Serial I/O Mode 1 The below figure shows a circuit application for the standard serial I/O mode 1. Control pins will vary according to programmer, therefore see the peripheral unit manual for more information. Clock input BUSY output Data input Data output CLK1 RTS1(BUSY) RXD1 TXD1 M16C/62N Group (Flash memory version) CNVss NMI P50(CE) P55(EPM) (1) Control pins and external circuitry will vary according to peripheral unit. For more information, see the peripheral unit manual. (2) In this example, the microprocessor mode and standard serial I/O mode are switched via a switch. Figure 1.32.20. Example circuit application for the standard serial I/O mode 1 228 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 2 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Overview of standard serial I/O mode 2 (clock asynchronized) In standard serial I/O mode 2, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial I/O (UART1). Standard serial I/O mode 2 is engaged by releasing the reset with the P65 (CLK1) pin "L" level. The TxD1 pin is for CMOS output. Data transfer is in 8-bit units with LSB first, 1 stop bit and parity OFF. After the reset is released, connections can be established at 9,600 bps when initial communications (Figure 1.32.21) are made with a peripheral unit. However, this requires a main clock with a minimum 2 MHz input oscillation frequency. Baud rate can also be changed from 9,600 bps to 19,200, 38,400 or 57,600 bps by executing software commands. However, communication errors may occur because of the oscillation frequency of the main clock. If errors occur, change the main clock's oscillation frequency and the baud rate. After executing commands from a peripheral unit that requires time to erase and write data, as with erase and program commands, allow a sufficient time interval or execute the read status command and check how processing ended, before executing the next command. Data and status registers in memory can be read after transmitting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained initial communications with peripheral units, how frequency is identified and software commands. Initial communications with peripheral units After the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation frequency of the main clock, by sending the code as prescribed by the protocol for initial communications with peripheral units (Figure 1.32.21). (1) Transmit "B016" from a peripheral unit. If the oscillation frequency input by the main clock is 10 or 16 MHz, the MCU with internal flash memory outputs the "B016" check code. If the oscillation frequency is anything other than 10 or 16 MHz, the MCU does not output anything. (2) Transmit "0016" from a peripheral unit 16 times. (The MCU with internal flash memory sets the bit rate generator so that "0016" can be successfully received.) (3) The MCU with internal flash memory outputs the "B016" check code and initial communications end successfully *1. Initial communications must be transmitted at a speed of 9,600 bps and a transfer interval of a minimum 15 ms. Also, the baud rate at the end of initial communications is 9,600 bps. *1. If the peripheral unit cannot receive "B016" successfully, change the oscillation frequency of the main clock. Peripheral unit MCU with internal flash memory Reset (1) Transfer "B016" (2) Transfer "0016" 16 times At least 15ms transfer interval 15 th 16th "B016" "B016" 1st 2nd "0016" "0016" "0016" "0016" "B016" (3) Transfer check code "B016" If the oscillation frequency input by the main clock is 10 or 16 MHz, the MCU outputs "B016". If other than 10 or 16 MHz, the MCU does not output anything. The bit rate generator setting completes (9600bps) Figure 1.32.21. Peripheral unit and initial communication 229 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 2 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER How frequency is identified When "0016" data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the bit rate generator is set to match the operating frequency (2 - 16 MHz). The highest speed is taken from the first 8 transmissions and the lowest from the last 8. These values are then used to calculate the bit rate generator value for a baud rate of 9,600 bps. Baud rate cannot be attained with some operating frequencies. Table 1.32.4 gives the operation frequency and the baud rate that can be attained for. Table 1.32.4 Operation frequency and the baud rate Operation frequency (MH Z) 16MH Z 12MH Z 11MH Z 10MH Z 8MH Z 7.3728MH Z 6MH Z 5MH Z 4.5MH Z 4.194304MH Z 4MH Z 3.58MH Z 3MH Z 2MH Z Baud rate 9,600bps √ √ √ √ √ √ √ √ √ √ √ √ √ √ Baud rate 19,200bps √ √ √ √ √ √ √ √ √ √ √ √ √ – Baud rate 38,400bps √ √ √ – – √ √ – – √ – √ √ – Baud rate 57,600bps √ – – √ √ √ – – √ – – √ – – √ : Communications possible – : Communications not possible 230 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 2 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Software Commands Table 1.32.5 lists software commands. In the standard serial I/O mode 2, erase operations, programs and reading are controlled by transferring software commands via the RxD1 pin. Standard serial I/O mode 2 adds four transmission speed commands - 9,600, 19,200, 38,400 and 57,600 bps - to the software commands of standard serial I/O mode 1. Software commands are explained here below. Table 1.32.5. Software commands (Standard serial I/O mode 2) Control command 1 2 Page read Page program 1st byte transfer 2nd byte Address (middle) Address (middle) Address (middle) D016 SRD output Address (middle) Address (middle) 3rd byte Address (high) Address (high) Address (high) SRD1 output Address (high) Address (high) 4th byte 5th byte 6th byte Data output Data input D016 Data output Data input Data output Data input Data output to 259th byte Data input to 259th byte FF16 4116 When ID is not verified Not acceptable Not acceptable Not acceptable Not acceptable Acceptable Not acceptable Not acceptable Not acceptable Not acceptable Not acceptable 3 4 5 6 7 8 9 Block erase Erase all unlocked blocks Read status register Clear status register Read lock bit status Lock bit program Lock bit enable 2016 A716 7016 5016 7116 7716 7A16 7516 Lock bit data output D016 10 Lock bit disable 11 ID check function 12 Download function Address (middle) Size FA16 Size (low) (high) F516 Version data output Address (middle) Version data output Address (high) Check data (high) Address (low) Address (high) Checksum Version data output Data output 13 Version data output function FB16 ID1 To Data required input number of times Version Version data data output output Data output Data output ID size To ID7 Acceptable Not acceptable 14 Boot ROM area output function 15 Read check data FC16 Version data output to 9th byte Data output to 259th byte Acceptable Not acceptable Not acceptable Check FD16 data (low) 16 Baud rate 9600 17 Baud rate 19200 18 Baud rate 38400 19 Baud rate 57600 B016 B116 B216 B316 B016 B116 B216 B316 Acceptable Acceptable Acceptable Acceptable Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is transferred from the peripheral unit to the flash memory microcomputer. Note 2: SRD refers to status register data. SRD1 refers to status register 1 data. Note 3: All commands can be accepted when the flash memory is totally blank. 231 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 2 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the “FF16” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first. RxD1 (M16C reception data) TxD1 (M16C transmit data) FF16 A8 to A15 A16 to A23 data0 data255 Figure 1.32.22. Timing for page read Read Status Register Command This command reads status information. When the “7016” command code is sent with the 1st byte, the contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1 (SRD1) specified with the 3rd byte are read. RxD1 (M16C reception data) TxD1 (M16C transmit data) 7016 SRD output SRD1 output Figure 1.32.23. Timing for reading the status register 232 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 2 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clear Status Register Command This command clears the bits (SR4, SR5) which are set when the status register operation ends in error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared. RxD1 (M16C reception data) TxD1 (M16C transmit data) 5016 Figure 1.32.24. Timing for clearing the status register Page Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the “4116” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (D0–D7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. The result of the page program can be known by reading the status register. For more information, see the section on the status register. Each block can be write-protected with the lock bit. For more information, see the section on the data protection function. Additional writing is not allowed with already programmed pages. RxD1 (M16C reception data) TxD1 (M16C transmit data) 4116 A8 to A15 A16 to A23 data0 data255 Figure 1.32.25. Timing for the page program 233 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 2 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Block Erase Command This command erases the data in the specified block. Execute the block erase command as explained here following. (1) Transfer the “2016” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, the erase operation will start for the specified block in the flash memory. Write the highest address of the specified block for addresses A8 to A23. After block erase ends, the result of the block erase operation can be known by reading the status register. For more information, see the section on the status register. Each block can be erase-protected with the lock bit. For more information, see the section on the data protection function. RxD1 (M16C reception data) TxD1 (M16C transmit data) 2016 A8 to A15 A16 to A23 D016 Figure 1.32.26. Timing for block erasing 234 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 2 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Erase All Unlocked Blocks Command This command erases the content of all blocks. Execute the erase all unlocked blocks command as explained here following. (1) Transfer the “A716” command code with the 1st byte. (2) Transfer the verify command code “D016” with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. The result of the erase operation can be known by reading the status register. Each block can be eraseprotected with the lock bit. For more information, see the section on the data protection function. RxD1 (M16C reception data) TxD1 (M16C transmit data) A716 D016 Figure 1.32.27. Timing for erasing all unlocked blocks Lock Bit Program Command This command writes “0” (lock) for the lock bit of the specified block. Execute the lock bit program command as explained here following. (1) Transfer the “7716” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, “0” is written for the lock bit of the specified block. Write the highest address of the specified block for addresses A8 to A23. Lock bit status can be read with the read lock bit status command. For information on the lock bit function, reset procedure and so on, see the section on the data protection function. RxD1 (M16C reception data) TxD1 (M16C transmit data) 7716 A8 to A15 A16 to A23 D016 Figure 1.32.28. Timing for the lock bit program 235 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 2 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Read Lock Bit Status Command This command reads the lock bit status of the specified block. Execute the read lock bit status command as explained here following. (1) Transfer the “7116” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) The lock bit data of the specified block is output with the 4th byte. The lock bit data is the 6th bit(D6) of the output data. Write the highest address of the specified block for addresses A8 to A23. RxD1 (M16C reception data) TxD1 (M16C transmit data) 7116 A8 to A15 A16 to A23 D6 Figure 1.32.29. Timing for reading lock bit status Lock Bit Enable Command This command enables the lock bit in blocks whose bit was disabled with the lock bit disable command. The command code “7A16” is sent with the 1st byte of the serial transmission. This command only enables the lock bit function; it does not set the lock bit itself. RxD1 (M16C reception data) TxD1 (M16C transmit data) 7A16 Figure 1.32.30. Timing for enabling the lock bit 236 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 2 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Lock Bit Disable Command This command disables the lock bit. The command code “7516” is sent with the 1st byte of the serial transmission. This command only disables the lock bit function; it does not set the lock bit itself. However, if an erase command is executed after executing the lock bit disable command, “0” (locked) lock bit data is set to “1” (unlocked) after the erase operation ends. In any case, after the reset is cancelled, the lock bit is enabled. RxD1 (M16C reception data) TxD1 (M16C transmit data) 7516 Figure 1.32.31. Timing for disabling the lock bit Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the “FA16” command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM. RxD1 (M16C reception data) TxD1 (M16C transmit data) FA16 Data size (low) Check sum Program data Program data Data size (high) Figure 1.32.32. Timing for download 237 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 2 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Version Information Output Command This command outputs the version information of the control program stored in the boot area. Execute the version information output command as explained here following. (1) Transfer the “FB16” command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters. RxD1 (M16C reception data) TxD1 (M16C transmit data) FB16 'V' 'E' 'R' 'X' Figure 1.32.33. Timing for version information output Boot ROM Area Output Command This command outputs the control program stored in the boot ROM area in one page blocks (256 bytes). Execute the boot ROM area output command as explained here following. (1) Transfer the “FC16” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first. RxD1 (M16C reception data) TxD1 (M16C transmit data) FC16 A8 to A15 A16 to A23 data0 data255 Figure 1.32.34. Timing for boot ROM area output 238 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 2 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ID Check This command checks the ID code. Execute the boot ID check command as explained here following. (1) Transfer the “F516” command code with the 1st byte. (2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd, 3rd and 4th bytes respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code. RxD1 (M16C reception data) TxD1 (M16C transmit data) F516 DF16 FF16 0F16 ID size ID1 ID7 Figure 1.32.35. Timing for the ID check ID Code When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write a program into the flash memory, which already has the ID code set for these addresses. Address 0FFFDC16 to 0FFFDF16 0FFFE016 to 0FFFE316 0FFFE416 to 0FFFE716 0FFFE816 to 0FFFEB16 0FFFEC16 to 0FFFEF16 0FFFF016 to 0FFFF316 0FFFF416 to 0FFFF716 0FFFF816 to 0FFFFB16 0FFFFC16 to 0FFFFF16 ID1 Undefined instruction vector ID2 Overflow vector BRK instruction vector ID3 Address match vector ID4 Single step vector ID5 Watchdog timer vector ID6 DBC vector ID7 NMI vector Reset vector 4 bytes Figure 1.32.36. ID code storage addresses 239 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 2 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Read Check Data This command reads the check data that confirms that the write data, which was sent with the page program command, was successfully received. (1) Transfer the "FD16" command code with the 1st byte. (2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd. To use this read check data command, first execute the command and then initialize the check data. Next, execute the page program command the required number of times. After that, when the read check command is executed again, the check data for all of the read data that was sent with the page program command during this time is read. The check data is the result of CRC operation of write data. RxD1 (M16C reception data) TxD1 (M16C transmit data) FD16 Check data (low) Check data (high) Figure 1.32.37. Timing for the read check data Baud Rate 9600 This command changes baud rate to 9,600 bps. Execute it as follows. (1) Transfer the "B016" command code with the 1st byte. (2) After the "B016" check code is output with the 2nd byte, change the baud rate to 9,600 bps. RxD1 (M16C reception data) TxD1 (M16C transmit data) B016 B016 Figure 1.32.38. Timing of baud rate 9600 240 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 2 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Baud Rate 19200 This command changes baud rate to 19,200 bps. Execute it as follows. (1) Transfer the "B116" command code with the 1st byte. (2) After the "B116" check code is output with the 2nd byte, change the baud rate to 19,200 bps. RxD1 (M16C reception data) TxD1 (M16C transmit data) B116 B116 Figure 1.32.39. Timing of baud rate 19200 Baud Rate 38400 This command changes baud rate to 38,400 bps. Execute it as follows. (1) Transfer the "B216" command code with the 1st byte. (2) After the "B216" check code is output with the 2nd byte, change the baud rate to 38,400 bps. RxD1 (M16C reception data) TxD1 (M16C transmit data) B216 B216 Figure 1.32.40. Timing of baud rate 38400 Baud Rate 57600 This command changes baud rate to 57,600 bps. Execute it as follows. (1) Transfer the "B316" command code with the 1st byte. (2) After the "B316" check code is output with the 2nd byte, change the baud rate to 57,600 bps. RxD1 (M16C reception data) TxD1 (M16C transmit data) B316 B316 Figure 1.32.41. Timing of baud rate 57600 241 Mitsubishi microcomputers Appendix Standard Serial I/O Mode 2 (Flash Memory Version) M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Example Circuit Application for The Standard Serial I/O Mode 2 The below figure shows a circuit application for the standard serial I/O mode 2. CLK1 Monitor output Data input Data output BUSY RXD1 TXD1 M16C/62N Group (Flash memory version) CNVss NMI P50(CE) P55(EPM) (1) In this example, the microprocessor mode and standard serial I/O mode are switched via a switch. Figure 1.32.42. Example circuit application for the standard serial I/O mode 2 242 Mitsubishi microcomputers Package Outline M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Package Outline 100P6S-A MMP JEDEC Code – HD D Weight(g) 1.58 Lead Material Alloy 42 Plastic 100pin 14✕20mm body QFP MD EIAJ Package Code QFP100-P-1420-0.65 e 1 80 b2 100 81 I2 Recommended Mount Pad Symbol Dimension in Millimeters Min Nom Max 3.05 – – 0.1 0.2 0 2.8 – – 0.25 0.3 0.4 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 0.65 – – 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 – – – – 0.13 0.1 – – 0° 10° – – – 0.35 1.3 – – 14.6 – – – – 20.6 HE E 30 51 31 50 A L1 A A1 A2 b c D E e HD HE L L1 x y b2 I2 MD ME A2 F b A1 e y x M Detail F 100P6Q-A MMP JEDEC Code – Weight(g) 0.63 Lead Material Cu Alloy c L Plastic 100pin 14✕14mm body LQFP MD e EIAJ Package Code LQFP100-P-1414-0.50 D 100 76 1 75 b2 HD l2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp A3 25 51 26 50 A e F L1 x y b2 I2 MD ME M Detail F Lp c b x y L Dimension in Millimeters Min Nom Max 1.7 – – 0.1 0.2 0 1.4 – – 0.13 0.18 0.28 0.105 0.125 0.175 13.9 14.0 14.1 13.9 14.0 14.1 0.5 – – 15.8 16.0 16.2 15.8 16.0 16.2 0.3 0.5 0.7 1.0 – – 0.45 0.6 0.75 – 0.25 – – – 0.08 0.1 – – 0° 10° – 0.225 – – 0.9 – – 14.4 – – – – 14.4 HE E A2 A1 A3 ME ME 243 Rev.1.0 Mitsubishi microcomputers Differences between M16C/62N and M16C/62M M16C / 62N Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Differences between M16C/62N and M16C/62M Differences between M16C/62N and M16C/62M(Note) Item Shortest instruction execution time Supply voltage M16C/62N 62.5ns (f(XIN)=16MHZ, VCC=3.0V to 3.6V) 142.9ns (f(XIN)=7MHZ, VCC=2.4V to 3.6V without software wait) M16C/62M 100ns (f(XIN)=10MHZ, VCC=2.7V to 3.6V) 142.9ns (f(XIN)=7MHZ, VCC=2.2V to 3.6V with software one-wait) 2.7V to 3.6V (f(XIN)=10MHZ, without 3.0V to 3.6V (f(XIN)=16MHZ, without software wait) software wait) 2.4V to 3.0V (f(XIN)=7MHZ, without 2.4V to 2.7V (f(XIN)=7MHZ, without software wait) software wait) 2.2V to 3.0V (f(XIN)=7MHZ, with software 2.2V to 2.4V (f(XIN)=7MHZ with one-wait) :mask ROM version software one-wait) 34.0mW (VCC = 3V, f(XIN)=10MHZ, without software wait) 66.0mW (VCC = 3.3V, f(XIN)=16MHZ, without software wait) Memory area expansion (4 Mbytes) Main clock division rate when main clock is stopped: Division by 8 mode Watchdog timer interrupt or reset is selected Only digital delay is selected as SDA delay 10 bits X 8 channels Expandable up to 18 channels 28.5mW (VCC = 3V, f(XIN)=10MHZ, without software wait) Low power consumption Memory area Clock Generating Circuit Watchdog timer Serial I/O (IIC bus mode) A-D converter 1 Mbytes fixed Main clock division rate when main clock is stopped: Does not change Watchdog timer interrupt Analog or digital delay is selected as SDA delay 10 bits X 8 channels Expandable up to 10 channels Note: About the details and the electric characteristics, refer to data sheet. Differences in SFR between M16C/62N and M16C/62M Address 000516 Register name Processor mode register 1 (PM1) b5,b4 b2 000B16 037716 03D416 Data bank register (DBR) UART2 special mode register (U2SMR) A-D control register 2 (ADCON2) Have b7 SDA digital delay select bit ("1" when reset) b2, b1 Analog input group select bit b0 A-D conversion method select bit Have Reserved register b7 b6 Erase status flag Program status flag M16C/62N Memory area expansion bits Watchdog timer function select bit M16C/62M b5,b4 b2 Reserved bits Nothing is assigned Reserved register b7 SDA digital delay select bit ("0" when reset) b2,b1 Reserved bits b0 Reserved bit 03B416 03B616 03B716 Flash identification register (FIDR) Flash memory control register 1 (FMR1) Flash memory control register 0 (FMR0) Reserved register Have b7 b6 Nothing is assigned Nothing is assigned 244 REVISION HISTORY Rev. 1.0 Date Page 29/05/02 6 14 67 206 M16C/62N GROUP DATA SHEET Description Summary Table 1.1.2 Delete “**” Figure 1.5.1 Add “More than...needed” _______ (3) The NMI interrupt Line 12 is partly revised. ROM code protect Line 6 to 9 Delete “ROM code...selected by default.” Figure 1.30.1 is partly revised. (1/1) HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. 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