M32000D4

MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER DESCRIPTION The M32000D4AFP is a new generation microcomputer with a 32-bit CPU and built-in high capacity DRAM. Using this device it is possible to implement the complex applications of the multimedia age with high performance and low power consumption. The M32000D4AFP contains 2M bytes of DRAM and 4K bytes of cache memory. The CPU is implemented with a RISC architecture and has a high performance figure of 52.4 MIPS (at an internal clock rate of 66.6 MHz ). Memory for main storage is provided internally to the device eliminating external memory and associated control circuits thus reducing overall system noise and power consumption. The CPU, internal DRAM and cache memory are connected by a 128-bit, 15 ns/cycle internal bus which virtually eliminates transfer bottlenecks in between the CPU and the memory. The M32000D4AFP internally multiplies the frequency of the input clock signals by four. For an internal operating frequency of 66.6 MHz the input clock frequency is 16.65MHz. A 16-bit data and 24-bit address bus are the M32000D4AFP's external bus and the interface to external peripheral controllers. When the hold state is set, the internal DRAM can be accessed from an external device. A 3-chip basic system configuration using the M32000D4AFP is the device itself plus an ASIC as a peripheral controller and a program ROM. Execution starts from the reset vector entry on the external ROM after power on, a program requiring high speed execution is then transferred to internal DRAM and this is then executed. The M32000D4AFP also has a slave mode additional to its master mode. When set to slave mode the M32000D4AFP can be used as a coprocessor. In this mode it does not access its external bu s immediatly after reset, but waits for the master to start its operation. FEATURES • CPU .......................................................... M32R family CPU core • Pipeline .............................................................................. 5 steps • Basic bus cycle ................................. 15 ns (at internal 66.6 MHz) • Logical address space ............................................ 4G-byte linear • External bus ........................................................ data bus: 16 bits • • • • • • • • • • • • • address bus: 24 bits Internal DRAM ............................................... 16M bits (2M bytes) Cache .......................................................... 4K bytes (direct map) Register configuration ...... general-purpose registers: 32 bits x 16 control registers: 32 bits x 5 Instruction set ....................... 83 instructions/6 addressing modes Instruction format .................................................... 16 bits/32 bits Multiply-accumulate operation unit (DSP function instruction) Internal memory controller Programmable I/O ports Power management function .................................. standby mode /CPU sleep mode PLL clock generating circuit ................. four-time clock PLL circuit Operation mode .............................................. master/slave mode ___ ___ Interrupt input ............................................................ INT and SBI Power source .......................................................... 3.3 V (±10 %) APPLICATIONS Portable equipment, Still camera, Navigation system, Digital instrument, Printer, Scanner, FA equipment MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (TOP VIEW) VCC VCC VCC BCH VCC 71 79 64 56 72 80 65 73 58 57 66 74 59 67 75 60 68 76 61 69 77 62 70 VSS D15 D14 D13 D12 VCC BURST 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 78 63 55 54 53 52 51 50 49 48 47 46 45 44 43 VCC VSS VSS VSS A27 RST BCL R/W A25 VSS A22 A28 A26 *1 A21 SID A20 A30 A29 M/S A24 *1 *1 A23 *1 VSS D7 D6 D5 D4 VCC VCC VSS VSS VCC HREQ HACK SBI INT *1 D3 D2 D1 D0 VSS ST VCC VSS VCC VSS VCC WKUP VCC D11 D10 D9 D8 VSS M32000D4AFP 100-pin QFP/0.65 mm pitch 42 41 40 39 38 37 36 35 34 33 32 31 10 17 25 16 23 24 15 22 14 21 13 20 12 19 11 PLLCAP A14 BS 18 A16 A13 *2 26 27 28 VCC VSS A10 A17 A15 A11 STBY VCC PLLVCC VSS VSS A18 PP0 A19 A9 A8 *1 29 PLLVSS CLKIN Note: Connect *1 pins to VCC. Connect *2 pins to VSS. 2 VCC CS PP1 A12 DC 30 2 3 4 5 1 6 7 8 9 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER BLOCK DIAGRAM 128 cache memory (4K bytes) 128 instruction queue (128 bits x 2 stages) M32000D4AFP 32 bits M32R CPU core instruction decoder M/S 128-bit internal bus RST register PC 32 bits x 16 ALU shift load/ store multiplyaccumulate unit 32 x 16 bits MUL + 56-bit -AC C INT SBI WKUP STBY 128 DRAM (2M bytes) 32 bits 128 data selector 32 bits⇔128 bits memory controller programmable I/O port PP0 PP1 CLKIN PLLCAP PLLVCC PLLVSS 128 external bus interface unit 128 bits⇔16 bits PLL clock generating circuit 23 16 BCL ST BURST DC D0 - D15 HREQ HACK A8 - A30 BCH R/W SID CS BS 3 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER FUNCTIONS function block CPU core characteristics • bus specification basic bus cycle: 15 ns (internal operation at 66.6 MHz) logical address space: linear 4G bytes ____ ____ external address bus: 24 bits (external output pin: A8 to A3 0, BCH, BCL) external data bus: 16 bits • implementation: 5-stage pipeline • core internal: 32 bits • register configuration general-purpose registers: 32 bits ! 1 6 control registers: 32 bits ! 5 • instruction set 16-bit/32-bit instruction format 83 instructions/6 addressing modes • multiply-accumulate operation built in • 16M bits (2M bytes) • • • • 4K bytes (internal instruction/data cache mode, instructio n cache mode, cache-off mode) cache control internal DRAM control, refresh control power management function (standby mode, CPU sleep mode se lection control) internal D RAM cache memory memory c ontroller programmable I/O port • two programmable I/O ports 4 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER PIN FUNCTION DIAGRAM CLKIN SID BCL BCH BS ST R/W clock PLLCAP PLLVCC PLLVSS bus control RST BURST system control M/S WKUP STBY M32000D4AFP DC HREQ HACK CS address bus A8 - A30 23 INT data bus D0 - D15 16 SBI interrupt input PP0 PP1 programmable I/O port 16 15 VCC VSS 5 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER PIN DESCRIPTION (1/3) type power source clock pin name VCC VSS CLKIN name power source ground clock input I/O – – input function All power source pins should be connected to VCC. All ground pins should be connected to VSS. Clock input pin. The M32000D4AFP has an internal PLL multiplier circuit, and an input clock which is 1/4 of the internal ope rating frequency (when the internal operating frequency is 66.6 MHz , the CLKIN input is 16.65 MHz). Connects a capacitor for the internal PLL. Power source for the internal PLL. Ground for the internal PLL. Internally resets the M32000D4AFP. It is also used to return from standby mode and CPU sleep mode. Sets the M32000D4AFP default operation to either system bus master (M/S = "H") or bus slave (M/S = "L"). When the M32000D4AFP is set to bus slave, it does not carry out a reset vector entry fetch after a reset. _ The setting of M/S cannot be changed during operation. Keep at either an "H" or an "L" level. Input pin to request return from standby mode. _____ This is only accepted when STBY is "L" level. It generates the wakeup interrupt. Indicates that the M32000D4AFP has switched to standby mode. An "L" level is output while the device is in standby mode. The M32000D4AFP has a 24-bit address (A8 to A31) b us for a 1 6 M B a ddress space. A31 is not output. During the write cycle, the valid byte positions on the 16-bit data bus are output ____ ____ as BCH or BCL. During the read cycle, the 16-bit data bus is read, however,only data in the valid byte positions is transferred to the M32000D4AFP. Address bus pins are bidirectional. When accessing the internal DRAM from an external bus master while the M32000D4AFP is in the hold state, input the address from the system bus sid e. 16-bit data bus for connecting to external devices. PLLCAP PLLVCC PLLVSS ____ system control RST _ C connection for PLL power s ource for PLL ground for PLL reset master/slave – – – input input M/S ______ WKUP _____ wakeup input STBY standby output address bus A8 to A30 address bus I/O (Hi-z)* data bus D0 to D15 data bus I/O (Hi-z)* * (Hi-z): This pin goes to high-impedance in the hold state. 6 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER PIN DESCRIPTION (2/3) type bus control pin name SID name space identifier ____ I/O output (Hi-z)* function Space identifier between user space and I/O space. SID = "L": user space SID = "H": I/O space SID = undefined: when idle Indicates the valid byte positions of transferred data. ____ ____ BCH corresponds to the MSB side (D0 to D7), and BCL corresponds ____ to the LSB side (D8 to D15). During a read bus cycle, both BCH ____ and BCL are an "L" level. ____ ____ During a write bus cycle, either BCH and/or BCL is an "L" level depending on the byte(s) to be written. When accessing the internal DRAM from an external bus master, the byte control signal is input from the system bus side. __ When the M32000D4AFP drives an external bus cycle, BS goes to an "L" level at __ start of the bus cycle. the In burst transfer, BS goes to the "L" level for each transf er cycle. When accessing internal__ resources such as an internal DRAM or internal I/O register, BS is not output. Indicates whether the bus cycle that the M32000D4AFP drives is an instruction fetch access cycle or an operand access cycle . ST = "L": for instruction fetch access ST = "H": for operand access ST __ undefined: when idle = Outputs R/W to identify whether the external bus cycle a read or a write cycle. When accessing the internal DRAM from an external __ bus master, R/W is input from the external bus. The M32000D4AFP drives two consecutive bus cycles to access 32-bit data allocated on the 32-bit word boundary. For instruction fetches, it drives 8 (max.) consecutive cycl es (8 cycles in instruction cache mode) to data on the 128-bit boundary. ______ During these consecutive bus cycles, BURST goes to "L" level . When accessing 32-bit data, an "L" level followed by an "H" level is output from address A30, because the MSB-side 16 bits are accessed prior to the LSB-side 16 bits. When accessing 128-bit data, the addresses are output from an arbitrary 16-bit aligned address and wraparound within a 128-bit aligned boundary. ____ BCH, BCL byte control I/O (Hi-z)* __ BS bus start output (Hi-z)* ST bus status output (Hi-z)* __ R/W ______ read/write I/O (Hi-z)* output (Hi-z)* BURST burst * (Hi-z): This pin goes to high-impedance in the hold state. 7 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER PIN DESCRIPTION (3/3) type bus control (cont.) pin name __ name data complete I/O I/O (Hi-z) function When the M32000D4AFP drives an __ external bus cycle, it automatically inserts wait cycles until DC is input by the s lave device in the system bus. When the M32000D4AFP is in the hold state and the internal DRAM is __ accessed from an external bus master, the M32000D4AFP outputs DC to notify to the external bus master that the bus cycle to the internal DRAM has been completed. ______ Bus right request input pin of the system bus. When HREQ is an "L" level, the M32000D4AFP switches to the hold state. Indicates that the M32000D4AFP has switched to the hold state and releases the bus right of the system bus to the requesto r. Signal input to the M32000D4AFP when it is in the hold state to request access to the internal DRAM from an external bus master. __ When an "L"level is input to CS, the M 32000D4AFP access accesses the internal DRAMat the address input via the address pins. System break interrupt input pin. The SBI is not masked by the IE bit in the PSW register. It is also used to return from C PU sleep mode and to request the start of operation in slave mode. External interrupt request input pin. It is also used to return from CPU sleep mode and to request the start of operation the slave mode. Two programmable I/O ports. DC* ______ HREQ _____ hold hold acknowledge chip select input output input HACK __ CS ___ interrupt controller SBI ___ INT system break interrupt external interrupt port __ input input programmable I/O port __ PP0, PP1 I/O * The DC pin becomes an output pin when the CS signal is inp ut to the M32000D4AFP. 8 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION CPU The M32R CPU has 16 general-purpose registers, 5 control registers, an accumulator and a program counter. The accumulator is of 64-bit width. The registers and program counter are of 32-bit width. Control registers There are 5 control registers which are the processor status word register (PSW), the condition bit register (CBR), the interrupt stack pointer (SPI), the user stack pointer (SPU) and the backup PC (BPC). The MVTC and MVFC instructions are used for writing and reading these control registers. General-purpose registers The 16 general-purpose registers (R0 - R15) are of 32-bit width and are used to retain data and base addresses. R14 is used as the link register and R15 as the stack pointer (SPI or SPU). The link register is used to store the return address when executing a subroutine call instruction. The interrupt stack pointer (SPI) and the user stack pointer (SPU) are alternatively represented by R15 depending on the value of the stack mode bit (SM) in the processor status word register (PSW). (see notes) CRn CR0 CR1 CR2 CR3 0 31 PSW CBR SPI SPU processor status word register condition bit register interrupt stack pointer user stack pointer 0 31 0 31 CR6 BPC backup PC R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 (link register) R15 (stack pointer) (see note) Notes 1: CRn (n = 0 - 3, 6) denotes the control register number. 2: The MVTC and MVFC instructions are used for writing and reading these control registers. Fig. 2 Control registers Note: The interrupt stack pointer (SPI) and the user stack pointer (SPU) are alternatively represented by R15 depending on the value of the stack mode bit (SM) in the PSW. Fig. 1 General-purpose registers 9 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Processor status word register: PSW (CR0) The processor status word register (PSW) shows the M32R CPU status. It consists of the current PSW field, and the BPSW field where a copy of the PSW field is saved when EIT occurs. The PSW field is made up of the stack mode bit (SM), the interrupt enable bit (IE) and the condition bit (C). The BPSW field is made up of the backup stack mode bit (BSM), the backup interrupt enable bit (BIE) and the backup condition bit (BC). BPSW field PSW field 0 7 8 15 16 17 23 24 25 31 PSW 0000000000000000 00000 00000 BSM BIE BC SM IE C D 16 17 23 24 25 31 bit name BSM (backup SM) BIE (backup IE) BC (backup C) SM (stack mode) IE (interrupt enable) C (condition bit) function saves value of SM bit when EIT occurs saves value of IE bit when EIT occurs saves value of C bit when EIT occurs 0: uses R15 as the interrupt stack pointer 1: uses R15 as the user stack pointer 0: does not accept interrupt 1: accepts interrupt indicates carry, borrow and overflow resulting from operations (instruction dependent) init. undefined undefined undefined 0 0 0 R W Note: "init." ...initial state immediately after reset "R" .... : read enabled "W" .... : write enabled Fig. 3 Processor status word register 10 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Condition bit register The condition bit register (CBR) is a separate read-only register which contains a copy of the current value of the condition bit (C) in the PSW. An attempt to write to the CBR with the MVTC instruction is ignored. Backup PC The backup PC (BPC) is the register where a copy of the PC value is saved when EIT occurs. Bit 31 is fixed at "0". When EIT occurs, the PC value immediately before EIT occurrence or that of the next instruction is set. The value of the BPC is reloaded to the PC when the RTE instruction is executed. However, the values of the lower 2 bits of the PC become "00" on returning (It always returns to the word boundary). Interrupt stack pointer, User stack pointer The interrupt stack pointer (SPI) and the user stack pointer (SPU) retain the current stack address. The SPI and SPU can be accessed as the general-purpose register R15. R15 switches between representing the SPI and SPU depending on the value of the stack mode bit (SM) in the PSW. 0 31 CBR 0000000000000000000000000000000C 0 31 SPI 0 SPI 31 SPU 0 SPU 31 BPC BPC 0 Fig. 4 Condition bit register, interrupt stack pointer, user stack pointer and backup PC 11 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Accumulator The accumulator (ACC) is a 64-bit register used for DSP type functions. Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The high-order 32 bits (bit 0 - bit 31) can be set with the MVTACHI instruction and the low-order 32 bits (bit 32 - bit 63) can be set with the M VTACLO i nstruction. Use the M VFACHI , MVFACLO and MVFACMI instructions for reading from the accumulator. The high-order 32 bits (bit 0 - bit 31) are read with the MVFACHI instruction, the low order 32 bits (bit 32 - bit 63) with the MVFACLO instruction and the middle 32 bits (bit 16 - bit 47) with the MVFACMI instruction. Program counter The program counter (PC) is a 32-bit counter that retains the address of the instruction being executed. Since the M32R CPU instruction starts with even-numbered addresses, the LSB (bit 31) is always "0". (see note) 0 78 15 16 read range with MVFACMI instruction 31 32 47 48 63 ACC read/write range with MVTACHI or MVFACHI instruction read/write range with MVTACLO or MVFACLO instruction Note: Bits 0 - 7 are always read as the sign-extended value of bit 8. An attempt to write to this area is ignored. Fig. 5 Accumulator 0 31 PC PC 0 Fig. 6 Program counter 12 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Data types Signed and unsigned integers of byte (8 bits), halfword (16 bits), and word (32 bits) types are supported as data in the M32R CPU instruction set. A signed integer is represented in a 2's complement format. Data formats Data size of a register of the M32R CPU is always a word (32 bits). Byte (8 bits) and halfword (16 bits) data in memory are sign-extended (the LDB and LDH instructions) or zero-extended (the LDUB and LDUH instructions) to 32 bits, and loaded into the register. Word (32 bits) data in a register is stored to memory by the ST instruction. Halfword (16 bits) data in the LSB side of a register is stored to memory by the STH instruction. Byte (8 bits) data in the LSB side of a register is stored to memory by the STB instruction. Data stored in memory can be one of these types: byte (8 bits), halfword (16 bits) or word (32 bits). Although the byte data can be located at any address, the halfword data and the word data can only be located on the halfword boundary and the word boundary, respectively. If an attempt is made to access data in memory which is not located on the correct boundary, an address exception occurs. 0 7 signed byte (8-bit) integer S 0 7 unsigned byte (8-bit) integer 0 15 signed halfword (16-bit) integer S 0 15 unsigned halfword (16-bit) integer 0 31 signed word (32-bit) integer S 0 31 unsigned word (32-bit) integer S: sign bit Fig. 7 Data type from memory (LDB , LDUB instruction) 24 31 address +0 0 78 < load > 0 sign-extention ( LDB instruction) or zero-extention ( LDUB instruction) +1 15 16 +2 23 24 +3 31 Rn sign-extention ( LDH instruction) or zero-extention ( LDUH instruction) 0 16 byte from memory ( LDH, LDUH instruction) 31 byte byte byte byte byte from memory ( LD instruction) 0 31 Rn halfword Rn word halfword halfword halfword < store > 0 24 31 word word Rn byte to memory ( STB instruction) 0 16 31 Rn halfword to memory ( STH instruction) 0 31 Rn word to memory ( ST instruction) Fig. 8 Data format 13 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Address space The M32000D4AFP logical address is 32-bit wide and offers 4 GB linear space. The M32000D4AFP has address spaces allocated as shown below. The user space is specified by SID = 0 (H'0000 0000 to H'7FFF FFFF). The area available to the user is 16 MB from address H'0000 0000 to address H'00FF FFFF. The I/O space is specified by SID = 1 (H'8000 0000 to H'FFFF FFFF). The area available to the user is 16 MB from address H’FF00 0000 to address H'FFFF FFFF. The I/O space cannot be cached. These areas below are allocated in each space. • User space internal DRAM area external area • I/O space user I/O area system area internal I/O area < logical space > < physical space > EIT vector entry (except for reset interrupt) logical address SID logical address physical address (24 bits) H'0000 0000 (16M bytes) H'0000 0000 internal DRAM area (2M bytes) 0 : H'00 0000 0 : H'1F FFFF 0 : H'20 0000 H'001F FFFF H'0020 0000 user space (SID = 0) external area (14M bytes) H'00FF FFFF 0 : H'FF FFFF H'7FFF FFFF H'8000 0000 EIT vector entry (reset interrupt) physical address (24 bits) SID logical address H'FF00 0000 user I/O area (8M bytes) I/O space (SID = 1) 1 : H'00 0000 H'FF7F FFFF H'FF80 0000 H'FFBF FFFF H'FFC0 0000 (16M bytes) system area (4M bytes) 1 : H'7F FFFF 1 : H'80 0000 1 : H'BF FFFF 1 : H'C0 0000 internal I/O area (4M bytes) H'FFFF FFFF H'FFFF FFFF 1 : H'FF FFFF Fig. 9 Address space 14 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER The internal DRAM (2 MB) is allocated from address H'0000 0000 to address H'001F FFFF. The EIT vector entry (other than the reset interrupt) is allocated in the address H'0000 0000 to address H'0000 008F of this area. The internal DRAM is connected to the M32R CPU via a 4 KB cache memory with a 128-bit bus. When the M32000D4AFP is in the hold state, the internal DRAM can be accessed from an external bus master by inputting control signals. The external area consists of 14 MB from address H'0020 0000 to address H'00FF FFFF. When this space is accessed, the control signals to access external devices are output. The bottom 16 bytes in this area (H'00FF FFF0 to H'00FF FFFF) are the reset interrupt EIT vector entry. The user I/O area is 8 MB from address H'FF00 0000 to address H'FF7F FFFF. When this space is accessed, the control signals to access external devices are output. The system area is 4 MB from address H'FF80 0000 to address H'FFBF FFFF. This area is reserved for development tools such as in-circuit emulators or debug monitors. The user cannot use this area. The internal I/O area is 4 MB from address H'FFC0 0000 to address H'FFFF FFFF. The memory controller and programmable I/O port registers are allocated in this area. logical address +0 address +1 address +2 address +3 address 0 31 (reserved) H'FFC0 0000 H'FFFF FFE0 H'FFFF FFE4 H'FFFF FFE8 H'FFFF FFEC (reserved) PPCR0 PPCR1 programmable I/O port PPDR0 PPDR1 H'FFFF FFF4 H'FFFF FFF8 H'FFFF FFFC PPCR0: programmable I/O port direction control register 0 PPCR1: programmable I/O port direction control register 1 PPDR0: programmable port data register 0 PPDR1: programmable port data register 1 MLCR MPMR MCCR memory controller MLCR: lock control register MPMR: power management control register MCCR: cache control register Fig. 10 Internal I/O space memory map 15 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER EIT While the CPU is executing a program, sometimes it is necessary to suspend execution, because a certain event occurs, and execute another program. These kinds of events are referred to as EIT (Exception, Interrupt, Trap). • Exception The event is related to the context being executed. It is generated by errors or violations that occur during instruction execution. With the M32000D4AFP, the address exception (AE) and reserved instruction exception (RIE) are of this type. • Interrupt The event is not related to the context being executed. It is generated by an external hardware signal. With the M32000D4AFP, the external interrupt (EI), system break interrupt (SBI), wakeup interrupt (WI) and reset interrupt (RI) are of this type. • Trap This is a software interrupt which is generated by executing the TRAP instruction. It is intentionally added to the program by the programmer, as a system call. EIT Exception Reserved Instruction Exception (RIE) Address Exception (AE) Interrupt Reset Interrupt (RI) Wakeup Interrupt (WI) System Break Interrupt (SBI) External Interrupt (EI) EIT events are shown below. • Reserved instruction exception (RIE) The reserved instruction exception (RIE) occurs when execution of a reserved instruction (unimplemented instruction) is detected. • Address exception (AE) The address exception (AE) occurs if an attempt is made to access an unaligned address with either a load instruction or a store instruction. • Reset interrupt (RI) ___ The reset interrupt (RI) is always accepted when the RST signal is input. It has the highest priority. • Wakeup interrupt (WI) ______ The wakeup interrupt (WI) is accepted when the WKUP signal is input while the M32000D4AFP is in standby mode. It is only used to return from standby mode. • System break interrupt (SBI) ___ The system break interrupt (SBI) is an interrupt request from the SBI pin. It is used when a break in power source or an error from an external watchdog timer is detected. It is also used to return from CPU sleep mode and to start an M32000D4AFP set to slave mode. • External interrupt (EI) ___ The external interrupt (EI) is an interrupt request from the INT pin. It is used by an interrupt from the external peripheral I/O and can be masked by the IE bit in the PSW register. It is also used to return from CPU sleep mode and to start an M32000D4AFP set to slave mode. • Trap The trap (TRAP) is a software interrupt which is generated by executing the TRAP instruction. A total of 16 EIT vector entries are available for operands 0 to 15 of the TRAP instruction. Trap Trap (TRAP) Fig. 11 EIT events 16 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Internal memory system The memory system built into the M32000D4AFP has the following characteristics. • internal 16M-bit (2M-byte) DRAM • internal 4K-byte cache memory • CPU, cache and internal DRAM are connected by a 128-bit bus • selectable cache memory operation mode – internal instruction/data cache mode – instruction cache mode – cache-off mode cache control register (MCCR) < address: H'FFFF FFFF> D24 CP D25 D26 D27 D28 D29 D30 CM0 D31 CM1 When the internal instruction/data cache mode is selected, the cache memory functions as a cache for both instruction and data from the internal DRAM, and caches all bus access to the DRAM. This mode is for a system which uses the internal DRAM as main memory. Transfer between the M32R CPU, cache memory and internal DRAM is always carried out in blocks of 128 bits. Caching is carried out by the direct map method. Writing is by the copy back method. When the M32000D4AFP access destination is an external space, data transfer between the M32R CPU and the external device is carried out via the bus interface unit (BIU). The BIU has a 128-bit data buffer which converts the bus width between the 128-bit bus in the M32000D4AFP and the external bus. Caching is not applicable in this case of data transfer. When accessing the internal DRAM from an external bus master, and a cache hit occurs (the accessed data is inside the cache), data transfer between the cache memory and the external bus via the BIU is carried out. When a cache miss occurs, (the accessed data is not inside the cache) data transfer is carried out between the internal DRAM and the external bus via the BIU without cache replacement. D 24 25 - 29 30, 31 bit name CP (cache purge) Not assigned. CM0, CM1 (cache mode) function 0: no purge 1: p urge D24 D25 D26 D27 D28 D29 D30 D31 LM no access to external bus M/S M/S M32000D4AFP (master) M32000D4AFP (slave) HREQ D 24 - 30 31 bit name Not assigned. LM (lock mode) function D24 D25 D26 D27 D28 D29 D30 PM0 D31 PM1 D 24 - 29 30, 31 bit name Not assigned. PM0, PM1 (low power consumption mode) function D24 D25 D26 D27 D28 D29 D30 D31 PP0C When an "L" level is input to RST, the M32000D4AFP switches to the reset state. The reset state is released when an "H" level is input ____ to RST, and the program is executed from the EIT vector entry of the reset interrupt. All internal resources including the internal PLL (4x clock generator) are initialized. In order to stabilize PLL oscillation, ____ the "L" input to RST should last a minimum of 2 ms after the clock input to CLKIN stabilizes and VCC stabilizes to the specified voltage level. Table 2 Internal state after reset internal resources DRAM cache memory state undefined invalid (purged all) undefined programmable I/O port direction control register 1 (PPCR1) < address: H'FFFF FFE7> D24 D25 D26 D27 D28 D29 D30 D31 PP1C general purpose registers (R0 - R15) control registers PSW (CR0) CBR (CR1) SPI (CR2) SPU (CR3) BPC (CR6) PC B'0000 0000 0000 0000 ??00 000? 0000 0000 D 24 - 30 31 bit name Not assigned. PP0C, PP1C (port I/O direction) function function R W  0 0: data = "0" 1: data = "1" R = ... read enabled W =  : write disabled R = 0 ... "0" when reading W= ... write enabled Fig. 31 Programmable I/O port data register 28 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Clock generating circuit The M32000D4AFP has a clock multiplier circuit and operates at four times the input frequency. The internal operation frequency becomes 66.6 MHz when a 16.65 MHz clock is input to CLKIN. A capacitor (C) should be connected to the PLLCAP pin, and the clock is input to the CLKIN pin. The PLLVCC and PLLVSS pins should be connected to the power source or the ground, respectively. ADDRESSING MODE M32R family supports the following addressing modes. < register direct > The general-purpose register or the control register to be processed is specified. < register indirect > The contents of the register specify the address in memory to be accessed. This mode can be used by all load/store instructions. < register relative indirect > (The contents of the register) + (16-bit immediate value which is signextended to 32 bits) specify the address in memory to be accessed. < register indirect and register update > • 4 is added to the register contents (the contents of the register before update specify the address in memory to be accessed) [LD instruction] • 4 is added to the register contents (the contents of the register after update specify the address in memory to be accessed) [ST instruction] • 4 is subtracted from the register contents (the contents of the register after update specify the address in memory to be accessed) [ST instruction] < immediate > The 4-, 5-, 8-, 16- or 24-bit immediate value. < PC relative > (The contents of PC) + (8, 16, or 24-bit displacement which is signextended to 32 bits and 2 bits left-shifted) specify the address in memory to be accessed. M32000D4AFP VCC 14 (PLLVCC) 18 (CLKIN) clock input PLL clock generating circuit 16 (PLLCAP) 15 (PLLVSS) C recommended values in circuit C: 1000 pF Fig. 32 Oscillation circuit 29 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER INSTRUCTION FORMAT There are two major instruction formats: two 16-bit instructions packed together within a word boundary, and a single 32-bit instruction. INSTRUCTION SET A total of 83 instructions are implemented. The load/store instructions carry out data transfers between a register and a memory. LD Load LDB Load byte LDUB Load unsigned byte LDH Load halfword LDUH Load unsigned halfword LOCK Load locked ST Store STB Store byte STH Store halfword UNLOCK Store unlocked The transfer instructions carry out data transfers between registers or a register and an immediate value. LD24 Load 24-bit immediate LDI Load immediate MV Move register MVFC Move from control register MVTC Move to control register SETH Set high-order 16-bit Compare, arithmetic/logic operation, multiply and divide, and shift are carried out between registers. • compare instructions CMP Compare CMPI Compare immediate CMPU Compare unsigned CMPUI Compare unsigned immediate • arithmetic operation instructions ADD Add ADD3 Add 3-operand ADDI Add immediate ADDV Add with overflow checking ADDV3 Add 3-operand ADDX Add with carry NEG Negate SUB Subtract SUBV Subtract with overflow checking SUBX Subtract with borrow < 16-bit instruction > op1 R1 op2 R2 R1 = R1 op R 2 op1 R1 c R1 = R1 op c op1 cond c Branch (Short Displacement) < 32-bit instruction > op1 R1 op2 R2 c R1 = R2 op c op1 R1 op2 R2 c Compare and Branch op1 R1 c R1 = R1 op c op1 cond c Branch Fig. 33 Instruction format 30 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER • logic operation instructions AND AND AND3 AND 3-operand NOT Logical NOT OR OR OR3 OR 3-operand XOR Exclusive OR XOR3 Exclusive OR 3-operand • multiply/divide instructions DIV Divide DIVU Divide unsigned MUL Multiply REM Remainder REMU Remainder unsigned • shift instructions SLL Shift left logical SLL3 Shift left logical 3-operand SLLI Shift left logical immediate SRA Shift right arithmetic SRA3 Shift right arithmetic 3-operand SRAI Shift right arithmetic immediate SRL Shift right logical SRL3 Shift right logical 3-operand SRLI Shift right logical immediate The branch instructions are used to change the program flow. BC Branch on C-bit BEQ Branch on equal BEQZ Branch on equal zero BGEZ Branch on greater than or equal zero BGTZ Branch on greater than zero BL Branch and link BLEZ Branch on less than or equal zero BLTZ Branch on less than zero BNC Branch on not C-bit BNE Branch on not equal BNEZ Branch on not equal zero BRA Branch JL Jump and link JMP Jump NOP No operation The EIT-related instructions carry out the EIT events (Exception, Interrupt and Trap). Trap initiation and return from EIT are EIT-related instructions. TRAP Trap RTE Return from EIT The DSP function instructions carry out multiplication of 32 bits ! 16 bits and 16 bits ! 16 bits or multiply and add operation; there are also instructions to round off data in the accumulator and carry out transfer of data between the accumulator and a general-purpose register. MACHI Multiply-accumulate high-order halfwords MACLO Multiply-accumulate low-order halfwords MACWHI Multiply-accumulate word and high-order halfword MACWLO Multiply-accumulate word and low-order halfword MULHI Multiply high-order halfwords MULLO Multiply low-order halfwords MULWHI Multiply word and high-order halfword MULWLO Multiply word and low-order halfword MVFACHI Move from accumulator high-order word MVFACLO Move from accumulator low-order word MVFACMI Move from accumulator middle-order word MVTACHI Move to accumulator high-order word MVTACLO Move to accumulator low-order word RAC Round accumulator RACH Round accumulator halfword 31 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER ABSOLUTE MAXIMUM RATINGS Ratings Symbol VCC VI VO PD TOPR TSTG Power source voltage Input voltage Output voltage Power consumption Operating temperature Storage temperature TOPR = 25 °C 0 –65 Parameter Conditions Min. –0.5 –0.5 –0.5 Max. 4.6 4.6 4.6 1000 70 150 Unit V V V mW °C °C RECOMMENDED OPERATING CONDITIONS (VCC = 3.3 V ± 0.3 V, TOPR = 0 to 70 °C unless otherwise noted) Symbol VCC VIH VIL Power source voltage “H” input voltage “L” input voltage All inputs except following ____ Parameter Ratings Min. 3.0 2.0 0.8VCC –0.3 –0.3 Typ. Max. 3.6 VCC+0.3 VCC+0.3 0.8 0.2VCC 2 2 50 Unit V V V V V mA mA pF RST pin All inputs except following ____ RST pin IOH (see note) “H” output current IOL (see note) “L” output current CL output load capacity Note: IOH and IOL represent the maximum values of DC current load. Intermittent current that is generated during output need not to be considered as long as the output load capacity is within the specified range. 32 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER DC CHARACTERISTICS ELECTRICAL CHARACTERISTICS (VCC = 3.3 V ± 0.3 V, TOPR = 0 to 70 °C unless otherwise noted) Symbol VOH VOL IOZ IIH IIL ICC Parameter “H” output voltage “L” output voltage Output current in off state “H” input current “L” input current Power source current Test conditions IOH = –2 mA IOL = 2 mA VO = 0 to VCC VIH = 0 to VCC +0.3 V VIH = 0 to VCC +0.3 V Average in normal operation mode VCC = 3.3 V Average in CPU sleep mode VCC = 3.3 V Average in standby mode VCC = 3.3 V All pins 140 100 –10.0 Ratings Min. 2.4 0.4 10.0 10.0 –10.0 220 170 2000 15 Typ. Max. Unit V V µA µA µA mA mA µA pF C Pin capacitance 33 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER AC CHARACTERISTICS TIMING REQUIREMENTS (VCC = 3.3 ± 0.3 V, CL = 50 pF, TOPR = 0 to 70 °C unless otherwise noted) (1) Input transition time Symbol tr(INPUT) tf(INPUT) Parameter Input rise transition time Input fall transition time ____ Test conditions CMOS input RST pin CMOS input ____ Limits Min. Max. 5 2 5 2 Unit ns ms ns ms Reference number 1 2 RST pin (2) Clock, reset and wakeup timing Symbol tc(CLKIN) tw(CLKINH) tw(CLKINL) tr(CLKIN) tf(CLKIN) tw(RST) tw(WKUP) Parameter Clock input cycle time External clock input “H” pulse width External clock input “L” pulse width External clock input rising time External clock input falling time Reset input “L” pulse width Wakeup input “L” pulse width 2 2 Test conditions Limits Min. 60 1/4CLKIN 1/4CLKIN 5 5 Max. 100 Unit ns ns ns ns ns ms ms Reference number 5 6 7 8 9 10 11 (3) Read and write timing Symbol tsu(D-CLKIN) th(CLKIN-D) th(CLKIN-DCH) tsu(DCL-CLKIN) th(CLKIN-DCL) Parameter Data input set-up time before CLKIN Data input hold time after CLKIN __ __ Test conditions Min. 5.5 2 10 2 10 2 Limits Max. Unit ns ns ns ns ns ns Reference number 30 31 36 37 38 39 tsu(DCH-CLKIN) DC input “H” set-up time before CLKIN DC input “H” hold time after CLKIN __ DC input “L” set-up time before CLKIN __ DC input “L” hold time after CLKIN 34 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER (4) Arbitration and external bus master read/write timing Symbol _____ _____ Parameter Test conditions Limits Min. 5 2 7 2 5 3 5 3 Max. Unit ns ns ns ns ns ns ns ns Reference number 40 41 48 49 50 51 52 53 tsu(HREQ-CLKIN) HREQ input set-up time before CLKIN th(CLKIN-HREQ) tsu(CS-CLKIN) th(CLKIN-CS) tsu(A-CLKIN) th(CLKIN-A) tsu(D-CLKINL) th(CLKINL-D) HREQ input hold time after CLKIN __ CS input set-up time before CLKIN __ CS input hold time after CLKIN Address input set-up time before CLKIN Address input hold time after CLKIN Data input set-up time before CLKIN Data input hold time after CLKIN (5) Interrupt control unit timing Symbol ___ Parameter INT input pulse width (see note) ___ ___ Test conditions Limits Min. tc(CLKIN) tc(CLKIN) Max. Unit ns ns Reference number 63 64 tw(INT) tw(SBI) SBI input pulse width (see note) ___ Note: B oth INT and SBI are level-sense inputs. Keep them at an " L" level until the interrupt is accepted. (6) I/O port timing Symbol tw(PORTINL) tw(PORTINH) Parameter Port input “L” pulse width Port input “H” pulse width Test conditions Limits Min. 30 30 Max. Unit ns ns Reference number 69 70 35 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER SWITCHING CHARACTERISTICS (VCC = 3.3 ± 0.3 V, CL = 50 pF, TOPR = 0 to 70 °C unless otherwise noted) (1) Output transition time Symbol tr(OUTPUT) tf(OUTPUT) Parameter Output rising transition time Output falling transition time Test conditions Limits Min. Typ. Max. 8 8 Unit ns ns Reference number 3 4 (2) Read and write timing Test Symbol __ Limits Min. 0 12 tc(CLKIN)/4 tc(CLKIN)/4+8 16 0 16 0 16 0 16 0 16 0 0 12 0 12 0 18 0 16 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter BS = “H” effective time after CLKIN __ conditions Reference number 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 32 33 34 35 td(CLKIN-BSHX) td(CLKIN-BSL) td(CLKIN-BSLX) td(CLKIN-BSH) td(CLKIN-AV) td(CLKIN-AX) td(CLKIN-BCV) td(CLKIN-BCX) td(CLKIN-SIDV) td(CLKIN-SIDX) td(CLKIN-STV) td(CLKIN-STX) td(CLKIN-RWV) td(CLKIN-RWX) BS = “L” delay time after CLKIN __ BS = “L” effective time after CLKIN __ BS = “H” delay time after CLKIN Address delay time after CLKIN Address effective time after CLKIN ____ ____ ___ ___ BCH, BCL delay time after CLKIN BCH, BCL effective time after CLKIN SID delay time after CLKIN SID effective time after CLKIN ST delay time after CLKIN ST effective time after CLKIN __ R/W delay time after CLKIN __ R/W effective time after CLKIN ______ td(CLKIN-BURSTHX) BURST = “H” effective time after CLKIN ______ td(CLKIN-BURSTL) BURST = “L” delay time after CLKIN ______ td(CLKIN-BURSTLX) td(CLKIN-BURSTH) td(CLKIN-DZX) td(CLKIN-DV) td(CLKIN-DVX) td(CLKIN-DXZ) BURST = “L” effective time after CLKIN ______ BURST = “H” delay time after CLKIN Data output enable time after CLKIN Data output delay time after CLKIN Data output effective time after CLKIN Data output disable time after CLKIN 36 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER (3) Arbitration and external bus master read/write timing Symbol _____ Parameter HACK = “H” effective time after CLKIN _____ Test conditions Min. 0 0 Limits Max. 12 12 16 0 0 18 16 0 0 0 16 16 0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Reference number 42 43 44 45 46 47 54 55 56 57 58 59 60 61 62 td(CLKIN-HACKHX) td(CLKIN-HACKL) td(CLKIN-HACKLX) td(CLKIN-HACKH) td(CLKIN-AZ) td(CLKIN-AZX) td(CLKIN-DZX) td(CLKIN-DV) td(CLKIN-DXZ) td(CLKIN-DVX) td(CS-DCZX) td(CLKIN-DCHX) td(CLKIN-DCL) td(CLKIN-DCXZ) td(CLKIN-DCLX) HACK = “L” delay time after CLKIN _____ HACK = “L” effective time after CLKIN _____ HACK = “H” delay time after CLKIN Address output disable time after CLKIN Address output enable time after CLKIN Data output enable time after CLKIN Data output delay time after CLKIN Data output disable time after CLKIN Data output effective time after CLKIN __ __ __ DC output enable time after CS DC = “H” effective time after CLKIN __ DC = “L” delay time after CLKIN __ DC output disable time after CLKIN __ DC = “L” effective time after CLKIN (4) Standby timing Symbol _____ Parameter STBY = “H” effective time after CLKIN _____ Test conditions Limits Min. 0 tc(CLKIN)n/4+15 0 tc(CLKIN)n/4+15 Max. Unit ns ns ns ns Reference number 65 66 67 68 td(CLKIN-STBYHX) td(CLKIN-STBYL) td(CLKIN-STBYLX) td(CLKIN-STBYH) _____ STBY = “L” delay time after CLKIN (see note) _____ STBY = “L” effective time after CLKIN _____ STBY = “H” delay time after CLKIN (see note) Note: The STBY signal is synchronized with the internal clock, therefore its timing changes at 0, 90, 180 and 270 (n=0, 1, 2, 3) degree phase of CLKIN. (5) I/O port timing Symbol tw(PORTOUTL) tw(PORTOUTH) Parameter Port output “L” pulse width (see note) Port output “H” pulse width (see note) Test conditions Limits Min. 12 12 Max. Unit ns ns Reference number 71 72 Note: The minimum pulse width value is that where the output is changed within 1 clock of the internal clock. Software processing time to write to the port data register is not included. 37 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 0.5VCC 1.0 k Ω measured pin measured pin CL = 50 pF CL = 50 pF CMOS output CMOS output (during floating delay time measurement) Fig. 34 Output switching characteristic measurement circuit timing reference point (when not specified) CMOS input "H" input level "L" input level 0.9VCC 0.1VCC 0.8VCC 0.2VCC schmitt trigger input "H" input level "L" input level VCC 0.0 V 0.9VCC 0.1VCC CLKIN input "H" input level "L" input level VCC 0.0 V Fig. 35 Input waveform and timing reference point during characteristic measurement timing reference point CMOS output (when not specified) 0.8VCC 0.2VCC "H" → "Z" "Z" → "H" CMOS output (during floating delay time measurement) "L" → "Z" 0.9VCC 0.1VCC "Z" → "L" 0.6VCC 0.4VCC Fig. 36 Output timing measurement point during characteristic measurement 38 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 1 tr(INPUT) 2 tf(INPUT) CMOS input (except for schmitt trigger input and CLKIN input) 0.8VCC 0.2VCC 1 tr(INPUT) schmitt trigger input (RST) 2 tf(INPUT) 0.9VCC 0.1VCC Fig. 37 Input transition time 3 tr(OUTPUT) 4 tf(OUTPUT) output pin 0.8VCC 0.2VCC Fig. 38 Output transition time 5 tc(CLKIN) 6 7 tw(CLKINH) tw(CLKINL) CLKIN (input) 0.5VCC 8 tr(CLKIN) 9 tf(CLKIN) 0.8VCC 0.2VCC *1 10 tw(RST) RST (input) *1 11 tw(WKUP) WKUP (input) *1 The WKUP and RST signals can be input asynchronously. When returning from standby mode, the same timing applies. Fig. 39 Clock reset and wakeup timing 39 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 0.5 VCC 0.5 VCC CLKIN (input) 12 td(CLKIN-BSHX) 13 td(CLKIN-BSL) 14 td(CLKIN-BSLX) *2 *2 15 td(CLKIN-BSH) BS (output) 16 td(CLKIN-AV) 17 td(CLKIN-AX) A8 to A30 (output) 18 td(CLKIN-BCV) 19 td(CLKIN-BCX) BCH, BCL (output) 20 td(CLKIN-SIDV) 22 td(CLKIN-STV) 21 td(CLKIN-SIDX) 23 td(CLKIN-STX) SID, ST (output) 24 td(CLKIN-RWV) 25 td(CLKIN-RWX) R/W (output) *2 26 td(CLKIN-BURSTHX) 27 td(CLKIN-BURSTL) *2 28 td(CLKIN-BURSTLX)*2 29 td(CLKIN-BURSTH) *2 BURST (output) 30 tsu(D-CLKIN) 31 th(CLKIN-D) D0 to D15 (input) 32 td(CLKIN-DZX) 33 td(CLKIN-DV) 34 td(CLKIN-DVX) 35 td(CLKIN-DXZ) D0 to D15 (output) *1 37 th(CLKIN-DCH) 38 tsu(DCL-CLKIN) *1 36 tsu(DCH-CLKIN) 39 th(CLKIN-DCL) DC (input) *1 The set up/hold of DC = "H" may vary depending on the wait cycle insertion. *2 All switching characteristics and timing requirements based on the falling edge of CLKIN are calculated according to the internal CLKIN (duty ratio is 50%) . When designing external peripheral circuits, the correction for the duty cycle of the actual CLKIN is necessary. [example] BS signal transition ("L" –> "H") when inputting 16.65 MHz clock whose duty ratio is 45 - 55% (± 5%) to CLKIN: • minimum value of td(CLKIN-BSLX) = (value in table) – (correction value) = 15 – (60 x 5/100) = 12 [ns] • maximum value of td(CLKIN-BSH) = (value in table) + (correction value) = (60/4 + 8) + (60 x 5/100) = 26 [ns] Fig. 40 Read/write timing 40 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 0.5VCC (input) 0.5VCC CLKIN *1 40 tsu(HREQ-CLKIN) *1 41 th(CLKIN-HREQ) HREQ (input) *2 42 td(CLKIN-HACKHX) 43 td(CLKIN-HACKL)*2 *2 44 td(CLKIN-HACKLX) *2 45 td(CLKIN-HACKH) HACK (output) 46 td(CLKIN-AZ) 47 td(CLKIN-AZX) A8 to A30, SID, ST, BS, BCH, BCL, (output) R/W, BURST *1 The HREQ signal can be input asynchronously. *2 All switching characteristics and timing requirements based on the falling edge of CLKIN are calculated according to the internal CLKIN (duty ratio is 50%) . When designing external peripheral circuits, the correction for the duty cycle of the actual CLKIN is necessary. [example] HACK signal transition ("H" –> "L") when inputting 16.65 MHz clock whose duty ratio is 45 - 55% (± 5%) to CLKIN: • minimum value of td(CLKIN-HACKHX) = (value in table) – (correction value) = 0 – (60 x 5/100) = –3 [ns] • maximum value of td(CLKIN-HACKL) = (value in table) + (correction value) = 12 + (60 x 5/100) = 15 [ns] Fig. 41 Bus arbitration timing 41 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 0.5 VCC CLKIN (input) 40 tsu(HREQ-CLKIN) *1 41 th(CLKIN-HREQ) *1 HREQ (input) 42 td(CLKIN-HACKHX) 43 td(CLKIN-HACKL) *1 *1 *1 44 td(CLKIN-HACKLX) 45 td(CLKIN-HACKH) *1 HACK (output) *1 48 tsu(CS-CLKIN) *1 49 th(CLKIN-CS) 48 49 48 49 CS (input) 50 tsu(A-CLKIN) *1 51 th(CLKIN-A) *1 50 51 R/W (input) 50 51 50 51 A8 to A30 BCH, BCL (input) *1 *1 52 tsu(D-CLKINL) 53 th(CLKINL-D) D0 to D15 (input) *1 54 td(CLKIN-DZX) 55 td(CLKIN-DV) *1 56 td(CLKIN-DXZ) *1 57 td(CLKIN-DVX)*1 D0 to D15 (output) *1 59 td(CLKIN-DCHX) *1 60 td(CLKIN-DCL) 58 td(CS-DCZX) 58 61 td(CLKIN-DCXZ)*1 62 td(CLKIN-DCLX)*1 59 60 61 62 *1 DC (output) *1 All switching characteristics and timing requirements based on the falling edge of CLKIN are calculated according to the internal CLKIN (duty ratio is 50%) . When designing external peripheral circuits, the correction for the duty cycle of the actual CLKIN is necessary. [example] CS signal transition ("L" –> "H") when inputting 16.65 MHz clock whose duty ratio is 45 - 55% (± 5%) to CLKIN: • minimum value of tsu(CS-CLKIN) = (value in table) + (correction value) = 10 + (60 x 5/100) = 13 [ns] • minimum value of th(CLKIN-CS) = (value in table) + (correction value) = 2 + (60 x 5/100) = 5 [ns] Fig. 42 External bus master read/write timing 42 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 63 tw(INT) *1 INT (input) 64 tw(SBI) *1 SBI (input) *1 The INT and SBI signals can be input asynchronously. When returning from CPU sleep mode, the same timing applies. This timing value is "a value necessary for sampling the input to pins", however, not "a value that guarantees the interrupt acceptance". The interrupt request is a level-sensed input , and should be kept "L" until it is accepted. Fig. 43 Interrupt input timing CLKIN (input) internal clock (66.6 MHz) 65 td(CLKIN-STBYHX) 66 td(CLKIN-STBYL) *1 *2 67 td(CLKIN-STBYLX) 68 td(CLKIN-STBYH) *1 *3 STBY (output) *1 The STBY signal is synchronized with the internal clock therefore, its timing changes at 0, 90, 180 and 270 degree phase of CLKIN. *2 The STBY goes to an "L" level when switched to the standby mode. *3 When returning from standby mode, the STBY signal goes to an "H" level 1 CLKIN after sampling that WKUP has returned from "L" to "H", or 3 CLKINs after sampling that RST = "L". Fig. 44 Standby timing [for input] 69 tw(PORTINL) 70 tw(PORTINH) PX [for output] 71 tw(PORTOUTL) 72 tw(PORTOUTH) PX Fig. 45 I/O port timing 43 MITSUBISHI MICROCOMPUTERS M32000D4AFP SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making y our circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. N otes regarding these materials • • • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product b est suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products a t the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a pro duct contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these m aterials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a licen se from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is pro hibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. • • • • © 1998 MITSUBISHI ELECTRIC CORP. Revised edition, effective May. 1998 Specifications subject to change without notice. REVISION DESCRIPTION LIST Rev. No. 1.0 1.1 First Edition __ M32000D4AFP DATA SHEET Revision Description Rev. date 970901 980501 • "After DC outputs an ~ CLKIN falling edge." revised (line 18, page 24). • Notes in Figure 23 revised (page 24). __ • "After DC outputs an ~ CLKIN falling edge." revised (line 19, page 25). • Notes in Figure 24 revised (page 25). • Table 2 revised (page 28). • (3) Arbitration and external bus master read/write timing Symbol Parameter ~ ~ __ __ ~ corrected (page 37). td(CS-DCZX) DC output enable time after CS •" 58 td(CS-DCZX) *1 " in Fig. 42 corrected (page 42). • Notes in Figure 44 revised (page 43). 1.2 • Figure 23 revised (page 24). 980911 (1/1)