M32171F2VFP

2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Description 32171 Group is a 32-bit, single-chip RISC microcomputer with built-in flash memory, which was developed for use in general industrial and household equipment. To make full use of microcomputer built-in mass volume flash memory, this microcomputer contains a variety of peripheral functions ranging from two independent blocks of 16-channel A-D converters to 37-channel multifunction timers, 10-channel DMAs, 3-channel serial I/Os, and 1-channel real time debugger. Also included 1-channel Full-CAN modules and JTAG (boundary scan facility). With lower power consumption and low noise characteristics also considered, these microcomputers are ideal for embedded equipment applications. Real-time Debugger • Includes dedicated clock-synchronized serial I/O that can read and write the contents of the internalRAM independently of the CPU. • Can look up and update the data table in real time while the program is running. • Can generate a dedicated interrupt based on RTD communication. Abundant internal peripheral functions In addition to the timers and real-time debugger, the microcomputer contains the following peripheral functions. • DMAC ............................................................ 10 channels • A-D converter .................... 10-bit converter × 16 channels • Serial I/O ........................................................... 3 channels • Interrupt controller ......... 22 interrupt sources, 8 priority levels • Wait controller • Full CAN ............................................................ 1 channel • JTAG (Boundary scan function, Mitsubishi original) Features M32R RISC CPU core • Uses the M32R family RISC CPU core (Instruction set common to all microcomputers in the M32R family) • Five-stage pipelined processing • Sixteen 32-bit general-purpose registers • 16-bit/32-bit instructions implemented • DSP function instructions (sum-of-products calculation using 56-bit accumulator) • Built-in flash memory • Built-in flash programming boot program • Built-in RAM • PLL clock generating circuit .............. Built-in × 4 PLL circuit • Maximum operating frequency of the CPU clock 40MHz(when operating at -40 to +85oC) 32MHz(when operating at -40 to +125oC) Table 1 Type Name List (32171 Group) Type Name M32171F4VFP M32171F3VFP M32171F2VFP RAM Size 16K bytes 16K bytes 16K bytes ROM Size 512K bytes 384K bytes 256K bytes Designed to operate at high temperatures To meet the need for use at high temperatures, the microcomputer is designed to be able to operate in the temperature range of -40 to +125oC when CPU clock operating frequency = 32 MHz. When CPU clock operating frequency = 40 MHz, the microcomputer can be used in the temperature range of -40 to +85oC. Note: This does not guarantee continuous operation at 125oC. If you are considering use of the microcom puter at 125oC, please consult Mitsubishi. Applications Automobile equipment control (e.g., Engine, ABS, AT), industrial equipment system control, and high-function OA equipment (e.g., PPC) 37-channel multijunction timers (MJT) Multifunction timers are incorporated that support various purposes of use. 16-bit output related timers ....................................... 35ch 16-bit input/output related timers .............................. 10ch 16-bit input related timers ........................................... 8ch 32-bit input related timers ........................................... 8ch • Flexible configuration is possible through interconnection of timers. • The internal DMAC and A-D converter can be started by a timer. 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Pin Assignment(top view) VDD P102/TO10 P101/TO9 P100/TO8 P117/TO7 P116/TO6 P115/TO5 P114/TO4 P113/TO3 P112/TO2 P111/TO1 P110/TO0 VSS VCCE FP MOD1 MOD0 RESET P97/TO20 P96/TO19 P95/TO18 P94/TO17 P93/TO16 P77/RTDCLK P76/RTDACK P75/RTDRXD P74/RTDTXD P73/ HACK P72/ HREQ P71/ WAIT P70/BCLK / WR P64/ SBI P63 P62 P61 FVCC JTMS JTCK JTR ST JTDO JTDI P103/TO11 P104/TO12 P105/TO13 P106/TO14 P107/TO15 P124/TCLK0 P125/TCLK1 P126/TCLK2 P127/TCLK3 VCCI P130/TIN16 P131/TIN17 P132/TIN18 P133/TIN19 P134/TIN20 P135/TIN21 P136/TIN22 P137/TIN23 VCCE P150 /TIN0 P153 /TIN3 P41/ BLW / BLE P42/ BHW / BHE VCCI VSS P43/ RD P44/ CS0 P45/ CS1 P46/A13 P47/A14 P220/CTX 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 M32171F4VFP M32171F3VFP M32171F2VFP 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 VSS P87/SCLKI1/SCLKO1 P86/RXD1 P85/TXD1 P84/SCLKI0/SCLKO0 P83/RXD0 P82/TXD0 VCCE P175/RXD2 P174/TXD2 VSS VCCI AVSS0 AD0IN15 AD0IN14 AD0IN13 AD0IN12 AD0IN11 AD0IN10 AD0IN9 AD0IN8 AD0IN7 AD0IN6 AD0IN5 AD0IN4 AD0IN3 AD0IN2 AD0IN1 AD0IN0 AVCC0 VREF0 P17/DB15 P16/DB14 P15/DB13 P14/DB12 P13/DB11 P221/CRX P225/A12 OSC-VSS XIN XOUT OSC-VCC VCNT Package 144P6Q-A Figure 1 Pin Layout Diagram of the M32171 2 P12/DB10 P30/A15 P31/A16 P32/A17 P33/A18 P34/A19 P35/A20 P36/A21 P37/A22 P20/A23 P21/A24 P22/A25 P23/A26 VCCE VSS P24/A27 P25/A28 P26/A29 P27/A30 P00/DB0 P01/DB1 P02/DB2 P03/DB3 P04/DB4 P05/DB5 P06/DB6 P07/DB7 P10/DB8 P11/DB9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 32171 Internal bus interface DMAC (10 channels) M32R CPU core (max 40MHz) Multiplieraccumulator (32 × 16 + 56) Multijunction timer (MJT : 37 channels) Internal 16-bit bus Internal flash memory (M32171F4VFP : 512KB) (M32171F3VFP : 384KB) (M32171F2VFP : 256KB) Internal 32-bit bus A-D converter (10-bit, 16 channels) Serial I/O (3 channels) Interrupt controller (22 sources, 8 levels) Internal RAM (16KB ) Wait controller Full CAN (1 channel) Real-time debugger (RTD) PLL clock generation circuit External bus interface Address Data Input/output port(JTAG) 97 lines Figure 2 Block diagram 3 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 2 Outline Performance (1/2) Functional Block M32R CPU core Features M32R family CPU core, internally configured in 32 bits Built-in multiplier-accumulator (32 × 16 + 56) Basic bus cycle : 25 ns (CPU clock frequency at 40 MHz, Internal peripheral clock frequency at 20 MHz) Logical address space : 4G bytes, linear General-purpose register : 32-bit register × 16, Control register: 32-bit register × 5 accumulator : 56 bits External data bus Instruction set 16 bits data bus 16-bit/32-bit instruction formats 83 instructions/ 9 addressing modes Internal flash memory M32171F4VFP : 512K bytes M32171F3VFP : 384K bytes M32171F2VFP : 256K bytes Rewrite durability : 100 times Internal RAM DMAC 16K bytes 10 channels (DMA transfers between internal peripheral I/Os, between internal peripheral I/O and internal RAM, and between internal RAMs) Channels can be cascaded and can operate in combination with internal peripheral I/O Multijunction timer 37 channels of multijunction timers • 16-bit output-related timers × 11 channels (single-shot, delayed single-shot) • 16-bit input/output-related timers × 10 channels (event count mode, single-shot, PWM, measurement) • 16-bit input-related timers × 8 channels (measurement, event count mode) • 32-bit input-related timers × 8 channels (measurement) Flexible timer configuration is possible through interconnection of channels using the event bus. A-D converter 10-bit multifunction A-D converters • Input 16 channels • Scan-based conversion can be switched with 4, 8, and 16 • Capable of interrupt conversion during scan • 8-bit/10-bit readout function available Serial I/O 3 channels (The serial I/Os can be set for synchronous serial I/O or UART. SIO2 is UART mode only) Real-time debugger (RTD) 1-channels dedicated clock-synchronized serial • The entire internal RAM can be read or rewritten from the outside without CPU intervention Interrupt controller Controls interrupts from internal peripheral I/Os (Priority can be set to one of 8 levels including interrupt disabled) Wait controller Controls wait when accessing external extended area (1 to 4 wait cycles inserted + prolonged by external WAIT signal input) CAN JTAG 16-channels message slots Boundary-Scan function 4 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 1 Outline Performance (2/2) Function Block Clock Features Maximum internal CPU memory clock : 40MHz (access to CPU, internal ROM, andinternal RAM) Maximum internal peripheral clock : 20MHz (access to internal peripheral module) Maximum external input clock : 10.0MHz, Built-in multiply-by-4 PLL circuit Power Supply Voltage External I/O : 5V (±0.5V) or 3.3V (±0.3V) Internal logic : 3.3V (±0.3V) Operating temperature rang -40 to +125° C (CPU memory clock 32MHz , internal peripheral clock 16MHz) -40 to +85° C (CPU memory clock 40MHz , internal peripheral clock 20MHz) Package 0.5mm pitches / 144-pin plastic LQFP 5 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Outline of the CPU core The M32171 Group uses the M32R RISC CPU core, and has an instruction set which is common to all microcomputers in the M32R family. Instructions are processed in five pipelined stages consisting of instruction fetch, decode, execution, memory access, and write back. Thanks to its “out-of-order-completion” mechanism, the M32R CPU allows for clock cycle efficient, instruction execution control. The M32R CPU internally has sixteen 32-bit general-purpose registers. The instruction set consists of 83 discrete instructions, which come in either a 16-bit instruction or a 32-bit instruction format. Use of the 16-bit instruction format helps to reduce the code size of a program. Also, the availability of 32bit instructions facilitates programming and increases the performance at the same clock speed, as compared to architectures with segmented address spaces. Address space The M32171 Group’s logical addresses are always handled in 32 bits, providing 4 Gbytes of linear address space. The M32171 Group’s address space consists of the following. User space A 2-Gbyte area from H’0000 0000 to H’7FFF FFFF is the user space. Located in this space are the user ROM area, external extended area, internal RAM area, and SFR (Special Function Register) area (internal peripheral I/O registers). Of these, the user ROM area and external extended area are located differently depending on mode settings. Boot program space A 1-Gbyte area from H’8000 0000 to H’BFFF FFFF is the boot program area. This space contains the on-board programming program (boot program) used in blank state by the internal flash memory. Sum-of-products instructions comparable to DSP The M32R CPU contains a multiplier/accumulator that can execute 32 bits × 16 bits in one cycle. Therefore, it executes a 32 bit × 32 bit integer multiplication instruction in three cycles. Also, the M32R CPU supports the following four sum-of-products instructions (or multiplication instructions) for DSP function use. (1) 16 high-order register bits × 16 high-order register bits (2) 16 low-order register bits × 16 low-order register bits (3) All 32 register bits × 16 high-order register bits (4) All 32 register bits × 16 low-order register bits Furthermore, the M32R CPU has instructions for rounding the value stored in the accumulator to 16 or 32 bits, and instructions for shifting the accumulator value to adjust digits before storing in a register. Because these instructions also can be executed in one cycle, DSP comparable data processing capability can be obtained by using them in combination with high-speed data transfer instructions such as Load & Address Update or Store & Address Update. System space A 1-Gbyte area from H’C000 0000 to H’FFFF FFFF is the system area. This space is reserved for use by development tools such as an in-circuit emulator and debug monitor, and cannot be used by the user. Three operation modes The M32170 and M32174 Group has three operation modes: single-chip mode, external extended mode, and processor mode. These operation modes are changed from one to another by setting the MOD0 and MOD1 pins. 6 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Clock XOUT VCNT OSC-VCC OSC-VSS 3.3V (Note) XIN P45 / CS1 P44 / CS0 P43 / RD P42 / BHW / BHE P41 / BLW / BLE P71 / WAIT P72 / HREQ P73 / HACK Port 7 Bus control Port 4 Port 7 P70 / BCLK / WR Reset RESET 19 M32171F4VFP, M32171F3VFP, M32171F2VFP MOD0 Mode MOD1 FP P220 / CTX P221 / CRX 10 Port 15 Port 13 P150,P153 / TIN0,TIN3 P130-P137 / TIN16-TIN23 P20-P27 / A23-A30 P30-P37 / A15-A22 P46, P47 / A13, A 14 P225 / A12 Address bus Port 2 Port 3 Port 4 Port 22 Port 22 CAN 16 P00-P07 / DB0-DB7 P10-P17 / DB8-DB15 Data bus Port 0 Port 1 P82 / TXD0 5V 5V P83 / RXD0 P84 / SCLKI 0 / SCLKO 0 P85 / TXD1 P86 / RXD1 P87 / SCLKI 1 / SCLKO 1 P174 / TXD2 P175 / RXD2 Serial I/O Port 8 Port 17 Port 12 Multijunction timer P124-P127 / TCLK0-TCLK3 4 Port 11 Port 10 Port 9 P93-P97 / TO16-TO720 P100-P107 / TO8-TO15 P110-P117 / TO0-TO7 21 16 AD0IN0A-D0IN15 A-D converter AVCC0 AVSS0 VREF0 P74 / RTDTXD P75 / RTDRXD P76 / RTDACK P77 / RTDCLK Real-time debugger Port 7 Port 6 P61-P63 JTMS JTCK JTRST 4 JTDO JTDI Port 6 Interrupt controller P64 / SBI VCCE JTAG VCCI 3 3.3V 3.3V VDD FVCC 5 VSS Note: 3.3V 5V : Operates with a 3.3V power supply. : Operates with a 5V or 3.3V power supply. Figure 3 Pin Function Diagram of 240QFP 7 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 4 Description of Pin Function (1/4 ) Type Power supply Pin Name VCCE VCCI VDD FVCC VSS Clock XIN, XOUT Description Power supply Power supply Input/Output — — Function Supplies power (5 V or 3.3V) to external I/O ports. Supplies power (3.3 V) to the internal logic. nternal RAM backup power supply (3.3 V). Internal flash memory backup power supply (3.3 V). Connect all VSS pins to ground (GND). Clock input/output pins. These pins contain a PLL-based frequency multiply-by-4, so input the clock whose frequency is quarter the operating frequency. (XIN input = 10 MHz when CPU clock operates at 40 MHz) BCLK / ______ RAM power supply — Flash power supply — Ground Clock — Input Output System clock Output When this signal is System Clock(BCLK), it outputs a clock whose is twice that of external inpout clock. (BCLK output = 20 MHz when CPU clock operates at 40 MHz). Use this clock when circuits are synchronized externally. ______ WR When this signal is Write(WR), during external write access it indicates the valid data on the data bus to transfer. OSC-VCC OSC-VSS VCNT ______ RESET MOD0 MOD1 Power supply Ground PLL control Reset Mode — — Input Input Input Power supply to the PLL circuit. Connect OSC-VCC to the power supply(3.3V) Connect OSC-VSS to ground. This pin controls the PLL circuit. Connect a resistor and capacitor to this pin. This pin resets the internal circuits. These pins set an operation mode. MOD0 0 0 1 0 0 1 Address bus A12-A30 Address bus Output 1 MOD1 0 1 0 Mode Single-chip mode Expanded external mode Processor mode (Boot mode) (Note) (Reserved) Reset Mode 19 lines of address bus (A12-A30) are provided to accommodate two channels of 1 MB memory space (max.) connected external to the chip. A31 is not output. In the write cycle, of the 16-bit data bus the valid byte positions to write are _________ ________ ________ _______ output as BHW/ BHE and BLW/ BLE. In read cycle, data on the entire 16-bit data bus is read. However, only the data at the valid byte positions are transferred to the M32R’s internal circuit. Data bus DB0-DB15 Data bus Input/output This 16-bit data bus connects to external device. Note: FP pin should be “H” level in Boot Mode. 8 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 5 Description of Pin Function (2/4) Type Bus control Pin type ___ Description Chip select Read Input/Output Function Output Chip select signals for external devices. CS0, CS1 __ RD ___ _______ Output Output This signal is output when reading external devices. Indicates the byte positions to which valid are transferred when writing to ________ _______ ________ _______ external devices.BHW/ BHE and BLW/ BLE correspond to the upper address side(D0-D7 effective) and the lower address side(D8-D15 effective),respectivel. BHW/ BHE ___ _______ Byte high write Byte low write Wait BLW/ BLE ____ Output _________ WAIT _____ Input If WAIT input is low when the M32R accesses external devices, the wait cycle extended. This pin is used by an external device to request control of the external bus. __________ HREQ ____ Hold request Input The M32R goes to a hold state when HREQ input is pulled low. Output This signal indicates to the external device that the M32R has entered a hold state and relinquished control of the external bus. Input Input pins for multijunction timer. HACK Hold acknowledge Multijunction TIN0, TIN3 timer TIN16-TIN23 TO0 -TO20 TCLK0 -TCLK3 A-D converter AVCC0, AVSS0 AD0IN0 -AD0IN15 VREF0 ___ SBI Timer input Timer output Output Output pins for multijunction timer. Timer clock Input Clock input pins for multijunction timer. Analog power – upply Analog ground – Analog input Input AVCC0 is the power supply for the A-D0 converters.Connect AVCC0 to the power supply (5V or 3.3V). AVSS0 is the analog ground for the A-D0 converters. Connect AVCC0 to ground 16-channel analog input pin for A-D0 converter. Reference voltage input Input VREF0 is the reference voltage input pin (5V or 3.3V) for the A-D0 converters. Interrupt controller System break interrupt Input System break interrupt(SBI) input pin of the interrupt controller. 9 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 6 Description of Pin Functions (3/4) Type Serial I/O Pin name SCLKI0/ SCLKO0 Description UART transmit/ receive clock output or CSIO transmit/receive clock input/output SCLKI1/ SCLKO1 UART transmit/ receive clock output or CSIO transmit/receive clock input/output TXD0 RXD0 TXD1 RXD1 TXD2 RXD2 Real-Time Debugger RTDTXD RTDRXD RTDCLK RTDACK Transmit data Receive data Transmit data Receive data Transmit data Receive data Transmit data Receive data Clock input Acknowledge Output Input Output Input Output Input Output Input Input Output When channel 1 is in CSIO mode: Transmit/receive clock input when external clock is selected Transmit/receive clock output when internal clock is selected Transmit data output pin for serial I/O channel 0 Receive data input pin for serial I/O channel 0 Transmit data output pin for serial I/O channel 1 Receive data input pin for serial I/O channel 1 Transmit data output pin for serial I/O channel 2 Receive data input pin for serial I/O channel 2 Serial data output pin of the real-time debugger Serial data input pin of the real-time debugger Serial data transmit/receive clock input pin of the real-time debugger This pin outputs a low pulse synchronously with the real-time debugger’s first clock of serial data output word. The low pulse width indicates the type of the command/data the realtime debugger has received. Flashonly CAN FP Flash protect Input This pin protects the flash memory against E/W in hardware. Input/output When channel 0 is in CSIO mode: Transmit/receive clock input when external clock is selected Transmit/receive clock output when internal clock is selected When channel 1 is in UART mode: Clock output derived from BRG output by dividing it by 2 Input/output Input/output Function When channel 0 is in UART mode: Clock output derived from BRG output by dividing it by 2 CTX CRX Transmit data Receive data Test mode Clock Test reset Serial output Serial input Output Input Input Input Input Output Input Data output pin from CAN module. Data input pin to CAN module. Test select input for controlling the test circuit’s state transition Clock input to the debugger module and test circuit. Test reset input for initializing the test circuit asynchronously. Serial output of test instruction code or test data. Serial input of test instruction code or test data. JTAG JTMS JTCK JTRST JTDO JTDI 10 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 7 Description of Pin Functions (4/4) Type Input/ output port (Note) Pin name P00-P07 P10-P17 P20-P27 P30-P37 P41-P47 P61-P64 Description Input/output port 0 Input/output port 1 Input/output port 2 Input/output port 3 Input/output port 4 Input/output port 6 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Function Programmable input/output port. Programmable input/output port. Programmable input/output port. Programmable input/output port. Programmable input/output port. Programmable input/output port. (However, P64 is an input-only port) P70-P77 P82-P87 P93-P97 P100 -P107 P110 -P117 P124 -P127 P130 -P137 P150, P153 P174, P175 P220, P221, P225 Note: Input/output port 5 is reserved for future use. Input/output ports 14, 16, 18, 19, 20, and 21 do not exist. Input/output port 15 Input/output port 17 Input/output port 22 Input/output Input/output Input/output Programmable input/output port. Programmable input/output port. Programmable input/output port. (However, P221 is an input-only port) Input/output port 13 Input/output Programmable input/output port. Input/output port1 2 Input/output Programmable input/output port. Input/output port 11 Input/output Programmable input/output port. Input/output port 7 Input/output port 8 Input/output port 9 Input/output port 10 Input/output Input/output Input/output Input/output Programmable input/output port. Programmable input/output port. Programmable input/output port. Programmable input/output port. 11 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Logical space of the M32171F4VFP > Logical address Expanded external area (4M bytes) EIT vector entry H'0000 0000 (16M bytes) User ROM area Reserved area (512K bytes) H'0000 0000 H'0007 FFFF H'000F FFFF H'0010 0000 CS0 area 2G bytes User space Ghost area in units of 16M bytes H'001F FFFF H'0020 0000 CS1 area Ghost area in CS1 (1M byte) H'002F FFFF H'0030 0000 H'7FFF FFFF H'8000 0000 BOOT ROM area (8K bytes) Reserved area (8K bytes) H'8000 0000 H'8000 1FFF H'8000 2000 H'8000 3FFF H'8000 4000 SFR area (16K bytes) Ghost area in units of 16K bytes H'003F FFFF H'0040 0000 Ghost area in units of 4M bytes H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000 H'0080 7FFF H'0080 8000 Reserved area (96K bytes) 1G bytes Boot program space Internal RAM (16K bytes) H'BFFF FFFF H'C000 0000 H'BFFF FFFF H'0081 FFFF H'0082 0000 1G bytes System space Ghost area in units of 128K bytes H'FFFF FFFF H'00FF FFFF Figure 4 Address Space of the M32171F4VFP 12 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Logical space of the M32171F3VFP > Logical address Expanded external area (4M bytes) EIT vector entry H'0000 0000 (16M bytes) User ROM area Reserved area (640K bytes) H'0000 0000 H'0005 FFFF H'000F FFFF H'0010 0000 CS0 area 2G bytes User space Ghost area in units of 16M bytes H'001F FFFF H'0020 0000 CS1 area Ghost area in CS1 (1M byte) H'002F FFFF H'0030 0000 H'003F FFFF H'0040 0000 Ghost area in units of 4M bytes H'7FFF FFFF H'8000 0000 BOOT ROM area (8K bytes) Reserved area (8K bytes) H'8000 0000 H'8000 1FFF H'8000 2000 H'8000 3FFF H'8000 4000 SFR area (16K bytes) Ghost area in units of 16K bytes H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000 H'0080 7FFF H'0080 8000 Reserved area (96K bytes) 1G bytes Boot program space Internal RAM (16K bytes) H'BFFF FFFF H'C000 0000 H'BFFF FFFF H'0081 FFFF H'0082 0000 1G bytes System space Ghost area in units of 128K bytes H'FFFF FFFF H'00FF FFFF Figure 5 Address Space of the M32171F3VFP 13 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Logical space of the M32171F2VFP > Logical address Expanded external area (4M bytes) EIT vector entry H'0000 0000 (16M bytes) User ROM area Reserved area (768K bytes) H'0000 0000 H'0003 FFFF H'000F FFFF H'0010 0000 CS0 area 2G bytes User space Ghost area in units of 16M bytes H'001F FFFF H'0020 0000 CS1 area Ghost area in CS1 (1M byte) H'002F FFFF H'0030 0000 H'003F FFFF H'0040 0000 Ghost area in units of 4M bytes H'7FFF FFFF H'8000 0000 BOOT ROM area (8K bytes) Reserved area (8K bytes) H'8000 0000 H'8000 1FFF H'8000 2000 H'8000 3FFF H'8000 4000 SFR area (16K bytes) Ghost area in units of 16K bytes H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000 H'0080 7FFF H'0080 8000 Reserved area (96K bytes) 1G bytes Boot program space Internal RAM (16K bytes) H'BFFF FFFF H'C000 0000 H'BFFF FFFF H'0081 FFFF H'0082 0000 1G bytes System space Ghost area in units of 128K bytes H'FFFF FFFF H'00FF FFFF Figure 6 Address Space of the M32171F2VFP 14 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 0 +0 address 78 +1 address 15 H'0080 07E0 0 +0 address 78 +1 address 15 H'0080 0000 to H'0080 007E H'0080 0080 to H'0080 00EE H'0080 0100 to H'0080 0146 Serial I/O Interrupt controller (ICU) A-D converter to H'0080 07F2 Flash control H'0080 0FE0 to H'0080 0FFE H'0080 1000 to H'0080 0180 Wait controller CAN MJT (TML1) H'0080 11FE H'0080 0200 to H'0080 023E H'0080 0240 to H'0080 02FE H'0080 0300 to H'0080 03BE H'0080 03C0 to H'0080 03D8 MJT (common part) H'0080 3FFE MJT (TOP) MJT (TIO) Multijunction timer (MJT) MJT (TMS) H'0080 03E0 to H'0080 03FE H'0080 0400 to H'0080 047E MJT (TML0) DMAC H'0080 0700 to H'0080 0756 Input/output ports Note: The Real-time debugger (RTD) is an independent module operated from external circuits, and is transparent to the CPU. Figure 7 SFR Area 15 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Built-in Flash Memory and RAM The M32171F4VFP contains 512-Kbyte flash memory and 16-Kbyte RAM. The M32171F3VFP contains 384-Kbyte flash memory and 16-Kbyte RAM. The M32171F2VFP contains 256-Kbyte flash memory and 16-Kbyte RAM. The internal flash memory can be programmed on-board (i.e., while being mounted on the printed circuit board). This means that the same chip as will be used in mass-production can be used directly from the development stage on, allowing for system development without having to change the printed circuit board when proceeding from trial production to mass-production. Built-in Virtual-Flash Emulation Function Internal flash memory, which is divided from the first address in units of 8 Kbyte (L banks), can be replaced in 8 -Kbyte blocks (H70080 4000-H’0080 5FFF) from the beginning of the internal RAM. And also the internal flash memory, which is divided from the first address in units of 4-Kbyte area (All S banks), can be replaced within two 4 Kbytes areas (H’0080 6000-H’0080 7FFF). This function allows parts of the program which are frequently changed during development to be altered or evaluated without having to reset the microcomputer each time. What’s more, when combined with the realtime debugger, this function helps to reduce the program evaluation period, because data in the RAM can be rewritten without requiring any CPU load. < Internal flash > H'0000 0000 H'0000 1FFF H'0000 2000 H'0000 3FFF H'0000 4000 H'0000 5FFF L bank 0 (8K bytes) L bank 1 (8K bytes) L bank 2 (8K bytes) · · · · · · · · · · · · · · · · · · · · · · · · · · < Internal RAM > H'0080 4000 8K bytes 4K bytes 4K bytes H'0080 5FFF H'0080 6000 H'0080 7FFF H'0007 C000 H'0007 DFFF H'0007 E000 H'0007 FFFF L bank 62 (8K bytes) L bank 63 (8K bytes) Note 1: If the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is enabled, the corresponding internal RAM area is assigned to either bank register according to the priority FELBANK0 > FESBANK0 > FESBANK1. Note 2: When access is made to the 8-Kbyte area (L bank) specified with pseudo-flash bank register 0, the internal RAM area is accessed. During pseudo-flash emulation mode, RAM data can read and written to and from both the internal RAM area and the virtual-flash setup area. Figure 8 Virtual-Flash Emulation Areas of the M32171F4VFP (Replaced in Units of 8 Kbytes) 16 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Internal flash > H'0000 0000 H'0000 0FFF H'0000 1000 H'0000 1FFF H'0000 2000 H'0000 2FFF S bank 0 (4K bytes) S bank 1 (4K bytes) S bank 2 (4K bytes) · · · < Internal RAM> H'0080 4000 8K bytes 4K bytes 4K bytes · · · · · · · · · · · · · · · · · · · · · · · · H'0080 5FFF H'0080 6000 H'0080 7000 H'0007 E000 H'0007 EFFF H'0007 F000 H'0007 FFFF S bank 126 (4K bytes) S bank 127 (4K bytes) Note 1: If the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is enabled, the corresponding internal RAM area is assigned to either bank register according to the priority FELBANK0 > FESBANK0 > FESBANK1. Note 2: When access is made to the 4-Kbyte area (S bank) specified with virtual-flash bank registers 0 and 1, the internal RAM area is accessed. During virtual-flash emulation mode, RAM data can read and written to and from both the internal RAM area and the virtual-flash setup area. Figure 9 Virtual-Flash Emulation Areas of the M32171F4VFP (Replaced in Units of 4 Kbytes) Virtual-Flash Emulation Areas of M32171F4VFP, M32171F3VFP, and M32171F2VFP are shown as follows. Table 8 Virtual-Flash Emulation Areas Type Name M32171F4VFP M32171F3VFP M32171F2VFP Virtual-Flash Emulation Areas H’ 0000 0000 - H’ 0007 FFFF H’ 0000 0000 - H’ 0005 FFFF H’ 0000 0000 - H’ 0003 FFFF 17 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Input/output Ports The microcomputer has a total of 97 input/output ports P0-P22. (However, P5 is reserved for future use, P14, P16, and P18-P21 do not exist.) The input/output ports can be used as input ports or output ports by setting uptheir direction registers. Each input/output port is a dual-function pin shared with otherinternal peripheral I/O or external extended bus signal lines. These pin functions are selected by using the chip operation mode select or the input/output port operation mode registers. These input/output ports are interfaced using a dedicated power supply to allow for connections to the peripheral circuits operating with 5V or 3.3V. Table 9 Outline of Input/output Ports Item Number of Port Specification Total 97 ports P0 P1 P2 P3 P4 P6 P7 P8 P9 P10 P11 P12 P13 P15 P17 P22 Port function : : : : : : : : : : : : : : : : P00 - P07 P10 - P17 P20 - P27 P30 - P37 P41 - P47 P61 - P64 P70 - P77 P82 - P87 P93 - P97 P100 - P107 P110 - P117 P124 - P127 P130 - P137 P150, P153 P174, P175 (8 lines) (8 lines) (8 lines) (8 lines) (7 lines) (4 lines) (8 lines) (6 lines) (5 lines) (8 lines) (8 lines) (4 lines) (8 lines) (2 lines) (2 lines) P220, P221, P225 (3 lines) The input/output ports can be set for input or output mode bitwise by using the input/output port ___ direction control register. (However, P64 is an SBI input-only port, and P221 is CAN input-only port.) Dual-functions shared with peripheral I/O or external extended signals (or multi-functions shared with peripheral I/Os which have multiple functions.) P0 - P4 : Changed by setting CPU operation mode (MOD0 and MOD1 pins) P6 - 22 : Changed by setting the input/output port operation mode register. (However, peripheral I/O pin functions are selected using the peripheral I/O register.) Pin function Pin function changeover Note: Input/output ports P14, P16, and P18-P21 do not exist. Table 10 CPU Operation Modes and P0-P4 Pin Functions MOD0 VSS VSS VCCE VCCE MOD1 VSS VCCE VSS VCCE Operation mode Single-chip mode External extended mode External extended signal pin Processor mode (FP pin = VSS) Reserved (use inhibited) – Pin functions of P0-P4 Input/output port pin Note: VCCE connects to +5V or +3.3V, and VSS connects to GND. 18 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 0 P0 P1 CPU operation mode settings (Note1) P2 P3 P4 DB0 DB8 A23 A15 1 2 DB2 DB10 A25 A17 BHW/BHE 3 4 5 DB5 DB13 A28 A20 CS1 6 7 DB7 DB15 A30 A22 A14 DB1 DB9 A24 A16 BLW/BLE DB3 DB11 A26 A18 RD DB4 DB12 A27 A19 CS0 DB6 DB14 A29 A21 A13 (Reserved) P5 P6 P7 P8 P9 P10 P11 P12 P13 Input/output port operation mode register settings P14 P15 P16 P17 P18 P19 P20 P21 P22 CTX TIN 0 TIN 16 TO 8 TO 0 BCLK/ WR (P61) WAIT (P62) HREQ TXD0 (P63) HACK RXD0 TO 16 SBI RTDTXD RTDRXD RTDACK RTDCLK SCLKI 0/ SCLKO 0 TXD1 TO 18 TO 13 TO 5 TCLK 1 TIN 21 RXD1 T O 19 T O 14 TO 6 TCLK 2 TIN 22 SCLKI 1/ SCLKO 1 T O 17 T O 12 TO 4 TCLK 0 TO 20 TO 15 TO 7 TCLK 3 TIN 23 TO 9 TO 1 TO 10 TO 2 TO 11 TO 3 TIN 17 TIN 18 TIN 19 TIN 20 TIN 3 TXD 2 R XD 2 CR X A1 2 Note 1: The pin function are selected by setting the MOD0 and MOD1 pins. Note 2: P14, P16, P18, P19, P20, and P21 do not exist. Figure 10 Input/output Ports and Pin Function Assignments 19 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Built-in 10-Channel DMAC The microcomputer contains 10 channels of DMAC, allowing for data transfer between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and between internal RAMs. DMA transfer requests can be issued from the user-cre ated software, as well as can be triggered by a signal generated by the internal peripheral I/O (A-D converter, MJT, or serial I/O). The microcomputer also supports cascaded connection between DMA channels (starting DMA transfer on a channel at end of transfer on another channel). This makes advanced transfer processing possible without causing any additional CPU load. Table 11 Outline of the DMAC Item Number of channels Transfer request Content 10 channels • Software trigger • R equest from internal peripheral I/O: A-D converter, multijunction timer, or serial I/O (reception completed, transmit buffer empty) • Cascaded connection between DMA channels possible (Note) 256 times • 64 Kbytes (address space from H’0080 0000 to H’0080 FFFF) • Transfers between internal peripheral I/Os, between internal RAM and internal peripheral IO, and between internal RAMs are supported Transfer data size Transfer method 16 bits or 8 bits Single transfer DMA (control of the internal bus is relinquished for each transfer performed), dual-address transfer Single transfer mode One of three modes can be selected for the source and destination of transfer: • Address fixed • Address increment • 32-channel ring buffer Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7 > channel 8 > channel 9 (Fixed priority) 13.3 Mbytes per second (when internal peripheral clock = 20 MHz) Group interrupt request can be generated when each transfer count register underflows 64 Kbytes from H’0080 0000 to H’0080 FFFF (Transfer is possible in the entire internal RAM/SFR area) Note: The following DMA channels can be cascaded. DMA transfer on channel 1 started at end of one DMA transfer on channel 0 DMA transfer on channel 2 started at end of one DMA transfer on channel 1 DMA transfer on channel 0 started at end of one DMA transfer on channel 2 DMA transfer on channel 4 started at end of one DMA transfer on channel 3 DMA transfer on channel 6 started at end of one DMA transfer on channel 5 DMA transfer on channel 7 started at end of one DMA transfer on channel 6 DMA transfer on channel 5 started at end of one DMA transfer on channel 7 DMA transfer on channel 9 started at end of one DMA transfer on channel 8 DMA transfer on channel 5 started at end of all DMA transfers on channel 0 (underflow of transfer count register) Maximum number of times transferred Transferable address space Transfer mode Direction of transfer Channel priority Maximum transfer rate Interrupt request Transfer area 20 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Internal bus One DMA2 transfer completed Software start A-D conversion completed MJT (TIO8_udf) MJT (input event bus 2) DMA channel 0 Source DMA request selector Destination Transfer count udf DMA channel 1 Software start MJT (output event bus 0) One DMA0 transfer completed DMA channel 2 Software start MJT (output event bus 1) MJT (TIN18 input signal) One DMA1 transfer completed DMA request selector Source Destination Transfer count udf DMA request selector Source Destination Transfer count udf DMA channel 3 Software start Serial I/O0 (transmit buffer empty) Serial I/O1 (reception completed) MJT (TIN0 input signal) DMA request selector Source Destination Transfer count udf DMA channel 4 Software start One DMA3 transfer completed Serial I/O0 (reception completed) MJT (TIN19 input signal) DMA request selector Source Destination Transfer count udf Interrupt request DMA start Determination block Software start One DMA7 transfer completed All DMA0 transfers completed (udf) Serial I/O2 (reception completed) MJT (TIN20 input signal) DMA channel 6 Software start Serial I/O1 (transmit buffer empty) One DMA5 transfer completed DMA channel 7 Software start Serial I/O2 (transmit buffer empty) One DMA6 transfer completed DMA channel 8 Software start MJT (input event bus 0) DMA request selector Source Destination Transfer count udf DMA request selector Source Destination Transfer count udf DMA request selector Source Destination Transfer count udf DMA channel5 DMA request selector Source Destination Transfer count udf Internal bus arbitration DMA channel 9 Software start One DMA8 transfer completed DMA request selector Source Destination Transfer count DMA start Determination block udf Interrupt request Internal bus arbitration Figure 11 Block Diagram of the DMAC 21 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Built-in 37-Channel Multijunction Timers (MJT) The microcomputer contains a total of 37 channels of multijunction timers consisting of 11 channels of 16-bit output related timers, 10 channels of 16-bit input/output related timers, eight channels of 16-bit input related timers, eight channels of 32-bit input related timers, Each timer has multiple operation modes to choose from, depending on the purposes of use. Also, the maltijunction timers internally have a clock bus, input event bus, and an output event bus, so that multiple timers can be used in combination allowing for a flexible timer configuration. The output related timers have a correcting function that allows the timer’s count value to be incremented or decremented as necessary while count is in progress, making real time output control possible. Input event bus TCLK pin E/L Output related timer : 11ch Input/output related timer : 10ch 16-bit input related timer : 8ch 32-bit input related timer : 8ch · · · CLK Timer Output event bus Clock bus To DMAC, A-D converter Interrupt output F/F TO pin EN 1/2 internal peripheral clock PRS CLK Timer · · · · Interrupt output EN F/F TO pin E/L PRS : Edge/Level selector : Prescaler TIN pin E/L : Junction box (Selector) F/F Note: This is a conceptual diagram and does not show the actual timer configuration. : Output flip-flop Figure 12 Conceptual Diagram of the Multijunction Timer (MJT) 22 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 12 Outline of Multijunction Timers Name TOP (Timer Output) Type Output-related 16-bit timer (down-counter) Number of channels 11 Content One of three input modes can be selected in software. < With correction function > • Single-shot output mode • Delayed single-shot output mode < Without correction function > • Continuous output mode TIO (Timer Input Output) Input/output-related 16-bit timer (down-counter) 10 One of three input modes or four output modes can be selected by software. < Input modes > • Measure clear input mode • Measure free-run input mode • Noise processing input mode < Output mode without correction function • PWM output mode • Single-shot output mod • Delayed single-shot output mode • Continuous output mode TMS (Timer Measure Small) TML (Timer Measure Large) Input-related 16-bit timer (up counter) Input-related 32-bit timer (up counter) 8 32-bit input measure timer. 8 16-bit input measure timer. 23 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Clock bus 3210 Input event bus 3210 Output event bus IRQ2 0123 clk S TCLK 0 TCLK0S IRQ 9 en en en en en en en TOP 0 TOP 1 TOP 2 TOP 3 TOP 4 TOP 5 TOP 6 udf IRQ2 F/ F0 F/ F1 IRQ2 TO 0 TO 1 TO 2 TO 3 TO 4 TO 5 TO 6 clk clk S DRQ 7 udf udf IRQ2 F/F2 F/F3 IRQ2 TIN 0 TIN0 S clk clk clk clk udf udf IRQ2 F/ F4 F/F5 IRQ1 udf udf IRQ1 S S S S S S F/ F6 clk en TOP 7 udf IRQ6 S F/F7 TO 7 clk clk clk en en en TOP 8 TOP 9 TOP 10 TIO 0 TIO 1 TIO 2 TIO 3 TIO 4 udf udf udf IRQ0 IRQ6 S S IRQ5 F/F8 F/F9 F/F10 F/F11 F/F12 F/F13 F/F14 TO 8 TO 9 TO 10 TO 11 TO 12 TO 13 TO 14 S S IRQ0 IRQ12 S S clk clk S clk S clk TIN3 TIN3S en/ cap en/ cap en/ cap en/cap en/ cap udf udf IRQ0 S S IRQ0 udf udf IRQ4 S S 1/2 internal peripheral clock PRS 0 PRS1 PRS 2 clk S udf S F/F15 TO 15 S TCLK1 TCLK1S IRQ4 S S clk en/cap TIO 5 udf IRQ4 S F/F16 TO 16 TCLK2 TCLK2S S S S S S S clk en/cap TIO 6 udf IRQ4 S F/F17 TO 17 clk en/cap TIO 7 udf DRQ0 IRQ3 S F/F18 TO 18 clk en/cap TIO 8 udf IRQ3 S F/F19 TO 19 S S 3210 3210 PSC0-2 clk en/ cap TIO 9 udf F/F20 TO 20 0123 : Prescaler F/F : Output flip-flop S : Selector Figure 13 Block Diagram of Multijunction Timers (MJT) (1/3) 24 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Clock bus 3210 Input event bus 3210 Output event bus 0123 IRQ 7 TCLK3 TCLK3S S S S S clk cap3 TMS 0 cap2 cap1 cap0 ovf S (Note1) IRQ10 S S clk cap3 TMS 1 cap2 cap1 IRQ 7 cap0 ovf TIN16 TIN17 TIN18 TIN16S IRQ10 TIN17S IRQ10 S S DRQ5 IRQ10 TIN18S TIN19 1/2 internal peripheral clock TIN20 TIN21 TIN22 TIN23 TIN19S DRQ6 S S DRQ12 IRQ11 clk cap3 S TML 0 cap2 cap1 cap0 TIN20S TIN21S TIN22S IRQ11 S IRQ11 S IRQ11 TIN23S S AD0TRG (To A-D0 converter) 1/2 internal peripheral clock S S clk cap3 S S S cap2 TML 1 cap1 cap0 3210 3210 0123 Figure 14 Block Diagram of Multijunction Timers (MJT) (2/3) 25 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Clock bus 3210 Input event bus 3210 Output event bus 0123 AD0 completed TIO8-udf S DMA0 udf end udf end udf end udf end DMAIRQ0 S DMA 1 DMAIRQ0 TIN18 SIO0-TXD SIO1-RXD S DMA 2 DMAIRQ0 TIN0 S DMA 3 DMAIRQ0 SIO0-RXD TIN19 SIO2- RXD S DMA 4 udf DMAIRQ 0 TIN20 S DMA 5 udf end udf end udf end DMAIRQ1 SIO1-TXD S DMA 6 DMAIRQ1 SIO2- TXD S DMA 7 DMAIRQ1 S DMA 8 udf end udf DMAIRQ1 S DMA 9 DMAIRQ1 3210 3210 0123 Figure 15 Block Diagram of Multijunction Timers (MJT) (3/3) 26 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Built-in Two Independent A-D Converters The microcomputer contains two 16-channel converters with 10-bit resolution (A-D0 converter and A-D1 converter). In addition to single conversion on each channel, continuous A-D conversion on a combined group of 4, 8, and 16 channels is possible. The A-D converted value can be read out in either 10 bits or 8 bits. In addition to ordinary A-D conversion, the converters support comparator mode in which the set value and A-D converted value are compared to determine which is larger or smaller than the other. When A-D conversion is finished, the converters can generated a DMA transfer request, as well as an interrupt. The A-D converters are interfaced using a dedicated power supply to allow for connections to the peripheral circuits operating with 5V or 3.3V. Table 13 Outline of the A-D Converters Item Analog input A-D conversion method Resolution Absolute accuracy (Conditions: Ta = -40 ~ +125°C, AVCC0 = VREF0 = 5.12V) (Note 1) Conversion mode Operation mode Scan mode Conversion start trigger Content 16 channels Successive approximation method. 10 bits (Conversion results can be read out in either 10 or 8 bits.) Normal rate mode Double rate mode +2 LSB +2 LSB A-D conversion mode,comparator mode Single mode, scan mode Single -shot scan mode, continuous scan mode. Software start Hardware start Started by setting A-D conversion start bit to 1. A-D0 converter started by MJT output event bus 3. Normal Double speed Normal Double speed 299 × 1/ f (BCLK) 173 × 1/ f (BCLK) 47 × 1/ f (BCLK) 29 × 1/ f (BCLK) Conversion rate f(BCLK) : Internal peripheral clock (Note 2) operating frequency During single mode (Shortest time ) During comparator mode (Shortest time ) Interrupt request generation When A-D conversion is finished, when comparate operation is finished, when single-shot scan is finished, or when one cycle of continuous scan is finished. DMA transfer request generation When A-D conversion is finished, when comparate operation is finished, when single-shot scan is finished, or when one cycle of continuous scan is finished. Note 1: The rated value of conversion accuracy here is that of the microcomputer's own as a single unit which can be exhibited when the microcomputer is used in an environment where it may not be affected by the power supply wiring or noise on the board. Note 2: When input clock (XIN) = 10 MHz, f(BCLK) = 20 MHz. 27 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Internal data bus 8-bit readout 10-bit readout Shifter AD0DT0 AD0DT1 AD0DT2 AD0DT3 AD0DT4 AD0DT5 AD0DT6 AD0DT7 AD0DT8 AD0DT9 AD0DT10 AD0DT11 AD0DT12 AD0DT13 AD0DT14 AD0DT15 AD0CMP 10-bit A-D0 Data Register 0 10-bit A-D0 Data Register 1 10-bit A-D0 Data Register 2 10-bit A-D0 Data Register 3 10-bit A-D0 Data Register 4 10-bit A-D0 Data Register 5 10-bit A-D0 Data Register 6 10-bit A-D0 Data Register 7 10-bit A-D0 Data Register 8 10-bit A-D0 Data Register 9 10-bit A-D0 Data Register 10 10-bit A-D0 Data Register 11 10-bit A-D0 Data Register 12 10-bit A-D0 Data Register 13 10-bit A-D0 Data Register 14 10-bit A-D0 Data Register 15 A-D comparate Data Register A-D Control Circuit Output event bus 3 (multijunction timer) AD0SIM0,1 AD0SCM0,1 Single Mode Register Scan Mode Register AVCC0 AVSS0 10-bit A-D Successive Approximation Register (AD0SAR) VREF0 10-bit D-A Converter Comparator • Mode selection • Channel selection Interrupt request • Conversion time selection • Flag control DMA transfer request • Interrupt control AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AD0IN8 AD0IN9 AD0N10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 Selector Successive Approximation -type A-D Converter Unit Figure 16 Block Diagram of the A-D0 Converter 28 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 3-channel High-speed Serial I/Os The microcomputer contains three channels of serial I/Os consisting of two channels that can be set for CSIO mode (clock-synchronized serial I/O) or UART mode (asynchronous serial I/O) and one other channel that can only be set for UART mode. The SIO has the function to generate a DMA transfer request when data reception is completed or the transmit register becomes empty, and is capable of high-speed serial communication without causing any additional CPU load. Table 14 Outline of Serial I/O Item Number of channels Content CSIO/UART: 2 channels (SIO0,SIO1) UART only : 1 channels (SIO2) Clock During CSIO mode : Internal clock / external clock, selectable (Note1) During UART mode : Internal clock only Transfer mode BRG count sourcef Data format Transmit half-duplex, receive half-duplex, transmit/receive full-duplex (BCLK), f(BCLK)/8, f(BCLK)/32, f(BCLK)/256 (When internal clock is selected) (Note2) CSIO mode : Data length = Fixed to 8 bits Order of transfer = Fixed to LSB first UARTmode : Start bit = 1 bit Character length = 7, 8, or 9 bits Parity bit = Added or not added (When added, selectable between odd and even parity) Stop bit = 1 or 2 bits Order of transfer = Fixed to LSB first Baud rate CSIO mode : UARTmode : Error detection CSIO mode : UARTmode : 152 bits per second to 2 Mbits per second (when operating with f(BCLK) = 20 MHz) 19 bits per second to 156 Kbits per second (when operating with f(BCLK) = 20 MHz) Overrun error only Overrun, parity, and framing errors (The error-sum bit indicates which error has occurred) Fixed cycle clock output function When using SIO0 and SIO1 as UART, this function outputs a divided-by-2 BRG clock from the SCLK pin. Note 1: During CSIO mode, the maximum input frequency of an external clock is f(BCLK) divided by 16. Note 2: When f(BCLK) is selected for the BRG count source, the BRG set value is subject to limitations. 29 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER SIO0 SIO0 Transmit Buffer Register Transmit interrupt TXD0 SIO0 Transmit Shift Register Transmit/receive control circuit Receive interrupt Transmit DMA transfer request Receive DMA transfer request To interrupt controller To DMA3 To DMA4 RXD0 SIO0 Receive Shift Register SIO0 Receive Buffer Register UART mode CSIO mode When external clock selected When internal clock selected BCLK Clock divider Baud rate generator (BRG) CSIO mode When internal clock selected When UART mode selected SIO1 Transmit interrupt Transmit/receive control circuit Receive interrupt Transmit DMA transfer request Receive DMA transfer request TXD1 SIO1 Transmit Shift Register Internal data bus BCLK, BCLK/8, BCLK/32, BCLK/256 1/16 1 (Set value + 1) 1/2 SCLKI0/ SCLKO0 To interrupt controller To DMA6 To DMA3 SCLKI1/ SCLKO1 RXD1 SIO1 Receive Shift Register SIO2 TXD2 Transmit interrupt Transmit/receive control circuit Receive interrupt Transmit DMA transfer request Receive DMA transfer request SIO2 Transmit Shift Register To interrupt controller RXD2 To DMA7 To DMA5 SIO2 Receive Shift Register Note 1 : When BCLK is selected, the BRG set value is subject to limitations. Note 2 : SIO2 does not have the SCLKI/SCLKO function. Figure 17 Block Diagram of Serial I/O 30 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER CAN Module The M32171 Group contains two Full CAN modules compliant with CAN Specification V2.0B (CAN0 and CAN1), each of which has 16-channel message slots and three mask registers. Data bus CAN0 Status Register CAN0 REC Register CAN0 TEC Register CAN0 Message Slot 0-15 Control Register CAN0 Extended Register CAN0 Configuration Register CAN0 Control Register CAN0 Global Mask Register CAN0 Local Mask Register A CAN0 Local Mask Register B Message Memory (1) Message ID (2) Data length code (3) Message data (4) Time stamp CAN0 Slot Status Register CAN0 Slot Interrupt Control Register CAN0 Error Interrupt Control Register Interrupt Control Circuit CAN0 Transmit/Receive & Error Interrupt CTX CAN0 Protocol Controller 2.0B active Acceptance Filtering 16-bit Timer CAN0 Time Stamp Register CRX Figure 18 Block Diagram of the CAN Module 31 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 8-level Interrupt Controller The Interrupt Controller controls interrupt requests from each internal peripheral I/O (31 sources) by using eight priority levels assigned to each interrupt source, including interrupts disabled. In addition to these interrupts, it handles System Break Interrupt (SBI), Reserved Instruction Exception (RIE), and Address Exception (AE) as nonmaskable interrupts. Realtime Debugger (RTD) The Realtime Debugger (RTD) provides a function for accessing directly from the outside to the internal RAM. It uses a dedicated clock-synchronized serial I/O to communicate with the outside. Use of the RTD communicating via dedicated serial lines allows the internal RAM to be read out and rewritten without having to halt the CPU. Wait Controller The Wait Controller supports access to external devices. For access to an external extended area of up to 1 Mbytes (during external extended or processor mode), the Wait Controller controls bus cycle extension by inserting one to ____ four wait cycles or using external WAIT signal input. M32171F4VFP, M32171F3VFP, M32171F2VFP RTDCLK Internal RAM (16KB) Virtual-DPRAM structure RTDRXD Real-Time Debugger (RTD) RTDTXD RTDACK Command address Data Data M32R CPU Data R/W without CPU intervention Data Bus(CPU) Data Bus(RTD) Figure 19 Conceptual Diagram of the Realtime Debugger (RTD) 32 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER CPU Instruction Set The M32R employs a RISC architecture, supporting a total of 83 discrete instructions. • Arithmetic operation ADD ADD3 ADDI ADDV ADDV3 ADDX NEG SUB SUBV SUBX Add Add 3-operand Add immediate Add (with overflow checking) Add 3-operand Add with carry Negate Subtract Subtract (with overflow checking) Subtract with borrow (1) Load/store instructions Perform data transfer between memory and registers. LD LDB LDUB LDH LDUH LOCK ST STB STH UNLOCK Load Load byte Load unsigned byte Load halfword Load unsigned halfword Load locked Store Store byte Store halfword Store unlocked • Multiplication/division DIV DIVU MUL REM REMU Divide Divide unsigned Multiply Remainder Remainder unsigned (2) Transfer instructions Perform register to register transfer or register to immediate transfer. LD24 LDI MV MVFC MVTC SETH Load 24-bit immediate Load immediate Move register Move from control register Move to control register Set high-order 16-bit • Shift SLL SLL3 SLLI SRA SRA3 SRAI SRL SRL3 SRLI Shift Shift Shift Shift Shift Shift Shift Shift Shift left logical left logical 3-operand left logical immediate right arithmetic right arithmetic 3-operand right arithmetic immediate right logical right logical 3-operand right logical immediate (5) Instructions for the DSP function (3) Branch instructions Used to change the program flow. BC Branch on C-bit BEQ Branch on equal BEQZ Branch on equal zero BGEZ Branch on greater than or equal zero BGTZ Branch on greater than zero BL Branch and link BLEZ Branch on less than or equal zero BLTZ Branch on less than zero BNC Branch on not C-bit BNE Branch on not equal BNEZ Branch on not equal zero BRA Branch JL Jump and link JMP Jump NOP No operation Perform 32 bit × 16 bit or 16 bit × 16 bit multiplication or sumof-products calculation. These instructions also perform rounding of the accumulator data or transfer between accumulator and general-purpose register. MACHI MACLO MACWHI MACWLO MULHI MULLO MULWHI MULWLO MVFACHI MVFACLO MVFACMI MVTACHI MVTACLO RAC RACH Multiply-accumulate high-order halfwords Multiply-accumulate low-order halfwords Multiply-accumulate word and high-order halfword Multiply-accumulate word and low-order halfword Multiply high-order halfwords Multiply low-order halfwords Multiply word and high-order halfword Multiply word and low-order halfword Move from accumulator high-order word Move from accumulator low-order word Move from accumulator middle-order word Move to accumulator high-order word Move to accumulator low-order word Round accumulator Round accumulator halfword (4) Arithmetic/logic instructions Perform comparison, arithmetic/logic operation, multiplication/division, or shift between registers. • Comparison CMP CMPI CMPU CMPUI Compare Compare immediate Compare unsigned Compare unsigned immediate • Logical operation AND AND3 NOT OR OR3 XOR XOR3 AND AND 3-operand Logical NOT OR OR 3-operand Exclusive OR Exclusive OR 3-operand (6) EIT related instructions Start trap or return from EIT processing. RTE TRAP Return from EIT Trap 33 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Multiply instruction > 0 H Rsrc1 15 16 L 31 0 H Rsrc2 15 16 L 31 < Multiply-accumulate instruction > 0 ACC 63 0 H Rsrc1 15 16 L 31 0 H Rsrc2 15 16 L 31 × × MULHI instruction 0 ACC MULLO instruction 63 × × + + Rsrc2 15 16 MACHI instruction 0 31 L 0 63 ACC ACC MACLO instruction 63 0 Rsrc1 32 bit 31 0 H × × MULWHI instruction 0 ACC MULWLO instruction 63 0 Rsrc1 32 bit 31 0 H Rsrc2 15 16 L 31 × × + < Ropund off instruction > 0 ACC RAC instruction sign data 0 0 15 16 63 MACWHI instruction 0 ACC + MACWLO instruction 63 0 63 < Accumulator - register transfer instruction > MVFACMI instruction 31 32 ACC MVFACHI instruction MVFACLO instruction 1 Rdest 0 MVTACHI instruction 31 32 ACC 0 ACC RACH instruction 0 sign data 0 63 47 48 63 0 Rsrc 31 MVTACLO instruction 63 63 0 Figure 20 Instructions for the DSP Function 34 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Package Dimensions Diagram 144P6Q-A EIAJ Package Code LQFP144-P-2020-0.50 HD JEDEC Code – Weight(g) Lead Material Cu Alloy Plastic 144pin 20✕20mm body LQFP MD 144 109 1 108 b2 l2 Recommended Mount Pad Dimension in Millimeters Max Nom Min 1.7 – – 0.125 0.2 0.05 – 1.4 – 0.27 0.22 0.17 0.175 0.125 0.105 20.1 20.0 19.9 20.1 20.0 19.9 – 0.5 – 22.2 22.0 21.8 22.2 22.0 21.8 0.65 0.5 0.35 1.0 – – – 0.1 – – 8° 0° – – 0.225 – – 1.0 – 20.4 – – 20.4 – HE E Symbol A A1 A2 b c D E e HD HE L L1 y b2 I2 MD ME 36 73 37 72 A F L1 A2 e b y Detail F A1 L c ME D e 35 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32171 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. 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The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. • • • • • © 2001 MITSUBISHI ELECTRIC CORP. New publication, effective May 2001. Specifications subject to change without notice. Revision Description List Rev. No. 1.0 32171Group Data Sheet Revision Description Rev. date 010514 Page First Edition Point (1/1)