M32174F4VWG

2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Description The M32170 and M32174 Group are 32-bit single chip RISC microcomputers designed for use in general industrial and household equipment. These microcomputers contains a variety of peripheral functions ranging from16-channel A-D converters to 64channel multifunction timers, 10-channel DMAs, 6-channel serial I/Os, 1-channel real time debugger, 1-channel Full-CAN, and JTAG (boundary scan facility). With lower power consumption and low noise characteristics also considered, these microcomputers are ideal for embedded equipment applications. 64-channel multijunction timers (MJT) Multifunction timers are incorporated that support various purposes of use. 16-bit output related timers ....................................... 35ch 16-bit input/output related timers .............................. 10ch 16-bit input related timers ......................................... 11ch 32-bit input related timers .......................................... 8ch • Flexible configuration is possible through interconnection of timers. • The internal DMAC and A-D converter can be started by a timer. Real-time Debugger Features M32R RISC CPU core • Uses the M32R family RISC CPU core (Instruction set common to all microcomputers in the M32R family) • Five-stage pipelined processing • Sixteen 32-bit general-purpose registers • 16-bit/32-bit instructions implemented • DSP function instructions (sum-of-products calculation using 56-bit accumulator) • Built-in flash memory • Built-in flash programming boot program • Built-in RAM • PLL clock generating circuit ........... Built-in × 4 PLL circuit • Maximum operating frequency of the CPU clock 40MHz(when operating at -40 to +85oC) 32MHz(when operating at -40 to +125oC) Table 1 32170 Group Name List by type Type Name M32170F6VFP M32170F4VFP M32170F3VFP M32170F6VWG M32170F4VWG M32170F3VWG RAM Size 40K bytes 32K bytes 32K bytes 40K bytes 32K bytes 32K bytes ROM Size 768K bytes 512K bytes 384K bytes 768K bytes 512K bytes 384K bytes Package 240QFP 240QFP 240QFP 255FBGA 255FBGA 255FBGA • Includes dedicated clock-synchronized serial I/O that can read and write the contents of the internal RAM independently of the CPU. • Can look up and update the data table in real time while the program is running. • Can generate a dedicated interrupt based on RTD communication. Abundant internal peripheral functions In addition to the timers and real-time debugger, the microcomputer contains the following peripheral functions. • DMAC .............................................................. 10 channels • Two independent A-D converter .............. (10-bit converter × 16 channels) × 2 • Serial I/O ............................................................ 6 channels • Interrupt controller ........... 31 interrupt sources, 8 priority levels • Wait controller • Full CAN .............................................................. 1 channel • JTAG (boundary scan function) Designed to operate at high temperatures To meet the need for use at high temperatures, the microcomputer is designed to be able to operate in the temperature range of -40 to +125oC when CPU clock operating frequency = 32 MHz. When CPU clock operating frequency = 40 MHz, the microcomputer can be used in the temperature range of -40 to +85oC. Note: This does not guarantee continuous operation at 125oC. If you are considering use of the microcom puter at 125oC, please consult Mitsubishi. Note: 255FBGA is currently under development. Table 2 32170 Group Name List by type Type Name M32174F4VFP M32174F3VFP M32174F4VWG M32174F3VWG RAM Size 40K bytes 40K bytes 40K bytes 40K bytes ROM Size 512K bytes 384K bytes 512K bytes 384K bytes Package 240QFP 240QFP 255FBGA 255FBGA Applications Automobile equipment control (e.g., Engine, ABS, AT), industrial equipment system control, and high-function OA equipment (e.g., PPC) Note: 255FBGA is currently under development. 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Pin Assignment(top view) P217/TO44 P216/TO43 P215/TO42 P214/TO41 P213/TO40 P212/TO39 P211/TO38 P210/TO37 VSS VCCI VDD P102/TO10 P101/TO9 P100/TO8 P117/TO7 P116/TO6 P115/TO5 P114/TO4 P113/TO3 P112/TO2 P111/TO1 P110/TO0 VSS VCCE FP MOD1 MOD0 RESET P97/TO20 P96/TO19 P95/TO18 P94/TO17 P93/TO16 P77/RTDCLK P76/RTDACK P75/RTDRXD P74/RTDTXD P73/ HACK P72/ HREQ P71/WAIT P70/BCLK/WR VCCE VSS VCCI P67/ADTRG P66/SCLKI5/SCLKO5 P65/SCLKI4/SCLKO4 P64/SBI P63 P62 P61 VSS FVCC VSS VCCI P203/RXD5 P202/TXD5 P201/RXD4 P200/TXD4 P87/SCLKI1/SCLKO1 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 JTMS JTCK JTRST JTDO JTDI P103/TO11 P104/TO12 P105/TO13 P106/TO14 P107/TO15 P124/TCLK0 P125/TCLK1 P126/TCLK2 P127/TCLK3 VCCI VSS P130/TIN16 P131/TIN17 P132/TIN18 P133/TIN19 P134/TIN20 P135/TIN21 P136/TIN22 P137/TIN23 VCCE VSS P140/TIN8 P141/TIN9 P142/TIN10 P143/TIN11 P144/TIN12 P145/TIN13 P146/TIN14 P147/TIN15 P150/TIN0 P151/TIN1 P152/TIN2 P153/TIN3 P154/TIN4 P155/TIN5 P156/TIN6 P157/TIN7 P41/BLW/BLE P42/BHW/BHE VCCI VSS VREF1 AVCC1 AD1IN0 AD1IN1 AD1IN2 AD1IN3 AD1IN4 AD1IN5 AD1IN6 AD1IN7 AD1IN8 AD1IN9 AD1IN10 AD1IN11 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 M32170F3VFP M32170F4VFP M32170F6VFP M32174F3VFP M32174F4VFP 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P86/RXD1 P85/TXD1 P84/SCLKI0/SCLKO0 P83/RXD0 P82/TXD0 VSS VCCE P177/RXD3 P176/TXD3 P175/RXD2 P174/TXD2 P173/TIN25 P172/TIN24 P167/TO28 P166/TO27 P165/TO26 P164/TO25 P163/TO24 P162/TO23 P161/TO22 P160/TO21 VSS VCCI P197/TIN33 P196/TIN32 P195/TIN31 P194/TIN30 P193/TIN29 P192/TIN28 P191/TIN27 P190/TIN26 P187/TO36 P186/TO35 P185/TO34 P184/TO33 P183/TO32 P182/TO31 P181/TO30 P180/TO29 VSS VCCE AVSS0 AD0IN15 AD0IN14 AD0IN13 AD0IN12 AD0IN11 AD0IN10 AD0IN9 AD0IN8 AD0IN7 AD0IN6 AD0IN5 AD0IN4 AD0IN3 AD0IN2 AD0IN1 AD0IN0 AVCC0 VREF0 Note: Use caution when using these pins because they nave a debug event function. Figure 1 Pin Layout Diagram of the 240QFP 2 AD1IN12 AD1IN13 AD1IN14 AD1IN15 AVSS1 P43/RD P44/CS0 P45/CS1 P46/A13 P47/A14 P220/CTX P221/CRX P222 P223 (Note) P224/A11 (Note) P225/A12 VSS OSC-VSS XIN XOUT OSC-VCC VSS VCNT VSS P30/A15 P31/A16 P32/A17 P33/A18 P34/A19 P35/A20 P36/A21 P37/A22 P20/A23 P21/A24 P22/A25 P23/A26 VCCE VSS P24/A27 P25/A28 P26/A29 P27/A30 P00/DB0 P01/DB1 P02/DB2 P03/DB3 P04/DB4 P05/DB5 P06/DB6 P07/DB7 VCCE VSS P10/DB8 P11/DB9 P12/DB10 P13/DB11 P14/DB12 P15/DB13 P16/DB14 P17/DB15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Package 240P6Y-A 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Pin Assignment(top view) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 JTMS P216 /TO43 P217 /TO44 P214 /TO41 P215 /TO42 P213 /TO40 JTDO P210 /TO37 P211 /TO38 P212 /TO39 VSS P102 /TO10 P116 TRDATA /TO6 6 P117 TRDATA /TO7 7 P100 /TO8 P115 /TO5 P112 /TO2 P113 /TO3 VCCE RESET P96 P77/ P73 /TO19 RTDCLK /HACK P95 P76/ P72 /TO18 RTDACK /HREQ P94 P75/ P71 /TO17 RTDRXD /WAIT VCCE P66 /SCLK5 P65 /SCLK4 P64 /SBI P63 P62 VSS P202 /TXD5 P200 /TXD4 P201 TRDATA /RXD4 3 TRDATA 1 JTCK VDD VSS MOD0 VSS P61 VCCI N.C JEVENT 0 JDBI VCCI P114 TRDATA /TO4 4 TRDATA 5 P111 /TO1 P110 /TO0 FP MOD1 VCCI VSS P203 /RXD5 P83 /RXD0 P177 /RXD3 P173 /TIN25 P165 /TO26 P161 /TO22 P87 TRDATA TRDATA 2 0 /SCLK1 P84 /SCLK0 P86 /RXD1 P82 /TXD0 P176 /TXD3 P172 /TIN24 P164 /TO25 P160 /TO21 P196 /TIN32 P190 /TIN26 P184 /TO33 P180 /TO29 P85 /TXD1 JEVENT JTRST 1 P104 /TO12 P124 /TCLK0 P103 /TO11 P107 /TO15 P127 /TCLK3 P131 /TIN17 P135 /TIN21 P101 /TO9 P97 /TO20 P70 P93 P74/ P67 /TO16 RTDTXD /BCLK /ADTRG FVCC P105 /TO13 P125 /TCLK1 JTDI VCCE VSS P106 /TO14 P126 /TCLK2 P130 /TIN16 P134 /TIN20 P174 /TXD2 P166 /TO27 P162 /TO23 P175 /RXD2 P167 /TO28 P163 /TO24 VCCI P132 /TIN18 P136 /TIN22 P140 /TIN8 P144 /TIN12 P150 /TIN0 P154 /TIN4 P41 /BLW VSS P133 /TIN19 P137 /TIN23 P141 /TIN9 P143 /TIN11 P147 /TIN15 P153 /TIN3 P157 /TIN7 VSS VCCE P145 /TIN13 P151 /TIN1 P155 /TIN5 P42 /BHW P142 /TIN10 P146 /TIN14 P152 /TIN2 P156 /TIN6 M32170F3VWG M32170F4VWG M32170F6VWG M32174F3VWG M32174F4VWG P197 /TIN33 P193 /TIN29 P187 /TO36 P183 /TO32 VCCI VSS P194 /TIN30 P192 /TIN28 P186 /TO35 P182 /TO31 P195 /TIN31 P191 /TIN27 P185 /TO34 P181 /TO30 VSS AD0IN14 VCCE AD0IN15 AVSS0 VREF1 AVCC1 VSS VCCI AD0IN10 AD0IN13 AD0IN11 AD0IN12 AD1IN2 AD1IN3 AD1IN1 AD1IN0 AD0IN6 AD0IN9 AD0IN7 AD0IN8 AD1IN6 AD1IN7 AD1IN5 AD1IN15 P45 /CS1 P46 /A13 P47 /A14 P220 /CTX P221 /CRX P225 /A12 XOUT VSS P33 /A18 P34 /A19 P35 /A20 TRSYNC P21 /A24 VSS P27 /A30 P02 /DB2 P01 /DB1 P00 /DB0 P03 /DB3 P06 /DB6 P05 /DB5 P04 /DB4 P07 /DB7 P10 /DB8 P11 /DB9 P14 /DB12 P13 /DB11 P12 /DB10 AD0IN5 AD0IN3 AD0IN4 AD1IN8 AD1IN10 AD1IN4 AVSS1 P222 VSS OSCVCC P30 /A15 P31 /A16 P32 /A17 P20 /A23 P37 /A22 P36 /A21 VCCE P26 /A29 P25 /A28 P24 /A27 AD0IN1 AD0IN0 AD0IN2 AD1IN9 AD1IN11 AD1IN13 P43 /RD P44 /CS0 P223 OSCVSS VSS P23 /A26 P22 /A25 VSS P17 /DB15 P15 /DB13 VREF0 AVCC0 AD1IN12 AD1IN14 P224 /A11 XIN VCNT TRCLK VCCE P16 /DB14 N.C A B C D E F G H J K L M N P R T U V W Y Package 255FBGA Note 1: NC pin (W19, Y1) shows non-connect. Be open state. Note 2: Use caution when using P224/A11 and P225/A12 because they have a debug event function. Note 3: 255FBGA is currently under development. Figure 2 Pin Layout Diagram of the 255FBGA 3 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 32170/32174 Internal bus interface DMAC (10 channels) M32R CPU core (max 40MHz) Multiplieraccumulator (32 × 16 + 56) Multijunction timer (MJT : 64 channels) Internal flash memory ( M32170F6 : 768KB ) ( M32170F4 : 512KB ) ( M32170F3 : 384KB ) ( M32174F4 : 512KB ) ( M32174F3 : 384KB ) Internal 32-bit bus Internal 16-bit bus A-D converter (10-bit, 16 channels) × 2 Serial I/O (6 channels) Interrupt controller (31 sources, 8 levels) Wait controller Internal RAM ( M32170F6 : 40KB ) ( M32170F4 : 32KB ) ( M32170F3 : 32KB ) ( M32174F4 : 40KB ) ( M32174F3 : 40KB ) Full CAN (1 channel) Real-time debugger (RTD) PLL clock generation circuit External bus interface Address Data Input/output port(JTAG) 157 lines Figure 3 Block diagram 4 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 3 Outline Performance (1/2) Functional Block M32R CPU core Features M32R family CPU core, internally configured in 32 bits Built-in multiplier-accumulator (32 × 16 + 56) Basic bus cycle : 25 ns (Internal CPU clock frequency at 40 MHz, Internal peripheral clock frequency at 20 MHz) Logical address space : 4G bytes, linear General-purpose register : 32-bit register × 16, Control register: 32-bit register × 5 accumulator : 56 bits External data bus Instruction set 16 bits data bus 16-bit/32-bit instruction formats 83 instructions/ 9 addressing modes Internal flash memory M32170F6 : 768K bytes M32170F4, M32174F4 : 512K bytes M32170F3, M32174F3 : 384K bytes Rewrite durability : 100 times Internal RAM M32170F6, M32174F4, M32174F3 : 40K bytes M32170F4, M32170F3 : 32K bytes DMAC 10 channels (DMA transfers between internal peripheral I/Os, between internal peripheral I/O and internal RAM, and between internal RAMs) Channels can be cascaded and can operate in combination with internal peripheral I/O Multijunction timer 64 channels of multijunction timers. • 16-bit output-related timers × 35 channels (single-shot, delayed single-shot, PWM, single-shot PWM) • 16-bit input/output-related timers × 10 channels (event count mode, single-shot, PWM, measurement) • 16-bit input-related timers × 11 channels (measurement, event count mode, multiply-by-4 count 3 channels) • 32-bit input-related timers × 8 channels (measurement) Flexible timer configuration is possible through interconnection of channels using the event bus. A-D converter 2 independent 10-bit multifunction A-D converters • Input 16 channels × 2 • Scan-based conversion can be switched with 4, 8, and 16 • Capable of interrupt conversion during scan • 8-bit/10-bit readout function available Serial I/O 6 channels (The serial I/Os can be set for synchronous serial I/O or UART. SIO2,3 are UART mode only) Real-time debugger (RTD) 1-channels dedicated clock-synchronized serial The entire internal RAM can be read or rewritten from the outside without CPU intervention. Interrupt controller Controls interrupts from internal peripheral I/Os (Priority can be set to one of 8 levels including interrupt disabled) Wait controller Controls wait when accessing external extended area (1 to 4 wait cycles inserted + prolonged by external WAIT signal input) CAN JTAG 16-channels message slots Boundary-Scan function 5 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 4 Outline Performance (2/2) Function Block Clock Features Maximum internal CPU memory clock : 40MHz (access to CPU, internal ROM, and internal RAM) Maximum internal peripheral clock : 20MHz (access to internal peripheral module) Maximum external input clock : 10.0MHz, Built-in multiply-by-4 PLL circuit Power Supply Voltage External I/O : 5V (±0.5V) or 3.3V (±0.3V) Internal logic : 3.3V (±0.3V) Operating temperature rang -40 to +125° C(Internal CPU memory clock 32MHz, internal peripheral clock 16MHz) -40 to +85° C(Internal CPU memory clock 40MHz, internal peripheral clock 20MHz) Package 0.5mm pitches / 240-pin plastic QFP, 0.8mm pitches / 255-pin FBGA (Note) Note: 255-pin FBGA is currently under development. 6 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Outline of the CPU core The M32170 and M32174 Group uses the M32R RISC CPU core, and has an instruction set which is common to all microcomputers in the M32R family. Instructions are processed in five pipelined stages consisting of instruction fetch, decode, execution, memory access, and write back. Thanks to its “out-of-order-completion” mechanism, the M32R CPU allows for clock cycle efficient, instruction execution control. The M32R CPU internally has sixteen 32-bit general-purpose registers. The instruction set consists of 83 discrete instructions, which come in either a 16-bit instruction or a 32-bit instruction format. Use of the 16-bit instruction format helps to reduce the code size of a program. Also, the availability of 32bit instructions facilitates programming and increases the performance at the same clock speed, as compared to architectures with segmented address spaces. Three operation modes The M32170 and M32174 Group has three operation modes: single-chip mode, external extended mode, and processor mode. These operation modes are changed from one to another by setting the MOD0 and MOD1 pins. Address space The M32170 and M32174 Group’s logical addresses are always handled in 32 bits, providing 4 Gbytes of linear address space. The M32170 and M32174 Group’s address space consists of the following. User space A 2-Gbyte area from H’0000 0000 to H’7FFF FFFF is the user space. Located in this space are the user ROM area, external extended area, internal RAM area, and SFR (Special Function Register) area (internal peripheral I/O registers). Of these, the user ROM area and external extended area are located differently depending on mode settings. Sum-of-products instructions comparable to DSP The M32R CPU contains a multiplier/accumulator that can execute 32 bits × 16 bits in one cycle. Therefore, it executes a 32 bit × 32 bit integer multiplication instruction in three cycles. Also, the M32R CPU supports the following four sum-of-products instructions (or multiplication instructions) for DSP function use. (1) 16 high-order register bits × 16 high-order register bits (2) 16 low-order register bits × 16 low-order register bits (3) All 32 register bits × 16 high-order register bits (4) All 32 register bits × 16 low-order register bits Furthermore, the M32R CPU has instructions for rounding the value stored in the accumulator to 16 or 32 bits, and instructions for shifting the accumulator value to adjust digits before storing in a register. Because these instructions also can be executed in one cycle, DSP comparable data processing capability can be obtained by using them in combination with high-speed data transfer instructions such as Load & Address Update or Store & Address Update. Boot program space A 1-Gbyte area from H’8000 0000 to H’BFFF FFFF is the boot program area. This space contains the on-board programming program (boot program) used in blank state by the internal flash memory. System space A 1-Gbyte area from H’C000 0000 to H’FFFF FFFF is the system area. This space is reserved for use by development tools such as an in-circuit emulator and debug monitor, and cannot be used by the user. Built-in clock multiplier circuit The clock multiplier circuit multiplies the frequency of the input clock signal by 4 to produce the internal operating clock. When the maximum CPU memory clock frequency = 40 MHz, the input clock frequency is 10.0 MHz. 7 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Clock XOUT VCNT OSC-VCC OSC-VSS 3.3V (Note 1) XIN P45/CS1 P44/CS0 P43/RD P42/BHW/BHE Bus control Port 4 Port 7 Reset P70/BCLK/WR RESET MOD0 MOD1 FP P220/CTX P221/CRX P190-P197/TIN26-TIN33 P172, P173/TIN24, TIN25 P150-P157/TIN0-TIN7 P140-P147/TIN8-TIN15 P130-P137/TIN16-TIN23 Multijunction timer P124-P127/ TCLK0-TCLK 3 P210-P217/TO37-TO44 P180-P187/TO29-TO36 P160-P167/TO21-TO28 P110-P117/TO0-TO7 P100-P107/TO8-TO15 P93-P97/TO16-TO20 16 AD0IN0-AD0IN15 AD1IN0-AD1IN15 16 34 M32170F6VFP , M32170F4VFP , M32170F3VFP , M32174F4VFP , M32174F3VFP P41/BLW/BLE P71/WAIT P72/HREQ P73/HACK P224/A11 (Note 2) P225/A12 (Note 2) 20 P20-P27/A23-A30 P30-P37/A15-A22 P46, P47/A13, A14 P00-P07/DB0-DB7 P10-P17/DB8-DB15 P82/TXD0 P83/RXD0 Port 7 Mode Port 22 CAN Address bus Port 22 Port 2 Port 3 Port 4 Port 19 Port 17 Port 15 Port 14 Port 13 Port 12 Port 21 Port 18 Port 16 Port 11 Port 10 Port 9 16 Data bus Port 0 Port 1 4 5V 5V 45 P84/SCLKI0/SCLKO0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 P174/TXD2 P175/RXD2 P176/TXD3 P177/RXD3 P200/TXD4 P201/RXD4 P202/TXD5 P203/RXD5 P65/SCLKI4/SCLKO4 P66/SCLKI5/SCLKO5 P74/RTDTXD P75/RTDRXD P76/RTDACK P77/RTDCLK JTMS JTCK JTRST JTDO JTDI Serial I/O Port 6 Port 8 Port 17 Port 20 Port 6 A-D converter P67/ADTRG AVCC0, AVCC1 AVSS0, AVSS1 AVREF0, AVREF1 2 2 2 3 Port 6 Port 22 Port 6 Interrupt controller P61-P63 P222, P223 P64/SBI VCCE Real-time debugger Port 7 7 JTAG VCCI 3.3V 6 3.3V VDD FVCC 16 VSS Note 1: 3.3V 5V : Operates with a 3.3V power supply. : Operates with a 3.3V or 5V power supply. Note 2: Use caution when using this port because it has a debug event function. Figure 4 Pin Function Diagram of 240QFP 8 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Clock XOUT VCNT OSC-VCC OSC-VSS 3.3V (Note 1) XIN P45/CS1 P44/CS0 P43/RD P42/BHW/BHE Bus control Port 4 Port 7 Reset P70/BCLK/WR RESET MOD0 MOD1 FP P220/CTX P221/CRX P190-P197/TIN26-TIN33 P172, P173/TIN24, TIN25 P150-P157/TIN0-TIN7 P140-P147/TIN8-TIN15 P130-P137/TIN16-TIN23 Multijunction timer P124-P127/ TCLK0-TCLK 3 P210-P217/TO37-TO44 P180-P187/TO29-TO36 P160-P167/TO21-TO28 P110-P117/TO0-TO7 P100-P107/TO8-TO15 P93-P97/TO16-TO20 16 AD0IN0-AD0IN15 AD1IN0-AD1IN15 16 34 M32170F6VWG , M32170F4VWG , M32170F3VWG , M32174F4VWG , M32174F3VWG P41/BLW/BLE P71/WAIT P72/HREQ P73/HACK P224/A11 (Note 2) P225/A12 (Note 2) 20 P20-P27/A23-A30 P30-P37/A15-A22 P46, P47/A13, A14 P00-P07/DB0-DB7 P10-P17/DB8-DB15 P82/TXD0 P83/RXD0 P84/SCLKI0/SCLKO0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 P174/TXD2 P175/RXD2 P176/TXD3 P177/RXD3 P200/TXD4 P201/RXD4 P202/TXD5 P203/RXD5 P65/SCLKI4/SCLKO4 P66/SCLKI5/SCLKO5 Port 7 Mode Port 22 CAN Address bus Port 22 Port 2 Port 3 Port 4 Port 19 Port 17 Port 15 Port 14 Port 13 Port 12 Port 21 Port 18 Port 16 Port 11 Port 10 Port 9 16 Data bus Port 0 Port 1 4 45 5V 5V Serial I/O Port 6 Port 8 Port 17 Port 20 Port 6 A-D converter P67/ADTRG AVCC0, AVCC1 AVSS0, AVSS1 AVREF0, AVREF1 2 2 2 3 Port 6 Port 22 Port 6 Interrupt controller P61-P63 P222, P223 P64/SBI TRCLK TRSYNC TRDATA JDBI JEVENTO JEVENT1 VCCE VCCI P74/RTDTXD P75/RTDRXD P76/RTDACK P77/RTDCLK JTMS JTCK JTRST JTDO JTDI Real-time debugger Port 7 DEBUG 8 JTAG 7 3.3V 3.3V 6 VDD FVCC 16 VSS Note 1: 3.3V 5V : Operates with a 3.3V power supply. : Operates with a 3.3V or 5V power supply. Note 2: Use caution when using this port because it has a debug event function. Note 3: 255FBGA is currently under development. Figure 5 Pin Function Diagram of 255FBGA 9 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 5 Description of Pin Function (1/5 ) Type Power supply Pin Name VCCE VCCI VDD FVCC VSS Clock XIN, XOUT Description Power supply Power supply Input/Output — — Function Supplies power (5 V or 3.3V) to external I/O ports. Supplies power (3.3 V) to the internal logic. nternal RAM backup power supply (3.3 V). Internal flash memory backup power supply (3.3 V). Connect all VSS pins to ground (GND). Clock input/output pins. These pins contain a PLL-based frequency multiply-by-4, so input the clock whose frequency is quarter the operating frequency. (XIN input = 10 MHz when CPU clock operates at 40 MHz) BCLK / ______ RAM power supply — Flash power supply — Ground Clock — Input Output System clock Output When this signal is System Clock(BCLK), it outputs a clock whose is twice that of external inpout clock. (BCLK output = 20 MHz when CPU clock operates at 40 MHz). Use this clock when circuits are synchronized externally. ______ WR When this signal is Write(WR),during external write access it indicates the valid data on the data bus to transfer. OSC-VCC OSC-VSS VCNT ______ RESET MOD0 MOD1 Power supply Ground PLL control Reset Mode — — Input Input Input Power supply to the PLL circuit. Connect OSC-VCC to the power supply(3.3V) Connect OSC-VSS to ground. This pin controls the PLL circuit. Connect a resistor and capacitor to this pin. This pin resets the internal circuits. These pins set an operation mode. MOD0 0 0 1 0 0 1 Address bus A11-A30 Address bus Output 1 MOD1 0 1 0 Mode Single-chip mode Expanded external mode Processor mode (Boot mode) (Note) (Reserved) Reset Mode 20 lines of address bus (A11-A30) are provided to accommodate two channels of 2 MB memory space (max.) connected external to the chip. A31 is not output. In the write cycle, of the 16-bit data bus the valid byte positions to write are _________ ________ ________ _______ output as BHW/ BHE and BLW/ BLE. In read cycle, data on the entire 16-bit data bus is read. However, only the data at the valid byte positions are transferred to the M32R’s internal circuit. Data bus DB0-DB15 Data bus Input/output This 16-bit data bus connects to external device. Note: FP pin should be “H” level in Boot Mode. 10 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 6 Description of Pin Function (2/5) Type Bus control Pin type ___ Description Chip select Read Input/Output Function Output Chip select signals for external devices. CS0, CS1 __ RD ___ _______ Output Output This signal is output when reading external devices. Indicates the byte positions to which valid are transferred when writing to ________ _______ ________ _______ BHW/ BHE ___ _______ Byte high write external devices.BHW/ BHE and BLW/ BLE correspond to the upper address Output side(D0-D7 effective) and the lower address side(D8-D15 effective),respectivel. _________ BLW/ BLE ____ Byte low write WAIT Wait Input If WAIT input is low when the M32R accesses external devices, the wait cycle extended. _____ HREQ Hold request Input This pin is used by an external device to request control of the external bus. __________ The M32R goes to a hold state when HREQ input is pulled low. Output This signal indicates to the external device that the M32R has entered a hold state and relinquished control of the external bus. Input Input pins for multijunction timer. ____ HACK Hold acknowledge Multijunction TIN0 timer -TIN33 TO0 -TO44 TCLK0 -TCLK3 A-D converter AVCC0, AVCC1 Timer input Timer output Output Output pins for multijunction timer. Timer clock Input Clock input pins for multijunction timer. Analog power – upply AVCC0 is the power supply for the A-D0 converters. AVCC1 is the power supply for the A-D1 converters. Connect AVCC0 and AVCC1 to the power supply (5V or 3.3V). AVSS0, AVSS1 Analog ground – AVSS0 is the analog ground for the A-D0 converters. AVSS1 is the analog ground for the A-D1 converters. Connect AVCC0 and AVCC1 to ground. AD0IN0 -AD0IN15 AD1IN0 -AD1IN15 VREF0, VREF1 _____ ADTRG ___ SBI Analog input Input One block of 16-channel analog input pin for A-D0 converter. Two blocks of 16-channel analog input pin for A-D1 converter. Reference voltage input Conversion trigger Input VREF0 is the reference voltage input pin (5V or 3.3V) for the A-D0 converters. VREF1 is the reference voltage input pin (5V or 3.3V) for the A-D1 converters. Input Hardware trigger input pin to start A-D conversion. Interrupt controller System break interrupt Input System break interrupt(SBI) input pin of the interrupt controller. 11 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 7 Description of Pin Functions (3/5) Type Serial I/O Pin name SCLKI0/ SCLKO0 Description UART transmit/ receive clock output or CSIO transmit/receive clock input/output SCLKI1/ SCLKO1 UART transmit/ receive clock output or CSIO transmit/receive clock input/output SCLKI4/ SCLKO4 UART transmit/ receive clock output or CSIO transmit/receive clock input/output SCLKI5 SCLKO5 UART transmit/ receive clock output or CSIO transmit/receive clock input/output TXD0 RXD0 TXD1 RXD1 TXD2 RXD2 TXD3 RXD3 TXD4 RXD4 TXD5 RXD5 Transmit data Receive data Transmit data Receive data Transmit data Receive data Transmit data Receive data Transmit data Receive data Transmit data Receive data Outpt Input Output Input Output Input Output Input Output Input Output Input When channel 5 is in CSIO mode: Transmit/receive clock input when external clock is selected Transmit/receive clock output when internal clock is selected Transmit data output pin for serial I/O channel 0 Receive data input pin for serial I/O channel 0 Transmit data output pin for serial I/O channel 1 Receive data input pin for serial I/O channel 1 Transmit data output pin for serial I/O channel 2 Receive data input pin for serial I/O channel 2 Transmit data output pin for serial I/O channel 3 Receive data input pin for serial I/O channel 3 Transmit data output pin for serial I/O channel 4 Receive data input pin for serial I/O channel 4 Transmit data output pin for serial I/O channel 5 Receive data input pin for serial I/O channel 5 Input/output When channel 4 is in CSIO mode: Transmit/receive clock input when external clock is selected Transmit/receive clock output when internal clock is selected When channel 5 is in UART mode: Clock output derived from BRG output by dividing it by 2 Input/output When channel 1 is in CSIO mode: Transmit/receive clock input when external clock is selected Transmit/receive clock output when internal clock is selected When channel 4 is in UART mode: Clock output derived from BRG output by dividing it by 2 Input/output When channel 0 is in CSIO mode: Transmit/receive clock input when external clock is selected Transmit/receive clock output when internal clock is selected When channel 1 is in UART mode: Clock output derived from BRG output by dividing it by 2 Input/output Input/output Function When channel 0 is in UART mode: Clock output derived from BRG output by dividing it by 2 12 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 8 Description of Pin Functions (4/5) Type Real-Time Debugger Pin name RTDTXD RTDRXD RTDCLK RTDACK Description Transmit data Receive data Clock input Acknowledge Input/output Output Input Input Output Function Serial data output pin of the real-time debugger Serial data input pin of the real-time debugger Serial data transmit/receive clock input pin of the real-time debugger This pin outputs a low pulse synchronously with the real-time debugger’s first clock of serial data output word. The low pulse width indicates the type of the command/data the realtime debugger has received. Flashonly CAN FP Flash protect Input This pin protects the flash memory against E/W in hardware. CTX CRX Transmit data Receive data Test mode Clock Test reset Serial output Serial input Output Input Input Input Input Output Input Data output pin from CAN module. Data input pin to CAN module. Test select input for controlling the test circuit’s state transition Clock input to the debugger module and test circuit. Test reset input for initializing the test circuit asynchronously. Serial output of test instruction code or test data. Serial input of test instruction code or test data. Programmable input/output port. Programmable input/output port. Programmable input/output port. Programmable input/output port. Programmable input/output port. Programmable input/output port. (However, P64 is an input-only port) JTAG JTMS JTCK JTRST JTDO JTDI Input/ output port (Note) P00-P07 P10-P17 P20-P27 P30-P37 P41-P47 P61-P67 Input/output port 0 Input/output Input/output port 1 Input/output Input/output port 2 Input/output Input/output port 3 Input/output Input/output port 4 Input/output Input/output port 6 Input/output P70-P77 P82-P87 P93-P97 P100 -P107 Input/output port 7 Input/output Input/output port 8 Input/output Input/output port 9 Input/output Input/output port 10 Input/output Programmable input/output port. Programmable input/output port. Programmable input/output port. Programmable input/output port. Note: Input/output port 5 is reserved for future use. 13 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 9 Description of Pin Functions (5/5) Type Input/ output port Pin name P110 -P117 P124 -P127 P130 -P137 P140 -P147 P150 -P157 P160 -P167 P172 -P177 P180 -P187 P190 -P197 P200 -P203 P210 -P217 P220 -P225 Input/output port 22 Input/output Programmable input/output port. (Note) (However, P221 is an input-only port) Input/output port 21 Input/output Programmable input/output port. Input/output port 20 Input/output Programmable input/output port. Input/output port 19 Input/output Programmable input/output port. Input/output port 18 Input/output Programmable input/output port. Input/output port 17 Input/output Programmable input/output port. Input/output port 16 Input/output Programmable input/output port. Input/output port 15 Input/output Programmable input/output port. Input/output port 14 Input/output Programmable input/output port. Input/output port 13 Input/output Programmable input/output port. Input/output port 12 Input/output Programmable input/output port. Description Input/output port 11 Input/output Input/output Function Programmable input/output port. Note: Use caution when using P224 and P225 because they have a debug event function. 14 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Logical space of the M32170F6 > Logical address Expanded external area (4M bytes) EIT vector entry H'0000 0000 (16M bytes) Internal ROM area 768K bytes Reserved area (256K bytes) H'0000 0000 H'000B FFFF H'000F FFFF H'0010 0000 CS0 area 2G bytes User space Ghost area in units of 16M bytes H'001F FFFF H'0020 0000 CS1 area H'7FFF FFFF H'8000 0000 BOOT ROM area (8K bytes) Reserved area (8K bytes) H'8000 0000 H'8000 1FFF H'8000 2000 H'8000 3FFF H'8000 4000 SFR area (16K bytes) Ghost area in units of 16K bytes H'003F FFFF H'0040 0000 Ghost area in units of 4M bytes H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000 1G bytes Boot program space Internal RAM (40K bytes) H'0080 DFFF H'0080 E000 Reserved area (72K bytes) H'BFFF FFFF H'C000 0000 H'BFFF FFFF H'0081 FFFF H'0082 0000 1G bytes System space Ghost area in units of 128K bytes H'FFFF FFFF H'00FF FFFF Figure 6 Address Space of the M32170F6 15 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Logical space of the M32170F4 > Logical address Expanded external area (4M bytes) EIT vector entry H'0000 0000 (16M bytes) Internal ROM area 512K bytes Reserved area (512K bytes) H'0000 0000 H'0007 FFFF H'000F FFFF H'0010 0000 CS0 area 2G bytes User space Ghost area in units of 16M bytes H'001F FFFF H'0020 0000 CS1 area H'7FFF FFFF H'8000 0000 BOOT ROM area (8K bytes) Reserved area (8K bytes) H'8000 0000 H'8000 1FFF H'8000 2000 H'8000 3FFF H'8000 4000 SFR area (16K bytes) Ghost area in units of 16K bytes H'003F FFFF H'0040 0000 Ghost area in units of 4M bytes H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000 1G bytes Boot program space Internal RAM (32K bytes) H'0080 BFFF H'0080 C000 Reserved area (80K bytes) H'BFFF FFFF H'C000 0000 H'BFFF FFFF H'0081 FFFF H'0082 0000 1G bytes System space Ghost area in units of 128K bytes H'FFFF FFFF H'00FF FFFF Figure 7 Address Space of the M32170F4 16 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Logical space of the M32170F3 > Logical address Expanded external area (4M bytes) EIT vector entry H'0000 0000 (16M bytes) Internal ROM area 384K bytes Reserved area (640K bytes) H'0000 0000 H'0005 FFFF H'000F FFFF H'0010 0000 CS0 area 2G bytes User space Ghost area in units of 16M bytes CS1 area H'001F FFFF H'0020 0000 H'7FFF FFFF H'8000 0000 BOOT ROM area (8K bytes) Reserved area (8K bytes) H'8000 0000 H'8000 1FFF H'8000 2000 H'8000 3FFF H'8000 4000 SFR area (16K bytes) Ghost area in units of 16K bytes H'003F FFFF H'0040 0000 Ghost area in units of 4M bytes H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000 1G bytes Boot program space Internal RAM (32K bytes) H'0080 BFFF H'0080 C000 Reserved area (80K bytes) H'BFFF FFFF H'C000 0000 H'BFFF FFFF H'0081 FFFF H'0082 0000 1G bytes System space Ghost area in units of 128K byte H'FFFF FFFF H'00FF FFFF Figure 8 Address Space of the M32170F3 17 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Logical space of the M32174F4 > Logical address Expanded external area (4M bytes) EIT vector entry H'0000 0000 (16M bytes) Internal ROM area 512K bytes Reserved area (512 bytes) H'0000 0000 H'0007 FFFF H'000F FFFF H'0010 0000 CS0 area 2G bytes User space Ghost area in units of 16M bytes H'001F FFFF H'0020 0000 CS1 area H'7FFF FFFF H'8000 0000 BOOT ROM area (8K bytes) Reserved area (8K bytes) H'8000 0000 H'8000 1FFF H'8000 2000 H'8000 3FFF H'8000 4000 SFR area (16K bytes) Ghost area in units of 16K bytes H'003F FFFF H'0040 0000 Ghost area in units of 4M bytes H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000 1G bytes Boot program space Internal RAM (40K bytes) H'0080 DFFF H'0080 E000 Reserved area (72K bytes) H'BFFF FFFF H'C000 0000 H'BFFF FFFF H'0081 FFFF H'0082 0000 1G bytes System space Ghost area in units of 128K bytes H'FFFF FFFF H'00FF FFFF Figure 9 Address Space of the M32174F4 18 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Logical space of the M32174F3 > Logical address Expanded external area (4M bytes) EIT vector entry H'0000 0000 (16M bytes) Internal ROM area 384K bytes Reserved area (640K bytes) H'0000 0000 H'0005 FFFF H'000F FFFF H'0010 0000 CS0 area 2G bytes User space Ghost area in units of 16M bytes H'001F FFFF H'0020 0000 CS1 area H'7FFF FFFF H'8000 0000 BOOT ROM area (8K bytes) Reserved area (8K bytes) H'8000 0000 H'8000 1FFF H'8000 2000 H'8000 3FFF H'8000 4000 SFR area (16K bytes) Ghost area in units of 16K bytes H'003F FFFF H'0040 0000 Ghost area in units of 4M bytes H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000 1G bytes Boot program space Internal RAM (40K bytes) H'0080 DFFF H'0080 E000 Reserved area (72K bytes) H'BFFF FFFF H'C000 0000 H'BFFF FFFF H'0081 FFFF H'0082 0000 1G bytes System space Ghost area in units of 128K bytes H'FFFF FFFF H'00FF FFFF Figure 10 Address Space of the M32174F3 19 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 0 +0 address 78 +1 address 15 H'0080 078C H'0080 078E H'0080 0790 to H'0080 07DE 0 +0 address 78 +1 address 15 H'0080 0000 to H'0080 007E H'0080 0080 to H'0080 00EE H'0080 0100 to H'0080 0146 Serial I/O Interrupt controller (ICU) A-D0 converter MJT (TID0) MJT (TOD0) Multijunction timer (MJT) H'0080 07E0 to H'0080 07F2 H'0080 0A00 to H'0080 0A26 Wait controller Flash control Serial I/O H'0080 0180 H'0080 0200 to H'0080 023E H'0080 0240 to H'0080 02FE H'0080 0300 to H'0080 03BE H'0080 03C0 to H'0080 03D8 H'0080 0A80 to MJT (common part) A-D1 converter H'0080 0AEE MJT (TOP) H'0080 0B8C H'0080 0B8E H'0080 0B90 to Multijunction timer (MJT) H'0080 0BDE MJT (TID1) MJT (TOD1) MJT (TIO) MJT (TMS) H'0080 0C8C H'0080 0C8E H'0080 0C90 to H'0080 0CDE MJT (TID2) Multijunction timer (MJT) MJT (TOM) H'0080 03E0 to H'0080 03FE H'0080 0400 to H'0080 0478 MJT (TML0) H'0080 0FE0 DMAC to H'0080 0FFE H'0080 1000 to Input/output ports H'0080 11FE H'0080 3FFE MJT (TML1) H'0080 0700 to H'0080 077E CAN Note: The Real-time debugger (RTD) is an independent module operated from external circuits, and is transparent to the CPU. Figure 11 SFR Area 20 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Built-in Flash Memory and RAM 32170 and 32174 Group contain Flash Memory and RAM stated as follows. The internal flash memory can be programmed on-board (i.e., while being mounted on the printed circuit board). This means that the same chip as will be used in mass-production can be used directly from the development stage on, allowing for system development without having to change the printed circuit board when proceeding from trial production to mass-production. Table 10 Flash memory and RAM Size (32170 Group) Type Name M32170F6VFP M32170F4VFP M32170F3VFP M32170F6VWG M32170F4VWG M32170F3VWG ROM Size 768K bytes 512K bytes 384K bytes 768K bytes 512K bytes 384K bytes RAM Size 40K bytes 32K bytes 32K bytes 40K bytes 32K bytes 32K bytes Table 11 Flash memory and RAM Size (32174 Group) Type Name M32174F4VFP M32174F3VFP M32174F4VWG M32174F3VWG ROM Size 512K bytes 384K bytes 512K bytes 384K bytes RAM Size 40K bytes 40K bytes 40K bytes 40K bytes Built-in Virtual-flash Emulation Function Internal flash memory, which is divided from the first address in units of 8 Kbyte (L banks), can be replaced in 8 -Kbyte blocks (H70080 4000-H’0080 5FFF) of the internal RAM. And also the internal flash memory, which is divided from the first address in units of 4-Kbyte areas (S banks), can be replaced in 4 Kbytes areas. This function allows parts of the program which are frequently changed during development to be altered or evaluated without having to reset the microcomputer each time. What’s more, when combined with the realtime debugger, this function helps to reduce the program evaluation period, because data in the RAM can be rewritten without requiring any CPU load. 21 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Internal flash > H'0000 0000 H'0000 2000 H'0000 4000 L bank 0 (8K bytes) L bank 1 (8K bytes) L bank 2 (8K bytes) < Internal RAM > H'0080 4000 8K bytes H'0080 6000 8K bytes H'0080 8000 H'0006 4000 H'0006 6000 L bank 50 (8K bytes) L bank 51 (8K bytes) 8K bytes H'0080 A000 8K bytes 4K bytes 4K bytes H'000B C000 H'000B E000 L bank 94 (8K bytes) L bank 95 (8K bytes) Note 1: If the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is enabled, the corresponding internal RAM area is assigned to either bank register according to the priority FELBANK0 > FELBANK1 > FELBANK2 > FELBANK3 > FESBANK0 > FESBANK1. Note 2: When access is made to the 8-Kbyte area (L bank) specified with virtual-flash bank registers 0-3, the internal RAM area is accessed. During virtual-flash emulation mode, RAM data can read and written to and from both the internal RAM area and the virtual-flash setup area. Figure 12 Virtual-Flash Emulation Areas of the M32170F6VFP (Replaced in Units of 8 Kbytes) < Internal flash > H'0000 0000 H'0000 1000 H'0000 2000 S bank 0 (4K bytes) S bank 1 (4K bytes) S bank 2 (4K bytes) < Internal RAM > H'0080 4000 8K bytes 8K bytes 8K bytes 8K bytes 4K bytes 4K bytes H'0080 C000 H'0080 D000 H'000B E000 H'000B F000 S bank 190 (4K bytes) S bank 191 (4K bytes) Note 1: If the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is enabled, the corresponding internal RAM area is assigned to either bank register according to the priority FELBANK0 > FELBANK1 > FELBANK2 > FELBANK3 > FESBANK0 > FESBANK1. Note 2: When access is made to the 4-Kbyte area (S bank) specified with virtual-flash bank registers 0 and 1, the internal RAM area is accessed. During virtual-flash emulation mode, RAM data can read and written to and from both the internal RAM area and the virtual-flash setup area. Figure 13 Virtual-Flash Emulation Areas of the M32170F6VFP (Replaced in Units of 4 Kbytes) 22 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Internal flash > H'0000 0000 H'0000 2000 H'0000 4000 L bank 0 (8K bytes) L bank 1 (8K bytes) L bank 2 (8K bytes) < Internal RAM > 8K bytes H'0080 4000 H'0080 6000 8K bytes 8K bytes 4K bytes 4K bytes H'0080 8000 H'0007 C000 H'0007 E000 L bsnk 62 (8K bytes) L bank 63 (8K bytes) Note 1: If the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is enabled, the corresponding internal RAM area is assigned to either bank register according to the priority FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1. Note 2: When access is made to the 8-Kbyte area (L bank) specified with virtual-flash bank registers 0-2, the internal RAM area is accessed. During virtual-flash emulation mode, RAM data can read and written to and from both the internal RAM area and the virtual-flash setup area. Figure 14 Virtual-Flash Emulation Areas of the M32170F4VFP (Replaced in Units of 8 Kbytes) < Internal flash > H'0000 0000 H'0000 1000 H'0000 2000 S bank 0 (4K bytes) S bank 1 (4K bytes) S bank 2 (4K bytes) < Internal RAM > H'0080 4000 8K bytes 8K bytes 8K bytes H'0007 E000 H'0007 F000 S bank 126 (4K bytes) S bank 127 (4K bytes) 4K bytes 4K bytes H'0080 A000 H'0080 B000 Note 1: If the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is enabled, the corresponding internal RAM area is assigned to either bank register according to the priority FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1. Note 2: When access is made to the 4-Kbyte area (S bank) specified with virtual-flash bank registers 0 and 1, the internal RAM area is accessed. During virtual-flash emulation mode, RAM data can read and written to and from both the internal RAM area and the virtual-flash setup area. Figure 15 Virtual-Flash Emulation Areas of the M32170F4VFP (Replaced in Units of 4 Kbytes) The table below shows Virtual-Flash Emulation Areas of the M32170F4 and M32170F3. Table 12 Virtual-Flash Emulation Areas of the M32170F4 and M32170F3 Type M32170F4VFP,M32170F4VWG M32170F3VFP,M32170F3VWG Virtual-Flash Emulation Areas H’ 0000 0000 - H’ 0007 FFFF H’ 0000 0000 - H’ 0005 FFFF 23 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Internal flash > H'0000 0000 H'0000 2000 H'0000 4000 L bank 0 (8K bytes) L bank 1 (8K bytes) L bank 2 (8K bytes) < Internal RAM > H'0080 4000 8K bytes H'0080 6000 8K bytes H'0080 8000 8K bytes 4K bytes 4K bytes H'0080 C000 H'0080 DFFF H'0007 C000 H'0007 E000 L bank 62 (8K bytes) L bank 63 (8K bytes) 8K bytes Note 1: If the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is enabled, the corresponding internal RAM area is assigned to either bank register according to the priority FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1. Note 2: When access is made to the 8-Kbyte area (L bank) specified with virtual-flash bank registers 0-2, the internal RAM area is accessed. During virtual-flash emulation mode, RAM data can read and written to and from both the internal RAM area and the virtual-flash setup area. Note 3: Internal RAM area (H’0080 C000-H’0080 DFFF) cannot be used as Virtual Flash Emulation area. Figure 16 Virtual-Flash Emulation Areas of the M32174F4VFP (Replaced in Units of 8 Kbytes) < Internal flash > H'0000 0000 H'0000 1000 H'0000 2000 S bank 0 (4K bytes) S bank 1 (4K bytes) S bank 2 (4K bytes) < Internal RAM > H'0080 4000 8K bytes 8K bytes 8K bytes H'0007 E000 H'0007 F000 S bank 126 (4K bytes) S bank 127 (4K bytes) 4K bytes 4K bytes 8K bytes H'0080 A000 H'0080 B000 H'0080 C000 H'0080 DFFF Note 1: If the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is enabled, the corresponding internal RAM area is assigned to either bank register according to the priority FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1. Note 2: When access is made to the 4-Kbyte area (S bank) specified with virtual-flash bank registers 0 and 1, the internal RAM area is accessed. During virtual-flash emulation mode, RAM data can read and written to and from both the internal RAM area and the virtual-flash setup area. Note 3: Internal RAM area (H’0080 C000-H’0080 DFFF) cannot be used as Virtual Flash Emulation area. Figure 17 Virtual-Flash Emulation Areas of the M32174F4VFP (Replaced in Units of 4 Kbytes) The table below shows Virtual-Flash Emulation Areas of the M32174F4 and M32174F3. Table 13. Virtual-Flash Emulation Areas of the M32174F4 and M32174F3 Type Name M32174F4VFP,M32174F4VWG M32174F3VFP,M32174F3VWG Virtual-Flash Emulation Areas H’ 0000 0000 - H’ 0007 FFFF H’ 0000 0000 - H’ 0005 FFFF 24 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Input/output Ports The microcomputer has a total of 157 input/output ports P0-P22. (However, P5 is reserved for future use.) The input/ output ports can be used as input ports or output ports by setting up their direction registers. Each input/output port is a dual-function pin shared with Table 14 Outline of Input/output Ports Item Number of Port Specification Total 157 ports P0 P1 P2 P3 P4 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 Port function : : : : : : : : : : : : : : : : : : : : : : P00 - P07 P10 - P17 P20 - P27 P30 - P37 P41 - P47 P61 - P67 P70 - P77 P82 - P87 P93 - P97 P100 - P107 P110 - P117 P124 - P127 P130 - P137 P140 - P147 P150 - P157 P160 - P167 P172 - P177 P180 - P187 P190 - P197 P200 - P203 P210 - P217 P220 - P225 (8 lines) (8 lines) (8 lines) (8 lines) (7 lines) (7 lines) (8 lines) (6 lines) (5 lines) (8 lines) (8 lines) (4 lines) (8 lines) (8 lines) (8 lines) (8 lines) (6 lines) (8 lines) (8 lines) (4 lines) (8 lines) (6 lines) otherinternal peripheral I/O or external extended bus signal lines. These pin functions are selected by using the chip operation mode select or the input/output port operation mode registers. These input/output ports are interfaced using a dedicated power supply to allow for connections to the peripheral circuits operating with 5V or 3.3V. The input/output ports can be set for input or output mode bitwise by using the input/output port ___ direction control register. (However, P64 is an SBI input-only port, and P221 is CAN input-only port.) Dual-functions shared with peripheral I/O or external extended signals (or multi-functions shared with peripheral I/Os which have multiple functions.) P0-4, P225, P225 : Changed by setting CPU operation mode (MOD0 and MOD1 pins) P6-22 : Changed by setting the input/output port operation mode register. (However, peripheral I/O pin functions are selected using the peripheral I/O register.) Pin function Pin function changeover Table 15 CPU Operation Modes and P0-P4, P224, and P225 Pin Functions MOD0 VSS VSS VCCE VCCE MOD1 VSS VCCE VSS VCC Operation mode Single-chip mode External extended mode External extended signal pin Processor mode (FP pin = VSS) Reserved (use inhibited) – Pin functions of P0-P4, P224, P225 nput/output port pin Note: VCC and VSS are connected to +5 V and GND, respectively. 25 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 0 P0 P1 CPU operation mode settings (Note1) P2 P3 P4 DB0 DB8 A23 A15 1 DB1 DB9 A24 A16 BLW 2 DB2 DB10 A25 A17 BHW 3 DB3 DB11 A26 A18 RD 4 DB4 DB12 A27 A19 CS0 5 DB5 DB13 A28 A20 CS1 6 DB6 DB14 A29 A21 A13 7 DB7 DB15 A30 A22 A14 (Reserved) P5 P6 P7 P8 P9 P10 P11 P12 P13 Input/output port operation mode register settings P14 P15 P16 P17 P18 P19 P20 P21 P22 TO29 TIN26 TXD4 TO37 CTX TIN16 TIN8 TIN0 TO21 TO8 TO0 BCLK (P61) WAIT (P62) HREQ TXD0 (P63) HACK RXD0 TO16 SBI SCLKI4/ SCLKO4 SCLKI5/ SCLKO5 ADTRG RTDTXD RTDRXD RTDACK RTDCLK SCLKI0/ SCLKO0 TXD1 TO18 TO13 TO5 TCLK1 TIN21 TIN13 TIN5 TO26 RXD2 TO34 TIN31 RXD1 TO19 TO14 TO6 TCLK2 TIN22 TIN14 TIN6 TO27 TXD3 TO35 TIN32 SCLKI1/ SCLKO1 TO17 TO12 TO4 TCLK0 TO20 TO15 TO7 TCLK3 TIN23 TIN15 TIN7 TO28 RXD3 TO36 TIN33 TO9 TO1 TO10 TO2 TO11 TO3 TIN17 TIN9 TIN1 TO22 TIN18 TIN10 TIN2 TO23 TIN24 TIN19 TIN11 TIN3 TO24 TIN25 TO32 TIN29 RXD5 TO40 (P223) TIN20 TIN12 TIN4 TO25 TXD2 TO33 TIN30 TO30 TIN27 RXD4 TO38 CRX TO31 TIN28 TXD5 TO39 (P222) TO41 A11 (Note2) TO42 A12 (Note2) TO43 TO44 Note 1: The pin function are selected by setting the MOD0 and MOD1 pins. Note 2: The pin function are selected by setting the MOD0 and MOD1 pins. Also, use of this pin requires caution because it has a debug event function. Figure 18 Input/output Ports and Pin Function Assignments 26 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Built-in 10-Channel DMAC The microcomputer contains 10 channels of DMAC, allowing for data transfer between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and between internal RAMs. DMA transfer requests can be issued from the user-cre ated software, as well as can be triggered by a signal generated by the internal peripheral I/O (A-D converter, MJT, or serial I/O). The microcomputer also supports cascaded connection between DMA channels (starting DMA transfer on a channel at end of transfer on another channel). This makes advanced transfer processing possible without causing any additional CPU load. Table 16 Outline of the DMAC Item Number of channels Transfer request Content 10 channels • Software trigger • R equest from internal peripheral I/O: A-D converter, multijunction timer, or serial I/O (reception completed, transmit buffer empty) • Cascaded connection between DMA channels possible (Note) 256 times • 64 Kbytes (address space from H’0080 0000 to H’0080 FFFF) • Transfers between internal peripheral I/Os, between internal RAM and internal peripheral IO, and between internal RAMs are supported Transfer data size Transfer method 16 bits or 8 bits Single transfer DMA (control of the internal bus is relinquished for each transfer performed), dual-address transfer Single transfer mode One of three modes can be selected for the source and destination of transfer: • Address fixed • Address increment • 32-channel ring buffer Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7 > channel 8 > channel 9 (Fixed priority) 13.3 Mbytes per second (when internal peripheral clock = 20 MHz) Group interrupt request can be generated when each transfer count register underflows 64 Kbytes from H’0080 0000 to H’0080 FFFF (Transfer is possible in the entire internal RAM/SFR area) Note: The following DMA channels can be cascaded. DMA transfer on channel 1 started at end of one DMA transfer on channel 0 DMA transfer on channel 2 started at end of one DMA transfer on channel 1 DMA transfer on channel 0 started at end of one DMA transfer on channel 2 DMA transfer on channel 4 started at end of one DMA transfer on channel 3 DMA transfer on channel 6 started at end of one DMA transfer on channel 5 DMA transfer on channel 7 started at end of one DMA transfer on channel 6 DMA transfer on channel 5 started at end of one DMA transfer on channel 7 DMA transfer on channel 9 started at end of one DMA transfer on channel 8 DMA transfer on channel 5 started at end of all DMA transfers on channel 0 (underflow of transfer count register) Maximum number of times transferred Transferable address space Transfer mode Direction of transfer Channel priority Maximum transfer rate Interrupt request Transfer area 27 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Internal bus DMA channel 0 Software start One DMA2 transfer completed A-D0 conversion completed MJT (TIO8_udf) MJT (input event bus 2) DMA request selector Source Destination Transfer count udf DMA channel 1 Software start MJT (output event bus 0) MJT (TIN13 input signal) One DMA0 transfer completed DMA request selector Source Destination Transfer count udf DMA channel 2 Software start MJT (output event bus 0) MJT (TIN18 input signal) One DMA1 transfer completed DMA request selector Source Destination Transfer count udf DMA channel 3 Software start Serial I/O0 (transmit buffer empty) Serial I/O1 (reception completed) MJT (TIN0 input signal) DMA request selector Source Destination Transfer count udf DMA channel 4 Software start One DMA3 transfer completed Serial I/O0 (reception completed) MJT (TIN19 input signal) DMA request selector Source Destination Transfer count udf Interrupt request DMA start Determination block Software start One DMA7 transfer completed All DMA0 transfer completed (udf) Serial I/O2 (reception completed) MJT (TIN20 input signal) DMA channel 5 DMA request selector Source Destination Transfer count udf Internal bus arbitration DMA channel 6 Software start Serial I/O1 (transmit buffer empty) MJT (TIN1 input signal) One DMA5 transfer completed DMA channel 7 Software start Serial I/O2 (transmit buffer empty) MJT (TIN2 input signal) One DMA6 transfer completed DMA request selector Source Destination Transfer count udf DMA request selector Source Destination Transfer count udf DMA channel 8 Software start MJT (intput event bus 0) Serial I/O3 (reception completed) MJT (TIN7 input signal) DMA request selector Source Destination Transfer count udf DMA channel 9 Software start Serial I/O3 (transmit buffer empty) MJT (TIN8 input signal) One DMA8 transfer completed DMA request selector Source Destination Transfer count udf Interrupt request DMA start Determination block Internal bus arbitration Figure 19 Block Diagram of the DMAC 28 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Built-in 64-Channel Multijunction Timers (MJT) The microcomputer contains a total of 64 channels of multijunction timers consisting of 35 channels of 16-bit output related timers, 10 channels of 16-bit input/output related timers, 11 channels of 16-bit input related timers, eight channels of 32-bit input related timers. Each timer has multiple operation modes to choose from, depending on the purposes of use. Also, the maltijunction timers internally have a clock bus, input event bus, and an output event bus, so that multiple timers can be used in combination allowing for a flexible timer configuration. The output related timers have a correcting function that allows the timer’s count value to be incremented or decremented as necessary while count is in progress, making real time output control possible. Input event bus TCLK pin E/L Output related timer : 35ch Input/output related timer : 10ch 16-bit input related timer : 11ch 32-bit input related timer : 8ch · · · CLK Timer Output event bus Clock bus To DMAC, A-D converter Interrupt output F/F TO pin EN 1/2 internal peripheral clock PRS CLK Timer · · · · Interrupt output EN F/F TO pin E /L PRS : Edge/Level selector : Prescaler TIN pin E/L : Junction box (Selector) F/F Note: This is a conceptual diagram and does not show the actual timer configuration. : Output flip-flop Figure 20 Conceptual Diagram of the Multijunction Timer (MJT) 29 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 17 Outline of Multijunction Timers (1/2) Name TOP (Timer Output) Type Output-related 16-bit timer (down-counter) Number of channels 11 Content One of three input modes can be selected in software. < With correction function > • Single-shot output mode • Delayed single-shot output mode < Without correction function > • Continuous output mode TIO (Timer Input Output) Input/output-related 16-bit timer (down-counter) 10 One of three input modes or four output modes can be selected by software. < Input modes > • Measure clear input mode • Measure free-run input mode • Noise processing input mode < Output mode without correction function • PWM output mode • Single-shot output mod • Delayed single-shot output mode • Continuous output mode TMS (Timer Measure Small) TML (Timer Measure Large) TID (Timer Input Derivation) Input-related 16-bit timer (up counter) Input-related 32-bit timer (up counter) Input-related 16-bit timer (up counter) 3 One of three input modes can be selected in software. • Fixed cycle mode • Event count mode • Multiply-by-4 event count mode 8 32-bit input measure timer. 8 16-bit input measure timer. 30 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Table 18 Outline of Multijunction Timers (2/2) Name TOD (Timer output Modification) Type output-related 16-bit timer (down-counter) Number of channels 16 Content One of four output modes can be selected in software. < No correction function > • PWM output mode • Single-shot output mode • Delayed single-shot output mode • Continuous output mode TOM (Timer output Modification) output-related 16-bit timer (down-counter) 8 One of four output modes can be selected in software. < No correction function > • PWM output mode • Single-shot PWM output mode • One-shot output mode • Continuous output mode 31 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Clock bus Input event bus clk S TCLK0 TCLK0S IRQ9 Output event bus IRQ2 0123 3210 3210 en en en en en en en TOP 0 TOP 1 TOP 2 TOP 3 TOP 4 TOP 5 TOP 6 udf IRQ2 F/F0 F/F1 IRQ2 TO 0 TO 1 TO 2 TO 3 TO 4 TO 5 TO 6 clk clk S DRQ7 udf udf IRQ2 F/F2 F/F3 IRQ2 TIN0 TIN0S clk clk clk udf udf IRQ2 F/F4 F/F5 IRQ1 udf udf IRQ1 IRQ9 S S clk S F/F6 TIN1 TIN1S DRQ8 clk S en TOP 7 udf IRQ6 S F/F7 TO 7 IRQ9 S S clk clk clk en en en TOP 8 TOP 9 TOP 10 TIO 0 TIO 1 TIO 2 TIO 3 TIO 4 udf IRQ6 S S IRQ5 F/F8 F/F9 F/F10 F/F11 F/F12 F/F13 F/F14 TO 8 TO 9 TO 10 TO 11 TO 12 TO 13 TO 14 TIN2 TIN2S DRQ9 IRQ12 udf udf IRQ0 S S IRQ0 S S clk clk TIN3 TIN4 TIN5 TIN3S TIN4S TIN5S en/cap en/cap en/cap en/cap en/cap udf udf IRQ0 IRQ12 S S IRQ0 IRQ12 S clk S clk udf udf S IRQ4 IRQ12 S S clk udf S F/F15 TO 15 TIN6 1/2 internal peripheral clock TIN6S PRS0 PRS1 PRS2 S IRQ4 IRQ8 TCLK1 TIN7 TCLK2 TIN8 TCLK1S TIN7S S S clk en/cap TIO 5 udf IRQ4 S F/F16 TO 16 DRQ10 TCLK2S TIN8S IRQ8 S S clk en/cap TIO 6 udf IRQ4 S F/F17 TO 17 DRQ11 IRQ8 S S clk en/cap TIO 7 udf DRQ0 IRQ3 S F/F18 TO 18 TIN9 TIN9S IRQ8 S S clk TIN10 TIN10S IRQ8 en/cap TIO 8 udf IRQ3 S F/F19 TO 19 S S 3210 3210 clk TIN11 TIN11S en/cap TIO 9 udf 0123 F/F20 TO 20 PRS0-5 : Prescaler F/F : Output flip-flop S : Selector Figure 21 Block Diagram of Multijunction Timers (MJT) (1/4) 32 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Clock bus 3210 Input event bus 3210 Output event bus 0123 TCLK3 TCLK3S IRQ10 S S IRQ10 clk cap3 TMS 0 cap2 cap1 IRQ7 cap0 ovf TIN12 TIN13 TIN12S TIN13S DRQ3 IRQ10 S TIN14 TIN14S IRQ10 S TIN15 TIN15S S IRQ7 S IRQ10 clk cap3 S TMS 1 cap2 cap1 cap0 ovf TIN16 TIN16S IRQ10 TIN17 TIN17S IRQ10 S TIN18 TIN18S DRQ5 IRQ10 S TIN19 1/2 internal peripheral clock TIN19S DRQ6 S S clk cap3 S IRQ11 DRQ12 IRQ11 TML0 cap2 cap1 cap0 TIN20 TIN21 TIN22 TIN23 1/2 internal peripheral clock TIN20S TIN21S S IRQ11 TIN22S IRQ11 S S S clk IRQ18 TIN23S cap3 S TML1 cap2 cap1 cap0 AD0TRG (To A-D converter) DRQ2 TIN30 TIN31 TIN32 TIN33 TIN30S TIN31S TIN32S IRQ18 S IRQ18 S IRQ18 TIN33S S DRQ4 3210 3210 0123 S : Serector Figure 22 Block Diagram of Multijunction Timers (MJT) (2/4) 33 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Clock bus 3210 Input event bus 3210 IRQ13 clk clk clk clk TOD0_0 TOD0_1 TOD0_2 TOD0_3 TOD0_4 TOD0_5 TOD0_6 TOD0_7 udf udf IRQ13 udf IRQ13 udf IRQ13 udf IRQ13 clk clk clk udf IRQ13 udf IRQ13 udf ovf udf IRQ14 IRQ13 Output event bus 0123 F/F21 F/F22 F/F23 F/F24 F/F25 F/F26 F/F27 F/F28 TO21 TO22 TO23 TO24 TO25 TO26 TO27 TO28 1/2 internal peripheral clock PRS3 clk clk CLK1 CLK2 TID0 TIN24 TIN25 clk clk clk clk clk PRS4 clk clk clk EN EN EN EN EN EN EN EN TOD1_0 TOD1_1 TOD1_2 TOD1_3 TOD1_4 TOD1_5 TOD1_6 TOD1_7 IRQ16 udf IRQ16 udf IRQ16 udf IRQ16 udf IRQ16 udf IRQ16 udf IRQ16 udf IRQ16 udf IRQ15 ovf udf IRQ16 clk clk clk clk clk PRS5 clk clk clk EN EN EN EN EN EN EN EN TOM0_0 TOM0_1 TOM0_2 TOM0_3 TOM0_4 TOM0_5 TOM0_6 TOM0_7 udf IRQ16 udf IRQ16 udf IRQ16 udf IRQ16 udf IRQ16 udf IRQ16 udf IRQ16 udf ovf udf IRQ17 F/F44 TO44 F/F43 TO43 F/F42 TO42 F/F41 TO41 F/F40 TO40 F/F39 TO39 F/F38 TO38 F/F37 TO37 AD1TRG (To A-D converter) F/F36 TO36 F/F35 TO35 F/F34 TO34 F/F33 TO33 F/F32 TO32 F/F31 TO31 F/F30 TO30 F/F29 TO29 1/2 internal peripheral clock TIN26 TIN27 clk CLK1 CLK2 TID1 1/2 internal peripheral clock clk CLK1 CLK2 TID2 TIN28 TIN29 3210 3210 0123 Figure 23 Block Diagram of Multijunction Timers (MJT) (3/4) 34 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Clock bus 3210 Input event bus 3210 Output event bus 0123 AD0 completed TIO8-udf S DMA0 udf end DMAIRQ0 TIN13 S DMA1 udf end udf udf end DMAIRQ0 TIN18 S DMA2 DMAIRQ0 TIN0 SIO0-TXD SIO1-RXD S DMA3 udf end DMAIRQ0 SIO0-RXD TIN19 S DMA4 udf DMAIRQ0 SIO2-RXD TIN20 S DMA5 udf end DMAIRQ1 SIO1-TXD TIN1 S DMA6 udf end DMAIRQ1 TIN2 SIO2-TXD S DMA7 udf end DMAIRQ1 SIO3-RXD S TIN7 DMA8 udf end DMAIRQ1 SIO3-TXD TIN8 S DMA9 udf DMAIRQ1 3210 3210 0123 S : Selector Figure 24 Block Diagram of Multijunction Timers (MJT) (4/4) 35 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Built-in Two Independent A-D Converters The microcomputer contains two 16-channel converters with 10-bit resolution (A-D0 converter and A-D1 converter). In addition to single conversion on each channel, continuous A-D conversion on a combined group of 4, 8, and 16 channels is possible. The A-D converted value can be read out in either 10 bits or 8 bits. In addition to ordinary A-D conversion, the converters support comparator mode in which the set value and A-D converted value are compared to determine which is larger or smaller than the other. When A-D conversion is finished, the converters can generated a DMA transfer request (A-D0 converter only), as well as an interrupt. The A-D converters are interfaced using a dedicated power supply to allow for connections to the peripheral circuits operating with 5 V or 3.3V. Table 19 Outline of the A-D Converters Item Analog input A-D conversion method Resolution Absolute accuracy (Note 1) (Conditions: Ta = -40 ~ +125°C, AVCC0,1 = VREF0,1 = 5.12V) Conversion mode Operation mode Scan mode Conversion start trigger Content 16 channels × 2 Successive approximation method. 10 bits (Conversion results can be read out in either 10 or 8 bits.) Normal rate mode Double rate mode +2 LSB +2 LSB A-D conversion mode,comparator mode Single mode, scan mode Single -shot scan mode, continuous scan mode. Software start Hardware start Started by setting A-D conversion start bit to 1. A-D0 converter started by MJT output event bus 3, A-D1 converter started by TID1 overflow or underflow. _____ Started by external ADTRG pin input. Conversion rate f(BCLK) : Internal peripheral clock operating frequency During single mode (Shortest time ) During comparator mode (Shortest time ) Normal Double speed Normal Double speed 299 × 1/ f (BCLK) (Note 2) 173 × 1/ f (BCLK) 47 × 1/ f (BCLK) 29 × 1/ f (BCLK) Interrupt request generation When A-D conversion is finished, when comparate operation is finished, when single-shot scan is finished, or when one cycle of continuous scan is finished. DMA transfer request generation (Note 3) When A-D conversion is finished, when comparate operation is finished, when single-shot scan is finished, or when one cycle of continuous scan is finished. Note 1: The rated value of conversion accuracy here is that of the microcomputer's own as a single unit which can be exhibited when the microcomputer is used in an environment where it may not be affected by the power supply wiring or noise on the board. Note 2: When BCLK = 20 MHz, this is1/f (BCLK) = 50ns. Note 3: The DMA transfer request generation function is available for only the A-D0 converter. The A-D1 converter does not have this function. 36 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Internal data bus 8-bit readout 10-bit readout Shifter AD0DT0 AD0DT1 AD0DT2 AD0DT3 AD0DT4 AD0DT5 AD0DT6 AD0DT7 AD0DT8 AD0DT9 AD0DT10 AD0DT11 AD0DT12 AD0DT13 AD0DT14 AD0DT15 AD0CMP P67/ADTRG AVCC0 AVSS0 10-bit A-D0 Data Register 0 10-bit A-D0 Data Register 1 10-bit A-D0 Data Register 2 10-bit A-D0 Data Register 3 10-bit A-D0 Data Register 4 10-bit A-D0 Data Register 5 10-bit A-D0 Data Register 6 10-bit A-D0 Data Register 7 10-bit A-D0 Data Register 8 10-bit A-D0 Data Register 9 10-bit A-D0 Data Register 10 10-bit A-D0 Data Register 11 10-bit A-D0 Data Register 12 10-bit A-D0 Data Register 13 10-bit A-D0 Data Register 14 10-bit A-D0 Data Register 15 A-D comparate Data Register A-D Control Circuit 10-bit A-D Successive Approximation Register (AD0SAR) AD0SIM0,1 AD0SCM0,1 Single Mode Register Scan Mode Register Output event bus 3 (Multijunction timer) VREF0 10-bit D-A Converter Comparator • Mode selection • Channel selection Interrupt request • Conversion time selection • Flag control DMA transfer request • Interrupt control AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AD0IN8 AD0IN9 AD0N10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 Selector Successive Approximation -type A-D Converter Unit Figure 25 Block Diagram of the A-D0 Converter 37 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Internal data bus 8-bit readout 10-bit readout Shifter AD1DT0 AD1DT1 AD1DT2 AD1DT3 AD1DT4 AD1DT5 AD1DT6 AD1DT7 AD1DT8 AD1DT9 AD1DT10 AD1DT11 AD1DT12 AD1DT13 AD1DT14 AD1DT15 AD1CMP P67/ADTRG AVCC1 AVSS1 10-bit A-D1 Data Register 0 10-bit A-D1 Data Register 1 10-bit A-D1 Data Register 2 10-bit A-D1 Data Register 3 10-bit A-D1 Data Register 4 10-bit A-D1 Data Register 5 10-bit A-D1 Data Register 6 10-bit A-D1 Data Register 7 10-bit A-D1 Data Register 8 10-bit A-D1 Data Register 9 10-bit A-D1 Data Register 10 10-bit A-D1 Data Register 11 10-bit A-D1 Data Register 12 10-bit A-D1 Data Register 13 10-bit A-D1 Data Register 14 10-bit A-D1 Data Register 15 A-D Comparate Data Register A-D Control Circuit 10-bit A-D Successive Approximation Register (AD1SAR) AD1SIM0,1 AD1SCM0,1 Single Mode Register Scan Mode Register TID1 underflow /overflow VREF1 10-bit D-A Converter Comparator • Mode selection • Channel selection Interrupt request • Conversion time selection • Flag control • Interrupt control AD1IN0 AD1IN1 AD1IN2 AD1IN3 AD1IN4 AD1IN5 AD1IN6 AD1IN7 AD1IN8 AD1IN9 AD1N10 AD1IN11 AD1IN12 AD1IN13 AD1IN14 AD1IN15 Selector Successive Approximation -type A-D Converter Unit Note: The A-D converter does not have DMA transfer request generation function. Figure 26 Block Diagram of the A-D1 Converter 38 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 6-channel High-speed Serial I/Os The microcomputer contains six channels of serial I/Os consisting of four channels that can be set for CSIO mode (clock-synchronized serial I/O) or UART mode (asynchronous serial I/O) and two other channels that can only be set for UART mode. The SIO has the function to generate a DMA transfer request when data reception is completed or the transmit register becomes empty, and is capable of high-speed serial communication without causing any additional CPU load. Table 20 Outline of Serial I/O Item Number of channels Content CSIO/UART: 4 channels (SIO0,SIO1,SIO4,SIO5) UART only : 2 channels (SIO2,SIO3) Clock During CSIO mode : Internal clock / external clock, selectable (Note1) During UART mode : Internal clock only Transfer mode BRG count sourcef Data format Transmit half-duplex, receive half-duplex, transmit/receive full-duplex (BCLK), f(BCLK)/8, f(BCLK)/32, f(BCLK)/256 (When internal clock is selected) (Note2) CSIO mode : Data length = Fixed to 8 bits Order of transfer = Fixed to LSB first UARTmode : Start bit = 1 bit Character length = 7, 8, or 9 bits Parity bit = Added or not added (When added, selectable between odd and even parity) Stop bit = 1 or 2 bits Order of transfer = Fixed to LSB first Baud rate CSIO mode : UARTmode : Error detection CSIO mode : UARTmode : 152 bits per second to 2 Mbits per second (when operating with f(BCLK) = 20 MHz) 19 bits per second to 156 Kbits per second (when operating with f(BCLK) = 20 MHz) Overrun error only Overrun, parity, and framing errors (The error-sum bit indicates which error has occurred) Fixed cycle clock output function Note 1: During CSIO mode, the maximum input frequency of an external clock is f(BCLK) divided by 16. Note 2: When f(BCLK) is selected for the BRG count source, the BRG set value is subject to limitations. When SIO0, SIO1, SIO4, or SIO5 is in UART mode, this function outputs a 1/2 BRG clock from the SCLK pin. 39 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER SIO0 SIO0 Transmit Buffer Register Transmit interrupt TXD0 SIO0 Transmit Shift Register Transmit/ receive control circuit Receive interrupt Transmit DMA transfer request Receive DMA transfer request To interrupt controller RXD0 SIO0 Receive Shift Register To DMAC3 To DMAC4 SIO0 Receive Buffer Register UART Mode CSIO Mode When extended clock selected When internal clock selected BCLK Clock divider CSIO Mode When internal clock selected When UART mode selected SIO1 TXD1 SIO1 Transmit Shift Register Transmit interrupt Transmit/ receive control circuit Receive interrupt Transmit DMA transfer request Receive DMA transfer request Internal data bus BCLK, BCLK/8, BCLK/32, BCLK/256 1/16 1 (Set value + 1) Baud rate generator (BRG) 1/2 SCLKI0/ SCLKO0 To interrupt controller To DMAC6 To DMAC3 SCLKI1/ SCLKO1 RXD1 SIO1 Receive Shift Register SIO2 TXD2 SIO2 Transmit Shift Register Transmit interrupt Transmit/ receive control circuit Receive interrupt Transmit DMA transfer request Receive DMA transfer request To DMAC7 To DMAC5 RXD2 SIO2 Receive Shift Register SIO3 TXD3 SIO3 Transmit Shift Register Transmit/ receive control circuit Transmit interrupt Receive interrupt Transmit DMA transfer request Receive DMA transfer request To interrupt controller To DMAC9 To DMAC8 RXD3 SIO3 Receive Shift Register SIO4 TXD4 SIO4 Transmit Shift Register Transmit interrupt Transmit/ receive control circuit Receive interrupt RXD4 SIO4 Receive Shift Register SCLKI4 / SCLKO4 SIO5 TXD5 SIO5 Transmit Shift Register Transmit interrupt Transmit/ receive control circuit Receive interrupt To interrupt controller RXD5 SIO5 Receive Shift Register SCLKI5 / SCLKO5 Note 1: When BCLK is selected, the BRG set value is subject to limitations. Note 2: SIO2 and SIO3 do not have the SCLKI/SCLKO function. Figure 27 Block Diagram of Serial I/O 40 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER CAN Module The M32170 and M32174 Group contains two Full CAN modules compliant with CAN Specification V2.0B (CAN0 and CAN1), each of which has 16-channel message slots and three mask registers. Data bus CAN0 Status Register CAN0 REC Register CAN0 TEC Register CAN0 Message Slot 0-15 Control Register CAN0 Extended Register CAN0 Configuration Register CAN0 Control Register CAN0 Global Mask Register CAN0 Local Mask Register A CAN0 Local Mask Register B Message Memory (1) Message ID (2) Data length code (3) Message data (4) Time stamp CAN0 Slot Status Register CAN0 Slot Interrupt Control Register CAN0 Error Interrupt Control Register Interrupt Control Circuit CAN0 Transmit/Receive & Error Interrupt CTX CAN0 Protocol Controller 2.0B active Acceptance Filtering 16-bit Timer CAN0 Time Stamp Register CRX Figure 28 Block Diagram of the CAN Module 41 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 8-level Interrupt Controller The Interrupt Controller controls interrupt requests from each internal peripheral I/O (31 sources) by using eight priority levels assigned to each interrupt source, including interrupts disabled. In addition to these interrupts, it handles System Break Interrupt (SBI), Reserved Instruction Exception (RIE), and Address Exception (AE) as nonmaskable interrupts. Realtime Debugger (RTD) The Realtime Debugger (RTD) provides a function for accessing directly from the outside to the internal RAM. It uses a dedicated clock-synchronized serial I/O to communicate with the outside. Use of the RTD communicating via dedicated serial lines allows the internal RAM to be read out and rewritten without having to halt the CPU. Wait Controller The Wait Controller supports access to external devices. For access to an external extended area of up to 1 Mbytes (during external extended or processor mode), the Wait Controller controls bus cycle extension by inserting one to ____ four wait cycles or using external WAIT signal input. 32170, 32174 Group RTDCLK RTDRXD M32R CPU Internal RAM Virtual-DPRAM structure Real-Time Debugger (RTD) RTDTXD RTDACK Command address Data Data Data R/W without CPU intervention Data Bus(CPU) Data Bus(RTD) Figure 29 Conceptual Diagram of the Realtime Debugger (RTD) 42 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER CPU Instruction Set The M32R employs a RISC architecture, supporting a total of 83 discrete instructions. • Arithmetic operation ADD ADD3 ADDI ADDV ADDV3 ADDX NEG SUB SUBV SUBX Add Add 3-operand Add immediate Add (with overflow checking) Add 3-operand Add with carry Negate Subtract Subtract (with overflow checking) Subtract with borrow (1) Load/store instructions Perform data transfer between memory and registers. LD LDB LDUB LDH LDUH LOCK ST STB STH UNLOCK Load Load byte Load unsigned byte Load halfword Load unsigned halfword Load locked Store Store byte Store halfword Store unlocked • Multiplication/division DIV DIVU MUL REM REMU Divide Divide unsigned Multiply Remainder Remainder unsigned (2) Transfer instructions Perform register to register transfer or register to immediate transfer. LD24 LDI MV MVFC MVTC SETH Load 24-bit immediate Load immediate Move register Move from control register Move to control register Set high-order 16-bit • Shift SLL SLL3 SLLI SRA SRA3 SRAI SRL SRL3 SRLI Shift Shift Shift Shift Shift Shift Shift Shift Shift left logical left logical 3-operand left logical immediate right arithmetic right arithmetic 3-operand right arithmetic immediate right logical right logical 3-operand right logical immediate (5) Instructions for the DSP function (3) Branch instructions Used to change the program flow. BC Branch on C-bit BEQ Branch on equal BEQZ Branch on equal zero BGEZ Branch on greater than or equal zero BGTZ Branch on greater than zero BL Branch and link BLEZ Branch on less than or equal zero BLTZ Branch on less than zero BNC Branch on not C-bit BNE Branch on not equal BNEZ Branch on not equal zero BRA Branch JL Jump and link JMP Jump NOP No operation Perform 32 bit × 16 bit or 16 bit × 16 bit multiplication or sumof-products calculation. These instructions also perform rounding of the accumulator data or transfer between accumulator and general-purpose register. MACHI MACLO MACWHI MACWLO MULHI MULLO MULWHI MULWLO MVFACHI MVFACLO MVFACMI MVTACHI MVTACLO RAC RACH Multiply-accumulate high-order halfwords Multiply-accumulate low-order halfwords Multiply-accumulate word and high-order halfword Multiply-accumulate word and low-order halfword Multiply high-order halfwords Multiply low-order halfwords Multiply word and high-order halfword Multiply word and low-order halfword Move from accumulator high-order word Move from accumulator low-order word Move from accumulator middle-order word Move to accumulator high-order word Move to accumulator low-order word Round accumulator Round accumulator halfword (4) Arithmetic/logic instructions Perform comparison, arithmetic/logic operation, multiplication/division, or shift between registers. • Comparison CMP CMPI CMPU CMPUI Compare Compare immediate Compare unsigned Compare unsigned immediate • Logical operation AND AND3 NOT OR OR3 XOR XOR3 AND AND 3-operand Logical NOT OR OR 3-operand Exclusive OR Exclusive OR 3-operand (6) EIT related instructions Start trap or return from EIT processing. RTE TRAP Return from EIT Trap 43 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER < Multiply instruction > 0 H Rsrc1 15 16 L 31 0 H Rsrc2 15 16 L 31 < Multiply-accumulate instruction > 0 ACC 63 0 H Rsrc1 15 16 L 31 0 H Rsrc2 15 16 L 31 × × MULHI instruction 0 ACC MULLO instruction 63 × × + + Rsrc2 15 16 MACHI instruction 0 31 L 0 63 ACC ACC MACLO instruction 63 0 Rsrc1 32 bit 31 0 H × × MULWHI instruction 0 ACC MULWLO instruction 63 0 Rsrc1 32 bit 31 0 H Rsrc2 15 16 L 31 × × + < Ropund off instruction > 0 ACC RAC instruction sign data 0 0 15 16 63 MACWHI instruction 0 ACC + MACWLO instruction 63 0 63 < Accumulator - register transfer instruction > MVFACMI instruction 31 32 ACC MVFACHI instruction MVFACLO instruction 1 Rdest 0 MVTACHI instruction 31 32 ACC 0 ACC RACH instruction 63 47 48 63 0 Rsrc 31 MVTACLO instruction 63 0 sign 63 data 0 0 Figure 30 Instructions for the DSP Function 44 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER Package Dimensions Diagram 240P6Y-A EIAJ Package Code QFP240-P-3232-0.50 JEDEC Code – HD D 240 1 181 180 Plastic 240pin 32✕32mm body QFP Weight(g) Lead Material Cu Alloy e MD b2 I2 Recommended Mount Pad HE E Symbol A A1 A2 b c D E e HD HE L L1 y c 60 61 120 121 e F A L1 A2 b y L Detail F b2 I2 MD ME Dimension in Millimeters Max Nom Min 4.1 – – 0.35 0.45 0.25 3.6 – – 0.3 0.2 0.15 0.2 0.15 0.13 32.1 32.0 31.9 32.1 32.0 31.9 0.5 – – 34.8 34.6 34.4 34.8 34.6 34.4 0.7 0.5 0.3 1.3 – – 0.1 – – 10° 0° – – 0.225 – – – 1.2 – 32.6 – – 32.6 – A1 ME 45 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER 255F7F EIAJ Package Code – JEDEC Code – Weight(g) 255pin 17✕17mm body FBGA Under Development 17TYP (16.6) 0.20 C A 0.8✕19=15.2 0.35±0.05 0.8TYP A Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0.8✕19=15.2 17TYP (16.6) B 0.20 C B ✕4 0.2 C 255-φ0.45±0.05 1.2MAX φ0.08 M C AB Note: 255FBGA is currently under development. 46 0.8TYP 0.1 C 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170 Group, 32174 Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER MEMO 47 2001-5-14 Rev.1.0 Mitsubishi Microcomputers 32170Group, 32174Group SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials • • • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 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The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. • • • • • © 2001 MITSUBISHI ELECTRIC CORP. New publication, effective May 2001. Specifications subject to change without notice. Revision Description List Rev. No. Page 1.0 First Edition 32170 Group, 32174 Group Data Sheet Revision Description Point Rev. date 010514 (1/1)