M34282M2-XXXGP

MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER DESCRIPTION The 4282 Group enables fabrication of 8 × 7 key matrix and has the followin timers; • an 8-bit timer which can be used to set each carrier wave and has two reload register • an 8-bit timer which can be used to auto-control and has a reload register. FEATURES • Number of basic instructions ............................................. 68 • Minimum instruction execution time ............................ 8.0 µs (at f(XIN) = 4.0 MHz, system clock = f(XIN)/8) • Supply voltage ................................................. 1.8 V to 3.6 V • Subroutine nesting ..................................................... 4 levels • Timer Timer 1 ................................................................... 8-bit timer (This has a reload register and carrier wave output auto-control function) Timer 2 ................................................................... 8-bit timer (This has two reload registers and carrier wave output function) • Logic operation function (XOR, OR, AND) • RAM back-up function • Key-on wakeup function (ports D4–D7, E0–E2, G0–G3) .... 11 • I/O port (ports D, E, G, CARR) .......................................... 16 • Oscillation circuit ..................................... Ceramic resonance • Watchdog timer • Power-on reset circuit • Voltage drop detection circuit ......................... Typical:1.50 V (system reset) APPLICATION Various remote control transmitters Product M34282M1-XXXGP M34282M2-XXXGP M34282E2GP ROM (PROM) size (× 9 bits) 1024 words 2048 words 2048 words RAM size (× 4 bits) 48 words 64 words 64 words Package 20P2E/F-A 20P2E/F-A 20P2E/F-A ROM type Mask ROM Mask ROM One Time PROM PIN CONFIGURATION (TOP VIEW) VSS E2 E1 XIN XOUT E0 G0 G1 G2 G3 1 2 20 19 VDD CARR D0 D1 D2 D3 D4 D5 D6 D7 M34282Mx-XXXGP 3 4 5 6 7 8 9 10 18 17 16 15 14 13 12 11 Outline 20P2E/F-A 2 BLOCK DIAGRAM 1 2 4 4 4 I/O port Port E Port D Port G Internal peripheral function System clock generation circuit XIN -XOUT Timer/Remote-control carrier-wave output Timer 1 (8 bits, carrier wave output control) Timer 2 (8 bits, carrier wave generation) Reset (voltage drop detection circuit) Watchdog timer (14 bits) MITSUBISHI ELECTRIC Memory (Note) ROM (1024,2048 words ✕ 9 bits) 720 series CPU core ALU(4 bits) Register A (4 bits) Register B (4 bits) Register E (8 bits) Register D (3 bits) Stack register SK (4 levels) RAM (48,64 words ✕ 4 bits) MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER 4282 Group Note: PROM 2048 words ✕ 9 bits, RAM 64 words ✕ 4 bits for built-in PROM version. MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PERFORMANCE OVERVIEW Parameter Number of basic instructions Function 68 Minimum instruction execution time 8.0 µs (f(XIN) = 4.0 MHz, system clock = f(XIN)/8, VDD = 3 V) Memory sizes ROM M34282M2/E2 2048 words ✕ 9 bits RAM Input/Output ports 1024 words ✕ 9 bits M34282M1 M34282M2/E2 64 words ✕ 4 bits 48 words ✕ 4 bits M34282M1 Four independent output ports Four independent I/O ports with the pull-down function 3-bit input port with the pull-down function 2-bit output port (E0, E1) 4-bit I/O port with the pull-down function 1-bit output port; CMOS output 8-bit timer with a reload register 8-bit timer with two reload registers 4 levels (However, only 3 levels can be used when the TABP p instruction is executed) CMOS silicon gate 20-pin plastic molded SSOP (20P2E/F-A) –20 °C to 85 °C 1.8 V to 3.6 V D0–D3 Output D4–D7 I/O E0–E2 Input E0, E1 Output G0–G3 I/O CARR Output Timer Timer 1 Timer 2 Subroutine nesting Device structure Package Operating temperature range Supply voltage Power Active mode 400 µA dissipation (f(XIN) = 4.0 MHz, system clock = f(XIN)/8, VDD = 3 V) (typical value) RAM back-up mode 0.1 µA (at room temperature, VDD = 3 V) PIN DESCRIPTION Pin VDD VSS XIN XOUT D0–D3 D4–D7 Name Power supply Ground System clock input System clock output Output port D I/O port D Input/Output Function — Connected to a plus power supply. — Input Output Output I/O Connected to a 0 V power supply. I/O pins of the system clock generating circuit. Connect a ceramic resonator between pins XIN and XOUT. The feedback resistor is built-in between pins XIN and XOUT. Each pin of port D has an independent 1-bit wide output function. The output structure is P-channel open-drain. 1-bit I/O port. For input use, set the latch of the specified bit to “0.” When the builtin pull-down transistor is turned on, the key-on wakeup function using “H” level sense and the pull-down transistor become valid. The output structure is P-channel open-drain. E0–E2 I/O port E Output Input 2-bit (E0, E1) output port. The output structure is P-channel open-drain. 3-bit input port. For input use (E0, E1), set the latch of the specified bit to “0.” When the built-in pull-down transistor is turned on, the key-on wakeup function using “H” level sense and the pull-down transistor become valid. Port E2 has an input-only port and has a key-on wakeup function using “H” level sense and pulldown transistor. G0–G3 I/O port G I/O 4-bit I/O port. For input use, set the latch of the specified bit to “0.” The output structure is P-channel open-drain. When the built-in pull-down transistor is turned on, the keyon wakeup function using “H” level sense and pull-down transistor become valid. CARR Carrier wave output for remote control Output Carrier wave output pin for remote control. The output structure is CMOS circuit. MITSUBISHI ELECTRIC 3 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER CONNECTIONS OF UNUSED PINS Pin D0–D7 E 0, E 1 E2 G0–G3 Connection Open or connect to VDD pin (Note 1). Set the output latch to “ 1 ” a nd open, or connect to VDD pin (Note 2). Open or connect to VSS pin. Set the output latch to “ 1 ” a nd open, or connect to VDD pin (Note 2). Notes 1: Ports D4–D7: Set the bit 2 (PU02) of the pull-down control register PU1 to “0” by software and turn the pull-down transistor OFF. 2: Set the corresponding bits of the pull-down control register PU0 to “0” by software and turn the pull-down transistor OFF. (Note in order to set the output latch to “1” to make pins open) • After system is released from reset, a port is in a high-impedance state until the output latch of the port is set to “1” by software. Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur. • To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away (caused by noise). (Note when connecting to VSS and VDD) • Connect the unused pins to VSS or VDD at the shortest distance and use the thick wire against noise. PORT FUNCTION Port Port D Pin D0–D3 Input/ Output Output structure Control bits 1 bit Control instructions SD RD CLD SD RD CLD SZD Port E E0 E1 E2 Port G G 0– G 3 I/O (2) Input (1) I/O (4) Port CARR CARR Output CMOS (1) 1 bit P-channel open-drain P-channel open-drain Output: OEA 2 bits Input: 3 bits 4 bits IAE IAE OGA IAG SCAR RCAR PU0 Pull-down function and key-on wakeup function (programmable) PU0 PU1 Pull-down function and key-on wakeup function (programmable) Pull-down function and key-on wakeup function (programmable) Control registers Remark Output P-channel open-drain (4) I/O (4) D4–D7 DEFINITION OF CLOCK AND CYCLE • System clock (STCK) The system clock is the source clock for controlling this product. It can be selected as shown below whether to use the CCK instruction. CCK instruction When not using When using System clock f(XIN)/8 f(XIN) Instruction clock f(XIN)/32 f(XIN)/4 • Instruction clock (INSTCK) The instruction clock is a signal derived by dividing the system clock by 4, and is the basic clock for controlling CPU. The one instruction clock cycle is equivalent to one machine cycle. • Machine cycle The machine cycle is the cycle required to execute the instruction. 4 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PORT BLOCK DIAGRAMS Register Y SD instruction RD instruction Decoder (Note 1) S R CLD instruction Q Ports D 0–D3 Register Y SD instruction RD instruction Decoder (Note 1) SQ R Ports D 4–D7 (Note 5) CLD instruction Skip decision (SZD instruction) Key-on wakeup (Note 2) PU1i Register A Aj (Note 3) Aj Key-on wakeup input (Note 3) PU0j IAE instruction Register A A2 Key-on wakeup input Pull-down transistor Pull-down transistor DQ OEA instruction IAE instruction T (Note 1) Pull-down transistor Ports E 0, E1 (Note 5) Port E 2 (Note 5) (Note 1) Register A Aj (Note 3) Aj Key-on wakeup input PU02 Register A Ak (Note 4) Ak Key-on wakeup input Pull-down transistor PU03 CAR flag SCAR instruction RCAR instruction CARRYD (from timer 2) SQ R OGA instruction DQ T IAG instruction Pull-down transistor OGA instruction DQ T IAG instruction (Note 1) Ports G 0, G1 (Note 5) (Note 1) Ports G 2, G3 (Note 5) CARRY (to timer 1) (Note 1) Port CARR Timer 1 underflow signal V12 DQ TR V10 Carrier wave output control signal Notes 1: This symbol represents a parasitic diode. 2: i represents bits 0 to 3. 3: j represents bits 0, 1. 4: k represents bits 2, 3. 5: Applied voltage must be less than VDD. MITSUBISHI ELECTRIC 5 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER FUNCTION BLOCK OPERATIONS CPU (CY) (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-bit data addition, comparison, and bit manipulation. (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A0 i s stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction. (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4). (M(DP)) Addition (A) Fig. 1 AMC instruction execution example ALU SC instruction RC instruction CY A3 A2 A1 A0 RAR instruction A0 CY A3 A2 A1 Fig. 2 RAR instruction execution example Register B TAB instruction Register A B3 B2 B1 B0 A3 A2 A1 A0 TEAB instruction Register E ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 TABE instruction B3 B2 B1 B0 Register B A3 A2 A1 A0 TBA instruction Register A Fig. 3 Registers A, B and register E TABP p instruction Specifying address 8 ROM 4 0 Low-order 4 bits p3 PCH p2 p1 p0 PCL DR2 DR1 DR0 A3 A2 A1 A0 Register A (4) Middle-order 4 bits Register B (4) Most significant 1 bit Carry flag CY (1) Immediate field value p The contents of register D The contents of register A URS flag (1) URSC instruction Fig. 4 TABP p instruction execution example 6 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (5) Most significant ROM code reference enable flag (URS) URS flag controls whether to refer to the contents of the most significant 1 bit (bit 8) of ROM code when executing the TABP p instruction. If URS flag is “0,” the contents of the most significant 1 bit of ROM code is not referred even when executing the TABP p instruction. However, if URS flag is “1,” the contents of the most significant 1 bit of ROM code is set to flag CY when executing the TABP p instruction (Figure 4). URS flag is “0” after system is released from reset and returned from RAM back-up mode. It can be set to “1” with the URSC instruction, but cannot be cleared to “0.” (6) Stack registers (SKs) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when; • performing a subroutine call, or • executing the table reference instruction (TABP p). Stack registers (SKs) are four identical registers, so that subroutines can be nested up to 4 levels. However, one of stack registers is used when executing a table reference instruction. Accordingly, be careful not to over the stack. The contents of registers SKs are destroyed when 4 levels are exceeded. The register SK nesting level is pointed automatically by 2-bit stack pointer (SP). Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call. (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. Note : The 4282 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped. Program counter (PC) Executing BM instruction SK0 SK1 SK2 SK3 Executing RT instruction (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 Stack pointer (SP) points “3” at reset or returning from RAM back-up mode. It points “0” by executing the first BM instruction, and the contents of program counter is stored in SK0. When the BM instruction is executed after four stack registers are used ((SP) = 3), (SP) = 0 and the contents of SK0 is destroyed. Fig. 5 Stack registers (SKs) structure (SP) ← 0 (SK0) ← 000116 (PC) ← SUB1 Main program Address 000016 NOP 000116 BM SUB1 000216 NOP Subroutine SUB1 : NOP · · · RT (PC) ← (SK0) (SP) ← 3 Note: R eturning to the BM instruction execution address with the RT instruction, and the BM instruction is equivalent to the NOP instruction. Fig. 6 Example of operation at subroutine call MITSUBISHI ELECTRIC 7 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PCH (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PCH does not exceed after the last page of the built-in ROM. (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers X and Y. Register X specifies a file and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9). Program counter (PC) p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0 PCH Specifying page PCL Specifying address Fig. 7 Program counter (PC) structure Data pointer (DP) X1 X0 Y3 Y2 Y1 Y0 Register Y (4) Specifying RAM digit Register X (2) Specifying RAM file Fig. 8 Data pointer (DP) structure Specifying bit position Set D7 D5 D0 0 101 Register Y (4) 1 Port D output latch Fig. 9 SD instruction execution example 8 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PROGRAM MEMORY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 9 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 ROM size and pages Product M34282M2/E2 M34282M1 ROM size (✕ 9 bits) 2048 words 1024 words Pages 16 (0 to 15) 8 (0 to 7) 8 000016 007 F16 008016 00FF16 010016 017 F16 018016 7 6 5 4 3 2 10 Page 0 Page 1 Subroutine special page Page 2 Page 3 Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern of all addresses can be used as data areas with the TABP p instruction. 07FF16 Page 15 Fig. 10 ROM map of M34282M2/E2 DATA MEMORY (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers X and Y. Set a value to the data pointer certainly when executing an instruction to access RAM. Table 2 shows the RAM size. Figure 11 shows the RAM map. Table 2 RAM size Product M34282M2/E2 M34282M1 RAM 64 words ✕ 4 bits (256 bits) Register X 01 23 RAM size 64 words ✕ 4 bits (256 bits) 48 words ✕ 4 bits (192 bits) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 64 words M34282M2/E2 Fig. 11 RAM map MITSUBISHI ELECTRIC Register Y 48 words M34282M1 9 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER TIMERS The 4282 Group has the programmable timer. • Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer 1 underflow flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function). FF16 n: Counter initial value Count starts n The contents of counter Reload Reload 1st underflow 2nd underflow 0016 Time n+1 count Timer 1 underflow flag “1” “0” A skip instruction is executed n+1 count Fig. 12 Auto-reload function The 4282 Group timer consists of the following circuit. • Timer 1 : 8-bit programmable timer • Timer 2 : 8-bit programmable timer These timers can be controlled with the timer control registers V1 and V2. Each timer function is described below. Table 3 Function related timer Circuit Timer 1 Timer 2 14-bit timer Structure 8-bit programmable binary down counter 8-bit programmable binary down counter Frequency Use of output signal dividing ratio • Carrier wave output control • Carrier wave output (CARRY) 1 to 256 Count source • Bit 5 of watchdog timer • f(XIN) • f(XIN)/2 16384 • Watchdog timer • Timer 1 count source 1 to 256 • Carrier wave output Control register V1 V2 14-bit fixed frequency • Instruction clock 10 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER V10 (Note 1) V11 0 1 SNZT1 instruction Timer 1 (8) CARRY 0 1 T1F Timer 1 underflow signal (to port CARR) Reload register R1 (8) (T1AB)(Note 2) (TAB1) Register B Register A (TAB1) Register B Register A (T2HAB) Reload register R2H (8) V20 (Note 1) 0 1 V23 Timer 2(8) Reload control circuit T R Q SNZT2 instruction T2F T2F (TAB2) CARRYD (to port CARR) V21 XIN 1/2 0 1 (Note 3) (T2R2L) (T2AB) V22 (T2AB) Reload register R2L (8) (TAB2) Register B Register A CAR flag SCAR instruction RCAR instruction SQ R CARRY (to timer 1) Port CARR Timer 1 underflow signal DQ TR Carrier wave output control signal V12 V10 Frequency divider (divided by 8) STCK (System clock) Frequency divider (divided by 4) INSTCK (Instruction clock) XIN CCK instruction Initializing signal (Note 3) SQ R Synchronous circuit Initializing signal (Note 4) System reset 13 WDF1 WDF2 14-bit timer (WDT) INSTCK 0 5 WRST instruction Initializing signal (Note 4) Notes 1: Counting is stopped by clearing to “0.” 2: When the T1AB instruction is executed after V1 0 is set to “1,” writing is performed only to reload register R1. 3: The data of reload register R2L set with the T2AB instruction can be also written to timer 2 with the T2R2L instruction. 4: The initializing signal is output at reset or RAM back-up mode. Fig. 13 Timers structure MITSUBISHI ELECTRIC 11 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Table 4 Control registers related to timer Timer control register V1 V12 V11 V10 Carrier wave output auto-control bit Timer 1 count source selection bit Timer 1 control bit 0 1 0 1 0 1 at reset : 0002 at RAM back-up : 0002 W Auto-control output by timer 1 is invalid Auto-control output by timer 1 is valid Carrier wave output (CARRY) Bit 5 of watchdog timer (WDT) Stop (Timer 1 state retained) Operating at reset : 00002 at RAM back-up : 00002 W Timer control register V1 V13 V12 V11 V10 Carrier wave “H” interval expansion bit Carrier wave generation function control bit Timer 2 count source selection bit Timer 2 control bit 0 1 0 1 0 1 0 1 To expand “H” interval is invalid To expand “H” interval is valid (when V22=1 selected) Carrier wave generation function invalid Carrier wave generation function valid f(XIN) f(XIN)/2 Stop (Timer 2 state retained) Operating Note: “W” represents write enabled. (1) Control registers related to timer • Timer control register V1 Register V1 controls the timer 1 count source and autocontrol function of carrier wave output from port CARR by timer 1. Set the contents of this register through register A with the TV1A instruction. • Timer control register V2 Register V2 controls the timer 2 count source and the carrier wave generation function by timer. Set the contents of this register through register A with the TV2A instruction. (2) Precautions Note the following for the use of timers. • Count source Stop timer 1 or timer 2 counting to change its count source. • Watchdog timer Be sure that the timing to execute the WRST instruction in order to operate WDT efficiently. • Writing to reload register R1 When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. • Timer 1 count operation When the bit 5 of the watchdog timer (WDT) is selected as the timer 1 count source, the error of maximum ± 256 µs (at the minimum instruction execution time : 8 µ s) is generated from timer 1 start until timer 1 underflow. When programming, be careful about this error. • Stop of timer 2 Avoid a timing when timer 2 underflows to stop timer 2. • Writing to reload register R2H When writing data to reload register R2H while timer 2 is operating, avoid a timing when timer underflows. • Timer 2 carrier wave output function When to expand “H” interval of carrier wave is valid, set “1” or more to reload register R2H. 12 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (3) Timer 1 Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). When timer is stopped, data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. When timer is operating, data can be set to only reload register R1 with the T1AB instruction. When setting the next count data to reload register R1 at operating, set data before timer 1 underflows. Timer 1 starts counting after the following process; ➀ set data in timer 1, ➁ select the count source with the bit 1 of register V1, and ➂ set the bit 0 of register V1 to “1.” Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 underflow flag (T1F) is set to “1,” new data is loaded from reload register R1, and count continues (auto-reload function). When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). When the bit 2 of register V1 is set to “1,” the carrier wave output enable/disable interval of port CARR is alternately generated each timer 1 underflows (Figure 14). Data can be read from timer 1 to registers A and B. When reading the data, stop the counter and then execute the TAB1 instruction. (4) Timer 2 Timer 2 is an 8-bit binary down counter with the timer 2 reload registers (R2H and R2L). Data can be set simultaneously in timer 2 and the reload register (R2L) with the T2AB instruction. The contents of reload register (R2L) set with the T2AB instruction can be set again to timer 2 with the T2R2L instruction. Data can be set to reload register (R2H) with the T2HAB instruction. Timer 2 starts counting after the following process; ➀ set data in timer 2, ➁ select the count source with the bit 1 of register V2, and ➂ select the valid/invalid of the carrier wave generation function by bit 2 of register V1 (when this function is valid, select the valid/invalid of the carrier wave “H” interval expansion by bit 3), and ➃ set the bit 0 of register V1 to “1.” When the carrier wave generation function is invalid (V22=“0”), the following operation is performed; Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes “0”), the timer 2 underflow flag (T2F) is set to “1,” new data is loaded from reload register R2L, and count continues (auto-reload function). When a value set in reload register R2L is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). When the carrier wave generation function is valid (V22=“1”), the carrier wave which has the “L” interval set to the reload register R2L and “H” interval set to the reload register R2H can be output (Figure 15). After the count of the “L” interval of carrier wave is started, timer 2 underflows and the timer 2 underflow flag (T2F) is set to “1”. Then, the “H” interval data of carrier wave is reloaded from the reload register R2H, and count continues. When timer underflows again after auto-reload, the T2F flag is set to “1”. And then, the “L” interval data of carrier wave is reloaded from the reload register R2L, and count continues. After that, each timer underflows, data is reloaded from reload register R2H and R2L alternately. When a value set in reload register R2H is n, “H” interval of carrier wave is as follows; ➀ When to expand “H” interval is invalid (V23 = “0”), Count source ✕ (n+1), n = 0 to 255 ➁ When to expand “H” interval is valid (V23 = “1”), Count source ✕ (n+1.5), n = 1 to 255 When a value set in reload register R2L is m, “L” interval of carrier wave is as follows; Count source ✕ (m+1), m = 0 to 255 Data can be read from timer 2 to registers A and B. When reading the data, stop the counter and then execute the TAB2 instruction. (5) Timer underflow flags (T1F, T2F) Timer 1 underflow flag or timer 2 underflow flag is set to “1” when the timer 1 or timer 2 underflows. The state of flags T1F and T2F can be examined with the skip instruction (SNZT1, SNZT2). Flags T1F and T2F are cleared to “0” when the next instruction is skipped with a skip instruction. MITSUBISHI ELECTRIC 13 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Timer 1 starts Timer 1 underflow “1” “0” “H” (V10)← 1 Port CARR output “L” v v v Set the interval “a” to timer 1. Set the interval “b” Set the interval “c” to reload register R1. to reload register R1. Count source CARRY selected (V11)← 0 (V12)← 1 a b v Set the interval “d” to reload register R1. c d Auto-control valid Carrier wave output start Timer 1 stop (V10)← 0 Timer 1 underflow “1” “0” “H” CARRY “L” Port CARR output (Note) “H” “L” “0” Register V12 “1” Carrier wave output start Auto-control invalid Auto-control invalid Carrier wave output stop Note: When timer 1 is stopped, the port CARR output auto-control is terminated regardless of bit 2 (V12) of register V1. Fig. 14 Port CARR output control by timer 1 q In this case, the following is set; • Timer 2 carrier wave generation function is valid (V22=“1”), • “L” interval (0316) of carrier wave is set to reload register R2L • “H” interval (0216) of carrier wave is set to reload register R2H To expand “H” interval of carrier wave is invalid (V23=“0”) [Count source: 4.0 MHz, Resolution: 250 ns] Timer 2 count source Timer 2 count value 0316 (Reload register) Timer 2 underflow signal CARRYD Timer 2 starts 3 clocks interval 3 clocks interval 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 (R2H) (R2L) (R2H) (R2L) (R2H) (R2L) Carrier wave period: 7 clocks Carrier wave period: 7 clocks To expand “H” interval of carrier wave is valid (V23=“1”) (When count source is 4.0 MHz, carrier wave is expanded for 125 ns] Timer 2 count source Timer 2 count value 0316 (R2L) 0216 0116 0016 0216 (R2H) Timer 2 underflow signal CARRYD Timer 2 starts 3.5 clocks interval 3.5 clocks interval 0116 0016 0316 0216 0116 0016 (R2L) 0216 (R2H) 0116 0016 0316 0216 0116 0016 (R2L) 0216 (R2H) (Reload register) Carrier wave period: 7.5 clocks Carrier wave period: 7.5 clocks Note: When to expand “H” interval of the carrier wave is valid, set “0116” or more to reload register R2H. Fig. 15 Carrier wave generation example by timer 2 14 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER q In this case, the following is set; • To expand “H” interval of carrier wave is invalid (V23 = “0”), • Timer 2 carrier wave generation function is valid (V22=“1”), • Count source XIN/2 selected (V21=“1”), • “L” interval (0316) of carrier wave is set to reload register R2L • “H” interval (0216) of carrier wave is set to reload register R2H Timer 2 count start timing Machine cycle Mi Mi + 1 Mi + 2 TV2A instruction execution cycle (V20) ←1 Instruction clock =f(XIN)/8 XIN XIN/2 (Count source selected) Register V2 0 Timer 2 count value (Reload register) Timer 2 underflow signal CARRYD 0316 (R2L) 0216 0116 0016 0216 0116 0016 0316 0216 (R2H) (R2L) Timer 2 count start timing Timer 2 count stop timing Machine cycle Mi Mi + 1 Mi + 2 TV2A instruction execution cycle (V20)←0 Instruction clock =f(XIN)/8 XIN XIN/2 (Count source selected) Register V2 0 Timer 2 count value (Reload register) Timer 2 underflow signal (Note 1) 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 (R2L) (R2H) (R2L) 0216 (R2H) CARRYD Timer 2 count stop timing Notes 1: When the carrier wave generation function is vaild (V22=“1”), avoid a timing when timer 2 underflows to stop timer 2. When the timer 2 count stop occurs at the same timing with the timer 2 underflows, hazard may occur in the carrier wave output waveform. 2: When the timer 2 is stopped during “H” output of carrier wave while the carrier wave generation function is valid, it is stopped after the “H” interval set by reload register R2H is output. Fig. 16 Timer 2 count start/stop timing MITSUBISHI ELECTRIC 15 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER WATCHDOG TIMER Watchdog timer provides a method to reset and restart the system when a program runs wild. Watchdog timer consists of 14-bit timer (WDT) and watchdog timer flags (WDF1, WDF2). Watchdog timer downcounts the instruction clock (INSTCK) as the count source immediately after system is released from reset. When the timer WDT count value becomes 000016 and underflow occurs, the WDF1 flag is set to “1.” Then, when the WRST instruction is not executed before the timer WDT counts 16383, WDF2 flag is set to “1” and internal reset signal is generated and system reset is performed. Execute the WRST instruction at period of 16383 machine cycle or less to keep the microcomputer operation normal. Timer WDT is also used for generation of oscillation stabilization time. When system is returned from reset and from RAM backup mode by key-input, software starts after the stabilization oscillation time until timer WDT downcounts to 3E0016 elapses. Software start Software start Software start 3FFF16 3E0016 Value of timer WDT 0000 16 WDF1 flag WDF2 flag “1” “0” “1” “0” “ H” “L” POF instruction execution Return Internal reset signal System reset WRST instruction execution System reset Fig. 17 Watchdog timer function LOGIC OPERATION FUNCTION The 4282 Group has the 4-bit logic operation function. The logic operation between the contents of register A and the low-order 4 bits of register E is performed and its result is stored in register A. Table 5 Logic operation selection register LO Logic operation selection register LO Each logic operation can be selected by setting logic operation selection register LO. Set the contents of this register through register A with the TLOA instruction. The logic operation selected by register LO is executed with the LGOP instruction. Table 5 shows the logic operation selection register LO. at RAM back-up : 002 W at reset : 002 LO1 LO0 LO1 Logic operation selection bits LO0 Note: “W” represents write enabled. 0 0 1 1 Logic operation function 0 Exclusive logic OR operation (XOR) 1 OR operation (OR) 0 AND operation (AND) 1 Not available 16 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER RESET FUNCTION The 4282 Group has the power-on reset circuit, though it does not have RESET pin. System reset is performed automatically at power-on, and software starts program from address 0 in page 0. In order to make the built-in power-on reset circuit operate efficiently, set the voltage rising time until VDD = 0 to 2.2 V is obtained at power-on 1ms or less. f(XIN) Internal reset signal “H” “L” f(X IN) 16384 pulses Software operation starts (address 0 in page 0) Fig. 18 Reset release timing VDD Internal reset signal Power-on reset circuit Power-on reset circuit output voltage Reset state Voltage drop detection circuit Watchdog timer output Internal reset signal Reset released Power-on Fig. 19 Power-on reset circuit example MITSUBISHI ELECTRIC 17 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (1) Internal state at reset Table 6 shows port state at reset, and Figure 20 shows internal state at reset (they are retained after system is released from reset). The contents of timers, registers, flags and RAM except shown in Figure 20 are undefined, so set the initial value to them. • Program counter (PC) .............................................................. 0 Address 0 in page 0 is set to program counter. • Power down flag (P) ................................................................. 0 • Timer 1 underflow flag (T1F) ................................................... 0 • Timer 2 underflow flag (T2F) ................................................... 0 • Timer control register V1 .......................................................... 0 • Timer control register V2 .......................................................... 0 • Port CARR output flag (CAR) .................................................. 0 • Pull-down control register PU0 ................................................ 0 • Pull-down control register PU1 ................................................ 0 • Logic operation selection register LO ...................................... 0 • Most significant ROM code reference enable flag (URS) 0 • Carry flag (CY) ......................................................................... 0 • Register A ................................................................................. 1 • Register B ................................................................................. 1 • Register X ................................................................................. 0 • Register Y ................................................................................. 0 • Stack pointer (SP) .................................................................... 1 Fig. 20 Internal state at reset Table 6 Port state at reset Name State at reset D0–D3 High impedance state D4–D7 G0–G3 High impedance state (Pull-down transistor OFF) High impedance state (Pull-down transistor OFF) E0, E1 High impedance state (Pull-down transistor OFF) CARR “L” output Note: The contents of all output latch is initialized to “0.” 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 0 1 1 0 VOLTAGE DROP DETECTION CIRCUIT The built-in voltage drop detection circuit is designed to detect a drop in voltage at operating and to reset the microcomputer if the supply voltage drops below the specified value (Typ. 1.50 V) or less. The voltage drop detection circuit is stopped and power dissipation is reduced in the RAM back-up mode with the initialized CPU stopped. VDD Reset voltage (Note) TYP 1.5V Internal reset signal Microcomputer starts operation after f(X IN) is counted to 16384 times. Note: The voltage drop detection circuit does not have the hysteresis characteristics in the detected voltage. Fig. 21 Voltage drop detection circuit operation waveform 18 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER RAM BACK-UP MODE The 4282 Group has the RAM back-up mode. When the POF instruction is executed, system enters the RAM back-up state. As oscillation stops retaining RAM, the functions and states of reset circuit at RAM back-up mode, power dissipation can be reduced without losing the contents of RAM. Table 7 shows the function and states retained at RAM back-up. Figure 22 shows the state transition. (1) Warm start condition When the external wakeup signal is input after the system enters the RAM back-up state by executing the POF instruction, the CPU starts executing the software from address 0 in page 0. In this case, the P flag is “1.” (2) Cold start condition The CPU starts executing the software from address 0 in page 0 when any of the following conditions is satisfied . • reset by power-on reset circuit is performed • reset by watchdog timer is performed • reset by voltage drop detection circuit is performed In this case, the P flag is “0.” (3) Identification of the start condition Warm start (return from the RAM back-up state) or cold start (return from the normal reset state) can be identified by examining the state of the power down flag (P) with the SNZP instruction. Table 7 Functions and states retained at RAM back-up RAM back-up Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Port CARR Ports D0–D7 Ports E0, E1 Port G Timer control registers V1, V2 Pull-down control registers PU0, PU1 Logic operation selection register LO Timer 1 function, Timer 2 function Timer underflow flags (T1F, T2F) Watchdog timer (WDT) Watchdog timer flags (WDF1, WDF2) MostsignificantROMcodereferenceenableflag(URS) ✕ O ✕ O O O ✕ O ✕ ✕ ✕ ✕ ✕ ✕ Notes 1: “O” represents that the function can be retained, and “✕” represents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2:The stack pointer (SP) points the level of the stack register and is initialized to “112” at RAM back-up. A (Stabilizing time a ) Reset f(XIN) oscillation POF instruction is executed B f(XIN) stop Return input (Stabilizing time a ) (RAM back-up mode) Stabilizing time a : Microcomputer starts its operation after f(XIN) is counted to16384 times. Fig. 22 State transition Power down flag P POF instruction Reset input S Q Software start P = “1” ? No Cold start Yes R q Set source q Clear source POF instruction is executed Reset input Warm start Fig. 23 Set source and clear source of the P flag Fig. 24 Start condition identified example using the SNZP instruction MITSUBISHI ELECTRIC 19 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (4) Return signal An external wakeup signal is used to return from the RAM back-up mode. Table 8 shows the return condition for each return source. Table 8 Return source and return condition Return source Ports D4–D7 Ports E0, E1, G Ports E2 Return condition Remarks Return by an external “ H ” l evel Only key-on wakeup function of the port whose pull-down transistor is input. turned ON by register PU1 is valid. Return by an external “ H ” l evel Only key-on wakeup function of the port whose pull-down transistor is input. turned ON by register PU0 is valid. Return by an external “ H ” l evel Key-on wakeup function is always valid. input. (5) Pull-down control register Registers PU0 and PU1 are 4-bit registers and control the ON/OFF of pull-down transistor and key-on wakeup function for ports E0, E1, G and ports D4–D7. Table 9 Pull-down control registers Pull-down control register PU0 PU03 PU02 PU01 PU00 Ports G2, G3 pull-down transistor control bit Ports G0, G1 pull-down transistor control bit Port E1 pull-down transistor control bit Port E0 pull-down transistor control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained W Set the contents of register PU0 or PU1 through register A with the TPU0A or TPU1A instruction, respectively. Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down control register PU1 PU13 PU12 PU11 PU10 Port D7 pull-down transistor control bit Port D6 pull-down transistor control bit Port D5 pull-down transistor control bit Port D4 pull-down transistor control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained W Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Note: “ W ” r epresents write enabled. 20 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER CLOCK CONTROL The clock control circuit consists of the following circuits. • System clock generating circuit • Control circuit to stop the clock oscillation • Control circuit to return from the RAM back-up state CCK instruction XIN XOUT Frequency divider (divided by 8) OSC Multiplexer Internal clock generation circuit (divided by 4) STCK Internal power-on reset circuit INSTCK POF instruction R S Q Pull-down control register PU0 Pull-down control register 1 Ports E0,E1,G0–G3 Ports D4–D7 Port E2 Fig. 25 Clock control circuit structure System clock signal f(XIN) is obtained by externally connecting a ceramic resonator. Connect this external circuit to pins XIN and XOUT at the shortest distance as shown Figure 26. A feedback resistor is built-in between XIN pin and XOUT pin. 4282 XIN 4 XOUT 5 ROM ORDERING METHOD Please submit the information described below when ordering Mask ROM. (1) Mask ROM Order Confirmation Form* (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk. * For the mask ROM confirmation, refer to the “Mitsubishi MCU Technical Information” Homepage (http:// www.infomicom.maec.co.jp/indexe.htm). CIN Use the resonator manufacturer’s recommended value because constants such as capacitance depend on the resonator. COUT Fig. 26 Ceramic resonator external circuit MITSUBISHI ELECTRIC 21 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER LIST OF PRECAUTIONS ➀ Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; • connect a bypass capacitor (approx. 0.01 µF) between pins VDD and VSS at the shortest distance, • equalize its wiring in width and length, and • use the thickest wire. In the One Time PROM version, port E2 is also used as VPP pin. Connect this pin to VSS through the resistor about 5 kΩ which is assigned to E2/V PP pin as close as possible at the shortest distance. ➁ Notes on unused pins (Note in order to set the output latch to “0” to make pins open) • After system is released from reset, a port is in a highimpedance state until the output latch of the port is set to “0” by software. Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur. • To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away (caused by noise). (Note when connecting to VSS and VDD) • Connect the unused pins to V SS and VDD at the shortest distance and use the thick wire against noise. ➂ Timer • Count source Stop timer 1 or timer 2 counting to change its count source. • Watchdog timer Be sure that the timing to execute the WRST instruction in order to operate WDT efficiently. • Writing to reload register R1 When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. • Timer 1 count operation When the bit 5 of the watchdog timer (WDT) is selected as the timer 1 count source, the error of maximum ± 256 µs (at the minimum instruction execution time : 8 µ s) is generated from timer 1 start until timer 1 underflow. When programming, be careful about this error. • Stop of timer 2 Avoid a timing when timer 2 underflows to stop timer 2. • Writing to reload register R2H When writing data to reload register R2H while timer 2 is operating, avoid a timing when timer underflows. • Timer 2 carrier wave output function When to expand “H” interval of carrier wave is valid, set “1” or more to reload register R2H. ➃ Program counter Make sure that the program counter does not specify after the last page of the built-in ROM. 22 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER INSTRUCTIONS The 4282 Group has the 68 instructions. Each instruction is described as follows; (1) List of instruction function (2) Machine instructions (index by alphabet) (3) Machine instructions (index by function) (4) Instruction code table SYMBOL The symbols shown below are used in the following list of instruction function and the machine instructions. Symbol A B DR ER V1 V2 PU0 PU1 LO X Y DP PC PCH PCL SK SP CY R1 T1 T1F R2H R2L T2 T2F WDT WDF1 WDF2 URS P STCK INSTCK Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Timer control register V1 (3 bits) Timer control register V2 (4 bits) Pull-down control register PU0 (4 bits) Pull-down control register PU1 (4 bits) Logic operation selection register LO (2 bits) Register X (2 bits) Register Y (4 bits) Data pointer (6 bits) (It consists of registers X and Y) Program counter (11 bits) High-order 4 bits of program counter Low-order 7 bits of program counter Stack register (11 bits ✕ 4) Stack pointer (2 bits) Carry flag Timer 1 reload register Timer 1 Timer 1 underflow flag Timer 2 reload register Timer 2 reload register Timer 2 Timer 2 underflow flag Watchdog timer Watchdog timer flag 1 Watchdog timer flag 2 Most significant ROM code reference enable flag Power down flag System clock Instruction clock M(DP) a p, a C + x ← ↔ ? () — Direction of data movement Data exchange between a register and memory Decision of state shown before “?” Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p3 p2 p1 p0 Hex. number C + Hex. number x (also same for others) j A3A2A1A0 Contents D E G CARR CAR x y p n Symbol Port D (8 bits) Port E (3 bits) Port G (4 bits) Port CARR (1 bit) CAR flag (1 bit) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant which represents the immediate value Hexadecimal constant which represents the immediate value Binary notation of hexadecimal variable A (same for others) Contents Note : The 4282 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped. MITSUBISHI ELECTRIC 23 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER LIST OF INSTRUCTION FUNCTION Grouping Mnemonic Function (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) (ER7–ER4) ← (B) (ER3–ER0) ← (A) Page 38 40 Grouping Mnemonic Function (A) ← n n = 0 to 15 Page 31 TAB TBA LA n TABP p Register to register transfer (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p p=0 to 15 (PCL) ← (DR2–DR0, A3–A0) When URS=0 (B) ← (ROM(PC))7 to 4 (A) ← (ROM(PC))3 to 0 When URS=1 (CY) ← (ROM(PC))8 (B) ← (ROM(PC))7 to 4 (A) ← (ROM(PC))3 to 0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 39 TAY TYA TEAB 40 42 41 TABE (B) ← (ER7–ER4) (A) ← (ER3–ER0) 39 TDA LXY x, y (DR2–DR0) ← (A2–A0) (X) ← x, x = 0 to 3 (Y) ← y, y = 0 to 15 40 31 RAM addresses INY DEY TAM j (Y) ← (Y) + 1 (Y) ← (Y) – 1 (A) ← (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 Arithmetic operation AM AMC (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry 27 27 31 30 40 An (A) ← (A) + n n = 0 to 15 27 SC 43 RC SZC 43 CMA RAR LGOP (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → C Y → A 3 A 2A 1A 0 Logic operation instruction XOR, OR, AND 35 33 37 30 33 31 XAM j (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 XAMD j (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (Y) ← (Y) – 1 RAM to register transfer XAMI j (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (Y) ← (Y) + 1 43 SB j (Mj(DP)) ← 1 j = 0 to 3 34 Bit operation RB j (Mj(DP)) ← 0 j = 0 to 3 33 SZB j (Mj(DP)) = 0 ? j = 0 to 3 37 24 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Grouping Mnemonic Function (A) = (M(DP)) ? (A) = n ? n = 0 to 15 Page 36 35 Grouping Mnemonic Function (V12–V10) ← (A2–A0) (B) ← (T17–T14) (A) ← (T13–T10) Page 42 39 Comparison operation SEAM SEA n TV1A TAB1 Ba (PCL) ← a6–a0 (PCH) ← p (PCL) ← a6–a0 (PCL) ← (a6–a4, A3–A0) (PCH) ← p (PCL) ← (a6–a4, A3–A0) 27 28 T1AB at timer 1 stop (V10=0): (R17–R14) ← (B) (T17–T14) ← (B) (R13–R10) ← (A) (T13–T10) ← (A) at timer 1 operating (V10=1): (R17–R14) ← (B) (R13–R10) ← (A) 37 Branch operation BL p, a BA a BLA p, a 28 28 SNZT1 (T1F) = 1 ? After skipping the next instruction (T1F) ← 0 36 BM a (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← 2 (PCL) ← a6–a0 28 Subroutine operation TV2A BML p, a (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p p= 0 to 15 (PCL) ← a6–a0 BMLA p, (SP) ← (SP) + 1 (SK(SP)) ← (PC) a (PCH) ← p p= 0 to 15 (PCL) ← (a6–a4, A3–A0) T2HAB 29 29 TAB2 (V23–V20) ← (A3–A0) (B) ← (T27–T24) (A) ← (T23–T20) 42 39 Timer operation T2AB (R2L7–R2L4) ← (B) (T27–T24) ← (B) (R2L3–R2L0) ← (A) (T23–T20) ← (A) (R2H7–R2H4) ← (B) (R2H3–R2H0) ← (A) 38 38 Return operation RT (PC) ← (SK(SP)) (SP) ← (SP) – 1 34 T2R2L (T27–T24) ← (R2L7–R2L4) (T27–T24) ← (R2L3–R2L0) 38 RTS (PC) ← (SK(SP)) (SP) ← (SP) – 1 34 SNZT2 (T2F) = 1 ? After skipping the next instruction (T2F) ← 0 36 MITSUBISHI ELECTRIC 25 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER LIST OF INSTRUCTION FUNCTION (CONTINUED) Grouping Mnemonic Function (D) ← 0 (D(Y)) ← 0 (Y) = 0 to 7 (D(Y)) ← 1 (Y) = 0 to 7 (D(Y)) = 0 ? (Y) = 4 to 7 (E1, E0) ← (A1, A0) (A2–A0) ← (E2–E0) (G) ← (A) (A) ← (G) (CAR) ← 1 (CAR) ← 0 Page 29 34 CLD RD SD 35 Input/Output operation SZD 37 OEA IAE OGA IAG 32 30 32 30 35 33 Carrier wave control operation SCAR RCAR NOP POF SNZP CCK TLOA URSC TPU0A TPU1A WRST (PC) ← (PC) + 1 RAM back-up (P) = 1 ? STCK changes to f(XIN) (LO1, LO0) ← (A1, A0) (URS) ← 1 (PU03–PU00) ← (A3–A0) (PU13–PU10) ← (A3–A0) (WDF1) ← 0 32 32 36 29 41 42 41 41 43 Other operation 26 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) A n (Add n and accumulator) Instrunction code D8 0 1 0 1 0 D0 n3 n2 n1 n0 2 0 A n Number of words 16 Number of cycles 1 Flag CY – Skip condition Overflow = 0 1 Operation: (A) ← (A) + n n = 0 to 15 Grouping: Arithmetic operation Description: Adds the value n in the immediate field to register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. AM (Add accumulator and Memory) Instrunction code D8 0 0 0 0 0 1 0 1 D0 0 2 0 0 A Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (A) + (M(DP)) Grouping: Arithmetic operation Description: Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. AMC (Add accumulator, Memory and Carry) Instrunction code D8 0 0 0 0 0 1 0 1 D0 1 2 0 0 B Number of words 16 Number of cycles 1 Flag CY 0/1 Skip condition – 1 Operation: (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry Grouping: Arithmetic operation Description: Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. B a (Branch to address a) Instrunction code D8 1 1 D0 a6 a5 a4 a3 a2 a1 a0 2 1 8 +a a Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (PCL) ← a6–a0 Grouping: Branch operation Description: Branch within a page : Branches to address a in the identical page. 27 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER BA a (Branch to address a + Accumulator) Instrunction code D8 0 1 Operation: 0 1 0 0 0 0 0 0 D0 1 2 2 0 1 0 8 +a 1 16 a 16 Number of words 2 Number of cycles 2 Flag CY – Skip condition – a6 a5 a4 a3 a2 a1 a0 (PCL) ← a6–a4, A3–A0 Grouping: Branch operation Description: Branch within a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the low-order 4 bits of the address a in the identical page with register A. BL p, a (Branch Long to address a in page p) Instrunction code D8 0 1 Operation: 0 1 0 1 1 D0 p3 p2 p1 p0 2 0 1 3 8 +a p Number of words 16 Number of cycles 2 Flag CY – Skip condition – 2 a6 a5 a4 a3 a2 a1 a0 2 a 16 (PCH) ← (P) (PCL) ← a6–a0 Grouping: Branch operation Description: Branch out of a page : Branches to address a in page p. Note: p is 0 to 7 for M34282M1, p is 0 to 15 for M34282M2/E2. BLA p, a (Branch Long to address a in page p) Instrunction code D8 0 1 Operation: 0 1 0 0 1 0 0 0 D0 0 2 0 1 1 8 +a 0 Number of words 16 Number of cycles 2 Flag CY – Skip condition – 2 a6 a5 a4 p3 p2 p1 p0 2 p 16 (PCH) ← (P) (PCL) ← (a6–a4, A3–A0) Grouping: Branch operation Description: Branch within a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the low-order 4 bits of the address a in page p with register A. Note: p is 0 to 7 for M34282M1, p is 0 to 15 for M34282M2/E2. BM a (Branch and Mark to address a in page 2) Instrunction code D8 1 0 D0 a6 a5 a4 a3 a2 a1 a0 2 1 a a Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PCH) ← 2 (PCL) ← a6–a0 Grouping: Subroutine call operation Description: Call the subroutine in page 2 : Calls the subroutine at address a in page 2. 28 MITSUBISHI MICROCOMPUTERS 4282 Group BML p, a (Branch and Mark Long to address a in page p) Instrunction code D8 0 1 Operation: 0 0 1 1 1 D0 p3 p2 p1 p0 2 0 1 7 a p Number of words 16 Number of cycles 2 Flag CY – Skip condition – 2 a6 a5 a4 a3 a2 a1 a0 2 a 16 (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PCH) ← p (PCL) ← a6–a0 Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address a in page p. Note: p is 0 to 7 for M34282M1, p is 0 to 15 for M34282M2/E2. BMLA p, a (Branch and Mark Long to address a in page p) Instrunction code D8 0 1 Operation: 0 0 1 0 1 0 0 0 D0 0 2 0 1 5 a 0 Number of words 16 Number of cycles 2 Flag CY – Skip condition – 2 a6 a5 a4 p3 p2 p1 p0 2 p 16 (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PCH) ← p (PCL) ← (a6–a4, A3–A0) Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the low-order 4 bits of address a in page p with register A. Note: p is 0 to 7 for M34282M1, p is 0 to 15 for M34282M2/E2. CCK (Change system Clock to f(XIN)) Instrunction code D8 0 0 1 0 1 1 0 0 D0 1 2 0 5 9 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: Change to STCK = f(XIN) Grouping: Other operation Description: Changes system clock (STCK) from f(XIN)/8 to f(XIN). Execute this instruction at address 0 in page 0. CLD (CLear port D) Instrunction code D8 0 0 0 0 1 0 0 0 D0 1 2 0 1 1 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (D) ← 1 Grouping: Input/Output operation Description: Clears (0) to port D (high-impedance state). 29 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER CMA (CoMplement of Accumulator) Instrunction code D8 0 0 0 0 1 1 1 0 D0 02 0 1 C 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (A) ← (A) Grouping: Arithmetic operation Description: Stores the one’s complement for register A’s contents in register A. DEY (DEcrement register Y) Instrunction code D8 0 0 0 0 1 0 1 1 D0 1 2 0 1 7 Number of words 16 Number of cycles 1 Flag CY – Skip condition (Y) = 15 1 Operation: (Y) ← (Y) – 1 Grouping: RAM addresses Description: Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. IAE (Input Accumulator from port E) Instrunction code D8 0 0 1 0 1 0 1 1 D0 0 2 0 5 6 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A2–A0) ← (E2–E0) Grouping: Input/Output operation Description: Transfers the contents of port E to register A. IAG (Input Accumulator from port G) Instrunction code D8 0 0 0 1 0 1 0 0 D0 0 2 0 2 8 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (G) Grouping: Input/Output operation Description: Transfers the contents of port G to register A. 30 MITSUBISHI MICROCOMPUTERS 4282 Group INY (INcrement register Y) Instrunction code D8 0 0 0 0 1 0 0 1 D0 1 2 0 1 3 Number of words 16 Number of cycles 1 Flag CY – Skip condition (Y) = 0 1 Operation: (Y) ← (Y) + 1 Grouping: RAM addresses Description: Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. LA n (Load n in Accumulator) Instrunction code D8 0 1 0 1 1 D0 n3 n2 n1 n0 2 0 B n Number of words 16 Number of cycles 1 Flag CY – Skip condition Continuous description 1 Operation: (A) ← n n = 0 to 15 Grouping: Arithmetic operation Description: Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. LGOP (LoGic OPeration between accumulator and register E) Instrunction code D8 0 0 1 0 0 0 0 0 D0 1 2 0 4 1 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: Logic operation XOR, OR, AND Grouping: Arithmetic operation Description: Executes the logic operation selected by logic operation selection register LO between the contents of register A and register E, and stores the result in register A. LXY x, y (Load register X and Y with x and y) Instrunction code D8 0 1 1 D0 x1 x0 y3 y2 y1 y0 2 0 C +x y Number of words 16 Number of cycles 1 Flag CY – Skip condition Continuous description 1 Operation: (X) ← x, x = 0 to 3 (Y) ← y, y = 0 to 15 Grouping: RAM addresses Description: Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. 31 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER NOP (No OPeration) Instrunction code D8 0 0 0 0 0 0 0 0 D0 02 0 0 0 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (PC) ← (PC) + 1 Grouping: Other operation Description: No operation OEA (Output port E from Accumulator) Instrunction code D8 0 1 0 0 0 0 1 0 D0 02 0 8 4 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (E1, E0) ← (A1, A0) Grouping: Input/Output operation Description: Outputs the contents of register A to port E. OGA (Output port G from Accumulator) Instrunction code D8 0 1 0 0 0 0 0 0 D0 0 2 0 8 0 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (G) ← (A) Grouping: Input/Output operation Description: Outputs the contents of register A to port G. POF (Power OFf1) Instrunction code D8 0 0 0 0 0 1 1 0 D0 1 2 0 0 D Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: RAM back-up Grouping: Other operation Description: Puts the system in RAM back-up state. 32 MITSUBISHI MICROCOMPUTERS 4282 Group RAR (Rotate Accumulator Right) Instrunction code D8 0 0 0 0 1 1 1 0 D0 1 2 0 1 D Number of words 16 Number of cycles 1 Flag CY 0/1 Skip condition – 1 Operation: → C Y → A 3A 2A 1A 0 Grouping: Arithmetic operation Description: Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. RB j (Reset Bit) Instrunction code D8 0 0 1 0 0 1 1 j1 D0 j0 2 0 4 C +j 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (Mj(DP)) ← 0 j = 0 to 3 Grouping: Bit operation Description: Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). RC (Reset Carry flag) Instrunction code D8 0 0 0 0 0 0 1 1 D0 0 2 0 0 6 Number of words 16 Number of cycles 1 Flag CY 0 Skip condition – 1 Operation: (CY) ← 0 Grouping: Arithmetic operation Description: Clears (0) to carry flag CY. RCAR (Reset CAR flag) Instrunction code D8 0 1 0 0 0 0 1 1 D0 0 2 0 8 6 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (CAR) ← 0 Grouping: Carrier wave control operation Description: Clears (0) to port CARR output flag. 33 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER RD (Reset port D specified by register Y) Instrunction code D8 0 0 0 0 1 0 1 0 D0 0 2 0 1 4 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (D(Y)) ← 0 However, (Y) = 0 to 7 Grouping: Input/Output operation Description: Clears (0) to a bit of port D specified by register Y (high-impedance state). RT (ReTurn from subroutine) Instrunction code D8 0 0 1 0 0 0 1 0 D0 0 2 0 4 4 Number of words 16 Number of cycles 2 Flag CY – Skip condition – 1 Operation: (SP) ← (SP) – 1 (PC) ← (SK(SP)) Grouping: Return operation Description: Returns from subroutine to the routine called the subroutine. RTS (ReTurn form subroutine and Skip) Instrunction code D8 0 0 1 0 0 0 1 0 D0 1 2 0 4 5 Number of words 16 Number of cycles 2 Flag CY – Skip condition Skip at uncondition 1 Operation: (SP) ← (SP) – 1 (PC) ← (SK(SP)) Grouping: Return operation Description: Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition. SB j (Set Bit) Instrunction code D8 0 0 1 0 1 1 1 j1 D0 j0 2 0 5 C +j 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (Mj(DP)) ← 0 j = 0 to 3 Grouping: Bit operation Description: Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). 34 MITSUBISHI MICROCOMPUTERS 4282 Group SC (Set Carry flag) Instrunction code D8 0 0 0 0 0 0 1 1 D0 1 2 0 0 7 16 Number of words 1 Number of cycles 1 Flag CY 1 Skip condition – Operation: (CY) ← 1 Grouping: Arithmetic operation Description: Sets (1) to carry flag CY. SCAR (Set CAR flag) Instrunction code D8 0 1 0 0 0 0 1 1 D0 1 2 0 8 7 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (CAR) ← 1 Grouping: Carrier wave control operation Description: Sets (1) to port CARR output flag (CAR). SD (Set port D specified by register Y) Instrunction code D8 0 0 0 0 1 0 1 0 D0 1 2 0 1 5 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (D(Y)) ← 1 (Y) = 0 to 7 Grouping: Input/Output operation Description: Sets (1) to a bit of port D specified by register Y. SEA n (Skip Equal, Accumulator with immediate data n) Instrunction code D8 0 0 Operation: 0 1 0 0 1 1 0 1 0 1 0 D0 1 2 0 0 2 B 5 Number of words 16 Number of cycles 2 Flag CY – Skip condition (A) = n, n = 0 to 15 2 n3 n2 n1 n0 2 (A) = n ? n = 0 to 15 n 16 Grouping: Comparison operation Description: Skips the next instruction when the contents of register A is equal to the value n in the immediate field. 35 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER SEAM (Skip Equal, Accumulator with Memory) Instrunction code D8 0 0 0 1 0 0 1 1 D0 0 2 0 2 6 Number of words 16 Number of cycles 1 Flag CY – Skip condition (A) = (M(DP)) 1 Operation: (A) = (M(DP)) ? Grouping: Comparison operation Description: Skips the next instruction when the contents of register A is equal to the contents of M(DP). SNZP (Skip if Non Zero condition of Power down flag) Instrunction code D8 0 0 0 0 0 0 0 1 D0 1 2 0 0 3 Number of words 16 Number of cycles 1 Flag CY – Skip condition (P) = 1 1 Operation: (P) = 1 ? Grouping: Other operation Description: Skips the next instruction when P flag is “1”. After skipping, P flag remains unchanged. SNZT1 (Skip if Non Zero condition of Timer 1 underflow flag) Instrunction code D8 0 0 1 0 0 0 0 1 D0 0 2 0 4 2 Number of words 16 Number of cycles 1 Flag CY – Skip condition (T1F) = 1 1 Operation: (T1F) = 1 ? After skipping, (T1F) ← 0 Grouping: Timer operation Description: Skips the next instruction when the contents of T1F flag is “1.” After skipping, clears (0) to T1F flag. SNZT2 (Skip if Non Zero condition of Timer 2 inerrupt request flag) Instrunction code D8 0 0 1 0 1 0 0 1 D0 0 2 0 5 2 Number of words 16 Number of cycles 1 Flag CY – Skip condition (T2F) = 1 1 Operation: (T2F) = 1 ? After skipping, (T2F) ← 0 Grouping: Timer operation Description: Skips the next instruction when the contents of T2F flag is “1.” After skipping, clears (0) to T2F flag. 36 MITSUBISHI MICROCOMPUTERS 4282 Group SZB j (Skip if Zero, Bit) Instrunction code D8 0 0 0 1 0 0 0 j1 D0 j0 2 0 2 j Number of words 16 Number of cycles 1 Flag CY – Skip condition (Mj(DP)) = 0 j = 0 to 3 1 Operation: (Mj(DP)) = 0 ? j = 0 to 3 Grouping: Bit operation Description: Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” SZC (Skip if Zero, Carry flag) Instrunction code D8 0 0 0 1 0 1 1 1 D0 1 2 0 2 F Number of words 16 Number of cycles 1 Flag CY – Skip condition (CY) = 0 1 Operation: (CY) = 0 ? Grouping: Arithmetic operation Description: Skips the next instruction when the contents of carry flag CY is “0.” SZD (Skip if Zero, port D specified by register Y) Instrunction code D8 0 0 Operation: 0 0 0 0 1 1 0 0 0 1 1 0 0 1 D0 0 2 0 0 2 2 4 Number of words 16 Number of cycles 2 Flag CY – Skip condition (D(Y)) = 0 (Y) = 4 to 7 2 12 B 16 (D(Y)) = 0 ? (Y) = 4 to 7 Grouping: Input/Output operation Description: Skips the next instruction when a bit of port D specified by register Y is “0.” T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B) Instrunction code D8 0 0 1 0 0 0 1 1 D0 1 2 0 4 7 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: at timer 1 stop (V10=0) (R17–R14) ← (B), (R13–R10) ← (A) (T17–T14) ← (B), (T13–T10) ← (A) at timer 1 operating (V10=1) (R17–R14) ← (B), (R13–R10) ← (A) Grouping: Timer operation Description: At timer 1 stop (V10 = 0), transfers the contents of register A and register B to timer 1 and reload register R1. At timer 1 operating (V10 = 1), transfers the contents of register A and register B to reload register R1. 37 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER T2AB (Transfer data to timer 2 and register R2L from Accumulator and register B) Instrunction code D8 0 1 0 0 0 1 0 0 D0 0 2 0 8 8 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (R2L7–R2L4) ← (B) (R2L3–R2L0) ← (A) (T27–T24) ← (B) (T23–T20) ← (A) Grouping: Timer operation Description: Transfers the contents of registers A and B to timer 2 and timer 2 reload register R2L. T2HAB (Transfer data to register R2H Accumulator from register B) Instrunction code D8 0 1 0 0 0 1 0 0 D0 1 2 0 8 9 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (R2H7–R2H4) ← (B) (R2H3–R2H0) ← (A) Grouping: Timer operation Description: Transfers the contents of register A and register B to reload register R2H. T2R2L (Transfer data to timer 2 from register R2L) Instrunction code D8 0 0 1 0 1 0 0 1 D0 1 2 0 5 3 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (T27–T24) ← (R2L7–R2L4) (T23–T20) ← (R2L3–R2L0) Grouping: Timer operation Description: Transfers the contents of reload register R2L to timer 2. TAB (Transfer data to Accumulator from register B) Instrunction code D8 0 0 0 0 1 1 1 1 D0 0 2 0 1 E Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (B) Grouping: Register to register transfer Description: Transfers the contents of register B to register A. 38 MITSUBISHI MICROCOMPUTERS 4282 Group TAB1 (Transfer data to Accumulator and register B from timer 1) Instrunction code D8 0 0 1 0 1 0 1 1 D0 1 2 0 5 7 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (B) ← (T17–T14) (A) ← (T13–T10) Grouping: Timer operation Description: Transfers the contents of timer 1 to registers A and B. TAB2 (Transfer data to Accumulator and register B from timer 2) Instrunction code D8 0 0 1 0 0 0 0 0 D0 0 2 0 4 0 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (B) ← (T27–T24) (A) ← (T23–T20) Grouping: Timer operation Description: Transfers the contents of timer 2 to registers A and B. TABE (Transfer data to Accumulator and register B from register E) Instrunction code D8 0 0 0 1 0 1 0 1 D0 0 2 0 2 A Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (B) ← (ER7–ER4) (A) ← (ER3–ER0) Grouping: Register to register transfer Description: Transfers the contents of register E to registers A and B. TABP p (Transfer data to Accumulator and register B from Program memory in page p) Instrunction code D8 0 1 0 0 1 D0 p3 p2 p1 p0 2 0 9 p Number of words 16 Number of cycles 3 Flag CY Skip condition – 1 Operation: Note: SK(SP)) ← (PC) , (SP) ← (SP) + 1 (PCH) ← p, p = 0 to 7, (PCL) ← (DR2–DR0, A3–A0) When URS = 0, (B) ← (ROM(PC))7 to 4, (A) ← (ROM(PC))3 to 0 When URS = 1, (CY) ← (ROM(PC))8 (B) ← (ROM(PC))7 to 4, (A) ← (ROM(PC))3 to 0 (SP) ← (SP) – 1, (PC) ← (SK(SP)) p is 0 to 7 for M34282M1, p is 0 to 15 for M34282M2/E2. Grouping: Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A when URS flag is cleared to “0.” These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0) specified by registers A and D in page p. Transfers bit 8 of ROM pattern is transferred to flag CY when URS flag is set to “1” (after the URSC instruction is executed). (One of stack is used when the TABP p instruction is executed.) – 0/1 Arithmetic operation 39 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER TAM j (Transfer data to Accumulator from Memory) Instrunction code D8 0 0 1 1 0 0 1 j1 D0 j0 2 0 6 4 j +j Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 3 Grouping: RAM to register transfer Description: After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. TAY (Transfer data to Accumulator from register Y) Instrunction code D8 0 0 0 0 1 1 1 1 D0 1 2 0 1 F Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ← (Y) Grouping: Register to register transfer Description: Transfers the contents of register Y to register A. TBA (Transfer data to register B from Accumulator) Instrunction code D8 0 0 0 0 0 1 1 1 D0 0 2 0 0 E Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (B) ← (A) Grouping: Register to register transfer Description: Transfers the contents of register A to register B. TDA (Transfer data to register D from Accumulator) Instrunction code D8 0 0 0 1 0 1 0 0 D0 1 2 0 2 9 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (DR2–DR0) ← (A2–A0) Grouping: Register to register transfer Description: Transfers the contents of register A to register D. 40 MITSUBISHI MICROCOMPUTERS 4282 Group TEAB (Transfer data to register E from Accumulator and register B) Instrunction code D8 0 0 0 0 1 1 0 1 D0 0 2 0 1 A Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (ER7–ER4) ← (B) (ER3–ER0) ← (A) Grouping: Register to register transfer Description: Transfers the contents of register A and register B to register E. TLOA (Transfer data to register LO from Accumulator) Instrunction code D8 0 0 1 0 1 1 0 0 D0 0 2 0 5 8 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (LO1, LO0) ← (A1, A0) Grouping: Other operation Description: Transfers the contents of register A to logic operation selection register LO. TPU0A (Transfer data to register PU0 from Accumulator) Instrunction code D8 0 1 0 0 0 1 1 1 D0 1 2 0 8 F Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (PU03–PU00) ← (A3–A0) Grouping: Other operation Description: Transfers the contents of register A to pullup control register PU0. TPU1A (Transfer data to register PU1 from Accumulator) Instrunction code D8 0 1 0 0 0 1 1 1 D0 0 2 0 8 E Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (PU13–PU10) ← (A3–A0) Grouping: Other operation Description: Transfers the contents of register A to pullup control register PU1. 41 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER TV1A (Transfer data to register V1 from Accumulator) Instrunction code D8 0 0 1 0 1 0 1 1 D0 1 2 0 5 B Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (V12–V10) ← (A2–A0) Grouping: Timer operation Description: Transfers the contents of register A to register V1. TV2A (Transfer data to register V2 from Accumulator) Instrunction code D8 0 0 1 0 1 1 0 1 D0 02 0 5 A 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (V23–V20) ← (A3–A0) Grouping: Timer operation Description: Transfers the contents of register A to register V2. TYA (Transfer data to regiser Y from Accumulator) Instrunction code D8 0 0 0 0 0 1 1 0 D0 0 2 0 0 C 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition – Operation: (Y) ← (A) Grouping: Register to register transfer Description: Transfers the contents of register A to register Y. URSC (Sets Upper ROM Code reference enable flag) Instrunction code D8 0 1 0 0 0 0 0 1 D0 0 2 0 8 2 Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (URS) ← 1 Grouping: Other operation Description: Sets the most significant ROM code reference enable flag (URS) to “1.” 42 MITSUBISHI MICROCOMPUTERS 4282 Group WRST (Watchdog timer ReSeT) Instrunction code D8 0 0 0 0 0 1 1 1 D0 1 2 0 0 F Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (WDF1) ← 0 Grouping: Other operation Description: Initializes the watchdog timer flag (WDF1). XAM j (eXchange Accumulator and Memory data) Instrunction code D8 0 0 1 1 0 0 0 j1 D0 j0 2 0 6 j Number of words 16 Number of cycles 1 Flag CY – Skip condition – 1 Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 3 Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip) Instrunction code D8 0 0 1 1 0 1 1 j1 D0 j0 2 0 6 C +j 16 Number of words 1 Number of cycles 1 Flag CY – Skip condition (Y) = 15 Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 3 (Y) ← (Y) – 1 Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. D0 Number of words 1 Number of cycles 1 Flag CY – Skip condition (Y) = 0 XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip) Instrunction code D8 0 0 1 1 0 1 0 j1 j0 2 0 6 8 +j 16 Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 3 (Y) ← (Y) + 1 Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. 43 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MACHINE INSTRUCTIONS (INDEX BY FUNCTION) Number of words Parameter Instruction code Mnemonic D8 D7 D6 D5 D4 D3 D2 D1 D0 TAB TBA TAY TYA TEAB TABE TDA LXY x, y 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 1 1 0 0 0 1 0 0 0 1 Hexadecimal notation Number of cycles Function Type of instructions 01 00 01 00 01 02 02 E E F C A A 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) (ER7–ER4) ← (B) (ER3–ER0) ← (A) (B) ← (ER7–ER4) (A) ← (ER3–ER0) (DR2–DR0) ← (A2–A0) (X) ← x, x = 0 to 3 (Y) ← y, y = 0 to 15 Register to register transfer x1 x0 y3 y2 y1 y0 0Cy +x RAM addresses INY 0 0 0 0 1 0 0 1 1 01 3 1 1 (Y) ← (Y) + 1 DEY 0 0 0 0 1 0 1 1 1 017 1 1 (Y) ← (Y) – 1 TAM j 0 0 1 1 0 0 1 j1 j0 06 4 +j 1 1 (A) ← (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 XAM j 0 0 1 1 0 0 0 j1 j0 06 j 1 1 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 RAM to register transfer XAMD j 0 0 1 1 0 1 1 j1 j0 06 C +j 1 1 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (Y) ← (Y) – 1 XAMI j 0 0 1 1 0 1 0 j1 j0 06 8 +j 1 1 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (Y) ← (Y) + 1 44 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Skip condition Carry flag CY Detailed description – – – – – – – Continuous description – – – – – – – – Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of registers A and B to register E. Transfers the contents of register E to registers A and B. Transfers the contents of register A to register D. Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. (Y) = 0 – Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. (Y) = 15 – Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. – – After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. – – After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. (Y) = 15 – After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. (Y) = 0 – After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. MITSUBISHI ELECTRIC 45 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MACHINE INSTRUCTIONS (CONTINUED) Number of words Parameter Instruction code Mnemonic D8 D7 D6 D5 D4 D3 D2 D1 D0 LA n 0 1 0 1 1 n3 n2 n1 n0 Hexadecimal notation Number of cycles Function Type of instructions 0Bn 1 1 (A) ← n n = 0 to 15 TABP p 0 1 0 0 1 p3 p2 p1 p0 09 p 1 3 (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PCH) ← p, p=0 to 7 (Note) (PCL) ← (DR2–DR0, A3–A0) When URS=0, (B) ← (ROM(PC))7 to 4 (A) ← (ROM(PC))3 to 0 When URS=1, (CY) ← (ROM(PC))8 (B) ← (ROM(PC))7 to 4 (A) ← (ROM(PC))3 to 0 (SP) ← (SP) – 1 (PC) ← (SK(SP)) AM 0 0 0 0 0 1 0 1 0 00 A 1 1 (A) ← (A) + (M(DP)) Arithmetic operation AMC 0 0 0 0 0 1 0 1 1 00 B 1 1 (A) ← (A) + (M(DP))+ (CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 An 0 1 0 1 0 n3 n2 n1 n0 0An 1 1 SC RC SZC CMA RAR LGOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 0 0 0 1 0 1 0 1 1 00 00 02 01 01 04 7 6 F C D 1 1 1 1 1 1 1 1 1 1 1 1 1 (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → C Y → A 3 A 2A 1 A 0 Logic operation instruction XOR, OR, AND Note: p is 0 to 7 for M34282M1, p is 0 to 15 for M34282M2/E2. 46 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Skip condition Carry flag CY Detailed description Continuous description – Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. – – Transfers bits 7 to 4 to register B and bits 3 to 0 to register A when URS flag is cleared to “0.” These bits 7 to 0 are the ROM pattern in address (DR2 DR 1 DR0 A3 A2 A1 A0) specified by registers A and D in page p. 0/1 Transfers bit 8 of ROM pattern is transferred to flag CY when URS flag is set to “1” (after the URSC instruction is executed). (One of stack is used when the TABP p instruction is executed.) – – Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. – 0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. – Adds the value n in the immediate field to register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Overflow = 0 – – (CY) = 0 – – – 1 0 – – Sets (1) to carry flag CY. Clears (0) to carry flag CY. Skips the next instruction when the contents of carry flag CY is “0.” Stores the one‘s complement for register A‘s contents in register A. 0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. – Executes the logic operation selected by logic operation selection register LO between the contents of register A and register E, and stores the result in register A. MITSUBISHI ELECTRIC 47 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MACHINE INSTRUCTIONS (CONTINUED) Number of words Parameter Instruction code Mnemonic D8 D7 D6 D5 D4 D3 D2 D1 D0 SB j 0 0 1 0 1 1 1 j1 j0 Hexadecimal notation Number of cycles Function Type of instructions 05 C +j 1 1 (Mj(DP)) ← 1 j = 0 to 3 Bit operation RB j 0 0 1 0 0 1 1 j1 j0 04 C +j 1 1 (Mj(DP)) ← 0 j = 0 to 3 SZB j 0 0 0 1 0 0 0 j1 j0 02 j 1 1 (Mj(DP)) = 0 ? j = 0 to 3 SEAM 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 02 02 6 5 1 2 1 2 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 Comparison operation SEA n n3 n2 n1 n0 0Bn 1 8 +a a 1 1 (PCL) ← a6–a0 Ba 1 a6 a5 a4 a3 a2 a1 a0 BL p, a 0 0 0 1 1 p3 p2 p1 p0 03 p 2 2 (PCH) ← p (PCL) ← a6–a0 (Note) Branch operation 1 1 a6 a5 a4 a3 a2 a1 a0 18 +a a BA a 0 1 0 1 0 0 0 0 0 0 1 00 1 2 2 (PCL) ← (a6–a4, A3–A0) a6 a5 a4 a3 a2 a1 a0 18 a +a 01 18 +a 0 p 2 2 (PCH) ← p (PCL) ← (a6–a4, A3–A0) (Note) BLA p, a 0 1 0 1 0 0 1 0 0 0 0 a6 a5 a4 p3 p2 p1 p0 Note: p is 0 to 7 for M34282M1, p is 0 to 15 for M34282M2/E2. 48 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Skip condition Carry flag CY Detailed description – – Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). – – Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). (Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP)) (A) = n n = 0 to 15 – Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” – – Skips the next instruction when the contents of register A is equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field. – – Branch within a page : Branches to address a in the identical page. – – Branch out of a page : Branches to address a in page p. – – Branch within a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the loworder 4 bits of the address a in the identical page with register A. – – Branch out of a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the loworder 4 bits of the address a in page p with register A. MITSUBISHI ELECTRIC 49 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MACHINE INSTRUCTIONS (CONTINUED) Number of words Parameter Instruction code Mnemonic D8 D7 D6 D5 D4 D3 D2 D1 D0 BM a 1 0 a6 a5 a4 a3 a2 a1 a0 Hexadecimal notation Number of cycles Function Type of instructions 1 a a 1 1 (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PCH) ← 2 (PCL) ← a6–a0 Subroutine operation BML p, a 0 0 1 1 1 p3 p2 p1 p0 07 p 2 2 (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PCH) ← p (PCL) ← a6–a0 (Note) 1 0 a6 a5 a4 a3 a2 a1 a0 1aa BMLA p, a 0 1 0 0 1 0 1 0 0 0 0 05 1a 0 p 2 2 (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PCH) ← p (PCL) ← (a6–a4, A3–A0) (Note) a6 a5 a4 p3 p2 p1 p0 Return operation RT 0 0 1 0 0 0 1 0 0 04 4 1 2 (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) at timer 1 stop (V10=0) (R17–R14) ← (B), (R13–R10) ← (A) (T17–T14) ← (B), (T13–T10) ← (A) at timer 1 operating (V10=1) (R17–R14) ← (B), (R13–R10) ← (A) RTS 0 0 1 0 0 0 1 0 1 04 5 1 2 T1AB 0 0 1 0 0 0 1 1 1 047 1 1 TAB1 0 0 1 0 1 0 1 1 1 057 1 1 (B) ← (T17–T14) (A) ← (T13–T10) (V12–V10) ← (A2–A0) (T1F) = 1 ? After skipping the next instruction (T1F) ← 0 Timer operation TV1A SNZT1 0 0 0 0 1 1 0 0 1 0 1 0 0 0 1 1 1 0 05B 042 1 1 1 1 T2AB 0 1 0 0 0 1 0 0 0 088 1 1 (R2L7–R2L4) ← (B) (R2L3–R2L0) ← (A) (T27–T24) ← (B), (T23–T20) ← (A) Note : p is 0 to 7 for M34282M1, and p is 0 to 15 for M34282M2/E2. 50 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Skip condition Carry flag CY Detailed description – – Call the subroutine in page 2 : Calls the subroutine at address a in page 2. – – Call the subroutine : Calls the subroutine at address a in page p. – – Call the subroutine : Calls the subroutine at address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the low-order 4 bits of address a in page p with register A. – – Returns from subroutine to the routine called the subroutine. Skip at uncondition – Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition. – – At timer 1 stop (V10 = 0), transfers the contents of register A and register B to timer 1 and reload register R1. At timer 1 operating (V10 = 1), transfers the contents of register A and register B to reload register R1. – – Transfers the contents of timer 1 to registers A and B. – (T1F) = 1 – Transfers the contents of register A to registers V1. – Skips the next instruction when the contents of T1F flag is “1.” After skipping, clears (0) to T1F flag. – – Transfers the contents of register A and register B to timer 2 and reload register R2L. MITSUBISHI ELECTRIC 51 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MACHINE INSTRUCTIONS (CONTINUED) Number of words Parameter Instruction code Mnemonic D8 D7 D6 D5 D4 D3 D2 D1 D0 TAB2 TV2A 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 1 0 0 0 0 0 1 1 0 0 0 Hexadecimal notation Number of cycles Function Type of instructions 040 05A 052 1 1 1 1 1 1 (B) ← (T27–T24), (A) ← (T23–T20) (V23–V20) ← (A3–A0) (T2F) = 1 ? After skipping the next instruction (T2F) ← 0 Timer operation SNZT2 T2HAB 0 1 0 0 0 1 0 0 1 089 1 1 (R2H7–R2H4) ← (B) (R2H3–R2H0) ← (A) T2R2L 0 0 1 0 1 0 0 1 1 053 1 1 (T27–T24) ← (R2L7–R2L4) (T23–T20) ← (R2L3–R2L0) Carrier wave control operation SCAR RCAR 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 087 086 1 1 1 1 (CAR) ← 1 (CAR) ← 0 CLD RD 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 011 014 1 1 1 1 (D) ← 0 (D(Y)) ← 0 (Y) = 0 to 7 (D(Y)) ← 1 (Y) = 0 to 7 (D(Y)) = 0 ? (Y) = 4 to 7 SD 0 0 0 0 1 0 1 0 1 015 1 1 Input/Output operation SZD 0 0 0 0 1 0 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 024 02B 084 056 080 028 2 2 OEA IAE OGA IAG 0 0 0 0 1 1 1 1 1 1 1 1 (E1, E0) ← (A1, A0) (A2–A0) ← (E2–E0) (G) ← (A) (A) ← (G) 52 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Skip condition Carry flag CY Detailed description – – (T2F) = 1 – – – Transfers the contents of timer 2 to registers A and B. Transfers the contents of register A to registers V2. Skips the next instruction when the contents of T2F flag is “1.” After skipping, clears (0) to T2F flag. – – Transfers the contents of register A and register B to reload register R2H. – – Transfers the contents of reload register R2L to timer 2. – – – – Sets (1) to port CARR output flag (CAR). Clears (0) to port CARR output flag (CAR). – – – – Clears (0) to port D (high-impedance state). Clears (0) to a bit of port D specified by register Y (high-impedance state). – – Sets (1) to a bit of port D specified by register Y. (D(Y)) = 0 (Y) = 4 to 7 – Skips the next instruction when a bit of port D specified by register Y is “0.” – – – – – – – – Outputs the contents of register A to port E. Transfers the contents of port E to register A. Outputs the contents of register A to port G. Transfers the contents of port G to register A. MITSUBISHI ELECTRIC 53 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Number of words Parameter Instruction code Mnemonic D8 D7 D6 D5 D4 D3 D2 D1 D0 NOP POF 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 Hexadecimal notation Number of cycles Function Type of instructions 000 00 D 1 1 1 1 (PC) ← (PC) + 1 RAM back-up SNZP 0 0 0 0 0 0 0 1 1 00 3 1 1 (P) = 1 ? Other operation CCK 0 0 1 0 1 1 0 0 1 05 9 1 1 STCK changes to f(XIN) TLOA URSC TPU0A TPU1A WRST 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 1 0 0 1 1 1 0 1 1 1 1 0 0 1 0 1 05 08 08 08 00 8 2 F E F 1 1 1 1 1 1 1 1 1 1 (LO1, LO0) ← (A1, A0) (URS) ← 1 (PU03–PU00) ← (A3–A0) (PU13–PU10) ← (A3–A0) (WDF1) ← 0 54 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Skip condition Carry flag CY Detailed description – – – – No operation Puts the system in RAM back-up state. (P) = 1 – Skips the next instruction when P flag is “1.” After skipping, P flag remains unchanged. System clock (STCK) changes to f(XIN) from f(XIN)/8. Execute this CCK instruction at address 0 in page 0. Transfers the contents of register A to the logic operation selection register LO. Sets the most significant ROM code reference enable flag (URS) to “1.” Transfers the contents of register A to register PU0. Transfers the contents of register A to register PU1. Initializes the watchdog timer flag (WDF1). – – – – – – – – – – – – MITSUBISHI ELECTRIC 55 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER INSTRUCTION CODE TABLE D8–D4 D 3– D0 Hex. notation 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 00 NOP 01 BLA 02 SZB 0 SZB 1 SZB 2 SNZP INY RD SZB 3 SZD 03 BL BL 04 05 06 XAM 0 XAM 1 XAM 2 07 BML 08 09 0A A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15 0B LA 0 LA 1 LA 2 LA 3 LA 4 LA 5 LA 6 LA 7 LA 8 LA 9 LA 10 LA 11 LA 12 LA 13 LA 14 LA 15 0C LXY 0,0 LXY 0,1 LXY 0,2 LXY 0,3 LXY 0,4 LXY 0,5 LXY 0,6 LXY 0,7 LXY 0,8 LXY 0,9 LXY 0,10 LXY 011 LXY 0,12 LXY 0,13 LXY 0,14 LXY 0,15 0D LXY 1,0 LXY 1,1 LXY 1,2 LXY 1,3 LXY 1,4 LXY 1,5 LXY 1,6 LXY 1,7 LXY 1,8 LXY 1,9 LXY 1,10 LXY 1,11 LXY 1,12 LXY 1,13 LXY 1,14 LXY 1,15 0E LXY 2,0 LXY 2,1 LXY 2,2 LXY 2,3 LXY 2,4 LXY 2,5 LXY 2,6 LXY 2,7 LXY 2,8 LXY 2,9 LXY 2,10 LXY 2,11 LXY 2,12 LXY 2,13 LXY 2,14 LXY 2,15 0F LXY 3,0 LXY 3,1 LXY 3,2 LXY 3,3 LXY 3,4 LXY 3,5 LXY 3,6 LXY 3,7 LXY 3,8 LXY 3,9 LXY 3,10 LXY 3,11 LXY 3,12 LXY 3,13 LXY 3,14 LXY 3,15 10000 11000 10111 11111 10–17 18–1F BM BM B B B 0000 0001 0010 0 TAB2 BMLA OGA TABP 0 TABP 1 URSC TABP 2 TABP 3 OEA TABP 4 TABP 5 TABP 6 TABP 7 TABP 8* TABP 9* TABP 10* TABP 11* TABP 12* TABP 13* 1 2 BA CLD LGOP SNZT1 SNZT2 BML BL BL BML BM 0011 3 T2R2L XAM 3 RT RTS TAM 0 TAM 1 IAE TAM 2 TAM 3 XAMI 0 XAMI 1 XAMI 2 XAMI 3 BML BML BM BM BM B 0100 0101 4 5 RC BL BL B SD SEAn SEAM BML B 0110 6 BL BML RCAR BML SCAR BML* T2AB BML* T2HAB BML* BM B B B 0111 7 SC DEY IAG BL BL* T1AB TAB1 BM BM 1000 8 9 A B C AM TLOA 1001 1010 TDA BL* CCK TV2A BM B B TEAB TABE BL* BM BM BM 1011 AMC TYA CMA BL* BL* RB 0 RB 1 RB 2 RB 3 TV1A SB 0 SB 1 SB 2 SB 3 BML* B 1100 XAMD BML* 0 XAMD BML* 1 B B B 1101 1110 1111 D E F POF TBA RAR BL* BM TAB BL* SZC BL* XAMD BML* TPU1A TABP 2 14* TABP XAMD BML* TPU0A 15* 3 BM WRST TAY BM B The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order 4 bits of the machine language code, and D8–D4 show the high-order 5 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use the code marked “–.” The codes for the second word of a two-word instruction are described below. BL BML BA BLA BMLA SEA SZD The second word 1 1aaa aaaa 1 0aaa aaaa 1 1aaa aaaa 1 1aaa pppp 1 0aaa pppp 0 1011 nnnn 0 0010 1011 * cannot be used in the M34282M1. 56 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER REGISTER STRUCTURE Timer control register V1 V12 V11 V10 Carrier wave output auto-control bit Timer 1 count source selection bit Timer 1 control bit 0 1 0 1 0 1 at reset : 0002 at RAM back-up : 0002 W Auto-control output by timer 1 is invalid Auto-control output by timer 1 is valid Carrier wave output (CARRY) Bit 5 of watchdog timer (WDT) Stop (Timer 1 state retained) Operating at reset : 00002 0 1 0 1 0 1 0 1 at RAM back-up : 00002 W Timer control register V1 V13 V12 V11 V10 Carrier wave “H” interval expansion bit Carrier wave generation function control bit Timer 2 count source selection bit Timer 2 control bit To expand “H” interval is invalid To expand “H” interval is valid (when V22=1 selected) Carrier wave generation function invalid Carrier wave generation function valid f(XIN) f(XIN)/2 Stop (Timer 2 state retained) Operating Logic operation selection register LO at reset : 002 at RAM back-up : 002 W LO1 Logic operation selection bits LO0 LO1 LO0 Logic operation function 0 0 Exclusive logic OR operation (XOR) 0 1 OR operation (OR) 1 1 0 AND operation (AND) 1 Not available Pull-down control register PU0 PU03 PU02 PU01 PU00 Ports G2, G3 pull-down transistor control bit Ports G0, G1 pull-down transistor control bit Port E1 pull-down transistor control bit Port E0 pull-down transistor control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained W Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down control register PU1 PU13 PU12 PU11 PU10 Port D7 pull-down transistor control bit Port D6 pull-down transistor control bit Port D5 pull-down transistor control bit Port D4 pull-down transistor control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained W Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid MITSUBISHI ELECTRIC 57 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER ABSOLUTE MAXIMUM RATINGS Symbol VDD VI VO Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature range Storage temperature range Ta = 25 °C Conditions –0.3 to 5 –0.3 to VDD+0.3 –0.3 to VDD+0.3 300 –20 to 85 –40 to 125 Ratings Unit V V V mW °C °C RECOMMENDED OPERATING CONDITIONS (Ta = –20 °C to 85 °C, VDD = 1.8 V to 3.6 V, unless otherwise noted) Symbol VDD VRAM VSS VIH VIH VIL VIL Parameter Supply voltage RAM back-up voltage (at RAM back-up mode) Supply voltage “H” level input voltage Ports D4–D7, E, G “H” level input voltage XIN “L” level input voltage Ports D4–D7, E, G VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V 0.7VDD 0.8VDD 0 0 Conditions Limits Min. 1.8 1.1 0 VDD VDD 0.2VDD 0.2VDD –4 –24 –20 4 –2 –12 –10 2 4 500 1.10 1.40 1.50 0.2 1.80 1.56 1.2 1 Typ. Max. 3.6 3.6 Unit V V V V V V V mA mA mA mA mA mA mA mA MHz kHz V ms ms “L” level input voltage XIN IOH(peak) “H” level peak output current Ports D, E1, G IOH(peak) “H” level peak output current Port E0 IOH(peak) “H” level peak output current CARR IOL(peak) “L” level peak output current CARR IOH(avg) “H” level average output current Ports D, E1, G IOH(avg) “H” level average output current Port E0 IOH(avg) “H” level average output current CARR IOL(avg) “L” level average output current CARR f(XIN) VDET TDET TPON VDD = 3.0 V System clock frequency when STCK = f(XIN)/8 selected Ceramic resonance when STCK = f(XIN) selected Ceramic resonance Voltage drop detection circuit detection voltage Ta=25 °C Voltage drop detection circuit low voltage determination time Power-on reset circuit valid power source rising time When supply voltage passes the detected voltage at ±50V/s. VDD = 0 to 2.2 V Note: The average output current ratings are the average current value during 100 ms. 58 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS (Ta = –20 °C to 85 °C, VDD = 3 V, unless otherwise noted) Symbol VOL VOL VOH VOH VOH VOH IIL IIH IOZ IDD Parameter “L” level output voltage Port CARR “L” level output voltage XOUT “H” level output voltage Ports D, E1, G “H” level output voltage Port E0 “H” level output voltage CARR “H” level output voltage XOUT “L” level input current Ports D4–D7, E, G “H” level input current Ports E0, E1 Test conditions IOL = 2 mA IOL = 0.2 mA IOH = –2 mA IOH = –12 mA IOH = –10 mA IOH = –0.2 mA VI = VSS VI = VDD Pull-down transistor in off-state 400 250 1 Ta = 25 °C VDD = 3 V, VI = 3 V 75 700 0.1 150 2.1 1.5 1.0 2.1 –1 1 –1 800 500 3 0.5 300 3200 Limits Min. Typ. Max. 0.9 0.9 Unit V V V V V V µA µA µA µA µA µA µA kΩ kΩ Output current at off-state Ports D, E0, E1, G VO = VSS Supply current (when operating) f(XIN) = 4.0 MHz f(XIN) = 500 kHz Supply current (at RAM back-up) RPH ROSC Pull-down resistor value Ports D4–D7, E, G Feedback resistor value between XIN–XOUT BASIC TIMING DIAGRAM Parameter System clock Ports D, E, G output Machine cycle Pin name Mi Mi+1 STCK D0–D7,E0,E1 G0–G3 D4–D7 E0–E2 G0–G3 Ports D, E, G input MITSUBISHI ELECTRIC 59 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER BUILT-IN PROM VERSION In addition to the mask ROM versions, the 4282 Group has the One Time PROM versions whose PROMs can only be written to and not be erased. The built-in PROM version has functions similar to those of the mask ROM versions, but it has PROM mode that enables writing to built-in PROM. Table 10 Product of built-in PROM version PROM size Product (✕ 9 bits) M34282E2GP 2048 words Table 10 shows the product of built-in PROM version. Figure 27 and 28 show the pin configurations of built-in PROM versions. The One Time PROM version has pin-compatibility with the mask ROM version. RAM size (✕ 4 bits) 64 words Package 20P2E/F-A ROM type One Time PROM [shipped in blank] PIN CONFIGURATION (TOP VIEW) VSS E2 E1 XIN XOUT E0 G0 G1 G2 G3 1 2 3 4 5 6 7 8 9 10 Outline 20P2E/F-A 20 19 18 17 16 15 14 13 12 11 VDD CARR D0 D1 D2 D3 D4 D5 D6 D7 M34282E2GP MITSUBISHI ELECTRIC Fig. 27 Pin configuration of built-in PROM version 60 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (1) PROM mode (serial input/output) The M34282E2GP has a PROM mode in addition to a normal operation mode. It has a function to serially input/output the command codes, addresses, and data required for operation (e.g., read and program) on the built-in PROM using only a few pins. This mode can be selected by setting pins SDA (serial data input/output), SCLK (serial clock input), PGM and VPP to “H” after connecting wires as shown in Figure 28 and powering on the VDD pin, and then applying 12.5V to the VPP pin. In the PROM mode, three types of software commands (read, program, and program verify) can be used. Clock-synchronous serial I/O is used, beginning from the LSB (LSB first). Refer to the “Mitsubishi Microcomputer Development Support Tools” Hompage (http://www.tool-spt.maec.co.jp/ index_e.htm). about the serial programmer for the Mitsubishi single-chip microcomputers. PIN CONFIGURATION (TOP VIEW) Vss Vpp VSS 1 20 VDD 19 CARR 18 D0 17 D1 16 D2 15 D3 14 D4 13 D5 12 D6 11 D7 Outline 20P2E/F-A VDD E2 2 E1 3 XIN 4 M34282E2GP * SCLK XOUT 5 E0 6 G0 7 G1 8 G2 9 G3 10 SDA PGM * : connected to the ceramic resonance circuit. Note: The state of disconnected pins are the same as that at reset. Fig. 28 Pin configuration of built-in PROM version (continued) MITSUBISHI ELECTRIC 61 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (2) Functional outline In the PROM mode, data is transferred with the clocksynchronous serial input/output. The input data is read through the SDA pin into the internal circuit synchronously with the rising edge of the serial clock pulse. The output data is output from the SDA pin synchronously with the falling edge of the serial clock pulse. Data is transferred in units of 8 bits. Table 11 Software command Number of transfer Command Read Program Program verify Number of transfer Command Read Program Program verify First command code input 1516 2516 3516 Second Read address L (input) Program address L (input) Program address L (input) In the first transfer, the command code is input. Then, address input or data input/output is performed according to the contents of the command code. Table 11 shows the software command used in the PROM mode. The following explains each software command. Third Read address H (input) Program address H (input) Program address H (input) Fourth Read data L (output) Program data L (input) Program data L (input) Fifth Read data H (output) Program data H (input) Program data H (input) Sixth Seventh Verify data L (output) Verify data H (output) (3) Read Input the command code 1516 in the first transfer. Proceed and input the low-order 8 bits and the high-order 8 bits of the address and pull the PGM pin to “L.” When this is done, the contents of input address is read and stored into the internal data latch. When the PGM pin is released back to “H” and serial clock is input to the SCLK pin, the low-order 8 bits and high-order 8 bits of read data which have been stored into the data latch, are serially output from the SDA pin. tCH SCLK A0 A7 tCH tCH A8A9 A10 00000 Read address input (H) tCR D0 D7 Read data output (L) D8 0000000 Read data output (H) SDA 10101000 Command code input (1516) Read address input (L) tWR tRC PGM Read Note: When outputting the read data, the SDA pin is switched for output at the first falling of the serial clock. The SDA pin is placed in the high-impedance state during the th(C–E) period after the last rising edge of the serial clock (at the 16th bit). Fig. 29 Timing at reading 62 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (4) Program Input command code 2516 in the first transfer. Proceed and input the low-order 8 bits and high-order 8 bits of the address and the low-order 8 bits and high-order 8 bits of program data, and pull the PGM pin to “L.” When this is done, the program data is programmed to the specified address. tCH SCLK A0 A7 tCH tCH tCH A8A9 A10 00000 D0 D7 D8 0000000 SDA 10100100 P Commanf code input (2516 ) rogram address input (L) Program address input (H) Program data input (L) Program data input (H) tCP tWP PGM Program Fig. 30 Timing at programming (5) Program verify Input command code 3516 in the first transfer. Proceed and input the low-order 8 bits and high-order 8 bits of the address and the low-order 8 bits and high-order 8 bits of program data, and pull the PGM pin to “L.” When this is done, the program data is programmed to the specified address. Then, when the PGM pin is pulled to “L” again after it is released back to “H,” the address programmed with the program command is read and verified and stored into the internal data latch. When the PGM pin is released back to “H” and serial clock is input to the SCLK pin, the verify data that has been stored into the data latch is serially output from the SDA pin. tCH SCLK A0 A7 tCH tCH tCH A8 A9 A10 00000 D0 D7 D8 0000000 SDA 10101100 Command code input (3516) Program address input (L) Program address input (H) Program data input (L) Program data input (H) tCP tWP PGM Program tCH SCLK D0 D7 D8 0000000 SDA tCR PGM Verify tWR tRC Verify data output (L) Verify data output (H) Note: When outputting the verify data, the SDA pin is switched for output at the first falling of the serial clock. The SDA pin is placed in the high-impedance state during the th(C–E) period after the last rising edge of the serial clock (at the 16th bit). Fig. 31 Timing at program verifying MITSUBISHI ELECTRIC 63 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PROGRAM ALGORITHM FLOW CHART START VDD = 4V,VPP = 4V VDD = 4V,VPP = 12.5V ADRS = first location X=0 WRITE PROGRAM-VERIFY COMMAND 3516 WRITE PROGRAM DATA DIN PROGRAM ONE PULSE OF 0.2ms X=X+1 YES X = 25? NO FAIL VERIFY BYTE? PASS PASS WRITE PROGRAM COMMAND 2516 VERIFY BYTE? FAIL WRITE PROGRAM DATA DIN PROGRAM PULSE OF 0.2Xms DURATION INC ADRS NO LAST ADRS? YES READ COMMAND 1516 VERIFY ALL BYTE? PASS DEVICE PASSED FAIL DEVICE FAILED 64 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER TIMING REQUIREMENT CONDITION AND SWITCHING CHARACTERISTICS (Ta = 25 °C, VDD = 4.0 V, VPP = 12.5 V) Symbol tCH tCR tWR tRC tCP tWP tOWP tC(CK) tW(CKH) tW(CKL) tr(CK) tf(CK) td(C–Q) th(C–Q) th(C–E) tsu(D–C) th(C–D) Parameter Serial transfer width time Read wait time after transfer Read pulse width Transfer wait time after read Program wait time after transfer Program pulse width Added program pulse width SCLK input cycle time SCLK “H” pulse width SCLK “L” pulse width SCLK rising time SCLK falling time SDA output delay time SDA output hold time SDA output hold time (only for 16th bit) SDA input set-up time SDA input hold time Limits Min. Max. 2.0 2.0 500 2.0 2.0 0.19 0.19 1.0 450 450 40 40 0 0 100 60 180 180 0.21 5.25 Unit µs µs ns µs µs ms ms µs ns ns ns ns ns ns ns ns ns TIMING DIAGRAM tf(CK) tW(CKL) SCLK td(C-Q) SDA output tr(CK) tC(CK) tW(CKH) th(C-E) th(C-Q) tsu(D-C) th(C-D) SDA input Measurement condition Output timing voltage: VOL = 0.8 V, VOH = 2.0 V Input timing voltage: VIL = 0.2 VDD, VIH = 0.8 VDD MITSUBISHI ELECTRIC 65 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (6) Notes on handling ➀ A high-voltage is used for writing. Take care that overvoltage is not applied. Take care especially at turning on the power. ➁ For the One Time PROM version, Mitsubishi Electric corp. does not perform PROM writing test and screening in the assembly process and following processes. In order to improve reliability after writing, performing writing and test according to the flow shown in Figure 32 before using is recommended. Writing with PROM programmer Screening (Leave at 150 °C for 40 hours) (Note) Verify test with PROM programmer Function test in target device Note: Since the screening temperature is higher than storage temperature, never expose the microcomputer to 150 °C exceeding 100 hours. Fig. 32 Flow of writing and test of the product shipped in blank 66 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PACKAGE OUTLINE 20P2E/F-A EIAJ Package Code SSOP20-P-225-0.65 JEDEC Code – Weight(g) 0.08 Lead Material Alloy 42/Cu Alloy Plastic 20pin 225mil SSOP e b2 20 11 HE E F Recommended Mount Pad Symbol 1 10 e1 A G D b e x M A2 A1 y c z Z1 Detail G Detail F A A1 A2 b c D E e HE L L1 z Z1 x y b2 e1 I2 Dimension in Millimeters Min Nom Max 1.45 – – 0.2 0.1 0 – 1.15 – 0.32 0.22 0.17 0.2 0.15 0.13 6.6 6.5 6.4 4.5 4.4 4.3 – 0.65 – 6.6 6.4 6.2 0.7 0.5 0.3 – 1.0 – – 0.325 – – – 0.475 – – 0.13 0.1 – – 0° – 10° – 0.35 – – 5.8 – – 1.0 – L1 MITSUBISHI ELECTRIC L I2 67 MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER 20P2E/F-A (20-PIN SSOP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark 20 11 Mitsubishi IC catalog name Mitsubishi lot number (4-digit or 5-digit) Mitsubishi IC catalog name 1 10 B. Customer ’s Parts Number + Mitsubishi IC Catalog Name 20 11 ROM number (3-digit) Mitsubishi lot number (4-digit or 5-digit) Customer ’s Parts Number Note: The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name and Mitsubishi lot number Mitsubishi IC catalog name and Mitsubishi lot number Notes 1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer ’s Parts Number can be up to 4 characters: Only 0 to 9, A to Z, +, -, /, (, ), &, ©, . (period), and , (comma) are usable. 1 10 68 MITSUBISHI ELECTRIC MITSUBISHI MICROCOMPUTERS 4282 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials • • • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. • • • • © 2001 MITSUBISHI ELECTRIC CORP. New publication, effective July. 2001. Specifications subject to change without notice. REVISION DESCRIPTION LIST Rev. No. 1.0 1.1 First Edition Page 12 (2) Precautions revised. Page 13 (3) Timer 1, (4) Timer 2 revised. Page 22 ➂ Timer revised. 1.2 1.3 Pages 7, 8, 14, 18, 21: Character fonts errors revised. All pages: 4282 GROUP DATA SHEET Revision Description Rev. date 000619 000725 000823 010703 “PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change.” eliminated. Page 1: Product name table; “Under development” eliminated. Page 9: 48 words ✕ 4 bits (128 bits) → 48 words ✕ 4 bits (192 bits) Page 21: ROM ORDERING METHOD revised. Page 61: “Mitsubishi Microcomputer Development Support Tools” Hompage (http://www.tool-spt.mesc.co.jp/index_e.htm) → (http://www.tool-spt.maec.co.jp/index_e.htm) (1/1)