M35500

MITSUBISHI M35500AFP/BGP FLD(VFD) CONTROLLER DESCRIPTION/FEATURES • High-breakdown-voltage output port ......................................... 26 • Segment output ............................................ 8 to 18 • Digit output ................................................... 7 to 10 (Ports P0 to P7 are also used as ordinary output ports) • Output breakdown .................................. Vcc – 45 V • Output current .................. –18 mA (DIG0 to DIG17), –7 mA (SEG0 to SEG7) • Pull-down resistor ........................................ build-in • Dimmer switch ............................................ 4 levels A-D converter ................................................... 8-bit ! 6 channels • Absolute accuracy ....................................... ±3 LSB • Serial I/O ..................................... 4 (CS controller, external clock) • Noise filter .................................................... build-in (in serial input pin and clock pin, 2 MHz sampling) • FLD display data ............................................. input • A-D conversion data ..................................... output • Command ....................................................... input Package ................................................................. 44P6N/44P6X Oscillating circuit ........... RC oscillating cirucit (external capacitor) • Oscillating frequency ..................................... 4 MHz Power source voltage .................................................. 4.0 to 5.5 V • • • • PIN CONFIGURATION (TOP VIEW) DIG15/SEG10 DIG14/SEG11 DIG13/SEG12 DIG12/SEG13 DIG11/SEG14 DIG10/SEG15 DIG9/SEG16 DIG8/SEG17 DIG7/P7 25 DIG6/P6 24 33 32 31 30 29 28 27 26 DIG16/SEG9 DIG17/SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VDD 23 DIG5/P5 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 DIG4/P4 DIG3/P3 DIG2/P2 DIG1/P1 DIG0/P0 VEE VEE SCLK SOUT S IN CS M35500AFP M35500BGP VDD VSS X IN RESET AN5 AN4 AN3 AN2 AN1 Package type: 44P6N-A/44P6X Fig. 1. Pin configuration of M35500AFP/BGP XOUT AN0 1 MITSUBISHI M35500AFP/BGP FLD(VFD) CONTROLLER FUNCTIONAL BLOCK DIG8/SEG17 – DIG17/SEG8 SEG7 – SEG0 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 DIG7/P7 25 DIG6/P6 24 DIG5/P5 23 DIG4/P4 22 DIG3/P3 21 DIG2/P2 20 DIG1/P1 19 DIG0/P0 18 VEE 17 VEE 16 Memory address Display RAM Transfer counter Mode register Display control circuit FUNCTIONAL BLOCK DIAGRAM (Package: 44P6N-A) Command analytic circuit Byte end CS 12 SIN 13 SOUT 14 SCLK 15 VDD 44 VDD 1 VSS 3 RESET 5 2 4 6 7 8 9 10 11 Noise filter Noise filter Trigger Clock generating circuit Selector/A-D control circuit Serial I/O A-D XOUT XIN AN5 – AN0 Fig. 2. Functional block diagram 2 MITSUBISHI M35500AFP/BGP FLD(VFD) CONTROLLER PIN DESCRIPTION Table. 1. Pin description Pin VCC, VSS VEE XIN XOUT ______ Name Power source Pull-down power source Clock input Clock output ______ Input Output Function • Apply voltage of 5 V to VCC, and 0 V to VSS. • Applies voltage supplied to pull-down resistors. Input Output CMOS input CMOS input CMOS input Noise filter N-channel open-drain CMOS input Noise filter P-channel open-drain P-channel open-drain P-channel open-drain • RC oscillator pins for system clock. RESET ____ RESET input Chip select Serial clock Serial output Serial input Digit/Port Digit/Segment Segment • Reset input pin for active “L”. • Internal pull-up resistors connected between the RESET and VCC pins. • Serial transfer is possible by inputting “L” signal. • Clock for serial transfer is input. • Read a clock twice with 2 MHz sampling clock and judge if it is a noise or not. • Serial data is output. • During reset it is in high-impedance state. • Serial data is input. • Read a clock twice with 2 MHz sampling clock and judge if it is a noise or not. • Pin for ordinary output or digit output. • At reset this port is set to VEE level through a pull-down resistor. • Pin for digit output or segment output. • At reset this port is set to VEE level through a pull-down resistor. • Pin for segment output. • At reset this port is set to VEE level through a pull-down resistor. CS SCLK SOUT SIN DIG0/P0 – DIG7/P7 DIG8/SEG17 – DIG17/SEG8 SEG0 – SEG7 PORT BLOCK (1) Digit/Port pin Digit/Segment pin Shift signal from high-order Dimmer signal (Note) Data bus Segment data latch V (4) SOUT pin SOUT signal Shift signal to low-order (2) Digit pin Shift signal from high-order Dimmer signal (Note) latch (5) CS pin VEE CS input Noise filter V (6) SIN, SCLK pin Serial input Serial clock input Noise filter Shift signal to low-order VEE (7) A-D input (3) Segment pin Dimmer signal (Note) Segment data latch V A-D conversion input VEE V High-breakdown-voltage P-channel transistor Note: Dimmer signal is for setting the Toff time. Fig. 3. Port block diagram 3 MITSUBISHI M35500AFP/BGP FLD(VFD) CONTROLLER COMMAND STYLE b7 Display data setting (Command 0) 1 b6 1 b5 1 b4 — b3 b2 b1 b0 Number of segment setting 0 0 : 16 or less 0 1 : 17 or more Number of digit setting 00:7 01:8 10:9 1 1 : 10 Display state setting (Command 1) 1 1 0 — — Display ON or OFF setting 1 : ON 0 : OFF Display duty setting 1 1 : 15/16 1 0 : 14/16 0 1 : 6/16 0 0 : 5/16 Digit selection (Command 2) 1 0 1 — Digit start pin setting 0 0 0 0 : D17 0 0 0 1 : D16 0 0 1 0 : D15 0 0 1 1 : D14 0 1 0 0 : D13 0 1 0 1 : D12 0 1 1 0 : D11 0 1 1 1 : D10 1 0 0 0 : D9 1 0 0 1 : D8 1 0 1 0 : D7 Port data setting (Command 3) 1 0 0 P3 – P0/P7 – P4 output data Port selection (Note) 0 : P3 – P0 1 : P7 – P4 Note: When a digit or a port has to be selected, a digit output is selected for having higher priority. Fig. 4. Command style 4 MITSUBISHI M35500AFP/BGP FLD(VFD) CONTROLLER SERIAL I/O PROTOCOL Byte protocol CS CLK b0 b1 b2 b3 b4 b5 b6 b7 SIN SOUT X b0 b1 b2 b3 b4 b5 b6 b7 Note: SOUT is in high-impedance state during CS signal is “H”. Command protocol Display data setting (Command 0) CS CLK SIN SOUT Command 0 Data 1 Data 2 Data i X X A-D data 0 A-D data j Note 1: The serial data which is transmitted after executing command 0 is recognized as a display data. “A-D data 6 or more” data is defined as an undefined “X”. Note 2: Set the CS signal to “H” level after transferring a display data. Other setting except display data setting (Command 1 to 3) CS CLK SIN SOUT Command X Fig. 5. Serial I/O protocol 5 MITSUBISHI M35500AFP/BGP FLD(VFD) CONTROLLER SERIAL COMMUNICATION FORMAT (DISPLAY DATA, A-D OUTPUT) 17 or more segments (3-byte transfer) CS CLK SIN Command 0 SEG 0-7 SEG 8-15 DIG n SEG 16-17 SEG 0-7 SEG 8-15 SEG 16-17 SEG 0-7 SEG SEG 8-15 16-17 DIG n-2 SEG 0-7 SEG 8-15 DIG 0 SEG 16-17 DIG n-1 SOUT X X AD 0 AD 1 AD 2 AD 3 AD 4 AD 5 X X X X X AD valid data Note: 2 bytes “X” data is output before outputting AD valid data. 16 or less segments (2-byte transfer) CS CLK SIN Command 0 SEG 0-7 SEG 8-15 SEG 0-7 SEG 8-15 SEG 0-7 SEG 8-15 SEG 0-7 SEG 8-15 SEG 0-7 SEG 0-7 SEG 8-15 DIG n DIG n-1 DIG n-2 DIG n-3 DIG 0 SOUT X X AD 0 AD 1 AD 2 AD 3 AD 4 AD 5 X X X X X AD valid data Note: 2 bytes “X” data is output before outputting AD valid data. 8 or less segments (2-byte transfer) CS CLK SIN Command 0 SEG dummy SEG dummy SEG dummy SEG dummy SEG 0-7 0-7 0-7 0-7 0-7 data data data data DIG n DIG n-1 DIG n-2 DIG n-3 SEG dummy 0-7 data DIG 0 SOUT X X AD 0 AD 1 AD 2 AD 3 AD 4 AD 5 X X X X X AD valid data Note: 2 bytes “X” data is output before outputting AD valid data. Fig. 6. Serial communication format 6 MITSUBISHI M35500AFP/BGP FLD(VFD) CONTROLLER FLD DISPLAY TIMING Gn G n-1 G1 Segment output Tdisp Tscan = 0ns Digit Tdisp = 384 µs (oscillation frequency f(X IN) = 4.0 MHz) Toff= 264 µs ( 5/16 ! Tdisp) 240 µs ( 6/16 ! Tdisp) 48 µs (14/16 ! Tdisp) 24 µs (15/16 ! Tdisp) Tdisp Segment Toff Fig. 7. FLD display timing diagram SEGMENT/DIGIT SETTING EXAMPLE PORT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 DIG SEG SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 Grid :7 Segment : 8 S1 S2 S3 S4 S5 S6 S7 S8 G7 G6 G5 G4 G3 G2 G1 Grid : 10 Grid : 10 Grid :7 Segment : 8 Segment : 16 Segment : 18 S1 S1 S1 S2 S2 S2 S3 S3 S3 S4 S4 S4 S5 S5 S5 S6 S6 S6 S7 S7 S7 S8 S8 S8 G10 S9 S9 G9 S10 S10 G8 S11 S11 G7 S12 S12 G6 S13 S13 G5 S14 S14 G4 S15 S15 G3 S16 S16 G2 G10 S17 G1 G9 S18 G8 G7 G7 G6 G6 G5 G5 G4 G4 G3 G3 G2 G2 G1 G1 P7 P6 P5 P4 P3 P2 P1 P0 DIG17 DIG16 DIG15 DIG14 DIG13 DIG12 DIG11 DIG10 DIG9 DIG8 DIG7 DIG6 DIG5 DIG4 DIG3 DIG2 DIG1 DIG0 Fig. 8. Segment/Digit setting example 7 MITSUBISHI M35500AFP/BGP FLD(VFD) CONTROLLER BIT ALLOCATION FOR DISPLAY RAM ADDRESS 0916 0A16 0B16 0D16 0E16 0F16 1116 1216 1316 1516 1616 1716 1916 1A16 1B16 1D16 1E16 1F16 2116 2216 2316 2516 2616 2716 2916 2A16 2B16 2D16 2E16 2F16 b7 b0 SEG SEG 17 16 SEG SEG SEG SEG SEG SEG SEG SEG 15 14 13 12 11 10 9 8 SEG SEG SEG SEG SEG SEG SEG SEG 7 6 5 4 3 2 1 0 SEG SEG 17 16 SEG SEG SEG SEG SEG SEG SEG SEG 15 14 13 12 11 10 9 8 SEG SEG SEG SEG SEG SEG SEG SEG 7 6 5 4 3 2 1 0 SEG SEG 17 16 SEG SEG SEG SEG SEG SEG SEG SEG 15 14 13 12 11 10 9 8 SEG SEG SEG SEG SEG SEG SEG SEG 7 6 5 4 3 2 1 0 SEG SEG 17 16 SEG SEG SEG SEG SEG SEG SEG SEG 15 14 13 12 11 10 9 8 SEG SEG SEG SEG SEG SEG SEG SEG 7 6 5 4 3 2 1 0 SEG SEG 17 16 SEG SEG SEG SEG SEG SEG SEG SEG 15 14 13 12 11 10 9 8 SEG SEG SEG SEG SEG SEG SEG SEG 7 6 5 4 3 2 1 0 SEG SEG 17 16 SEG SEG SEG SEG SEG SEG SEG SEG 15 14 13 12 11 10 9 8 SEG SEG SEG SEG SEG SEG SEG SEG 7 6 5 4 3 2 1 0 SEG SEG 17 16 SEG SEG SEG SEG SEG SEG SEG SEG 15 14 13 12 11 10 9 8 SEG SEG SEG SEG SEG SEG SEG SEG 7 6 5 4 3 2 1 0 SEG SEG 17 16 SEG SEG SEG SEG SEG SEG SEG SEG 9 8 15 14 13 12 11 10 SEG SEG SEG SEG SEG SEG SEG SEG 7 6 5 4 3 2 1 0 SEG SEG 17 16 SEG SEG SEG SEG SEG SEG SEG SEG 15 14 13 12 11 10 9 8 SEG SEG SEG SEG SEG SEG SEG SEG 7 6 5 4 3 2 1 0 SEG SEG 17 16 SEG SEG SEG SEG SEG SEG SEG SEG 15 14 13 12 11 10 9 8 SEG SEG SEG SEG SEG SEG SEG SEG 7 6 5 4 3 2 1 0 Digit0 Digit1 Digit2 Digit3 Digit4 Digit5 Digit6 Digit7 Digit8 Digit9 Fig. 9. Bit allocation for display RAM 8 MITSUBISHI M35500AFP/BGP FLD(VFD) CONTROLLER RESET CIRCUIT To reset the controller, the RESET pin should be held at a “L” level for 2 µs or more. Then the RESET pin is returned to an “H” level (the power source voltage should be between 4.0 V and 5.5 V, and XIN oscillation is stable), reset is released. Make sure that the reset input voltage is 0.5 V or less for 4.0 V of VCC. Poweron (Note) RESET VCC 0V 0V 0.2VCC Note. Reset release voltage: VCC = 4.0 V Fig. 10. Reset circuit example CLOCK GENERATING CIRCUIT Oscillating circuit is built up by connecting pins XIN and XOUT as short as possible and connecting a capacitor between pins XIN (XOUT) and VSS. When supplying a clock externally, input it to XIN pin and leave XOUT pin open. X IN XOUT X IN XOUT External oscillation circuit Open COSC VCC VSS Fig. 11. RC generating circuit Fig. 12. External clock input circuit HANDLING OF UNUSED PINS Handle unused pins as the follow. Table. 2. Handling of unused pins Pin Segment Digit Analog input Open Open Connect to VCC or VSS through a resistor. Handling 9 MITSUBISHI M35500AFP/BGP FLD(VFD) CONTROLLER ABSOLUTE MAXIMUM RATINGS Symbol VCC VEE VI VI VI VO Parameter Power source voltage Pull-down power source voltage Input voltage AN0 – AN5 Input voltage CS, SIN, SCLK Input voltage RESET Output voltage DIG0 – DIG17 SEG0 – SEG17 Conditions • All voltage are based on VSS. • Output transistors are cut off. Ratings –0.3 to 7.0 VCC–45 to VCC+0.3 –0.3 to VCC+0.3 –0.3 to VCC+0.3 –0.3 to VCC+0.3 VCC–45 to VCC+0.3 Unit V V V V V • All voltage are based on VSS. • Output transistors are cut off. • A waveform: 450 µs or more frequency and 30 µs or less pulse width. • Connect only capacitor load (CL = 200pF). • All voltage are based on VSS. • Output transistors are cut off. Ta = 25 °C VCC–50 to VCC+0.3 V VO Output voltage SOUT –0.3 to VCC+0.3 600 –20 to 85 –40 to 125 V mW °C °C Pd Topr Tstg Power dissipation Operating temperature Storage temperature RECOMMENDED OPERATING CONDITIONS Symbol VCC VSS VEE VIH VIH VIL VIL Parameter Power source voltage Power source voltage Pull-down power source voltage “H” input voltage CS, SIN, SCLK “H” input voltage RESET “L” input voltage CS, SIN, SCLK “L” input voltage RESET (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Min. 4.0 VCC–38 0.75VCC 0.8VCC 0 0 Limits Typ. 5.0 0 Max. 5.5 VCC VCC VCC 0.25VCC 0.2VCC Unit V V V V V V V RECOMMENDED OPERATING CONDITIONS Symbol ΣIOH(peak) ΣIOH(avg) IOH(peak) IOH(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) f(XIN) f(SCLK) Parameter (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Min. (Note 1) (Note 2) (Note 2) (Note 3) (Note 3) (Note 4) 4.0 250 Limits Typ. Max. –240 –120 –40 –20 10 –18 –7 5.0 5.2 Unit mA mA mA mA mA mA mA mA MHz kHz “H” total peak output current DIG0 – DIG17, SEG0 – SEG17 “H” total peak output current DIG0 – DIG17, SEG0 – SEG17 “H” peak output current DIG0 – DIG17 “H” peak output current SEG0 – SEG7 “L” peak output current SOUT “H” peak output current DIG0 – DIG17 “H” peak output current SEG0 – SEG7 “L” peak output current SOUT Main clock input oscillation frequency Serial I/O external clock frequency Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current is an average value measured over 100 ms. 4: When the oscillation frequency has a 50 % duty cycle. 10 MITSUBISHI M35500AFP/BGP FLD(VFD) CONTROLLER ELECTRICAL CHARACTERISTICS Symbol VOH VOL VT+ — VT– IIH Parameter “H” output voltage “L” output voltage Hysteresis “H” input voltage (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Test conditions IOH = –18 mA IOH = –7 mA IOL = 5 mA VCC = 5.0 V VI = VCC 4.0 VI = VSS –150 –4.0 VEE = VCC–36 V VOL = VCC Output transistors “off” VEE = VCC–38 V VOL = VCC–38 V Output transistors “off” 250 500 750 –5.0 Min. VCC–2.0 VCC–2.0 Limits Typ. Max. Unit V V V V V µA µA µA µA µA µA µA IIL “L” input voltage ILOAD Output load current DIG output SEG output SOUT SIN, SCLK, CS RESET, XIN SIN, SCLK, CS RESET XIN SIN, SCLK, CS RESET XIN DIG0 – DIG17 SEG0 – SEG17 DIG0 – DIG17 SEG0 – SEG17 2.0 0.5 0.5 5.0 5.0 ILEAK Output leakage current –10 µA ELECTRICAL CHARACTERISTICS Symbol VRAM ICC Parameter RAM hold voltage Power source current (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Test conditions When clock is stopped VCC = 5 V, f(XIN) = 4.2 MHz Output transistors “off” at A-D converter operating Min. 2.0 Limits Typ. Max. 5.5 1.0 Unit V mA 0.5 A-D CONVERTER CHARACTERISTICS Symbol — — Tconv VIA IIA RLADDER Parameter (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Test conditions Min. Limits Typ. Max. 8 ±3 100 VCC 5.0 Unit Bits LSB tc(XIN) V µA kΩ Resolution Absolute accuracy (excluding quantization error) Conversion time Analog input voltage Analog port input current Ladder resistor VCC = 5.12 V 0 0.5 35 11 MITSUBISHI M35500AFP/BGP FLD(VFD) CONTROLLER TIMING REQUIREMENTS Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(SCLK) twH(SCLK) twL(SCLK) tsu(SIN-SCLK) th(SCLK-SIN) tsu(CS) th(CS) tre(SCLK) (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Parameter Min. 2 238 60 60 5 2 3 2 3 50 tc(XIN) 50 tc(XIN) 50 tc(XIN) Limits Typ. Max. Unit µs ns ns ns CLKs CLKs CLKs CLKs CLKs ns ns ns Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width Serial clock input cycle time (Note) Serial clock input “H” pulse width (Note) Serial clock input “L” pulse width (Note) Serial input setup time (Note) Serial input hold time (Note) Serial input setup time Serial input hold time Serial clock interval time Note: The unit means a number of noise filter sampling clock (2 ! tc(XIN)). SWITCHING CHARACTERISTICS Symbol td(SCLK-SOUT) tv(SCLK-SOUT) tr(Pch) COSC Parameter (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Test conditions Min. 2 CL = 100pF VEE = VCC–36 V 1.8 22 Limits Typ. Max. 3 3 Unit CLKs CLKs µs pF Serial I/O output delay time (Note 1) Serial I/O output valid time High-breakdown-voltage P-channel open-drain output rising time External capacitor size (Note 2) Note 1: The unit means a number of noise filter sampling clock (2 ! tc(XIN)). 2: An external capacitor size varies with a mounted condition. Measuring condition: Ta = 25 °C, VCC = 5.0 V 8.0 Frequency f(XIN) [MHz] 7.0 6.0 5.0 4.0 3.0 2.0 10 20 30 40 50 60 70 80 90 100 External capacitor size COSC [pF] Fig. 13. Standard characteristic example of f(XIN)–COSC 12 MITSUBISHI M35500AFP/BGP FLD(VFD) CONTROLLER Serial I/O clock output port P-channel output port RL CL VEE CL Fig. 14. Output switching characteristics measurement circuit diagram tw(RESET) RESET 0.2VCC 0.8VCC CS SCLK tsu(CS) trec(SCLK) th(CS) tC(SCLK) twL(SCLK) twH(SCLK) 0.8VCC th(SCLK-SIN) SCLK 0.2VCC tsu(SIN-SCLK) SIN td(SCLK-SOUT) 0.8VCC 0.2VCC tv(SCLK-SOUT) SOUT Fig. 15. Timing diagram 13 MITSUBISHI M35500AFP/BGP FLD(VFD) CONTROLLER PACKAGE OUTLINE 44P6N-A EIAJ Package Code QFP44-P-1010-0.80 HD JEDEC Code – Weight(g) 0.59 Lead Material Alloy 42 Plastic 44pin 10!10mm body QFP MD e D 44 34 1 33 b2 I2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 x y b2 I2 MD ME Dimension in Millimeters Min Nom Max – – 3.05 0.1 0.2 0 – – 2.8 0.3 0.35 0.45 0.13 0.15 0.2 9.8 10.0 10.2 9.8 10.0 10.2 – 0.8 – 12.5 12.8 13.1 12.5 12.8 13.1 0.4 0.6 0.8 1.4 – – – – 0.2 – – 0.1 – 0° 10° – – 0.5 1.3 – – 10.6 – – – – 10.6 HE E 11 23 12 22 A L1 F A1 e b A2 x M y L Detail F 14 c ME MITSUBISHI M35500AFP/BGP FLD(VFD) CONTROLLER 44P6X EIAJ Package Code QFP44-P-1010-0.80 JEDEC Code – HD Weight(g) – Lead Material Cu Alloy Plastic 44pin 10!10mm body QFP MD e 44 34 1 33 b2 I2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 x y b2 I2 MD ME Dimension in Millimeters Min Nom Max 2.3 – – 0 0.2 0.1 2.0 – – 0.3 0.375 0.45 0.15 0.175 0.2 9.9 10.0 10.1 9.9 10.0 10.1 0.8 – – 12.5 12.8 13.1 12.8 13.1 12.5 0.4 0.6 0.8 1.4 – – – – 0.2 0.1 – – 0° 10° – 0.5 – – 1.3 – – 10.6 – – 10.6 – – HE E 11 23 12 22 A L1 e y b F x M A2 A1 L Detail F Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. 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Page 1: Oscillating circuit.....RC oscillating... Page 3, Table 1: RC oscillator Page 9: Fig. 11. RC generating circuit M35500AFP/BGP DATA SHEET Revision Description Rev. date 11/15/97 01/07/00 Page 12, TIMING REQUIREMENTS: Limits of tc(SCLK) and twL(SCLK) Page 12, SWITCHING CHARACTERISTICS: Limits and Unit of tv(SCLK-SOUT) 2.1 Page 15: The 44P6X package outline is added. 03/09/00 (1/1)