M37471M4-833SP

MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 7470/7471 group is a single-chip microcomputer designed with CMOS silicon gate technology. It is housed in a 32-pin shrink plastic molded DIP. The M37471M2-XXXSP/FP is a single-chip microcomputer designed with CMOS silicon gate technology. It is housed in a 42-pin shrink plastic molded DIP or a 56-pin plastic molded QFP. These single-chip microcomputer are useful for business equipment and other consumer applications. In addition to its simple instruction set, the ROM, RAM, and I/O addresses are placed on the same memory map to enable easy programming . The differences between the M37471M2-XXXSP and the M37471M2-XXXFP are the package outline and the power dissipation ability (absolute maximum ratings). The differences among M37470M2-XXXSP, M37470M4-XXXSP, M37470M8-XXXSP, M37471M2-XXXSP/FP, M37471M4-XXXSP/ FP and M37471M8-XXXSP/FP are noted below. PIN CONFIGURATION (TOP VIEW) P17/SRDY P16/CLK P15/SOUT P14/SIN P13/ T1 P12/ T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS 1 2 3 4 5 32 31 30 29 28 P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33 /CNTR1 P32 /CNTR0 P31 /INT1 P30 /INT0 RESET VCC M37470M2-XXXSP M37470M4-XXXSP M37470E4-XXXSP M37470M8-XXXSP M37470E8-XXXSP 6 7 8 9 10 11 12 13 14 15 16 27 26 25 24 23 22 21 20 19 18 17 Type name M37470M2-XXXSP M37471M2-XXXSP/FP M37470M4-XXXSP M37471M4-XXXSP/FP M37470M8-XXXSP M37471M8-XXXSP/FP ROM size 4096 bytes 8192 bytes 16384 bytes RAM size 128 bytes 192 bytes 384 bytes I/O ports 26 36 26 36 26 36 Outline 32P4B APPLICATION Audio-visual equipment, VCR, Tuner, Office automation equipment FEATURES q Basic machine-language instructions ...................................... 71 q Memory size ROM ..................................................... 4096 bytes (M37471M2) RAM ........................................................ 128 bytes (M37471M2) q The minimum instruction execution time ....................................... 0.5 µ s (at 8 MHz oscillation frequency) q Power source voltage .............. 2.7 to 4.5 V (at 2.2VCC–2.0 MHz oscillation frequency) ............................... 4.5 to 5.5 V (at 8 MHz oscillation frequency) q Power dissipation in normal mode ................................... 35 mW (at 8.0 MHz oscillation frequency) q Subroutine nesting ...... 64 levels max. (M37470M2, M37471M2) q Interrupt ................................................... 12 sources, 10 vectors q 8-bit timers .................................................................................. 4 q Programmable I/O ports (Ports P0, P1, P2, P4) ......................................... 22(7470 group) 28(7471 group) q Input port (Port P3) ............................................... 4(7470 group) (Ports P3, P5) ....................................... 8(7471 group) q Serial I/O (8-bit) .......................................................................... 1 q A-D converter ............................... 8-bit, 4channels (7470 group) 8-bit, 8channels (7471 group) MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (TOP VIEW) NC P04 P03 P02 P01 P00 P43 P42 P41 P40 NC P33 /CNTR1 P32 /CNTR0 P31/INT1 P30/INT0 NC 43 37 35 39 41 44 38 36 33 31 40 42 34 32 30 29 P53 P17 /SRDY P16/CLK P15 /SOUT P14 /SIN P13/ T1 P12/ T0 P11 P10 P27 /IN7 P26 /IN6 P25 /IN5 P24 /IN4 P23 /IN3 P22 /IN2 P21 /IN1 P20 /IN0 VREF XIN XOUT VSS 1 2 3 4 5 6 7 42 41 40 39 38 37 36 P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0 RESET P51/XCOUT P50/XIN VCC NC P05 P06 P07 P52 NC VSS P53 P17 /SRDY P16/CLK P15/SOUT NC 45 46 47 48 49 50 51 52 53 54 55 56 28 27 26 8 9 10 11 12 13 14 15 16 17 18 19 20 21 35 34 33 32 31 30 29 28 27 26 25 24 23 22 M37471M2-XXXFP M37471M4-XXXFP M37471E4-XXXFP M37471M8-XXXFP M37471E8-XXXFP 25 24 23 22 21 20 19 18 17 RESET NC P51 /XCOUT P50 /XCIN NC VCC VSS AVSS NC XOUT XIN NC 10 12 11 13 14 Outline 42P4B 42S1B-A (Window) Note : The differences between 42P4B package type of 7471 group and 56P6N-A package type of 7471 group are package outline, power dissipation ability (absolute maximum ratings), and the provision of an AV SS pin by the 56P6N-A package type. NC : No connection 2 NC P14/SIN P13/ T1 P12/ T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23 /IN3 P22/IN2 P21/IN1 P20/IN0 VREF NC Outline 56P6N-A 15 16 1 2 3 4 5 6 7 8 9 M37471M2-XXXSP M37471M4-XXXSP M37471E4-XXXSP M37471M8-XXXSP M37471E8-XXXSP M37471E8SS M37470M2-XXXSP BLOCK DIAGRAM Reset input RESET 18 17 16 Clock input XIN VCC VSS Clock output XOUT 14 15 Clock generating circuit (Note 2) RAM 128 bytes Timer 2 (8) Control signal Processor status register PS (8) Index register Y(8) Stack pointer S(8) Timer 3 (8) Timer 4 (8) PWM control Index register X(8) Program counter PCH(8) 4096 bytes Timer 1 (8) Instruction decoder Program counter PCL (8) ROM Instruction register (8) (Note 1) Data bus 8-bit Arithmetic and logical unit Accumulator A(8) Byte counter (4) INT1 A-D converter S I/O(8) 4 P3(4) P2(4) P1(8) P0(8) CNTR1 CNTR0 INT0 P4(2) 24 23 22 21 20 19 13 9 10 11 12 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 I/O port P4 Input port P3 VREF Reference voltage input I/O port P2 I/O port P1 I/O port P0 Notes 1 : 8192 bytes for M37470M4/E4-XXXSP, and 16384 bytes for M37470M8/E8-XXXSP 2 : 192 bytes for M37470M4/E4-XXXSP, and 384 bytes for M37470M8/E8-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 7470/7471 Group 3 4 Reset input VCC 22 21 M37471M2-XXXSP BLOCK DIAGRAM VSS Main clock Main clock output input XOUT XIN 25 RESET 19 20 Clock generating circuit Data bus (Note 2) RAM ROM 4096 bytes Timer 2 (8) Control signal Processor status register PS (8) Index register X(8) Timer 3 (8) Timer 4 (8) PWM control Index register Y(8) Stack pointer S(8) Timer 1 (8) Instruction decoder 128 bytes Program counter PCH(8) Program counter PCL(8) Instruction register (8) (Note 1) XCIN Sub-clock input XCOUT Sub-clock output 8-bit Arithmetic and logical unit Accumulator A(8) Byte counter (4) INT1 A-D converter S I/O(8) 8 P3(4) P2(8) P1(8) P0(8) CNTR1 CNTR0 INT0 XCOUT XCIN P5(4) P4(4) 1 42 24 23 33 32 31 30 29 28 27 26 18 10 11 12 13 14 15 16 17 2 3 4 5 6 7 8 9 41 40 39 38 37 36 35 34 Input port P5 I/O port P4 Input port P3 VREF Reference voltage input I/O port P2 I/O port P1 I/O port P0 Notes 1 : 8192 bytes for M37471M4/E4-XXXSP, and 16384 bytes for M37471M8/E8-XXXSP, M37471E8SS 2 : 192 bytes for M37471M4/E4-XXXSP, and 384 bytes for M37471M8/E8-XXXSP, M37471E8SS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 7470/7471 Group M37471M2-XXXFP BLOCK DIAGRAM VCC 23 22 51 21 Reset input VSS AVSS Main clock Main clock output input XOUT XIN RESET 18 19 28 Clock generating circuit Data bus (Note 2) RAM ROM 4096 bytes Instruction decoder Timer 2 (8) Control signal Processor status register PS (8) Index register X(8) Index register Y(8) Timer 3 (8) Timer 4 (8) PWM control Stack pointer S(8) Timer 1 (8) 128 bytes Program counter PCH(8) Program counter PCL(8) Instruction register (8) (Note 1) XCIN Sub-clock input XCOUT Sub-clock output 8-bit Arithmetic and logical unit Accumulator A(8) Byte counter (4) INT1 A-D converter S I/O(8) 8 P3(4) P2(8) P1(8) P0(8) CNTR0 INT0 XCOUT XCIN CNTR1 P5(4) P4(4) 52 49 26 25 15 38 37 36 35 33 32 31 30 7 8 9 10 11 12 13 14 53 54 55 2 3 4 5 6 48 47 46 43 42 41 40 39 Input port P5 I/O port P4 Input port P3 VREF Reference voltage input I/O port P2 I/O port P1 I/O port P0 Notes 1 : 8192 bytes for M37471M4/E4-XXXFP, and 16384 bytes for M37471M8/E8-XXXFP 2 : 192 bytes for M37471M4/E4-XXXFP, and 384 bytes for M37471M8/E8-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 7470/7471 Group 5 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONS OF 7470/7471 GROUP Parameter Basic machine-language instructions Instruction execution time Clock input oscillation frequency M37470M2 M37471M2 Memory size M37470M4/E4 M37471M4/E4 M37470M8/E8 M37471M8/E8 P0, P1 Input/Output port P2 P3, P5 P4 Serial I/O Timers A-D converter ROM RAM ROM RAM ROM RAM I/O I/O Input I/O 71 0.5 µ s (the minimum instructions, at 8 MHz oscillation frequency) 8 MHz (max.) 4096 bytes 128 bytes 8192 bytes 192 bytes 16384 bytes 384 bytes 8-bit ! 2 8-bit ! 1 (4-bit ! 1 for 7470 group) 4-bit ! 2 (Port P5 is not included in 7470 group) 4-bit ! 1 (2-bit ! 1 for 7470 group) 8-bit ! 1 8-bit timer ! 4 8-bit ! 1 (8 channels) (8-bit ! 1 (4 channels) for M37470M2/M4/M8) 64 level max. (M37470M2, M37471M2) Subroutine nesting 96 level max. (M37470M4/E4, M37471M4/E4) 192 level max. (M37470M8/E8, M37471M8/E8) Interrupt Clock generating circuit Power source voltage Power dissipation Input/Output characters Input/Output voltage Output current 5 external interrupts, 6 internal interrupts, 1 software interrupt Built-in circuit with internal feedback resistor (a ceramic or a quartzcrystal oscillator) 2.7 to 4.5 V (at 2.2V CC–2.0 MHz oscillation frequency), 4.5 to 5.5 V (at 8 MHz oscillation frequency) 35 mW (at 8 MHz oscillation frequency) 5V –5 to 10 mA (P0, P1, P2, P4 : CMOS tri-states) –20 to 85° C CMOS silicon gate M37470M2/M4/M8/E4/E8-XXXSP Package M37471M2/M4/M8/E4/E8-XXXSP M37471M2/M4/M8/E4/E8-XXXFP M37471E8SS 32-pin shrink plastic molded DIP 42-pin shrink plastic molded DIP 56-pin plastic molded QFP 42-pin ceramic DIP Functions Operating temperature range Device structure 6 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Pin VCC , VSS AVSS (Note 1) RESET XIN Name Power source voltage Analog power source Reset input Clock input Input Input Input/ Output Functions Apply voltage of 2.7 to 5.5 V to VCC, and 0 V to V SS. Ground level input pin for A-D converter. Same voltage as VSS is applied. To enter the reset state, the reset input pin must be kept at “L” for 2 µ s or more (under normal V CC conditions). These are I/O pins of internal clock generating circuit for main clock. To control generating frequency, an external ceramic or a quartz-crystal oscillator is connected between the XIN and XOUT pins. If an external clock is used, the clock source should be connected the XIN pin and the XOUT pin should be left open. Feedback resistor is connected between XIN and XOUT. Reference voltage input pin for the A-D converter. Port P0 is an 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 1-bit and a key on wake up function is provided. Port P1 is an 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 4-bit. P12, P13 are in common with timer output pins T0 , T1 , P14, P15, P16 , P17 are in common with serial I/O pins SIN, SOUT, CLK, S RDY, respectively. The output structure of SOUT and SRDY can be changed to N-channel open drain output. Port P2 is an 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 4-bit. This port is in common with analog input pins IN0–IN7 . Port P3 is a 4-bit input port. P30, P31 are in common with external interrupt input pins INT0, INT1 , and P32 , P33 are in common with timer input pins CNTR0, CNTR1 . Port P4 is a 4-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 4-bit. Port P5 is a 4-bit input port and pull-up transistor can be connected in units of 4-bit. P50 , P51 are in common with input/output pins of clock for clock function XCIN , XCOUT. When P5 0, P51 are used as XCIN, XCOUT, connect a ceramic or a quartz-crystal oscillator between XCIN and XCOUT. If an external clock input is used, connect the clock input to the XCIN pin and open the XCOUT pin. Feedback resistor is connected between XCIN and XCOUT pins. XOUT Clock output Output VREF P00 –P07 Reference voltage input I/O port P0 Input I/O P10 –P17 I/O port P1 I/O P20 –P27 (Note 2) I/O port P2 I/O P30 –P33 Input port P3 Input P40 –P43 (Note 3) P50 –P53 (Note 4) I/O port P4 Input port P5 I/O Input Notes 1 2 3 4 : : : : AVSS for M37471M2/M4/M8/E4/E8-XXXFP. Only P20–P23 (IN0–IN 3) 4-bit for 7470 group. Only P40 and P4 1 2-bit for 7470 group. This port is not included in 7470 group. 7 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 7470/7471 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 User’s Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The MUL, DIV, WIT, and STP instruction can be used. CPU Mode Register The CPU mode register is allocated at address 00FB16. This register contains the stack page selection bit. b7 b0 CPU mode register (Address 00FB 16) These bits must always be set to “0”. Stack page selection bit (Note 1) 0 : In page 0 area 1 : In page 1 area P50, P51/XCIN , XCOUT selection bit (Note 2) 0 : P50 , P51 1 : XCIN , XCOUT XCOUT drive capacity selection bit (Note 2) 0 : Low 1 : High Clock (XIN -XOUT ) stop bit (Note 2) 0 : Oscillates 1 : Stops Internal system clock selection bit (Note 2) 0 : XIN -XOUT selected (normal mode) 1 : XCIN -XCOUT selected (low-speed mode) Notes 1 : In the M37470M2, M37470M4/E4, M37471M2, M37471M4/E4, set this bit to “0”. 2 : In the 7470 group, set this bit to “0”. Fig. 1 Structure of CPU mode register 8 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MEMORY • Special Function Register (SFR) Area The special function register (SFR) area contains the registers relating to functions such as I/O ports and timers. • RAM RAM is used for data storage as well as a stack area. • ROM ROM is used for storing user programs as well as the interrupt vector area. • Interrupt Vector Area The interrupt vector area is for storing jump destination addresses used at reset or when an interrupt is generated. • Zero Page Zero page addressing mode is useful because it enables access to this area with fewer instruction cycles. • Special Page Special page addressing mode is useful because it enables access to this area with fewer instruction cycles. 000016 RAM (192 bytes) for M37470M4/E4 M37470M8/E8 M37471M4/E4 M37471M8/E8 RAM (128 bytes) for M37470M2 M37471M2 007F 16 Not used 00BF16 Zero page SFR area 00FF16 010016 RAM (192 bytes) for M37470M8/E8 M37471M8/E8 01BF16 Not used C00016 E00016 F000 16 ROM (16K bytes) for M37470M8/E8 M37471M8/E8 ROM (8K bytes) for M37470M4/E8 M37471M4/E8 FF0016 ROM (4K bytes) for M37470M2 M37471M2 FFEA 16 Interrupt vector area FFFF16 Special page Fig. 2 Memory map 9 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 Port P0 Port P0 direction register Port P1 Port P1 direction register Port P2 Port P2 direction register Port P3 Port P4 Port P4 direction register Port P5 (Note 1) 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 P0 pull-up control register P1–P5 pull-up control register (Note 2) 00F016 00F116 00F216 00F316 Timer 1 Timer 2 Timer 3 Timer 4 Edge polarity selection register Input latch register 00F416 00F516 00F616 00F716 00F816 Timer FF register Timer 12 mode register Timer 34 mode register Timer mode register 2 CPU mode register Interrupt request register 1 Interrupt request register 2 Interrupt control register 1 Interrupt control register 2 A-D control register A-D conversion register 00F916 00FA16 00FB16 00FC16 00FD16 Byte counter 00FE16 00FF16 00DC16 Serial I/O mode register 00DD16 Serial I/O register 00DE16 00DF16 Serial I/O counter Notes 1 : This address is not used in the 7470 group. 2 : This address is allocated P1–P4 pull-up control register for the 7470 group. Fig. 3 SFR (Special Function Register) memory map 10 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER INTERRUPTS Interrupts can be caused by 12 different sources consisting of five external, six internal, and one software sources. Interrupts are vectored interrupts with priorities shown in Table 1. Reset is also included in the table because its operation is similar to an interrupt. When an interrupt is accepted, the registers are pushed, interrupt disable flag I is set, and the program jumps to the address specified in the vector table. The interrupt request bit is cleared automatically. The reset and BRK instruction interrupt can never be disabled. Other interrupts are disabled when the interrupt disable flag is set. All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit. The interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. External interrupts INT0 and INT1 can be asserted on either the falling or rising edge as set in the edge polarity selection register. When “0” is set to this register, the interrupt is activated on the falling edge; when “1” is set to the register, the interrupt is activated on the rising edge. When the device is put into power-down state by the STP instruction or the WIT instruction, if bit 5 in the edge polarity selection register is “1”, the INT1 interrupt becomes a key on wake up interrupt. When a key on wake up interrupt is valid, an interrupt request is generated by applying the “L” level to any pin in port P0. In this case, the port used for interrupt must have been set for the input mode. If bit 5 in the edge polarity selection register is “0” when the device is in power-down state, the INT1 interrupt is selected. Also, if bit 5 in the edge polarity selection register is set to “1” when the device is not in a power-down state, neither key on wake up interrupt request nor INT1 interrupt request is generated. The CNTR0/CNTR 1 interrupts function in the same as INT 0 and INT1 . The interrupt input pin can be specified for either CNTR0 or CNTR1 pin by setting bit 4 in the edge polarity selection register. Figure 4 shows the structure of the edge polarity selection register, interrupt request registers 1 and 2, and interrupt control registers 1 and 2. Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is “1”, interrupt request bit is “1”, and the interrupt disable flag is “0”. The interrupt request bit can be reset with a program, but not set. The interrupt enable bit can be set and reset with a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 5 shows interrupts control. Table 1. Interrupt vector address and priority Interrupt source RESET INT 0 interrupt INT 1 interrupt or key on wake up interrupt CNTR 0 interrupt or CNTR1 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt Serial I/O interrupt A-D conversion completion interrupt BRK instruction interrupt Priority 1 2 3 4 5 6 7 8 9 10 11 Vector addresses FFFF16 , FFFE 16 FFFD16 , FFFC 16 FFFB16 , FFFA16 FFF916, FFF816 FFF716, FFF616 FFF516, FFF416 FFF316, FFF216 FFF116, FFF016 FFEF16 , FFEE 16 FFED16 , FFEC16 FFEB16 , FFEA 16 Non-maskable software interrupt Non-maskable External interrupt (polarity programmable) External interrupt (INT1 is polarity programmable) External interrupt (polarity programmable) Remarks 11 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Edge polarity selection register (EG) (Address 00D4 16) INT0 edge selection bit INT1 edge selection bit CNTR0 edge selection bit CNTR1 edge selection bit 0 : Falling edge 1 : Rising edge CNTR0/CNTR1 interrupt selection bit 0 : CNTR0 1 : CNTR1 INT1 source selection bit (at power-down state) 0 : P31/INT1 1 : P00–P07 “L” level (for key-on wake-up) Nothing is allocated (The value is undefined at reading) b7 b0 b7 b0 Interrupt request register 1 (Address 00FC 16) Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Timer 4 interrupt request bit Nothing is allocated (The value is undefined at reading) Serial I/O transmit interrupt request bit A-D conversion completion interrupt request bit b7 b0 b7 b0 Interrupt request register 2 (Address 00FD 16) INT0 interrupt request bit INT1 interrupt request bit CNTR0 or CNTR1 interrupt request bit 0 : No interrupt request 1 : Interrupt requested Nothing is allocated (The value is undefined at reading) Interrupt control register 1 (Address 00FE 16) Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit Timer 4 interrupt enable bit Nothing is allocated (The value is undefined at reading) Serial I/O receive interrupt enable bit A-D conversion completion interrupt enable bit Interrupt control register 2 (Address 00FF 16) INT0 interrupt enable bit INT1 interrupt enable bit CNTR0 or CNTR1 interrupt enable bit 0 : Interrupt disable 1 : Interrupt enabled Nothing is allocated (The value is undefined at reading) Fig. 4 Structure of registers related to interrupt Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Interrupt request Fig. 5 Interrupt control 12 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMER The 7470/7471 group has four timers; timer 1, timer 2, timer 3, and timer 4. A block diagram of timer 1 through 4 is shown in Figure 6. Timer 1 can be operated in the timer mode, event count mode, or pulse output mode. Timer 1 starts counting when bit 0 in the timer 12 mode register (address 00F816 ) is set to “0”. The count source can be selected from the f(X IN) divided by 16, f(XCIN ) divided by 16, f(XCIN ), or event input from P32/CNTR0 pin. Do not select f(XCIN ) as the count source in the 7470 group. When bit 1 and bit 2 in the timer 12 mode register are “0”, f(X IN) divided by 16 or f(XCIN ) divided by 16 is selected. Selection between f(XIN) and f(XCIN) is done by bit 7 in the CPU mode register (address 00FB16 ). When bit 1 in the timer 12 mode register is “0” and bit 2 is “1”, f(X CIN) is selected. And, when bit 1 in the timer 12 mode register is “1”, an event input from the CNTR 0 p in is selected. Event inputs are selected depending on bit 2 in the edge polarity selection register (address 00D4 16). When this bit is “0”, the inverted value of CNTR 0 i nput is selected; when the bit is “1”, CNTR0 input is selected. When bit 3 in the timer 12 mode register is set to “1”, the P12 pin becomes timer output T0 . When the direction register of P12 is set for the output mode at this time, the timer 1 overflow divided by 2 is output from T0. Please set the initial output value in the following procedure. Œ Set “1” to bit 0 of the timer 12 mode register. (Timer 1 count stop.)  Set “1” to bit 0 of the timer mode register 2. Ž Set the output value to bit 0 of the timer FF register.  Set the count value to the timer 1.  Set “0” to bit 0 of the timer 12 mode register. (Timer 1 count start.) Timer 2 can only be operated in the timer mode. Timer 2 starts counting when bit 4 in the timer 12 mode register is set to “0”. The count source can be selected from the divide by 16, divide by 64, divide by 128, or divide by 256 frequency of f(XIN ) or f(XCIN ), and timer 1 overflow. Do not select f(XCIN ) as the count source in the 7470 group. When bit 5 in the timer 12 mode register is “0”, any of the divide by 16, divide by 64, divide by 128, or divide by 256 frequency of f(XIN) or (XCIN ) is selected. The divide ratio is selected according to bit 6 and bit 7 in the timer 12 mode register, and selection between f(X IN) and f(XCIN) is made according to bit 7 in the CPU mode register. When bit 5 in the timer 12 mode register is “1”, timer 1 overflow is selected as the count source. Timer 3 can be operated in the timer mode, event count mode, or PWM mode. Timer 3 starts counting when bit 0 in the timer 34 mode register (address 00F9 16) is set to “0”. The count source can be selected from the f(XIN ) divided by 16, f(XCIN) divided by 16, f(X CIN), timer 1 or timer 2 overflow, or an event input from P33/CNTR1 pin according to the statuses of bit 1 and bit 2 in the timer 34 mode register, bit 6 in the timer mode register 2 (address 00FA16 ) and bit 7 in the CPU mode register. Do not select f(XCIN) as the count source in the 7470 group. Note, however, that if timer 1 overflow or timer 2 overflow is selected for the count source of timer 3 when timer 1 overflow is selected for the count source of timer 2, timer 1 overflow is always selected regardless of the status of bit 6 in the timer mode register 2. Event inputs are selected depending on bit 3 in the edge polarity selection register. When this bit is “0”, the inverted value of CNTR1 input is selected; when the bit is “1”, CNTR1 input is selected. Timer 4 can be operated in the timer mode, event count mode, pulse output mode, pulse width measuring mode, or PWM mode. Timer 4 starts counting when bit 3 in the timer 34 mode register is set to “0” when bit 6 in this register is “0”. When bit 6 is “1”, the pulse width measuring mode is selected. The count source can be selected from timer 3 overflow, f(XIN) divided by 16, f(XCIN ) divided by 16, f(XCIN), timer 1 or timer 2 overflow, or an event input from P33/CNTR 1 pin according to the statuses of bit 4 and bit 5 in the timer 34 mode register, bit 6 in the timer mode register 2, and bit 7 in the CPU mode register. Do not select f(XCIN ) as the count source in the 7470 group. Note, however, that if timer 1 overflow or timer 2 overflow is selected for the count source of timer 4 when timer 1 overflow is selected for the count source of timer 2, timer 1 overflow is always selected regardless of the status of bit 6 in the timer mode register 2. Event inputs are selected depending on bit 3 in the edge polarity selection register. When this bit is “0”, the inverted value of CNTR1 input is selected; when the bit is “1”, CNTR1 input is selected. When bit 7 in the timer 34 mode register is set to “1”, the P13 pin becomes timer output T1. When the direction register of P1 3 is set for the output mode at this time, the timer 4 overflow divided by 2 is output from T1 when bit 7 in the timer mode register 2 is “0”. Please set the initial output value in the following procedure. Œ Set “1” to bit 3 of the timer 34 mode register. (Timer 4 count stop.)  Set “1” to bit 1 of the timer mode register 2. Ž Set the output value to bit 1 of the timer FF register.  Set the count value to the timer 4.  Set “0” to bit 3 of the timer 34 mode register. (Timer 4 count start.) (1) Timer mode Timer performs down count operations with the dividing ratio being 1/(n+1). Writing a value to the timer latch sets a value to the timer. When the value to be set to the timer latch is nn16 , the value to be set to a timer is nn16 , which is down counted at the falling edge of the count source from nn 16 t o (nn16-1) to (nn 16-2) to ...01 16 t o 0016 to FF16 . At the falling edge of the count source immediately after timer value has reached FF16, value (nn16-1) obtained by subtracting one from the timer latch value is set (reloaded) to the timer to continue counting. At the rising edge of the count source immediately after the timer value has reached FF16 , an overflow occurs and an interrupt request is generated. 13 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (2) Event count mode Timer operates in the same way as in the timer mode except that it counts input from the CNTR0 or CNTR1 pin. (3) Pulse output mode In this mode, duty 50% pulses are output from the T0 or T1 pin. When the timer overflows, the polarity of the T0 or T 1 pin output level is inverted. (4) Pulse width measuring mode The 7470/7471 group can measure the “H” or “L” width of the CNTR 0 or CNTR 1 input waveform by using the pulse width measuring mode of timer 4. The pulse width measuring mode is selected by writing “1” to bit 6 in the timer 34 mode register. In the pulse width measuring mode, the timer counts the count source while the CNTR0 or CNTR1 input is “H” or “L”. Whether the CNTR0 input or CNTR1 input to be measured can be specified by the status of bit 4 in the edge polarity selection register; whether the “H” width or “L” width to be measured can be specified by the status of bit 2 (CNTR 0) and bit 3 (CNTR1) in the edge polarity selection register. (5) PWM mode The PWM mode can be entered for timer 3 and timer 4 by setting bit 7 in the timer mode register 2 to “1”. In the PWM mode, the P13 pin is set for timer output T1 to output PWM waveforms by setting bit 7 in the timer 34 mode register to “1”. The direction register of P13 must be set for the output mode before this can be done. In the PWM mode, timer 3 is counting and timer 4 is idle while the PWM waveform is “L”. When timer 3 overflows, the PWM waveform goes “H”. At this time, timer 3 stops counting simultaneously and timer 4 starts counting. When timer 4 overflows, the PWM waveform goes “L”, and timer 4 stops and timer 3 starts counting again. Consequently, the “L” duration of the PWM waveform is determined by the value of timer 3; the “H” duration of the PWM waveform is determined by the value of timer 4. When a value is written to the timer in operation during the PWM mode, the value is only written to the timer latch, and not written to the timer. In this case, if the timer overflows, a value one less the value in the timer latch is written to the timer. When any value is written to an idle timer, the value is written to both the timer latch and the timer. In this mode, do not select timer 3 overflow as the count source for timer 4. INPUT LATCH FUNCTION The 7470/7471 group can latch the P30 /INT0 , P31 /INT 1 , P32 / CNTR0, and P3 3/CNTR1 pin level into the input latch register (address 00D616) when timer 4 overflows. The polarity of each pin latched to the input latch register can be selected by using the edge polarity selection register. When bit 0 in the edge polarity selection register is “0”, the inverted value of the P30/INT 0 pin level is latched; when the bit is “1”, the P30/INT0 pin level is latched as it is. When bit 1 in the edge polarity selection register is “0”, the inverted value of the P31 /INT 1 pin level is latched; when the bit is “1”, the P31/INT 1 pin level is latched as it is. When bit 2 in the edge polarity selection register is “0”, the inverted value of the P32 / CNTR0 pin level is latched; when the bit is “1”, the P3 2/CNTR0 pin level is latched as it is. When bit 3 in the edge polarity selection register is “0”, the inverted value of the P33 /CNTR1 pin level is latched; when the bit is “1”, the P33/CNTR1 pin level is latched as it is. 14 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XCIN (Note 1) Data bus 1/2 1/2 CM7 1/8 T12M 2 T12M 0 Timer 1 latch (8) Timer 1 interrupt request XIN P32/CNTR0 Timer 1 (8) EG 2 Port latch T12M 1 TM20 1/2 T12M3 P12/T0 Timer 2 latch (8) T12M6 T12M7 T12M 5 TM2 6 T34M 1 T34M 2 Timer 3 latch (8) T34M 0 P33/CNTR1 EG3 T34M 4 T34M 5 Timer 4 latch (8) Timer 4 interrupt request Timer 3 (8) Timer 3 interrupt request T12M4 Timer 2 (8) 1/4 1/8 1/16 Timer 2 interrupt request Timer 4 (8) Port latch P13 /T1 T34M 6 EG 4 T34M3 1/2 EG3 EG2 EG1 EG0 TM27 F/F T34M7 P33 /CNTR1 P32 /CNTR0 P31 /INT1 P30 /INT0 ( TM2 1 C D3 Q3 D2 Q2 D1 Q1 D0 Q0 Select gate : At reset, shaded side is connected.) Note 1 : The 7470 group does not have XCIN input. Fig. 6 Block diagram of timer 1 through 4 15 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Timer mode register 2 (TM2) (Address 00FA 16) Timer 1 overflow FF set enable bit 0 : Set disable 1 : Set enable Timer 4 overflow FF set enable bit 0 : Set disable 1 : Set enable Nothing is allocated (The value is undefined at reading) Timer 3, timer 4 count overflow signal selection bit 0 : Timer 1 overflow 1 : Timer 2 overflow Timer 3, timer 4 function selection bit 0 : Normal mode 1 : PWM mode b7 b0 Timer 34 mode register (T34M) (Address 00F9 16) Timer 3 count stop bit 0 : Count start 1 : Count stop Timer 3 count source selection bits (Note 3) 00 : f(XIN ) divided by 16 or f(X CIN ) divided by 16 01 : f(XCIN ) 10 : Timer 1 overflow or timer 2 overflow 11 : P33 /CNTR1 external clock Timer 4 count stop bit 0 : Count start 1 : Count stop Timer 4 count source selection bits (Note 3) 00 : Timer 3 overflow 01 : f(XIN ) divided by 16 or f(X CIN ) divided by 16 10 : Timer 1 overflow or timer 2 overflow 11 : P33 /CNTR1 external clock Timer 4 pulse width measuring mode selection bit 0 : Timer mode 1 : Pulse width measuring mode P13/T1 port output selection bit 0 : P13 port output 1 : Timer 4 overflow divided by 2 or PWM output b7 b0 Timer 12 mode register (T12M) (Address 00F8 16) Timer 1 count stop bit 0 : Count start 1 : Count stop Timer 1 count source selection bit 0 : Internal clock (Note 1) 1 : P32/CNTR0 external clock Timer 1 internal clock source selection bit (Note 2) 0 : f(XIN) divided by 16 or f(XCIN ) divided by 16 1 : f(XCIN ) P12 /T0 port output selection bit 0 : P12 port output 1 : Timer 1 overflow divided by 2 Timer 2 count stop bit 0 : Count start 1 : Count stop Timer 2 count source selection bit 0 : Internal clock 1 : Timer 1 overflow Timer 2 internal clock source selection bits (Note 3) 00 : f(XIN) divided by 16 or f(XCIN ) divided by 16 01 : f(XIN) divided by 64 or f(XCIN ) divided by 64 10 : f(XIN) divided by 128 or f(XCIN ) divided by 128 11 : f(XIN) divided by 256 or f(XCIN ) divided by 256 Notes 1 : f(X IN ) divided by 16 in the 7470 group. 2 : The 7470 group does not use this bit (bit 2). Set this bit to “0”. 3 : Do not select f(X CIN ) as the count source in the 7470 group. Fig. 7 Structure of timer mode registers 16 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SERIAL I/O The block diagram of serial I/O is shown in Figure 8. In the serial I/O mode, the receive ready signal (SRDY ), synchronous input/output clock (CLK), and the serial I/O (SOUT, SIN ) pins are used as P17, P16, P15 , and P14 , respectively. The serial I/O mode register (address 00DC 16) is an 8-bit register. Bit 2 of this register is used to select a synchronous clock source. When this bit is “0”, an external clock from P16 is selected. When this bit is “1”, an internal clock is selected. The internal clock can be selected from among the divide by 8, divide by 16, divide by 32, divide by 512 frequency of the oscillator frequency f(X IN ) or f(XCIN ). Do not select f(XCIN ) as the count source in the 7470 group. The divide ratio is selected according to bit 0 and bit 1 in the serial I/O mode register, and selection be- tween f(XIN ) and f(XCIN ) is mode according to bit 7 in the CPU mode register. Bits 3 and 4 decide whether parts of P1 will be used as a serial I/O or not. When bit 3 is “1”, P16 becomes an I/O pin of the synchronous clock. When an internal synchronous clock is selected, the clock is output from P1 6. If the external synchronous clock is selected, the clock is input to P16 . And P15 will be a serial output. To use P14 as a serial input, set the direction register bit which corresponds to P14, to “0”. For more information on the direction register, refer to the I/O pin section. (Note 1) XCIN 1/2 XIN 1/2 CM7 1/4 1/2 Counter 1/4 1/64 SARDY SM2 SRDY SM5 CLK input Sync. circuit SM1 SM0 CLK output Serial I/O counter (3) Serial I/O interrupt request SM6 Byte counter (4) SC Data bus SIN Serial I/O register (8) SOUT S Q R ( Select gate : At reset, shaded side is connected.) Note 1 : The 7470 group does not have X CIN input. Fig. 8 Block diagram of serial I/O 17 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Bit 4 determines if P1 7 is used as an output pin for the receive ready signal (bit 4=“1”, S RDY) or used as a normal I/O pin (bit 4=“0”). When the P17 pin is used as the SRDY output pin, output signal can be selected between SRDY signal and SARDY signal by using bit 5 in the serial I/O mode register. The SRDY signal is driven “L” by a signal written into the serial I/O register to inform that the device is ready to receive. Then, the SRDY signal is driven “H” on the first falling edge of the transfer clock. The SA RDY signal is driven “H” by a signal written into the serial I/O register, and driven “L” on the last rising edge of the transfer clock. The function of serial I/O differs depending on the clock source; external clock or internal clock. Internal Clock – The serial I/O counter is set to 7 when data is stored in the serial I/O register. At each falling edge of the transfer clock, serial data is output to P15 . During the rising edge of this clock, data can be input from P1 4 and the data in the serial I/O register will be shifted 1 bit. Data is output starting with the LSB. After the transfer clock has counted 8 times, the serial I/O register will be empty and the transfer clock will remain at a high level. At this time the interrupt request bit will be set. External Clock – If an external clock is used, the interrupt request bit will be set after the transfer clock has counted 8 times but the transfer clock will not stop. Due to this reason, the external clock must be controlled from the outside. Timing diagrams are shown in Figure 9. Synchronous clock Transfer clock Serial I/O register write signal Serial I/O output SOUT Serial I/O input SIN Receive ready signal SRDY Interrupt request bit set D0 D1 D2 D3 D4 D5 D6 D7 Fig. 9 Serial I/O timing 18 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Serial I/O mode register (SM) (Address 00DC 16) Internal clock selection bits 00 : f(XIN ) or f(XcIN ) divided by 8 01 : f(XIN ) or f(XcIN ) divided by 16 10 : f(XIN ) or f(XcIN ) divided by 32 11 : f(XIN ) or f(XcIN ) divided by 512 Synchronous clock selection bit 0 : External clock 1 : Internal clock Serial I/O port selection bit 0 : Normal I/O port 1 : S OUT , CLK pins SRDY signal output selection bit 0 : Normal I/O port 1 : S RDY signal output pin SRDY signal selection bit 0 : S RDY signal 1 : SARDY signal Serial I/O byte specify mode selection bit 0 : Normal mode 1 : Byte specify mode P15/SOUT, P17 /SRDY output structure selection bit 0 : CMOS output 1 : N-channel open drain output Note : Do not select f(X CIN) as the count source in the 7470 group. Fig. 10 Structure of serial I/O mode register BYTE SPECIFY MODE The serial I/O has a byte specify mode that allows one specific byte data to be selected for transmission or reception when serial I/O circuits of two or more microcomputers are connected to send or receive data through one bus. The data to be sent or received can be specified by writing a value into the byte counter. The value written in the byte counter is decremented by one each time eight cycles of transfer clock are input. When the value in the byte counter becomes “0”, serial transmission/reception is done by the next eight cycles of transfer clock. When the value in the byte counter is not “0”, the output on the SOUT pin is driven “H” by the falling edge of the first transfer clock pulse to inhibit transmission/ reception. Serial I/O interrupt requests are generated only when serial transmission/reception is done after the value in the byte counter is decremented to “0”. When the SA RDY signal output is selected, the SARDY signal is driven “L” by the last rising edge of the transfer clock after the value in the byte counter is decremented to “0”. Note that in the byte mode, an external clock must be used as the sync. clock for the purpose of the mode. 19 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D CONVERTER The A-D conversion uses an 8-bit successive comparison method. Figure 11 shows a block diagram of the A-D conversion circuit. Conversion is automatically carried out once started by the program. There are eight analog input pins which are shared with P20 to P27 of port P2 (Only P20 to P23 4-bit for 7470 group. Which analog inputs are to be A-D converted is specified by using bit 2 to bit 0 in the A-D control register (address 00D9 16 ). Pins for inputs to be A-D converted must be set for input by setting the direction register bit to “0”. Bit 3 in the A-D control register is an A-D conversion end bit. This is “0” during A-D conversion; it is set to “1” when the conversion is terminated. Therefore, it is possible to know whether A-D conversion is terminated by checking this bit. Bit 4 in the A-D control register is a V REF connection selection bit. During A-D conversion, this bit must be set “1” for the ladder resistor and V REF p in to be connected; after the A-D conversion is terminated, this bit can be reset to “0” to separate the ladder resistor from the VREF pin. In this way, power consumption in the ladder resistor can be suppressed while no A-D conversion is performed. Figure 13 shows the relationship between the contents of A-D control register and the selected input pins. The A-D conversion register (address 00DA 16 ) contains information on the results of conversion, so that it is possible to know the results of conversion by reading the contents of this register. The following explains the procedure to execute A-D conversion. First, set values to bit 2 to bit 0 in the A-D control register to select the pins that you want to execute A-D conversion. Next, clear the A-D conversion end bit to “0”. When the above is done, A-D conversion is initiated. The A-D conversion is completed after an elapse of 50 machine cycles (12.5 µs when f(XIN)= 8 MHz), the A-D conversion end bit is set to “1”, and the interrupt request bit is set to “1”. The results of conversion are contained in the A-D conversion register. Data bus bit 4 bit 0 A-D control register (Address 00D9 16) P20/IN0 P21/IN1 A-D control circuit A-D conversion completion interrupt request P23/IN3 P24/IN4 P25/IN5 P26/IN6 P27/IN7 Channel selector P22/IN2 Comparator A-D conversion register (Address 00DA 16) Switch tree Ladder resistor VSS (Note 1) Notes 1 : AVSS for M37471M2/M4/M8/E4/E8-XXXFP 2 : 7470 group does not have P2 4/IN4 to P27 /IN7 pins. VREF Fig. 11 A-D converter circuit 20 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 A-D control register (Address 00D9 16) Analog input selection bit s 000 : IN 0 001 : IN 1 010 : IN 2 011 : IN 3 100 : IN 4 101 : IN 5 (Note) 110 : IN 6 111 : IN 7 A-D conversion end bit 0 : Under conversion 1 : End conversion VREF connection selection bit 0 : VREF is separated 1 : VREF is connected Nothing is allocated (The value is undefined at reading) This bit must be set to “0”. Note : Do not select IN4 to IN7 in the 7470 group. Fig. 12 Structure of A-D control register 21 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER KEY ON WAKE UP “Key on wake up” is one way of returning from a power down state caused by the STP or WIT instruction. If any terminal of port P0 has “L” level applied, after bit 5 of the edge polarity selection register (EG 5 ) is set to “1”, an interrupt is generated and the microcomputer is returned to the normal operating state. A key matrix can be connected to port P0 and the microcomputer can be returned to a normal state by pushing any key. The key on wake up interrupt is common with the INT1 interrupt. When EG5 is set to “1”, the key on wake up function is selected. However, key on wake up cannot be used in the normal operating state. When the microcomputer is in the normal operating state, both key on wake up and INT1 are invalid. P33 /CNTR1 Port P33 data read circuit EG3 EG2 EG 4 Port P32 data read circuit XCIN (P50 ) XIN P30/INT 0 1/2 1/2 CM 7 Port P3 0 data read circuit Noise eliminating circuit CNTR interrupt request signal P32/CNTR0 INT0 interrupt request signal P31/INT 1 EG0 Port P3 1 data read circuit Noise eliminating circuit EG5 INT1 interrupt request signal EG1 CPU halt state signal Pull-up control register Direction register P07 P01 Pull-up control register Direction register Port P0 data read circuit Pull-up control register Direction register P00 ( Select gate: At reset, shaded side is connected.) Note : The 7470 group does not have X CIN input. Fig. 13 Block diagram of interrupt input and key on wake up circuit 22 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER RESET CIRCUIT The 7470/7471 group are reset according to the sequence shown in Figure 15. It starts the program from the address formed by using the content of address FFFF16 as the high order address and the content of the address FFFE16 as the low order address, when the RESET pin is held at “L” level for no less than 2 µs while the power voltage is in the recommended operating condition and then returned to “H” level. The internal initializations following reset are shown in Figure 16. Example of reset circuit is Figure 14. Immediately after reset, timer 3 and timer 4 are connected, and counts the f(X IN) divided by 16. At this time, FF16 is set to timer 3, and 0716 is set to timer 4. The reset is cleared when timer 4 overflows. Address (1) Port P0 direction register (2) Port P1 direction register (3) Port P2 direction register (4) Port P4 direction register (5) P0 pull-up control register (C116) … (C316) … (C516) … (C916) … (D016) … 0 0016 0016 0016 0000 0016 00000 000000 01000 0016 0016 0016 00 000 0000 000 0000 000 Contents of address FFFF16 Contents of address FFFE16 (6) P1–P5 pull-up control register (Note 1)(D116) … (7) Edge selection register (8) A-D control register (9) Serial I/O mode register (EG) (D416) … (D916) … 0 (SM) (DC16) … (10) Timer 12 mode register (T12M) (F816) … (11) Timer 34 mode register (T34M) (F916) … (12) Timer mode register 2 (13) CPU mode register (14) Interrupt request register 1 (TM2) (FA16) … 0 0 (CM) (FB16) … 0 0 0 0 (FC16) … 0 0 (FD16) … (FE16) … 0 0 (FF16) … (PCH) … (PC L) … 7470/7471 group (15) Interrupt request register 2 (16) Interrupt control register 1 RESET VCC (17) Interrupt control register 2 (18) Program counter (19) Processor status register (PS) … 1 Fig. 14 Example of reset circuit Notes 1 : This address is allocated P1–P4 pull-up control register for 7470 group. Bit 6 is not used. 2 : Since the contents of both registers other than those listed above (including timers and the serial I/O register) are undefined at reset, it is necessary to set initial values. Fig. 16 Internal state of microcomputer at reset XIN φ RESET Internal RESET SYNC Address Data ? ? 00, S 00, S-1 00, S-2 FFFE FFFF AD H,AD L ? ? PC H PC L PS AD L AD H Reset address from the vector table 32768 counts of f(X IN ) Notes 1 : Frequency relation of X IN and φ is f(XIN )=2·φ. 2 : The mark “?” means that the address is changeable depending upon the previous state. Fig. 15 Timing diagram at reset 23 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O PORTS (1) Port P0 Port P0 is an 8-bit I/O port with CMOS outputs. As shown in Figure 2, P0 can be accessed as memory through zero page address 00C016. Port P0’s direction register allows each bit to be programmed individually as input or output. The direction register (zero page address 00C116 ) can be programmed as input with “0”, or as output with “1”. When in the output mode, the data to be output is latched to the port latch and output. When data is read from the output port, the output pin level is not read, only the latched data of the port latch is read. Therefore, a previously output value can be read correctly even though the output voltage level has been shifted up or down. Port pins set as input are in the high impedance state so the signal level can be read. When data is written into the input port, the data is latched only to the output latch and the pin still remains in the high impedance state. Following the execution of STP or WIT instruction, key matrix with port P0 can be used to generate the interrupt to bring the microcomputer back in its normal state. When this port is selected for input, pull-up transistor can be connected in units of 1-bit. (2) Port P1 Port P1 has the same function as port P0. P1 2 –P1 7 s erve dual functions, and the desired function can be selected by the program. When this port is selected for input, pull-up transistor can be connected in units of 4-bit. (3) Port P2 Port P2 has the same function as port P0. In the 7470 group, this port is P2 0–P2 3, a 4-bit I/O port. This port can also be used as the analog voltage input pins. When this port is selected for input, pull-up transistor can be connected in units of 4-bit. (4) Port P3 Port P3 is a 4-bit input port. (5) Port P4 Port P4 is a 4-bit I/O port and has basically the same functions as port P0. In the 7470 group, this port is P40 and P41 , a 2-bit I/O port. When this port is selected for input, pull-up transistor can be connected in units of 4-bit . (6) Port P5 Port P5 is a 4-bit input port and pull-up transistor can be connected in units of 4-bit. P5 0 and P5 1 are shared with clock generating circuit input/output pins. The 7470 group does not have this port. (7) INT0 pin (P3 0/INT0 pin) This is an interrupt input pin, and is shared with port P30 . When “H” to “L” or “L” to “H” transition input is applied to this pin, the INT0 interrupt request bit (bit 0 of address 00FD 16) is set to “1”. (8) INT1 pin (P3 1/INT1 pin) This is an interrupt input pin, and is shared with port P31 . When “H” to “L” or “L” to “H” transition input is applied to this pin, the INT1 interrupt request bit (bit 1 of address 00FD 16) is set to “1”. (9) Counter input CNTR0 pin (P32 /CNTR0 pin) This is a timer input pin, and is shared with port P32 . When this pin is selected to CNTR0 or CNTR 1 interrupt input pin and “H” to “L” or “L” to “H” transition input is applied to this pin, the CNTR0 or CNTR 1 interrupt request bit (bit 2 of address 00FD16) is set to “1”. (10) Counter input CNTR1 pin (P33 /CNTR1 pin) This is a timer input pin, and is shared with port P33 . When this pin is selected to CNTR0 or CNTR 1 interrupt input pin and “H” to “L” or “L” to “H” transition input is applied to this pin, the CNTR0 or CNTR 1 interrupt request bit (bit 2 of address 00FD16) is set to “1”. 24 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port P0 Pull-up control register Tr1 Direction register Data bus Port latch Port P0 Interrupt control circuit Ports P10–P13 Data bus Pull-up control register T34M 7 Direction register Tr2 Data bus Port latch Port P13 T1 T12M3 Direction register Tr3 Data bus Port latch Port P1 2 T0 Tr4 Direction register Data bus Port latch Port P1 1 Tr5 Direction register Data bus Port latch Port P1 0 Tr1–T r5 are pull-up transistors Fig. 17 Block diagram of ports P0, P1 0–P13 25 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Ports P1 4 –P17 SM7 SM4 Direction register Tr6 Data bus Port latch Port P17 SRDY SM2 SM3 Tr7 Direction register Data bus Port latch Port P16 CLK output SM3 CLK input Tr8 Direction register SM7 Data bus Port latch Port P15 SOUT Tr9 Direction register Data bus Port latch Port P14 SIN Data bus Pull-up control register Tr6–Tr9 are pull-up transistors Fig. 18 Block diagram of ports P1 4–P17 26 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port P2 * : Control in units of 4-bit Pull-up control register * Tr10 Data bus Direction register Data bus Port latch Port P2 A-D conversion circuit Multiplexer Port P3 Data bus Port P3 INT0 , INT1 CNTR0 , CNTR1 Port P4 * : Control in units of 4-bit (Control in units of 2-bit for 7470 group) Data bus Pull-up control register * Tr11 Direction register Data bus Port latch Port P4 Tr10–T r11 are pull-up transistors Fig. 19 Block diagram of ports P2–P4 27 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port P5 Data bus Pull-up control register Tr12 Data bus Port P53 Tr13 Data bus Port P5 2 CM4 Tr14 Data bus Port P51 CM4 CM4 XCIN CM4 Tr15 Data bus Port P50 Tr12–Tr15 are pull-up transistors Note : 7470 group does not have this port. Fig. 20 Block diagram of port P5 28 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CLOCK GENERATING CIRCUIT The 7470 group has one internal clock generating circuit and 7471 group has two internal clock generating circuits. Figure 25 shows a block diagram of the clock generating circuit. Normally, the frequency applied to the clock input pin XIN divided by two is used as the internal clock φ . Bit 7 of CPU mode register can be used to switch the internal clock φ to 1/2 the frequency applied to the clock input pin XCIN in the 7471 group. Figure 21, 22 show a circuit example using a ceramic resonator (or a quartz-crystal oscillator). Use the manufacturer’s recommended values for constants such as capacitance which will differ depending on each oscillator. When using an external clock signal, input from the XIN(XCIN ) pin and leave the XOUT (XCOUT) pin open. A circuit example is shown in Figure 23, 24. The 7470/7471 group has two low power dissipation modes; stop and wait. The microcomputer enters a stop mode when the STP instruction is executed. The oscillator (both XIN clock and XCIN clock) stops with the internal clock φ held at “H” level. In this case timer 3 and timer 4 are forcibly connected and FF 16 is automatically set in timer 3 and 0716 in timer 4. Although oscillation is restarted when an external interrupt is accepted, the internal clock φ remains in the “H” state until timer 4 overflows. In other words, the internal clock φ is not supplied until timer 4 overflows. This is because when a ceramic or similar other oscillator is used, a finite time is required until stable oscillation is obtained after restart. The microcomputer enters an wait mode when the WIT instruction is executed. The internal clock φ stops at “H” level, but the oscillator does not stop. φ is re-supplied (wait mode release) when the microcomputer receives an interrupt. Instructions can be executed immediately because the oscillator is not stopped. The interrupt enable bit of the interrupt used to reset the wait mode or the stop mode must be set to “1” before executing the WIT or the STP instruction. Low power dissipation operation is also achieved when the XIN clock is stopped and the internal clock φ is generated from the XCIN clock (30 µA typ. at f(X CIN) = 32 kHz). This operation is only 7471 group. X IN clock oscillation is stopped when the bit 6 of CPU mode register is set and restarted when it is cleared. However, the wait time until the oscillation stabilizes must be generated with a program when restarting. Figure 27 shows the transition of states for the system clock. M37470M2-XXXSP XIN XOUT Rd CIN COUT Fig. 21 Example of ceramic resonator circuit (7470 group) M37471M2-XXXSP/FP XIN XOUT Rd CIN COUT CCIN XCIN XCOUT Rd CCOUT Fig. 22 Example of ceramic resonator circuit (7471 group) M37470M2-XXXSP XIN XOUT Open External oscillating circuit VCC VSS Fig. 23 External clock input circuit (7470 group) M37471M2-XXXSP/FP XIN XOUT Open XCIN XCOUT Open External oscillating External oscillating circuit or circuit external pulse VCC VSS VCC VSS Fig. 24 External clock input circuit (7471 group) 29 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XCIN XCOUT XIN XOUT 1/2 (Note 1) 1/2 CM 7 1/8 T34M 1 T34M 2 T34M0 Timer 3 Timer 4 CM6 CM7 Internal clock φ QS R STP instruction WIT instruction Reset SQ R QS QS R R STP instruction Reset Interrupt disable flag I Interrupt request Select gate : At reset, shaded side is connected Notes 1 : Refer to Timer 3 of [Figure 6 Block diagram of timer 1 through 4] 2 : 7470 group does not have X CIN input and XCOUT output. Fig. 25 Block diagram of clock generating circuit b7 b0 CPU mode register (Address 00FB 16) These bits must always be set to “0”. Stack page selection bit (Note 1) 0 : In page 0 area 1 : In page 1 area Nothing is allocated (The value is undefined at reading) S50, P51 /XCIN , XCOUT selection bit (Note 2) 0 : P50, P51 1 : XCIN , XCOUT XCOUT drive capacity selection bit (Note 2) 0 : Low 1 : High Clock (XIN -XOUT ) stop bit (Note 2) 0 : Oscillates 1 : Stops Internal system clock selection bit (Note 2) 0 : XIN -XOUT selected (normal mode) 1 : XCIN -XCOUT selected (low-speed mode) Notes 1 : In the M37470M2, M37470M4/E4, M37471M2, M37471M4/E4, set this bit to “0”. 2 : In the 7470 group, set this bit to “0”. Fig. 26 Structure of CPU mode register 30 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Reset CM4 = 0 CM5 = 0 CM6 = 0 CM7 = 0 f(XIN ) oscillation f(XCIN ) stop φ stop Timer operation WIT instruction f(X IN) oscillation f(X CIN) stop P50 , P51 input STP instruction f(XIN ) stop f(XCIN ) stop φ stop Interrupt φ = f(XIN )/2 Interrupt (Note 1) CM5 = 1 CM4 = 1 (Note 2) CM 4 = 0 f(XIN ) oscillation f(XCIN ) oscillation φ stop Timer operation WIT instruction f(XIN ) oscillation f(XCIN ) oscillation φ = f(XIN )/2 STP instruction f(XIN ) stop f(XCIN ) stop φ stop Interrupt Interrupt (Note 1) (CM5 = 0) CM7 = 1 CM 7 = 0 f(XIN ) oscillation f(XCIN ) oscillation φ stop Timer operation WIT instruction f(XIN ) oscillation f(XCIN ) oscillation φ = f(XCIN )/2 CM5 = 1 STP instruction f(XIN ) stop f(XCIN ) stop φ stop Interrupt Interrupt (Note 1) CM6 = 1 CM 6 = 0 (Note 2) f(XIN ) stop f(XCIN ) oscillation φ stop Timer operation WIT instruction f(XIN ) stop f(XCIN ) oscillation φ = f(XCIN )/2 CM5 = 1 STP instruction f(XIN ) stop f(XCIN ) stop φ stop Interrupt Interrupt (Note 1) Notes 1 : Latency time is automatically generated upon release from the STP instruction due to the connections of timer 3 and 4. 2 : When the system clock is switched over by restarting clock oscillation, a certain wait time required for oscillation to stabilize must be inserted by the program. Fig. 27 Transition of states for the system clock 31 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Operation on the clock function only Clock for clock function XC oscillation start (CM4 = 1, CM5 = 1) ↓ Latency time for oscillation to stabilize (by program) ← Operating at f(X IN) ↓ XC clock power down (CM5 : 1 →0) ↓ Internal clock φ source switching X →XC (CM7 : 0 →1) ↓ Clock X halt (XC in operation) (CM6 = 1) ↓ Internal clock halt (WIT instruction) ↓ Timer 4 (clock count) overflow ↓ Internal clock operation start (WIT instruction released) … Clock processing routine Internal clock halt (WIT instruction) Interrupts from INT0, INT 1, CNTR0/CNTR 1, timer 1, timer 2, timer 3, timer 4, serial I/O, key on wake up ↓ Internal clock operation start (WIT instruction released) ↓ Program start from interrupt vector ↓ Clock X oscillation start (CM 6 = 0) ↓ Latency time for oscillation to stabilize (by program) ← Operating at f(XCIN) ↓ Internal clock φ source switching (XC→X) (CM 7 : 1→0) … Normal program → Operating at f(XIN) … ← Operating at f(XCIN) 32 Return from clock function …                                                           Normal operation Power on reset ↓ Clock X oscillation ↓ Internal system clock start (X→1/2→ φ) ↓ Program start from RESET vector … Normal program ← Operating at f(X IN) MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Return from RAM backup function Normal program … …                                         STP instruction preparation (pushing registers) ↓ Timer 3, timer 4 interrupt disable ↓ X/16 or XC /16 selected for timer 3 count source; timer 3 overflow selected for timer 4 count source ↓ Timer 3, timer 4 start counting ↓ Values set to timer 3, timer 4 that do not cause timer 4 to overflow until STP instruction is executed ↓ Interrupt for return from STP enabled ↓ Timer 4 interrupt request bit cleared ↓ Clock X and clock for clock function X C halt (STP instruction) RAM backup status Interrupts from INT0 , INT1, CNTR0 /CNTR1 , timer 1, timer 2, serial I/O, key on wake up ↓ Clock X and clock for clock function X C oscillation start ↓ Timer 4 overflow (X/16 or XC/16→timer 3→timer 4) ↓ Internal system clock start ↓ Program start from interrupt vector … RAM backup function 33 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER BUILT-IN PROM TYPE MICROCOMPUTERS PIN DESCRIPTION Pin VCC,VSS AVSS (Note 1) RESET Mode Single-chip /EPROM Single-chip /EPROM Single-chip EPROM XIN XOUT VREF Single-chip EPROM P00 –P07 Single-chip Single-chip /EPROM Name Power source Analog power source Reset input Reset input Clock input Clock output Reference voltage input Select mode I/O port P0 Input Output Input Input I/O Input Input/ Output Functions Power source voltage inputs 2.7 to 5.5 V to VCC and 0 V to VSS . Ground level input pin for A-D converter. Same voltage as VSS is applied. To enter the reset state, the reset input pin must be kept at a “L” for 2 µs or more (under normal VCC conditions). Connect to VSS. These are I/O pins of internal clock generating circuit for main clock. To control generating frequency, an external ceramic or a quartz-crystal oscillator is connected between the XIN and XOUT pins. If an external clock is used, the clock source should be connected the X IN pin and the X OUT pin should be left open. Feedback resistor is connected between XIN and X OUT. Reference voltage input pin for the A-D converter. VREF works as CE input. Port P0 is an 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 1-bit and a key on wake up function is provided. Port P0 works as an 8-bit data bus (D 0–D7). Port P1 is an 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 4-bit. P12 , P13 are in common with timer output pins T0, T1 . P1 4, P1 5, P1 6, P1 7 are in common with serial I/O pins S IN , SOUT, CLK, SRDY, respectively. The output structure of SOUT and SRDY can be changed to N-channel open drain output. P11 –P17 works as the 7-bit address input (A4–A10). P1 0 must be opened. Port P2 is an 8-bit input port. This port is in common with analog input pins IN0–IN7. P20 –P23 works as the lower 4-bit address input (A0–A3). P24–P27 must be opened. Port P3 is a 4-bit input port. P3 0, P3 1 are in common with external interrupt input pins INT 0, INT 1 and P32, P33 are in common with timer input pins CNTR0, CNTR1. P30 , P31 works as the 2-bit address input (A11, A12 ). P32 works as OE input. Connect to P33 to VPP when programming or verifying. EPROM P10 –P17 Single-chip Data input/output D0–D7 I/O port P1 I/O I/O EPROM P20 –P27 (Note 2) Single-chip EPROM P30 –P33 Single-chip EPROM Address input A4–A10 I/O port P2 Address input A0–A3 Input port P3 Address input A11, A12 Select mode VPP input I/O port P4 Address input A13, A14 Input port P5 Input I/O Input Input Input P40 –P43 (Note 3) Single-chip EPROM I/O Input Input Port P4 is a 4-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 4-bit. P40 , P41 works as the higher 2-bit address input (A13 , A14 ). P42 , P43 must be opened. Port P5 is a 4-bit input port and pull-up transistor can be connected in units of 4bit. P50 , P51 are in common with input/output pins of clock for clock function X CIN, XCOUT. When P5 0, P51 are used as XCIN , XCOUT, connect a ceramic or a quartzcrystal oscillator between X CIN and XCOUT. If an external clock input is used, connect the clock input to the X CIN pin and open the XCOUT pin. Feedback resistor is connected between XCIN and XCOUT pins. Open. P50 –P53 (Note 4) Single-chip EPROM Notes 1 2 3 4 : : : : AVSS for M37471M2/M4/M8/E4/E8-XXXFP. Only P20–P23 (IN0–IN 3) 4-bit for the 7470 group. Only P40 and P4 1 2-bit for the 7470 group. This port is not included in the 7470 group. 34 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER EPROM MODE The M37470E4/E8, M37471E4/E8 feature an EPROM mode in addition to its normal modes. When the RESET signal level is low (“L”), the chip automatically enters the EPROM mode. Table 2 lists the correspondence between pins and Figure 30 to 32 give the pin connection in the EPROM mode. When in the EPROM mode, ports P0, P1 1–P17, P2 0–P23, P3, P4 0, P4 1, VREF are used for the PROM (equivalent to the M5L27256). When in this mode, the builtin PROM can be written to or read from using these pins in the same way as with the M5L27256. The oscillator should be connected to the X IN a nd X OUT p ins, or external clock should be connected to the XIN pin. Table 2. Pin function in EPROM mode M37470E4/E8, M37471E4/E8 VCC VPP VSS Address input Data I/O CE OE Ports VCC P33 VSS P11–P17, P20–P23 , P30, P31, P40 , P41 Port P0 VREF P32 M5L27256 VCC VPP VSS A0–A14 D0–D7 CE OE P53 A10 A9 A8 A7 A6 A5 A4 P17/SRDY P16 /CLK P15/SOUT P14/SIN P13/ T1 P12/ T0 P11 P10 P27/IN 7 P26/IN 6 P25/IN 5 P24/IN 4 A3 A2 A1 A0 CE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33 /CNTR1 P32 /CNTR0 P31 /INT1 P30 /INT0 RESET P51 /XCOUT P50 /XCIN VCC VCC VSS A14 A13 VPP OE D7 D6 D5 D4 D3 D2 D1 D0 M37471E4-XXXSP M37471E8-XXXSP M37471E8SS P23/IN 3 P22/IN 2 P21/IN 1 P20/IN 0 VREF XIN XOUT A12 A11 VSS VSS : Same functions as M5L27256 Fig. 28 Pin connection in EPROM mode 35 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VPP 33 A14 A13 39 41 43 37 35 31 40 42 44 38 36 34 32 30 29 NC P04 P03 P02 P01 P00 P43 P42 P41 P40 NC P33/CNTR1 P32/CNTR0 P31/INT1 P30 /INT0 NC A12 A11 D4 D3 D2 D1 D0 OE D5 D6 D7 VSS A10 A9 A8 NC P05 P06 P07 P52 NC VSS P53 P17/SRDY P16/SCLK P15 /SOUT NC 45 46 47 48 49 50 51 52 53 54 55 56 10 12 14 11 13 15 16 2 3 4 5 6 1 7 8 9 28 27 26 25 24 M37471E4-XXXFP M37471E8-XXXFP 23 22 21 20 19 18 17 RESET NC P51/XCOUT P50/XCIN NC VCC VSS AVSS NC XOUT XIN NC VCC VSS A3 A2 A1 A0 32 31 30 29 28 Fig. 29 Pin connection in EPROM mode A7 A6 A5 A4 : Same functions as M5L27256 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CE P17/SRDY P16 /CLK P15 /SOUT P14/SIN P13/ T1 P12/ T0 P11 P10 P23/IN 3 P22/IN 2 P21/IN 1 P20/IN 0 VREF XIN XOUT 1 2 3 4 5 P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0 RESET VCC CE NC P14/SIN P13/ T1 P12 / T0 P11 P10 P27/IN7 P26 /IN6 P25 /IN5 P24/IN 4 P23/IN3 P22/IN2 P21/IN1 P20 /IN0 VREF NC D7 D6 D5 D4 D3 D2 D1 D0 A14 A13 VPP OE M37470E4-XXXSP M37470E8-XXXSP 6 7 8 9 10 11 12 13 14 15 16 27 26 25 24 23 22 21 20 19 18 17 A12 A11 VSS VSS VCC VSS : Same functions as M5L27256 Fig. 30 Pin connection in EPROM mode 36 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PROM READING AND WRITING Reading To read the PROM, set the CE and OE pins to “L” level. Input the address of the data (A0–A14 ) to be read and the data will be output to the I/O pins (D0–D7). The data I/O pins will be floating when either the CE or OE pin is in the “H” state. NOTES ON HANDLING (1) Sunlight and fluorescent light contain wave lengths capable of erasing data. For ceramic package types, cover the transparent window with a seal (provided) when this chip is in use. However, this seal must not contact the lead pins. (2) Before erasing, the glass should be cleaned and stains such as finger prints should be removed thoroughly. If these stains are not removed, complete erasure of the data could be prevented. (3) Since a high voltage (12.5 V) is used to write data, care should be taken when turning on the PROM programmer’s power. (4) For the programmable microcomputer (shipped in One Time PROM version), Mitsubishi does not perform PROM write test and screening in the assembly process and following processes. To improve reliability after write, performing write and test according to the flow below before use is recommended. Writing To write to the PROM, set the OE pin to “H” level. The CPU will enter the program mode when VPP is applied to the VPP p in. The address to be written to is selected with pins A 0 –A14, and the data to be written is input to pins D0–D7. Set the CE pin to “L” level to begin writing. Notes on Writing • M37470E4, M37471E4 When using a PROM programmer, the address range should be between 6000 16 and 7FFF 16. Addresses 000016 to 5FFF 16 cannot be written to or read from correctly. • M37470E8, M37471E8 When using a PROM programmer, the address range should be between 4000 16 and 7FFF16 . When data is written between addresses 0000 16 a nd 7FFF 16, fill addresses 000016 t o 3FFF 16 with FF 16. Writing with PROM programmer Screening (Caution) (Leave at 150°C for 40 hours) Erasing Data can only erased on the M37471E8SS ceramic package, which includes a window. To erase data on this chip, use an ultraviolet light source with a 2537 Angstrom wave length. The minimum radiation power necessary for erasing is 15W·s/cm 2. Verify test with PROM programmer Function check in target device Caution : Since the screening temperature is higher than storage temperature, never expose to 150° C exceeding 100 hours. Table 3. I/O signal in each mode Pin Mode Read-out Output disable Programming Programming verify Program disable CE VIL VIL VIL VIH VIH OE VIL VIH VIH VIL VIH VPP VCC VCC VPP VPP VPP VCC VCC VCC VCC VCC VCC Data I/O Output Floating Input Output Floating Note : VIL and V IH indicate a “L” and “H” input voltage, respectively. 37 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PROGRAMMING NOTES (1) The frequency ratio of the timer is 1/(n+1). (2) The contents of the interrupt request bits are not modified immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before executing a BBC or BBS instruction. (3) To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. Only the ADC and SBC instruction yield proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. (4) An NOP instruction must be used after the execution of a PLP instruction. (5) Do not execute the STP instruction during A-D conversion. (6) In the M37470, set bit 0, bit 1, and bit 3–bit 7 to “0” of the CPU mode register. (7) Multiply/Divide instructions The index X mode (T) and the decimal mode (D) flag do not affect the MUL and DIV instruction. The execution of these instructions does not modify the contents of the processor status register. DATA REQUIRED FOR MASK ORDERING Please send the following data for mask orders. (1) mask ROM confirmation form (2) mark specification form (3) ROM data ......................................................... EPROM 3 sets 38 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37470M2/M4/M8-XXXSP, M37470E4/E8-XXXSP ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VI VO Pd Topr Tstg Parameter Power source voltage Input voltage XIN Input voltage P00–P07 , P10–P17, P20 –P23, P30–P33, P4 0, P41 , VREF, RESET Output voltage P00–P07, P10–P17 , P20–P23, P40, P41, XOUT Ta = 25° C All voltages are based on V SS. Output transistors are cut off. Conditions Ratings –0.3 to 7 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 1000 –20 to 85 –40 to 150 Unit V V V V mW °C °C Power dissipation Operating temperature Storage temperature RECOMMENDED OPERATING CONDITIONS Symbol Parameter (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C unless otherwise noted) Limits Min. f(XIN) = 2.2VCC–2.0 MHz f(XIN) = 8 MHz 2.7 4.5 5 0 0.8VCC 0.7VCC 0 0 0 0 VCC VCC 0.2V CC 0.25V CC 0.12V CC 0.16V CC –30 –30 60 60 –10 20 –5 10 1 2 1 2 2.2VCC – 2.0 8 MHz MHz Typ. Max. 4.5 5.5 Unit VCC VSS VIH VIH VIL VIL VIL VIL I OH(sum) I OH(sum) I OL(sum) I OL(sum) I OH(peak) I OL(peak) I OH(avg) I OL(avg) f( CNTR) Power source voltage Power source voltage “H” input voltage “H” input voltage V V V V V V V V mA mA mA mA mA mA mA mA MHz P00 –P07 , P10–P17, P30–P33 , RESET, XIN P20 –P23 , P40, P41 “L” input voltage P0 0–P07, P10–P17, P30–P33 “L” input voltage P20 –P23 , P40, P41 “L” input voltage RESET “L” input voltage XIN “H” sum output current P00–P07, P40 , P41 “H” sum output current P10–P17, P20–P23 “L” sum output current P0 0–P07, P40, P41 “L” sum output current P1 0–P17, P20–P23 “H” peak output current P0 0–P07, P10–P17 , P20–P23, P40 , P41 “L” peak output current P0 0–P07, P10–P17 , P20 –P23, P40, P41 “H” average output current P0 0–P07, P10–P17 , P20–P23, P40, P4 1 (Note 2) “L” average output current Timer input frequency CNTR1 (P33) (Note 1) P00–P07 , P10 –P17, P20–P23, P40, P41 (Note 2) f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz VCC = 2.7 to 4.5 V Clock input oscillation frequency (Note 1) VCC = 4.5 to 5.5 V CNTR0 (P3 2), f( CLK) Serial I/O clock input frequency SCLK (P16) (Note 1) f(XIN ) Notes 1 : Oscillation frequency is at 50% duty cycle. 2 : The average output current IOH (avg) and IOL (avg) are the average value during a 100 ms. 39 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37470M2/M4/M8-XXXSP, M37470E4/E8-XXXSP ELECTRICAL CHARACTERISTICS (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol Parameter “H” output voltage P00 –P07 , P10–P17 , P20–P23, P40 , P41 “L” output voltage P00–P07, P10 –P17, P20–P23, P4 0, P41 Hysteresis P00 – P07, P30 – P33 Hysteresis RESET Test Conditions VCC = 5 V, I OH = –5 mA VCC = 3 V, I OH = –1.5 mA VCC = 5 V, I OL = 10 mA VCC = 3 V, I OL = 3 mA VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V Hysteresis P16 /CLK VCC = 5 V use as CLK input VI = 0 V, not use pull-up transistor VI = 0 V, use pull-up transistor VI = 0 V VI = 0 V, not use as analog input, not use pull-up transistor I IL “L” input current P2 0–P23 VI = 0 V, not use as analog input, use pull-up transistor I IL “L” input current RESET, X IN “H” input current P00–P07, P10–P17 , P30–P32, P40 , P41 “H” input current P33 VI = 0 V (X IN is at stop mode) VI = VCC, not use pull-up transistor VI = VCC VI = VCC, not use as analog input, not use pull-up transistor VI = VCC, (X IN is at stop mode) At normal mode, A-D conversion is not executed. At normal mode, A-D conversion is executed. f(XIN)=8 MHz f(XIN)=4 MHz f(XIN)=8 MHz f(XIN)=4 MHz f(XIN)=8 MHz At wait mode. f(XIN)=4 MHz At stop mode, f(XIN)=0, VCC=5 V VRAM RAM retention voltage Stop all oscillation VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V I IH VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V Ta = 25° C Ta = 85° C 2 7 3.5 1.8 7.5 4 2 2 1 0.5 0.1 1 –0.25 –0.08 –0.5 –0.18 –0.25 –0.08 –0.5 –0.18 0.5 0.3 0.5 0.3 0.5 0.3 –5 –3 –1.0 –0.35 –5 –3 –5 –3 –1.0 –0.35 –5 –3 5 3 5 3 5 3 5 3 14 7 3.6 15 8 4 4 2 1 1 10 5.5 µA V mA mA mA µA mA µA µA mA µA µA µA µA µA V V Limits Min. 3 2 2 1 Typ. Max. Unit VOH V VOL V VT + – V T– V VT + – VT– VT + – VT– I IL “L” input current P00 –P07 , P10–P17 , P30–P32, P40 –P41 I IL “L” input current P33 I IH I IH “H” input current P20–P23 I IH “H” input current RESET, XIN I CC Power source current 40 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D CONVERTER CHARACTERISTICS (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, f(X IN)=4 MHz, unless otherwise noted) Symbol – – – VOT Resolution Non-linearity error Differential non-linearity error Zero transition error VCC = VREF = 5.12 V, IOL (sum) = 0 mA VCC = VREF = 3.072 V, IOL (sum) = 0 mA VFST Full-scale transition error VCC = VREF = 5.12 V VCC = VREF = 3.072 V t CONV VREF RLADDER VIA Conversion time Reference input voltage Ladder resistance value Analog input voltage VCC = 2.7 to 5.5 V, f(XIN) = 4 MHz VCC = 4.5 to 5.5 V, f(XIN) = 8 MHz 0.5VCC 2 0 5 Parameter Test Conditions Limits Min. Typ. Max. 8 ±2 ±0.9 2 3 4 7 25 12.5 VCC 10 VREF V kΩ V µs LSB LSB Unit bits LSB LSB 41 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37471M2/M4/M8-XXXSP/FP, M37471E4/E8-XXXSP/FP, M37471E8SS ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VI VO Pd Topr Tstg Parameter Power source voltage Input voltage XIN Input voltage P0 0–P07, P10 –P17, P20–P27, All voltages are based on V SS. P30–P3 3, P40–P43, P50–P53, VREF, RESET Output transistors are cut off. Output voltage P00–P07 , P10–P17, P20–P27 , P40–P43, XOUT Ta = 25°C Conditions Ratings –0.3 to 7 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 1000 (Note 1) –20 to 85 –40 to 150 Unit V V V V mW °C °C Power dissipation Operating temperature Storage temperature Note 1 : 500 mW for M37471M2/M4/M8-XXXFP. RECOMMENDED OPERATING CONDITIONS Symbol Parameter (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C unless otherwise noted) Limits Min. f(XIN) = 2.2V CC – 2.0 MHz f(XIN) = 8 MHz 2.7 4.5 5 0 0 0.8VCC 0.7VCC 0 0 0 0 VCC VCC 0.2V CC 0.25V CC 0.12V CC 0.16V CC – 30 – 30 60 60 – 10 20 –5 10 1 2 1 2 2.2V CC – 2.0 8 32 50 kHz MHz MHz Typ. Max. 4.5 5.5 Unit VCC VSS AVSS VIH VIH VIL VIL VIL VIL I OH(sum) I OH(sum) I OL(sum) I OL(sum) I OH(peak) I OL(peak) I OH(avg) I OL(avg) f( CNTR) Power source voltage Power source voltage Analog power source voltage “H” input voltage “H” input voltage V V V V V V V V V mA mA mA mA mA mA mA mA MHz P00–P07 , P10–P17, P30–P33, RESET, XIN P20–P27 , P40–P43, P50–P53 (Note 1) “L” input voltage P00 –P07 , P10 –P17 , P30 –P33 “L” input voltage P20–P27, P40–P43, P50–P53 (Note 1) “L” input voltage RESET “L” input voltage XIN “H” sum output current P00–P07, P40–P43 “H” sum output current P10–P17, P20–P27 “L” sum output current P0 0–P07, P40–P43 “L” sum output current P1 0–P17, P20–P27 “H” peak output current P00 –P07, P10–P17, P2 0–P27, P40–P43 “L” peak output current P0 0–P07, P10–P17, P20–P27 , P40 –P43 “H” average output current P0 0–P07, P10–P17, P20 –P27, P40–P43 (Note 2) “L” average output current P00–P07, P10–P17, P20–P27 , P40–P43 (Note 2) Timer input frequency CNTR 0 (P32), CNTR1 (P33) (Note 3) Serial I/O clock input frequency SCLK (P16) (Note 3) Main clock input oscillation frequency (Note 3) f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz VCC = 2.7 to 4.5 V VCC = 4.5 to 5.5 V f( CLK) f(XIN ) f(XCIN ) Notes 1 2 3 4 : : : : Sub-clock input oscillation frequency for clock function (Note 3, 4) It is except to use P50 as XCIN. The average output current IOH (avg) and IOL (avg) are the average value during a 100 ms. Oscillation frequency is at 50% duty cycle. When used in the low-speed mode, the clock oscillation frequency for clock function should be f(XCIN ) < f(XIN) / 3. 42 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37471M2/M4/M8-XXXSP/FP, M37471E4/E8-XXXSP/FP, M37471E8SS ELECTRICAL CHARACTERISTICS (V CC = 2.7 to 5.5 V, V SS = AVSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol VOH VOL VT + – V T– VT + – VT– VT + – VT– Parameter “H” output voltage “L” output voltage Hysteresis P00–P07, P00–P07, Test Conditions VCC = 5 V, IOH = –5 mA VCC = 3 V, IOH = –1.5 mA VCC = 5 V, IOL = 10 mA VCC = 3 V, IOL = 3 mA VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V Hysteresis P16 /CLK used as CLK input VI = 0 V, not use pull-up transistor VI = 0 V, use pull-up transistor VI = 0 V V I = 0 V, not use as analog input, not use pull-up transistor I IL “L” input current P20–P27 VI = 0 V, not use as analog input, use pull-up transistor I IL I IH I IH I IH I IH “L” input current RESET, XIN VI = 0 V (XIN is at stop mode) VI = VCC, not use pull-up transistor VI = VCC VI = VCC, not use as analog input, not use pull-up transistor VI = VCC, (XIN is at stop mode) At normal mode, A-D conversion is not executed. At normal mode, A-D conversion is executed. f(XIN)=8 MHz VCC = 5 V f(XIN)=4 MHz VCC = 3 V f(XIN)=8 MHz VCC = 5 V f(XIN)=4 MHz VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V f(XIN)=4 MHz VCC = 3 V At wait mode, XIN = 0 Hz, XCIN = 32 kHz, X COUT is low-power mode, T a=25°C Limits Min. 3 2 2 1 0.5 0.3 0.5 0.3 VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V 7 3.5 1.8 7.5 4 2 30 15 2 1 0.5 3 2 0.1 1 2 –0.25 –0.08 –0.5 –0.18 –0.25 –0.08 –0.5 –0.18 0.5 0.3 –5 –3 –1.0 –0.35 –5 –3 –5 –3 –1.0 –0.35 –5 –3 5 3 5 3 5 3 5 3 14 7 3.6 15 8 4 80 40 4 2 1 12 8 1 10 Typ. Max. Unit V V V V V µA mA µA µA mA µA µA µA µA µA P10–P17 , P20–P27, P4 0–P43 P10–P17 , P20–P27, P4 0–P43 P00–P07, P30–P33 Hysteresis RESET “L” input current I IL P00–P07, P1 0–P17, P30 –P32, P40–P43, P5 0–P53 I IL “L” input current P33 “H” input current P00–P07, P10–P17 , P30–P32 , P40–P43 , P50–P53 “H” input current P33 “H” input current P20–P27 “H” input current RESET, XIN mA mA I CC Power source current At low-speed mode, T a=25 ° C, f(XIN)=0, f(XCIN)=32 kHz, X COUT drive capacity is low, A-D conversion is not executed. µA f(XIN)=8 MHz At wait mode. mA VCC = 5 V VCC = 3 V Ta = 25°C Ta = 85°C Stop all oscillation VCC = 5 V VRAM RAM retention voltage Stop all oscillation µA V 43 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D CONVERTER CHARACTERISTICS (VCC = 2.7 to 5.5 V, VSS =AVSS = 0 V, Ta = –20 to 85° C, f(XIN) = 4 MHz, unless otherwise noted) Symbol – – – VOT Resolution Non-linearity error Differential non-linearity error Zero transition error VCC = VREF = 5.12 V, IOL (sum) = 0 mA VCC = VREF = 3.072 V, IOL (sum) = 0 mA VFST Full-scale transition error VCC = VREF = 5.12 V VCC = VREF = 3.072 V t CONV VREF RLADDER VIA Conversion time Reference input voltage Ladder resistance value Analog input voltage VCC = 2.7 to 5.5 V, f(XIN) = 4 MHz VCC = 4.5 to 5.5 V, f(XIN) = 8 MHz 0.5VCC 2 0 5 Parameter Test Conditions Limits Min. Typ. Max. 8 ±2 ±0.9 2 3 4 7 25 12.5 VCC 10 VREF V kΩ V µs LSB LSB Unit bits LSB LSB 44 MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials • • • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. • • • • © 1998 MITSUBISHI ELECTRIC CORP. New publication, effective Jan. 1998. Specifications subject to change without notice. REVISION DESCRIPTION LIST Rev. No. 1.0 First Edition 7470/7471 GROUP DATA SHEET Revision Description Rev. date 980110 (1/1)