M37510M6

MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 7510 group is the 8-bit microcomputer based on the 740 family core technology. This microcomputer is equipped with added functions such as a dot matrix type LCD controller/driver built in a contrast controller and UART. FEATURES q Basic machine-language instructions ...................................... 71 q The minimum instruction execution time ........................... 0.5 µ s (at 8.0 MHz oscillation frequency) q RAM for LCD display .................................................... 160 bytes q Programmable input/output ports ............................................ 41 q Interrupts ................................................. 15 sources, 15 vectors (includes key-on wake up) q Timers ........................................................... 8-bit ! 3, 16-bit ! 2 q Serial I/O ...................... 8-bit ! 2 (UART or clock-synchronized) q LCD controller/driver Bias ........................................ 1/4, 1/5 bias Duty ratio ...................... 1/8, 1/11, 1/16 duty Common output ...................................... 16 Segment output ...................................... 80 Built-in an LCD contrast controller (capable of 32-step contrast adjustment) q 2 Clock generating circuit (Connect to external ceramic resonator or quartz-crystal.) q Power source voltage In high-speed mode .................................................. 4.0 to 5.5 V In middle-speed mode ............................................... 2.5 to 5.5 V In low-speed mode .................................................... 2.5 to 5.5 V q Power dissipation In high-speed mode .......................................................... 32 mW (at 8.0 MHz oscillation frequency) In low-speed mode ............................................................ 60 µW (at 32 kHz oscillation frequency and 3.0 V power source voltage) In wait mode ........................................................................ 9 µW (at 32 kHz oscillation frequency and 3.0 V power source voltage) q Operating temperature range .................................. –20 to +85° C APPLICATION Cellular radio telephones, business telephones, facsimiles, and other portable equipment that need a large capacity of LCD display. MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (TOP VIEW) 129 124 112 119 107 131 126 114 121 109 128 116 123 111 118 106 104 102 130 125 113 120 108 132 127 115 122 110 117 105 103 101 100 99 94 96 98 95 93 91 97 NC NC SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 NC NC 92 90 89 NC NC SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 COM15 COM14 COM13 COM12 COM11 COM 10 COM9 COM8 VCC P30/R XD2 P31/TXD2 P32/SCLK2 P33 /SRDY2 P34 P35 P36 P37 P00 P01 P02 P03 P04 P05 P06 P07 P10 NC NC 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 26 14 19 31 24 36 12 17 29 22 34 10 27 39 41 43 15 20 32 25 37 13 18 30 23 35 11 16 28 21 33 38 40 42 44 3 5 1 4 6 8 2 7 9 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 M37510M6-XXXFP 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 NC NC NC NC NC NC P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN P50/XCOUT P51/XCIN RESET P40/INT0 P41/INT1 P42/CNTR0 P43/CNTR1 P44/RXD1 P45/TXD1 P46/SCLK1 P47/SRDY1 NC NC NC NC NC NC VSS NC NC NC NC SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 NC NC NC COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 VLCD VL3 VL2 NC NC Package type : 176P6D-A 176-pin plastic-molded QFP NC : No connect 2 M37510M6-XXXFP BLOCK DIAGRAM SubSubclock Clock Clock clock output input output input XIN XOUT XCIN/P51 XCOUT /P50 Reset input RESET (5V) VCC 108 (0V) VSS 67 47 (0V) VSS 65 66 63 64 62 Data bus Contrast controller Bias CPU A ROM RAM 512 bytes LCD RAM LCD 32 40 41 42 39 VLCD VL3 VL2 COM0 . . . Clock generating circuit X Y S PCL Timer PS (160 bytes) controller 24 K bytes resistor φ φ CLK COM7 109 PCH COM8 . . . 115 116 P5(2) COM14 COM15 28 27 26 25 24 23 22 21 Timer X (16) Timer Y (16) Timer 1 (8) Timer 2 (8) Timer 3 (8) S I/O1(8) CNTR1 CNTR0 S I/O2(8) 20 19 18 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 . . . 123 122 INT0 , INT1 P4(8) P3(8) P2(8) P1(8) P0(8) 121 120 119 118 117 Key-on wake up SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 91 92 93 94 95 96 97 98 99 54 55 56 57 58 59 60 61 100 101 102 103 104 105 106 107 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 7510 Group I/O port P4 I/O port P3 I/O port P2 I/O port P1 I/O port P0 MITSUBISHI MICROCOMPUTERS 3 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Pin VCC , VSS RESET XIN XOUT VLCD VL2 , VL3 COM0– COM15 SEG 0– SEG 79 P00–P07 P10–P17 P20–P27 P30 /RXD2 , P31 /TXD2, P32 / SCLK2, P33/SRDY2 P34–P37 P40/INT0 P41/INT1 P42/CNTR0, P43 /CNTR1 I/O port P4 P44 /RXD1 , P45 /TXD1, P46/ SCLK1, P47/SRDY1 A 7-bit I/O port with the same function as port P0. The port direction register allows each pin to be individually programmed as either input or output. Timer X, Timer Y function pins External interrupt input pins Input port P4 A 1-bit CMOS level input port. External interrupt input pins Name Power source Reset input Clock input Clock output LCD voltage source LCD bias control pin Function Function except a port function Apply voltage of 4.0 to 5.5 V to V CC, and 0 V to VSS (in high-speed mode). Reset input pin for active “L”. Input and output pins for the main clock generating circuit. Connect a ceramic resonator or quartz-crystal oscillator between the X IN and XOUT pins to set the oscillating frequency. If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. This pin is used as voltage supply input for LCD driver. Input VLCD ≤ V CC voltage. When the LCD is operated at 1/5 bias, leave these pins open. When the LCD is operated at 1/4 bias, connect these pins externally. LCD common output pins. Common output Segment output I/O port P0 I/O port P1 I/O port P2 LCD segment output pins. An 8-bit I/O port. The output structure of this port is CMOS 3-state, and the input levels are CMOS compatible. The port direction register allows each pin to be individually programmed as either input or output. Key input (Key-on wake-up) interrupt input pins. Serial I/O2 function pins I/O port P3 Serial I/O1 function pins P5 0/XCOUT, P51 /XCIN A 2-bit I/O port with the same function as port P0. I/O port P5 The port direction register allows each pin to be individually programmed as either input or output. I/O pins for the internal sub clock generating circuit. Connect an oscillator. 4 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PART NUMBERING Product M37510 M 6 XXX FP Package type FP: 176P6D-A package FS: 160D0 package ROM number Omitted in some types. ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes RAM size 512 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas; they cannot be used. Memory type M : Mask ROM version E : EPROM or One Time PROM version Currently supported products are listed below. As of May 1996 Product name M37510M6-XXXFP M37510E6-XXXFP M37510E6FP M37510E6FS (P) ROM size (bytes) RAM size (bytes) Package 176P6D-A 160D0 Remarks Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version 24K 512 5 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 7510 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 User’s Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction are not available for use. The STP, WIT, MUL, and DIV instruction can be used. CPU MODE REGISTER The CPU mode register is allocated at address 003B16 . The CPU mode register contains the stack page selection bit and the internal system clock selection bit. b7 b0 CPU mode register (CPUM : address 003B 16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Do not use 1 0 : Do not use 1 1 : Do not use Stack page selection bit 0 : RAM in the zero page is used as stack area 1 : RAM in page 1 is used as stack area XCOUT drivability selection bit 0 : Low drive 1 : High drive Port XC selection bit 0 : I/O port 1 : XCIN , XCOUT Main clock (X IN-X OUT ) stop bit 0 : Operating 1 : Stopped Main clock division ratio selection bit 0 : XIN /2 (high-speed mode) 1 : XIN /8 (middle-speed mode) Internal system clock selection bit 0 : XIN -XOUT selected (middle/high-speed mode) 1 : XCIN -XCOUT selected (low-speed mode) Fig. 1 Structure of CPU mode register 6 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MEMORY Special Function Register (SFR) Area The Special Function Register area contains registers which control functions such as I/O ports and timers, and is located in the zero page area. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page This dedicated zero page addressing mode enables access to this area with only 2 bytes. RAM RAM is used for data storage as well for stack area. Special Page This dedicated special page addressing mode enables access to this area with only 2 bytes. ROM The first 128 bytes and the last two bytes of ROM are reserved for device testing and the rest is user area for storing programs. 000016 SFR area 004016 LCD display RAM area 00DF16 RAM area Type name M37510M6-XXXFP Address XXXX 16 023F16 RAM 010016 V Zero page 034016 03DF16 XXXX16 LCD display RAM area V Not used YYYY16 ROM area Type name M37510M6-XXXFP Address YYYY 16 A00016 Address ZZZZ 16 A08016 ZZZZ16 Reserved ROM area (common ROM area, 128 bytes) ROM FF0016 FFDC16 Interrupt vector area Special page FFFE16 Reserved ROM area FFFF16 V LCD display RAM area can reside at either zero page (addresses 004016 to 00DF16) or third page (addresses 034016 to 03DF 16) by software. The third page is selected after reset. Fig. 2 Memory map diagram 7 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F 16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F 16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P0 pull-up control register (PULLP0) Port P1 pull-up control register (PULLP1) Port P2 pull-up control register (PULLP2) Port P3 pull-up control register (PULLP3) Port P4 pull-up control register (PULLP4) Port P5 pull-up control register (PULLP5) Transmit/receive buffer register 1 (TB1/RB1) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART1 control register (UART1CON) Baud rate generator 1 (BRG1) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Timer X (low) (TXL) Timer X (high) (TXH) Timer Y (low) (TYL) Timer Y (high) (TYH) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer X mode register (TXM) Timer Y mode register (TYM) Timer 123 mode register (T123M) Transmit/receive buffer register 2 (TB2/RB2) Serial I/O2 status register (SIO2STS) Serial I/O2 control register (SIO2CON) UART2 control register (UART2CON) Baud rate generator 2 (BRG2) LCD contrast control register (LC) LCD mode register (LM) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Fig. 3 Memory map of special function register (SFR) 8 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O PORTS Direction Registers The 7510 group has 41 programmable I/O pins arranged in six I/O ports (ports P0 to P5). The I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input or output. When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin. If data is read from a pin which is set for output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating and can read the value of the pin itself. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. When “0” is written to the pull-up control register, the pull up on the pin is disabled. When “1” is written to the pull-up control register, the pull-up on the pin is enabled. After reset, all the pull-up control registers are initialized to “0016 ”, disabling all the internal pull-ups. b7 b0 Port Pi pull-up control register (PULLPi : addresses 000C 16 to 001116 ) Pi0 pull-up Pi1 pull-up Pi2 pull-up Pi3 pull-up Pi4 pull-up Pi5 pull-up Pi6 pull-up Pi7 pull-up 0 : Disabled 1 : Enabled i = 0 to 5 Port Pull-up Control Registers The 7510 group is equipped with internal pull-ups that can be enabled by software. Each I/O port of ports P0–P5 has an port Pi (i= 0 to 5) pull-up control register (addresses 000C16 to 0011 16). Each bit of the pull-up control register controls a corresponding bit of the port. The value written to each individual bit determines whether the pull-up of the corresponding pin is either enabled or disabled. Fig. 4 Structure of port Pi pull-up control register Pin P00 –P07 P10 –P17 P20 –P27 P30 /RXD2 , P31 /TXD2, P32 / SCLK2, P33/SRDY2 P34 –P37 P40 /INT0 P41 /INT1 P42 /CNTR0 , P43 /CNTR1 P44 /RXD1 , P45 /TXD1, P46 / SCLK1, P47/SRDY1 P5 0/XCOUT, P51 /XCIN COM0– COM15 SEG 0– SEG 79 Name Port P0 Port P1 Port P2 Input/Output Input/output, individual bits Input/output, individual bits Input/output, individual bits I/O Format CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level Non-Port Function Related SFRs Ref. No. (1) (1) Key-on wake up interrupt input Serial I/O2 function I/O Interrupt control register 2 Serial I/O2 control register Serial I/O2 status register UART control register 2 (2) (3) (4) (5) (6) (1) (7) (8) (9) (8) (3) (4) (5) (6) (1) Port P3 Input/output, individual bits Input External interrupt input Timer X function I/O Timer Y function I/O Serial I/O1 function I/O Timer X mode register Timer Y mode register Serial I/O1 control register Serial I/O1 status register UART1 control register CPU mode register LCD mode register Port P4 Input/output, individual bits CMOS compatible input level CMOS 3-state output Port P5 Common Segment Input/output, individual bits Output Output CMOS compatible input level CMOS 3-state output LCD common output LCD segment output Sub-clock generating circuit I/O Notes 1: For details of how to use double-function ports as function I/O ports, refer to the applicable sections. 2: Make sure that the input level at each pin is either 0 V or V CC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from V CC to V SS through the input-stage gate. 9 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (1) Port P0, P1, P3 4 to P3 7, P5 Pull-up control (2) Port P2 Pull-up control Direction register Data bus Port latch Data bus Direction register Port latch Key-on wake up input (3) Port P3 0, P44 Serial I/O enable bit Receive enable bit Pull-up control (4) Port P3 1, P45 Pull-up control P-channel output disable bit Serial I/O enable bit Transmit enable bit Direction register Data bus Port latch Direction register Data bus Port latch Serial I/O input Serial I/O output (5) Port P3 2, P4 6 Serial I/O synchronous clock selection bit Serial I/O enable bit Serial I/O mode selection bit Serial I/O enable bit Direction register Data bus Port latch Pull-up control (6) Port P3 3, P4 7 Serial I/O mode selection bit Serial I/O enable bit SRDY output enable bit Direction register Data bus Port latch Pull-up control Serial clock output External clock input Serial ready output Fig. 5 Port block diagram (1) 10 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (7) Port P4 0 (8) Port P4 1, P43 Pull-up control Direction register Data bus Data bus INT0 interrupt input INT1 interrupt input CNTR1 interrupt input Port latch (9) Port P4 2 Pull-up control Direction register Data bus Port latch Pulse output mode Timer output CNTR0 interrupt input Fig. 6 Port block diagram (2) 11 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER INTERRUPTS A total of 15 sources can generate interrupts: 5 external, 9 internal, and 1 software. Interrupt Operation When an interrupt is received, the program counter and processor status register are automatically pushed onto the stack. The interrupt disable flag is set to inhibit other interrupts from interfering. The corresponding interrupt request bit is cleared and the interrupt jump destination address is read from the vector table into the program counter. Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt is generated if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The reset and BRK instruction can not be disabled with any flag or bit. The I flag disables all interrupts except for the BRK instruction interrupt and the reset. When several interrupts occur at the same time, the interrupts are received according to priority. Notes on Use When the active edge of an external interrupt (INT 0, INT1, CNTR0 , or CNTR 1) is changed, the corresponding interrupt request bit may also be set. Therefore, please take following sequence; (1) Disable the external interrupt which is selected. (2) Change the active edge selection. (3) Clear interrupt request which is selected to “0”. (4) Enable the external interrupt which is selected. Table 1 Interrupt vector addresses and priority Interrupt source Reset (Note 2) INT 0 INT 1 Serial I/O1 reception Serial I/O1 transmission Timer X Timer Y Timer 2 Timer 3 Serial I/O2 reception Serial I/O2 transmission CNTR 0 CNTR 1 Timer 1 Key-on wake up BRK instruction Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Vector addresses (Note 1) High Low FFFD 16 FFFC16 FFFB16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB 16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDD16 FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC 16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDC16 Interrupt request generating conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At end of serial I/O1 data reception At end of serial I/O1 transfer shift or when transmission buffer is empty At timer X underflow At timer Y underflow At timer 2 underflow At timer 3 underflow At end of serial I/O2 data reception At end of serial I/O2 transfer shift or when transmission buffer is empty At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At timer 1 underflow At falling of conjunction of input logic level for port P2 (at input) At BRK instruction execution Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected Valid when serial I/O2 is selected Valid when serial I/O2 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (valid when an “L” level is applied) Non-maskable software interrupt Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 12 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request Fig. 7 Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A 16 ) INT0 active edge selection bit INT1 active edge selection bit Not used (return “0” when read) 0 : Falling edge active 1 : Rising edge active b7 b0 Interrupt request register 1 (IREQ1 : address 003C 16) INT0 interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit b7 b0 Interrupt request register 2 (IREQ2 : address 003D 16 ) Serial I/O2 receive interrupt request bit Serial I/O2 transmit interrupt request bit CNTR0 interrupt request bit CNTR1 interrupt request bit Timer 1 interrupt request bit Key-on wake up interrupt request bit Not used (return “0” when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E 16) INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit b7 b0 Interrupt control register 2 (ICON2 : address 003F 16) Serial I/O2 receive interrupt enable bit Serial I/O2 transmit interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit Timer 1 interrupt enable bit Key-on wake up interrupt enable bit Not used (returns “0” when read) Not used (returns “0” when read) (Do not write “1” to this bit) 0 : Interrupts disabled 1 : Interrupts enabled Fig. 8 Structure of interrupt-related registers 13 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMERS The 7510 group has five built-in timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, whereas timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches “0016 ”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit cor- XCIN 1/32 Internal system clock selection bit XIN “1” “0” CNTR0 active edge selection bit P42/CNTR 0 “0” 1/16 Timer X stop control bit “00” Timer XL latch (8) “01” “11” Timer XL (8) “10” “1” Timer X operation mode bit Pulse output mode “0” Q Q Pulse width continuously measurement mode Rising edge detector Falling edge detector “00” Timer Y stop “01” control bit “11” “0” Timer YL (8) “10” “1” CNTR1 active edge selection bit Timer Y operation mode bit Timer Y operation mode bit “11” “00” “01” “10” CNTR1 interrupt request Timer YH (8) Timer Y interrupt request Period measurement mode S T CNTR0 interrupt request Timer X write control bit Timer XH latch (8) Timer XH (8) Timer X interrupt request P42 direction register P42 latch CNTR0 active “1” edge selection bit Pulse output mode Timer YL latch (8) Timer YH latch (8) P43 /CNTR1 Timer 2 write control bit Timer 1 latch (8) “0” Timer 1 (8) “1” Timer 1 count source selection bit “1” Timer 2 (8) “0” Timer 2 count source selection bit Timer 2 interrupt request Timer 2 latch (8) Timer 1 interrupt request Timer 3 latch (8) “0” Timer 3 (8) “1” Timer 3 interrupt request Timer 3 count source selection bit Fig. 9 Block diagram of Timer 14 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER responding to that timer is set to “1”. Read and write operation on 16-bit timer must be performed for both high and low-order bytes. When reading a 16-bit timer, read the high-order byte first. When writing to a 16-bit timer, write the low-order byte first. The 16-bit timer cannot perform the correct operation when reading during the write operation, or when writing during the read operation. If the value is written in latch only, unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer X are performed at the same timing. Note on CNTR 0 I nterrupt Active Edge Selection CNTR0 interrupt active edge depends on the CNTR0 active edge selection bit. Timer X Timer X is a 16-bit timer that can be selected in one of four modes and can be controlled the timer X write by setting the timer X mode register. Timer mode The timer counts f(X IN)/16 (or f(X CIN)/16, if the selected system clock φ is f(XCIN )/2). Pulse output mode Each time the timer underflows, a signal output from the CNTR 0 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P42 direction register to output mode. Event counter mode The timer counts signals input through the CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. Pulse width measurement mode The count source is f(XIN)/16 (or f(XCIN )/16, if the selected system clock φ is f(XCIN )/2). If CNTR 0 active edge selection bit is “0”, the timer counts while the input signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while the input signal of CNTR0 pin is at “L”. b7 b0 Timer X mode register (TXM : address 0027 16) Timer X write control bit 0 : Write data in latch and timer 1 : Write data in latch only Not used (Always write “0” ) Timer X operation mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge selection bit 0 : Count at rising edge in event counter mode Start from “H” output in pulse output mode Measure “H” pulse width in pulse width measurement mode Falling edge active for CNTR 0 interrupt 1 : Count at falling edge in event counter mode Start from “L” output in pulse output mode Measure “L” pulse width in pulse width measurement mode Rising edge active for CNTR 0 interrupt Timer X stop control bit 0 : Count start 1 : Count stop Timer X Write Control If the timer X write control bit is “0”, when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time. If the timer X write control bit is “1”, when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows. Fig. 10 Structure of timer X mode register 15 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer Y Timer Y is a 16-bit timer that can be selected in one of four modes. Timer mode The timer counts f(X IN)/16 (or f(X CIN)/16, if the selected system clock φ is f(XCIN )/2). Period measurement mode CNTR 1 i nterrupt request is generated at rising/falling edge of CNTR1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down. Except for the above-mentioned, the operation in period measurement mode is the same as in timer mode. The timer value just before the reloading at rising/falling of CNTR1 pin input signal is retained until the timer Y is read once after the reload. The rising/falling timing of CNTR1 p in input signal is found by CNTR1 interrupt. Event counter mode The timer counts signals input through the CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. Pulse width HL continuously measurement mode CNTR1 i nterrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. b7 b0 Timer Y mode register (TYM : address 0028 16) Not used (return “0” when read) Timer Y operation mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNTR1 active edge selection bit 0 : Count at rising edge in event counter mode Measure the falling edge to falling edge period in period measurement mode Falling edge active for CNTR 1 interrupt 1 : Count at falling edge in event counter mode Measure the rising edge to rising edge period in period measurement mode Rising edge active for CNTR 1 interrupt Timer Y stop control bit 0 : Count start 1 : Count stop Fig. 11 Structure of timer Y mode register Note on CNTR 1 I nterrupt Active Edge Selection CNTR 1 interrupt active edge depends on the CNTR1 active edge selection bit. However, in pulse width HL continuously measurement mode, CNTR 1 interrupt request is generated at both rising and falling edges of CNTR 1 pin input signal regardless of the setting of CNTR1 active edge selection bit. 16 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer 1, Timer 2, Timer 3 Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for each timer can be selected by timer 123 mode register. The timer latch value is not affected by a change of the count source. However, because changing the count source may cause an inadvertent count down of the timer. Therefore, rewrite the value of timer whenever the count source is changed. b7 b0 Timer 123 mode register (T123M : address 0029 16) Not used (Always write “0” ) Timer 2 write control bit 0 : Write data in latch and timer 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : XIN /16 (or XCIN /16 when system clock φ = XCIN /2) Timer 3 count source selection bit 0 : Timer 1 output 1 : XCIN /32 Timer 1 count source selection bit 0 : XIN /16 (or XCIN /16 when system clock φ = XCIN /2) 1 : XCIN /32 Not used (return “0” when read) Timer 2 Write Control If the timer 2 write control bit is “0”, when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. If the timer 2 write control bit is “1”, when the value is written in the address of timer 2, the value is loaded only in the latch. The value in the latch is loaded in timer 2 after timer 2 underflows. Note on Timer 1 to Timer 3 When the count source of timer 1 to 3 is changed, the timer counting value may be changed large because a thin pulse is generated in count input of timer. If the count source of timer 2 or timer 3 is connected to timer 1 output, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1 , timer 2 and timer 3 after the count source selection of timer 1 to 3. Fig. 12 Structure of timer 123 mode register 17 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SERIAL I/O The 7510 group has two built-in serial I/O channels (serial I/O1 and serial I/O2). Both serial I/O ports are functionally identical. Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation. Clock Synchronous Serial I/O Mode Clock synchronous serial I/O mode can be selected by setting the mode selection bit of the serial I/O control register (addresses 001A16 and 0032 16) to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the T B/RB (addresses 0018 16 a nd 003016 ). Data bus Address 0018 16 003016 Receive buffer P44 /RXD1 P30 /RXD2 Receive shift register Shift clock Clock control circuit Serial I/O control register Address 001A 16 0032 16 Receive buffer full flag (RBF) Receive interrupt request (RI) P46 /SCLK1 P32 /SCLK2 BRG count source selection bit f(XIN ) 1/4 P47/SRDY1 P33/SRDY2 P45/TXD1 P31/TXD2 F/F Falling-edge detector Serial I/O synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1/4 Address 001C16 003416 Clock control circuit Shift clock Transmit shift register Transmit buffer register Address 0018 16 003016 Data bus Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O status register Address 0019 16 003116 Contents in are for serial I/O2. Fig. 13 Block diagram of clock synchronous serial I/O Internal clock φ Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output T XD Serial input R XD Receive enable signal S RDY Write signal to receive/transmit buffer TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE = 1) or after the transmit shift operation has ended (TSC = 1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register. 2 : If data is written to the transmit buffer when TSC = 0, the transmit clock is generated continuously and serial data is output continuously from the TXD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”. D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Fig. 14 Operation of clock synchronous serial I/O function 18 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer can hold a character while the next character is being received. Data bus Address 001816 003016 OE Receive buffer Character length selection bit P44 /RXD1 P30 /RXD2 ST detector 7 bits 8 bits PE FE Receive shift register Serial I/O control register Address 001A 16 003216 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 SP detector Clock control circuit UART control register Address 001B 16 003316 Serial I/O synchronous clock selection bit P46 /SCLK1 P32 /SCLK2 BRG count source selection bit f(XIN ) 1/4 Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 003416 ST/SP/PA generator 1/16 P45/TXD1 P31/TXD2 Transmit shift register Character length selection bit Transmit buffer register Address 001816 003016 Data bus Contents in are for serial I/O2. Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O status register Address 0019 16 003116 Fig. 15 Block diagram of UART serial I/O Transmit or receive clock Transmit buffer write signal TBE = 0 TSC = 0 TBE = 1 Serial output TXD ST D0 TBE = 0 TBE = 1 D1 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit(s) SP ST D0 V TSC = 1 V D1 SP Generated at 2nd bit in 2-stop-bit mode Receive buffer read signal RBF = 0 RBF = 1 Serial input R XD ST D0 D1 SP ST D0 D1 RBF = 1 SP Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3 : The receive interrupt (RI) is set when the RBF flag becomes “1”. 4 : After data is written to the transmit buffer when TSC = 1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC = 0. Fig. 16 Operation of UART serial I/O function 19 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O Control Register SIO1CON (001A16), SIO2CON (003216) The serial I/O control register consists of eight control bits for the serial I/O function. UART Control Register UART1CON (001B 16), UART2CON (003316) The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P4 5/TXD1 (P31 / TXD2 ) pin. Serial I/O Status Register SIO1STS (001916), SIO2STS (003116) The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer, and the receive buffer full flag is set. Writing to the serial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of the serial I/O control register) also clears all the status flags, including the error flags. All bits of the serial I/O status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. Transmit Buffer Register/Receive Buffer Register TB1/RB1 (001816), TB2/RB2 (003016) The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer register is write-only and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer register is “0”. Baud Rate Generator BRG1 (001C16), BRG2 (003416) The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n+1), where n is the value written to the baud rate generator. 20 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Serial I/O status register (SIO1STS : address 0019 16) (SIO2STS : address 0031 16) Transmit buffer empty flag (TBE) 0 : Buffer full 1 : Buffer empty Receive buffer full flag (RBF) 0 : Buffer empty 1 : Buffer full Transmit shift completion flag (TSC) 0 : Transmit shift in progress 1 : Transmit shift completed Overrun error flag (OE) 0 : No error 1 : Overrun error Parity error flag (PE) 0 : No error 1 : Parity error Framing error flag (FE) 0 : No error 1 : Framing error Summing error flag (SE) 0 : (OE) U (PE) U (FE) = 0 1 : (OE) U (PE) U (FE) = 1 Not used (returns “1” when read) b7 b7 b0 UART control register (UART1CON : address 001B 16) (UART2CON : address 0033 16 ) Character length selection bit (CHAS) 0 : 8 bits 1 : 7 bits Parity enable bit (PARE) 0 : Parity checking disabled 1 : Parity checking enabled Parity selection bit (PARS) 0 : Even parity 1 : Odd parity Stop bit length selection bit (STPS) 0 : 1 stop bit 1 : 2 stop bits P45 /TXD 1 P-channel output disable bit (POFF) P31 /TXD2 P-channel output disable bit 0 : CMOS output (in output mode) 1 : N-channel open-drain output (in output mode) Not used (return “1” when read) b0 Serial I/O control register (SIO1CON : address 001A 16) (SIO2CON : address 0032 16) BRG count source selection bit (CSS) 0 : f(XIN ) 1 : f(XIN ) divided by 4 Serial I/O synchronous clock selection bit (SCS) 0 : BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1 : External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY output enable bit (S RDY ) 0 : P47 P33 pin operates as ordinary I/O pin 1 : P47 P33 pin operates as S RDY output pin Transmit interrupt source selection bit (TIC) 0 : Interrupt when transmit buffer has emptied 1 : Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0 : Transmit disabled 1 : Transmit enabled Receive enable bit (RE) 0 : Receive disabled 1 : Receive enabled Serial I/O mode selection bit (SIOM) 0 : Asynchronous serial I/O (UART) 1 : Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0 : Serial I/O disabled (pins P4 4 to P47 P30 to P3 3 operate as ordinary I/O pins) 1 : Serial I/O enabled (pins P4 4 to P47 P30 to P3 3 operate as serial I/O pins) Contents in are for serial I/O2. Fig. 17 Structure of serial I/O control registers 21 22 Data bus LCD contrast control register address 003716 7 LCD mode register address 0039 16 Duty ratio selection bit LCDCK division ratio selection bit LCDCK count source selection bit f(XIN )/1024 LCD clock generator LCD CONTROLLER/DRIVER 7 0 Fig. 18 Block diagram of LCD controller/driver 0 LCDCK count source selection bit LCD display RAM address selection bit LCD drive timing selection bit LCD enable bit LCDCK Bit selector Contrast controller Bias controller Common driver Bias resistor Common driver Bit selector Timing controller 1 5 .............. .............. 0 1 5 f(X CIN)/16 LCD contrast control enable bit .............. .............. LCD display RAM 004016, 009016 004116, 009116 008E16, 00DE16 008F 16, 00DF16 or 034016, 039016 ......... or or or 034116, 039116 038E16, 03DE16 038F 16, 03DF16 The 7510 group has a built-in Liquid Crystal Display (LCD) controller/driver consisting of the following. q A 160-byte LCD display RAM q Segment drivers q Common drivers q A timing generator q A built-in bias resistor 0 1 5 0 1 5 0 .............. .............. Bit selector Bit selector Segment driver Segment driver Segment driver Segment driver .............. SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 7510 Group q A timing controller q An LCD mode register q An LCD contrast control register q An LCD contrast controller A maximum of eighty segment output pins (SEG0–SEG79) and sixteen common output pins (COM 0–COM15 ) can be used to control an external LCD display controller. MITSUBISHI MICROCOMPUTERS SEG0 SEG78 SEG79 SEG1 VLCD VL2 VL3 VSS COM0 COM1 COM7 COM 8 COM9 COM15 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER LCD Controller/Driver Function The controller/driver reads the display data, performs bias and duty ratio control, and outputs the correct LCD timing signals on the segment and common pins according to the data in LCD display RAM. Table 2 Maximum number of display pixels for each duty ratio Duty ratio 1/8 1/11 Maximum number of display pixels 8 ! 80 dots (16 characters (5 ! 7 dots/1 character) + cursor) ! 1 line 11 ! 80 dots (16 characters (5 ! 10 dots/1 character) + cursor) ! 1 line 16 ! 80 dots (16 characters (5 ! 7 dots/1 character) + cursor) ! 2 line LCD Mode Register LM (003916) The LCD mode register is an 8-bit register. This register is used to match the characteristics of the controller/driver to the LCD panel used. 1/16 Note: Prior to executing an STP instruction, the LCD must be disabled by clearing the bit 3 of the LCD mode register to “0”. b7 b0 LCD mode register (LM : address 0039 16) Duty ratio selection bits b1 b0 0 0 : 1/8 duty (pins COM 0 – COM7) 0 1 : 1/8 duty (pins COM 8 – COM15) 1 0 : 1/11 duty (pins COM 0 – COM10) 1 1 : 1/16 duty (pins COM 0 – COM15) LCD display RAM address selection bit 0 : Third page 1 : Zero page LCD enable bit 0 : Turn off 1 : Turn on LCD drive timing selection bit 0 : Type-A 1 : Type-B LCDCK division ratio selection bits b6 b5 0 0 : Clock input 0 1 : Clock input/2 1 0 : Clock input/4 1 1 : Clock input/8 LCDCK count source selection bit 0 : f(XIN ) /1024 1 : f(XCIN ) /16 Fig. 19 Structure of LCD mode register 23 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER LCD Display RAM The 7510 group has LCD display RAM apart from user RAM at addresses 004016 to 043F16. The LCD display RAM consists of 160 bytes. The memory space for the LCD display RAM can be selected as zero page addresses 0040 16 to 00DF16 or third page addresses 034016 to 03DF16 , by setting the LCD display RAM address selection bit. When the LCD display RAM is at zero page, the addresses 004016 to 00DF 16 of user RAM can not be used. When the LCD display RAM is at third page, the addresses 034016 t o 03DF16 o f user RAM can not be used. After reset, the LCD display RAM is set to third page. Writing “1” to a bit of the LCD display RAM activates the corresponding pixel on the LCD panel and writing “0” to the bit turns the pixel off. Note: The data of user RAM at the same addresses with the LCD display RAM (addresses 0040 16 to 00DF 16 or 034016 to 03DF16) is retained. Therefore, user RAM can be used effectively by switching the LCD display RAM address. SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 LSB MSB LSB MSB LCD display RAM map At third page selection 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16 008616 008716 008816 008916 008A16 008B16 008C16 008D16 008E16 008F16 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 At zero page selection Fig. 20 LCD display RAM map and example of a display pattern for 1/16 duty operation 24 009016 009116 009216 009316 009416 009516 009616 009716 009816 009916 009A16 009B16 009C16 009D16 009E16 009F16 00A016 00A116 00A216 00A316 00A416 00A516 00A616 00A716 00A816 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Bias Control and Time Division Control The LCD controller/driver has built-in bias resistor and supports 1/ 4 bias or 1/5 bias. The bias setting is made by either floating pins VL2 and VL3 (1/5 bias) or shorting them together externally (1/4 bias). The number of common pins driven is determined by the duty ratio selected. Bits 0 and 1 of the LCD mode register are used to set the duty ratio. Table 3 Time division control Duty ratio 1/8 1/11 1/16 Duty ratio selection bit Bit 1 0 0 1 1 Bit 0 0 1 0 1 Common pins used COM0–COM7 COM8–COM15 COM0–COM10 COM0–COM15 When the contrast controller is used, it becomes possible to apply 32 steps of voltage to VL5 from 1/2 V LCD through VLCD . Consequently, 32 steps of contrast adjustment by the software becomes possible. Note: Supply power to the contrast controller from an external source through the VLCD pin. Also, when bit 7 of the LCD contrast control register is set to “0”, V LCD pin is coupled directly to VL5 (the contrast controller and V L5 become separated). In this case, perform contrast adjustment using an external circuit. b7 b0 LCD contrast control register (LC : address 0037 16) VLCD level selection bit Not used (returns “0” when read) LCD contrast control enable bit 0 : Built-in LCD contrast controller is not used 1 : Built-in LCD contrast controller is used. Note: For all duty ratios, the unused common pins output the non-select waveform. Contrast Controller The contrast controller is a circuit generating 32 steps of voltages using the voltage applied to the V LCD pin as the reference voltage. The voltage generated varies depending on the values given to bit 0–bit 4 with the LCD contrast control register. When bit 7 of the LCD contrast control register is set to “1”, the voltage generated by the contrast controller is applied to V L5. Given below is the relation between the values set to bit 0–bit 4 of LCD contrast control register and the voltages applied to VL5. Voltage applied to VL5 = Voltage applied to the VLCD pin ! (n+33)/64 Where: n = Value set to bit 0–bit 4 of the LCD contrast control register (in decimal values) Fig. 22 Structure of LCD contrast control register LCD Drive Timing The LCD controller/driver supports both type-A and type-B drive timing. The desired type is selected by setting the LCD drive timing selection bit (bit 4 of the LCD mode register). If the LCD drive timing selection bit is set to “0”, type-A is selected, and if this bit is set to “1”, type-B is selected. After reset, type-A is selected for the drive timing. The frame frequency can be determined by the following equation: Frame frequency = LCDCK count source frequency LCDCK division ratio ! duty ratio Variable resistance for brightness control VLCD “0” Variable resistance for brightness “1” control LCD contrast control enable bit Contrast controller VL5 R VL4 Contrast controller VLCD “0” “1” LCD contrast control enable bit VL5 R VL4 VL3 R VL3 VL2 R VL2 R VL1 R VL3 Open VL2 R VL3 R VL2 R VL1 R External connection 1/5 bias 1/4 bias Fig. 21 Example of circuit at 1/5 and 1/4 bias 25 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER LCDCK 1 frame VL5 VL4 COM7 VL3 VL2 VL1 VSS VL5 VL4 COM6 VL3 VL2 VL1 VSS VL5 VL4 SEG0 VL3 VL2 VL1 VSS VL5 VL4 VL3 VL2 VL1 SEG0 – COM7 VSS VL1 VL2 VL3 VL4 VL5 ON VL5 VL4 VL3 VL2 VL1 VSS SEG0 – COM6 VL1 VL2 VL3 VL4 VL5 OFF OFF OFF ON OFF Fig. 23 1/8 duty, 1/5 bias, type-A LCD wave diagram 26 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER LCDCK 1 frame VL5 VL4 VL3 VL2 VL1 VSS VL5 VL4 VL3 VL2 VL1 VSS VL5 VL4 VL3 VL2 VL1 VSS 1 frame COM7 COM6 SEG0 SEG0 – COM7 VL5 VL4 VL3 VL2 VL1 VSS VL1 VL2 VL3 VL4 VL5 ON VL5 VL4 VL3 VL2 VL1 VSS VL1 VL2 VL3 VL4 VL5 OFF ON OFF ON OFF SEG0 – COM6 OFF OFF OFF Fig. 24 1/8 duty, 1/5 bias, type-B LCD wave diagram 27 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER KEY-ON WAKE UP The 7510 group contains a key-on wake up interrupt function. The key-on wake up interrupt function is one way of returning from a power down state caused by the STP or WIT instruction. This interrupt is generated by applying “L” level to any pin of port P2 and the microcomputer is returned to the normal operating state. If a key matrix is connected to port P20 to P23 as shown in Figure 25, the microcomputer can be returned to a normal state by pressing any one of the keys. Port P2x (X = 0 to 7) “L” level output PULLP2 register bit 7 V VV P27 output PULLP2 register bit 6 V VV Port P27 latch Port P2 direction register bit 7 = “1” Key-on wake up input interrupt request P26 output PULLP2 register bit 5 V VV Port P26 latch Port P2 direction register bit 6 = “1” P25 output PULLP2 register bit 4 V VV Port P25 latch Port P2 direction register bit 5 = “1” P24 output PULLP2 register bit 3 V VV Port P24 latch Port P2 direction register bit 4 = “1” P23 input Port P23 latch Port P2 direction register bit 3 = “0” Port P2 input read circuit PULLP2 register bit 2 V VV P22 input Port P22 latch Port P2 direction register bit 2 = “0” PULLP2 register bit 1 V VV P21 input Port P21 latch Port P2 direction register bit 1 = “0” PULLP2 register bit 0 V VV P20 input Port P20 latch Port P2 direction register bit 0 = “0” V VV P-channel transistor for pull-up CMOS output buffer Fig. 25 Block diagram of port P2, and example of wired at used key-on wake up 28 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER RESET CIRCUIT To reset the microcomputer, RESET pin should be held at “L” level for 2 µ s or more. Then RESET pin is returned to “H” level (the power source voltage should be between 2.5 V and 5.5 V, and XIN oscillation width is stable), reset is released. In order to give the XIN clock time to stabilize, internal operation does not begin until after about 8000 XIN clock cycles are complete. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order) and address FFFC16 (low-order). Make sure that the reset input voltage is less than 0.5 V for V CC of 3.0 V at f(XIN) = 8.0 MHz. Address (1) Port P0 direction register (2) Port P1 direction register (3) Port P2 direction register (4) Port P3 direction register (5) Port P4 direction register (6) Port P5 direction register (7) Port P0 pull-up control register (8) Port P1 pull-up control register (9) Port P2 pull-up control register Poweron 3.0V Power source voltage 0V Register contents 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 000116 000316 000516 000716 000916 000B16 000C16 000D16 000E16 000F 16 001016 001116 (10) Port P3 pull-up control register (11) Port P4 pull-up control register (12) Port P5 pull-up control register (13) Serial I/O1 status register 001916 1 0 0 0 0 0 0 0 001A16 0016 Reset input voltage 0V 0.5V (14) Serial I/O1 control register (15) UART1 control register (16) Timer X (low) (17) Timer X (high) 001B16 1 1 1 0 0 0 0 0 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 FF16 FF16 FF16 FF16 FF16 0116 FF16 0016 0016 0016 VCC 1 5 M51953AL 4 3 VSS 7510 group 0.1µF RESET (18) Timer Y (low) (19) Timer Y (high) (20) Timer 1 (21) Timer 2 (22) Timer 3 (23) Timer X mode register (24) Timer Y mode register (25) Timer 123 mode register (26) Serial I/O2 status register (27) Serial I/O2 control register (28) UART2 control register 003116 1 0 0 0 0 0 0 0 003216 0016 f(XIN ) = 8.0MHz 003316 1 1 1 0 0 0 0 0 003716 003916 003A16 0016 0016 0016 Fig. 26 Example of reset circuit (29) LCD contrast control register (30) LCD mode register (31) Interrupt edge selection register (32) CPU mode register (33) Interrupt request register 1 (34) Interrupt request register 2 (35) Interrupt control register 1 (36) Interrupt control register 2 (37) Processor status register (38) Program counter 003B16 0 1 0 0 1 1 0 0 003C16 003D16 003E16 003F 16 (PS) (PC H) (PC L) 0016 0016 0016 0016 !!!!!1!! Contents of address FFFD 16 Contents of address FFFC 16 Note : The contents of all other registers and RAM are undefined after reset, so they must be initialized by software. ! : Undefined Fig. 27 Internal status of microcomputer after reset 29 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XIN φ RESET Internal reset Address ? ? ? ? FFFC FFFD ADH, ADL Reset address from vector table Data SYNC about 8000 clock cycles ? ? ? ? ADL ADH Notes 1 : f(XIN ) and f( φ) are in the relationship : f(X IN ) = 8.f(φ) 2 : A question mark (?) indicates an undefined status that depens on the previous status. Fig. 28 Reset sequence 30 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CLOCK GENERATING CIRCUIT The 7510 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and X COUT). Use the circuit constants in accordance with the resonator manufacturer’s recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and X COUT. Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O port. The pullup resistor of X CIN and XCOUT pins must be made invalid to use the XCIN oscillating circuit. Oscillation Control Stop mode If the STP instruction is executed, the internal clock φ stops at an “H” level. Timer 1 is set to “FF 16” and timer 2 is set to “0116 ”. Either XIN or XCIN divided by 16 is input to timer 1, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register are cleared to “0” except for bit 4. The timer 1 and timer 2 interrupt enable bits must be set to disabled (“0”), so a program must set these bits before executing a STP instruction. Oscillation restarts at reset or when an external interrupt is received, but the internal clock φ is not supplied to the CPU until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize. Wait mode If the WIT instruction is executed, the internal clock φ stops at an “H” level. XIN and XCIN are the same state with that before the execution of the WIT instruction. The internal clock restarts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. Frequency Control Middle-speed mode The internal clock φ is the frequency of XIN divided by 8. After reset, this mode is selected. High-speed mode The internal clock φ is half the frequency of XIN . Low-speed mode The internal clock φ is half the frequency of XCIN . Note: If you switch the mode between middle/high-speed and low-speed, both of X IN a nd XCIN o scillation must be stabilized. The sufficient time is required for the XCIN oscillation to stabilize, especially immediately after power-on and at returning from stop mode. The mode must be switched on condition that f(X IN) > 3f(X CIN ). Low-power consumption mode In low-speed mode, a low-power consumption operation can be entered by stopping the main clock XIN. To stop the main clock, set bit 5 of the CPU mode register to “1”. When the main clock XIN is restarted, the program must allow enough time for oscillation to stabilize. In low-power consumption mode, the XCIN-X COUT d rive performance can be reduced, allowing lower power consumption (8 µ A or less with XCIN = 32 kHz). To reduce the XCIN-X COUT drive performance, clear bit 3 of the CPU mode register to “0”. At reset or when the STP instruction is executed, this bit is set to “1” and strong drive is selected to help the oscillation to start. XCIN XCOUT Rf XIN XOUT Rd CCOUT CIN COUT CCIN Fig. 29 Ceramic resonator circuit XCIN XCOUT XIN XOUT Open External oscillator or pulse 2.5V VSS VCC VSS Open External oscillator Fig. 30 External clock input circuit 31 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XCIN XCOUT “1” “0” Port XC selection bit 1/32 XIN XOUT Internal system clock selection bit (Note 1) Low-speed mode 1/2 1/4 1/2 Timer 1 count source selection bit “1” Timer 1 “0” Timer 2 count source selection bit “0” Timer 2 “1” Middle/High-speed mode Main clock division ratio selection bit Middle-speed mode Timing φ (Internal clock) High-speed mode or Low-speed mode Main clock stop bit Q S R STP instruction WIT instruction S R Q Q S R STP instruction Reset Interrupt disable flag I Interrupt request Note : When using the low-speed mode, set the port X C selection bit to “1”. Fig. 31 System clock generating circuit block diagram 32 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Reset Middle-speed mode ( φ =1MHz) CM 7 = 0 (8.0MHz selected) CM 6 = 1 (Middle-speed) CM 5 = 0 (XIN oscillating) CM 4 = 0 (32kHz stopped) CM 6 “1” “0” High-speed mode ( φ = 4.0MHz) CM7 = 0 (8.0MHz selected) CM6 = 0 (High-speed) CM5 = 0 (XIN oscillating) CM4 = 0 (32kHz stopped) CM 4 “1” CM 6 “1” “0” “0” CM4 “0” CM6 “1” “0” “1” “0” CM 4 “1” CM 7 “1” “0” Middle-speed mode ( φ =1MHz) CM7 = 0 (8.0MHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (XIN oscillating) CM4 = 1 (32kHz oscillating) CM4 “1” CM 6 “1” “0” High-speed mode ( φ = 4.0MHz) CM7 = 0 (8.0MHz selected) CM6 = 0 (High-speed) CM5 = 0 (XIN oscillating) CM4 = 1 (32kHz oscillating) Low-speed mode ( φ =16kHz) CM7 = 1 (32kHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (XIN oscillating) CM4 = 1 (32kHz oscillating) CM7 “1” “0” CM 6 “1” “0” Low-speed mode ( φ = 16kHz) CM7 = 1 (32kHz selected) CM6 = 0 (High-speed) CM5 = 0 (XIN oscillating) CM4 = 1 (32kHz oscillating) “0” b7 b0 CPU mode register (CPUM : address 003B 16) CM 4 : Port X C selection bit 0 : I/O port 1 : X CIN , XCOUT CM 5 : Main clock (X IN -XOUT ) stop bit 0 : Operating 1 : Stopped CM 6 : Main clock division ratio selection bit 0 : X IN /2 (high-speed mode) 1 : X IN /8 (middle-speed mode) CM 7 : Internal system clock selection bit 0 : X IN -XOUT selected (middle/high-speed mode) 1 : X CIN -XCOUT selected (low-speed mode) CM 5 “1” CM 6 “1” “0” “0” CM5 “0” CM6 “1” “0” “1” “0” CM 5 “1” Low power consumption mode ( φ =16kHz) CM6 CM7 = 1 (32kHz selected) “1” “0” CM6 = 1 (Middle-speed) CM5 = 1 (XIN stopped) CM4 = 1 (32kHz oscillating) CM5 “1” Low power consumption mode ( φ =16kHz) CM7 = 1 (32kHz selected) CM6 = 0 (High-speed) CM5 = 1 (XIN stopped) CM4 = 1 (32kHz oscillating) Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.) 2 : The main clock must be oscillated (CM 5 : 1→0) before the switching from the low-speed mode to middle/high-speed mode (CM 7 : 1→0). 3 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. Timer and LCD operate in the wait mode. 4 : When the stop mode is ended, a delay of approximately 2ms is automatically generated by timer 1 and timer 2 in middle/high-speed mode. 5 : When the stop mode is ended, a delay of approximately 0.25s is automatically generated by timer 1 and timer 2 in low-speed mode. 6 : The example assumes that 8.0MHz is being applied to the X IN pin and 32kHz to the X CIN pin φ indicates the internal clock. Fig. 32 State transitions of system clock “0” 33 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal operation mode (D) flag because of their effect on calculations. Serial I/O In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to “1”. Serial I/O continues to output the final bit from the TXD pin after transmission is completed. Instruction Execution Time Interrupts The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. In high-speed mode, the frequency of the internal clock φ is half of the XIN frequency. In middle-speed mode, the frequency of the internal clock φ is one eighth the XIN frequency. Decimal Calculations To calculate in decimal notation, set the decimal operation mode flag (D) to “1”, then execute the ADC or the SBC instruction. Only the ADC and the SBC instruction yield proper decimal results. After executing the ADC or SBC instruction, execute at least one instruction before executing the SEC, the CLC, or the CLD instruction. In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flag are invalid. The carry flag can be used to indicate whether a carry or borrow has occurred. Initialize the carry flag before each calculation. Clear the carry flag before the ADC instruction and set the flag before the SBC instruction. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: 1. Mask ROM Order Confirmation Form 2. Mark Specification Form 3. Data to be written to ROM, in EPROM form (three identical copies) Timers If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). Multiplication and Division Instructions The index X mode (T) and the decimal mode (D) flag do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used: q the data transfer instruction (LDA, etc.) q the operation instruction when the index X mode flag (T) is “1” q the addressing mode which uses the value of a direction register as an index q the bit-test instruction (BBC or BBS, etc.) to a direction register q the read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direction registers. 34 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PROM Programming Method The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Package 176P6D-A Name of Programming Adapter PCA4738F-176A The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 33 is recommended to verify programming. Programming with PROM Programmer Screening (Caution) (150°C for 40 hours) Verification with PROM Programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150°C exceeding 100 hours. Fig. 33 Programming and testing of One Time PROM version 35 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VI VI VI VO VO VO Pd Topr Tstg Parameter Power source voltage Input voltage P00–P07, P10–P17 , P20–P27, P30–P37, P41–P47 , P50, P51 Input voltage P40 Input voltage VLCD Input voltage RESET, XIN, XCIN Output voltage P00–P07 , P10–P17, P20–P27 , P30–P37 , P41–P47, P50, P5 1, XOUT Output voltage SEG0 –SEG79, COM0 –COM15 Output voltage XCOUT Power dissipation Operating temperature Storage temperature Conditions Retings –0.3 to 7.0 –0.3 to VCC+0.3 –0.3 to 13 –0.3 to VCC+0.3 –0.3 to VCC+0.3 –0.3 to VCC+0.3 –0.3 to VLCD –0.3 to VCC 300 –20 to 85 –40 to 125 Unit V V V V V V V V mW °C °C All voltage are based on V SS. Output transistors are cut off. Ta = 25° C RECOMMENDED OPERATING CONDITIONS (VCC = 4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol Parameter High-speed mode f(φ ) ≥ 2.5 MHz Middle-speed mode 1.0 MHz ≤ f(φ ) < 2.5 MHz Low-speed mode f(φ ) ≤ 650 kHz Min. 4.0 3.0 2.5 Limits Typ. 5.0 5.0 5.0 0 0.8VCC 0.8VCC 0 0 0 VCC VCC 2.5 0.2VCC 0.2VCC 0.4 –80 80 –40 40 –10 10 –5 5 2.6 8.0 50 Max. 5.5 5.5 5.5 VCC Unit V V V V V V V V V V V mA mA mA mA mA mA mA mA MHz MHz kHz VCC VLCD VSS VIH VIH VIH VIL VIL VIL Σ IOH(peak) Σ I OL(peak) Σ I OH(avg) Σ I OL(avg) I OH(peak) I OL(peak) I OH(avg) I OL(avg) f(CNTR 0) f(CNTR 1) f(XIN ) f(XCIN ) Power source voltage Power source voltage for LCD driver Power source voltage “H” input voltage P00–P07, P1 0–P17, P20–P27, P30 –P37, P40–P47, P50 , P51 “H” input voltage RESET, XIN “H” input voltage XCIN “L” input voltage P00–P07, P10–P17, P20–P27, P30–P37 , P40–P47, P50, P51 “L” input voltage RESET, XIN “L” input voltage XCIN “H” total peak output current (Note 1) P00–P07 , P10–P17 , P20–P27 , P30–P37 , P41–P47 , P50, P51 “L” total peak output current P00–P07 , P10 –P17, P20 –P27 , P30–P37 , P41 –P47, P50 , P51 “H” total average output current P00 –P07, P10 –P17 , P20–P27 , P30 –P37 , P41–P47 , P50 , P51 “L” total average output current P00–P07 , P10–P1 7, P20 –P27, P3 0–P37 , P41–P47 , P50, P5 1 “H” peak output current (Note 2) P00 –P07 , P10–P1 7, P20 –P27 , P30 –P37, P41 –P47 , P50 , P51 “L” peak output current P00–P07 , P10–P1 7, P20 –P27, P30 –P37 , P41–P47 , P50 , P51 “H” average output current (Note 3) P00 –P07, P10 –P17, P20 –P27, P30 –P37, P41–P4 7, P50, P5 1 “L” average output current P00–P07 , P10–P17 , P20 –P27, P30 –P37, P4 1–P47 , P50, P51 Timer X, Timer Y input frequency (at 50% duty) Main clock input oscillation frequency (Note 4) Sub-clock input oscillation frequency (Note 4, 5) 32.768 Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current is an average value measured over 100 ms. 4: The oscillating frequency has a 50% duty cycle. 5: In low-speed mode, the sub-clock input oscillation frequency must be used on condition that f(XCIN ) < f(XIN)/3. 36 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS (VCC = 4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol VOH VOL VT+ –VT– VT+ –VT– VT+ –VT– I IH I IH I IH I IH Parameter “H” output voltage P00–P07, P1 0–P17, P20–P27 , P30–P37, P4 1–P47, P50, P5 1 “L” output voltage P00–P07, P1 0–P17, P20–P27 , P30–P37, P4 1–P47, P50, P5 1 Hysteresis INT0, INT 1, CNTR0 , CNTR1 Hysteresis SCLK1, SCLK2 , RXD1, RXD2 Hysteresis RESET “H” input current P00–P07 , P10–P17, P20 –P27, P30–P37 , P41–P47, P50 , P51 “H” input current RESET, P40 “H” input current XIN “H” input current XCIN Test conditions I OH = –10 mA I OL = 10 mA 0.4 0.5 0.5 5.0 VI = VCC VI = VCC VI = 2.5 V VI = 0 V Pull-ups “off” VCC = 5 V, VI = 0 V Pull-ups “on” VCC = 3 V, VI = 0 V Pull-ups “on” VI = VSS VI = VSS VI = VSS With clock stopped I O = –0.1 mA I O = ±0.1 mA I O = ±0.1 mA I O = 0.1 mA I O = –0.1 mA I O = ±0.1 mA I O = ±0.1 mA I O = 0.1 mA f(XIN) = 8.0 MHz f(XIN) = 5.0 MHz 6.4 4.0 5.0 4.0 2.0 –5.0 –30 –6 –70 –25 –140 –45 –5.0 –4.0 –2.0 2.0 3 0.5 4.5 4.5 0.5 0.5 6.5 6.5 0.5 13 8.0 5.5 Min. VCC–2.0 2.0 Limits Typ. Max. Unit V V V V V µA µA µA µA µA µA µA µA µA µA V kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ mA mA I IL “L” input current P00–P07, P10–P17 , P20–P27, P30–P37, P41–P47 , P50, P51 I IL I IL I IL VRAM Rbias RCOM5 RCOM4 RCOM1 RCOM0 RSEG5 RSEG3 RSEG2 RSEG0 “L” input current RESET, P4 0 “L” input current XIN “L” input current XCIN RAM hold voltage LCD bias resistance (Note) COM on-resistance with VL5 output from COM COM on-resistance with VL4 output from COM COM on-resistance with VL1 output from COM COM on-resistance with VL0 output from COM SEG on-resistance with V L5 output from SEG SEG on-resistance with V L3 output from SEG SEG on-resistance with V L2 output from SEG I CC SEG on-resistance with V L0 output from SEG In high-speed mode, VCC = 5 V Output transistors are isolated. In low-speed mode, VCC = 3 V f(XIN) = stopped f(XCIN) = 32 kHz Low-power consumption mode Output transistors are isolated. Power source current In low-speed mode, VCC = 3 V f(XIN) = stopped f(XCIN) = 32 kHz (in wait mode) Low-power consumption mode Output transistors are isolated. All oscillation are stopped. (in stop mode) Output transistors are isolated. 20 µA 4.5 9.0 µA Ta = 25°C Ta = 85°C 0.1 1.0 10 µA µA Note: This is the value of bias resistance for one stage. 37 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER LCD CONTRAST CONTROLLER CHARACTERISTICS (VCC = 4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol – – – VCCH Parameter Resolution Accuracy Iinearity Maximum output voltage (Note) Test conditions Limits Min. Typ. Max. 5 2.0 ±0.5 VLCD Unit Bits % LSB V VCC = 5.0 V, VLCD = VCC 4.9 Note: When the value in the LCD contrast control register (address 0037 16) is “9F16”. 38 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING REQUIREMENTS 1 (V CC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol t w(RESET) t c(X IN) t wH(XIN) t wL(XIN) t c(CNTR) t wH(CNTR) t wH(INT) t wL(CNTR) t wL(INT) t c(S CLK1) t c(S CLK2) t wH(SCLK1) t wH(SCLK2) t wL(SCLK1) t wL(SCLK2) t su(R XD 1–SCLK1) t su(R XD 2–SCLK2) t h(SCLK1 –R XD1 ) t h(SCLK2 –R XD2 ) Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0 , CNTR1 input cycle time CNTR0 , CNTR1 input “H” pulse width INT 0, INT1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 , INT1 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O2 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O2 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O2 input set up time Serial I/O1 input hold time Serial I/O2 input hold time Limits Min. 2 125 50 50 200 80 80 80 80 800 800 370 370 370 370 220 220 100 100 Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: When f( φ) = 4 MHz and bit 6 of address 001A16 or 003216 is “1” (clock synchronous). Divide this value by four when f(φ ) = 4 MHz and bit 6 of address 001A 16 or 003216 is “0” (clock asynchronous). TIMING REQUIREMENTS 2 (V CC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol t w(RESET) t c(X IN) t wH(XIN) t wL(XIN) t c(CNTR) t wH(CNTR) t wH(INT) t wL(CNTR) t wL(INT) t c(S CLK1) t c(S CLK2) t wH(SCLK1) t wH(SCLK2) t wL(SCLK1) t wL(SCLK2) t su(R XD 1–SCLK1) t su(R XD 2–SCLK2) t h(SCLK1 –R XD1 ) t h(SCLK2 –R XD2 ) Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0 , CNTR1 input cycle time CNTR0 , CNTR1 input “H” pulse width INT 0, INT1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 , INT1 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O2 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O2 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O2 input set up time Serial I/O1 input hold time Serial I/O2 input hold time Limits Min. 2 500 200 200 500 230 230 230 230 2000 2000 950 950 950 950 400 400 200 200 Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: When f( φ) = 1 MHz and bit 6 of address 001A16 or 003216 is “1” (clock synchronous). Divide this value by four when f(φ ) = 1 MHz and bit 6 of address 001A 16 or 003216 is “0” (clock asynchronous). 39 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SWITCHING CHARACTERISTICS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol t wH(SCLK1) t wH(SCLK2) t wL(SCLK1) t wL(SCLK2) t d(SCLK1 –TX D1) t d(SCLK2 –TX D2) t v(S CLK1–TX D1 ) t v(S CLK2–TX D2 ) t r(SCLK1 ) t f(SCLK1) t r(SCLK2 ) t f(SCLK2) t r(CMOS) t f(CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O2 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O2 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O2 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O2 output valid time (Note 1) Serial I/O1 clock output rise time Serial I/O1 clock output fall time Serial I/O2 clock output rise time Serial I/O2 clock output fall time CMOS output rise time (Note 2) CMOS output fall time (Note 2) Test conditions Limits Min. t c(SCLK1 )/2–30 t c(SCLK2 )/2–30 t c(SCLK1 )/2–30 t c(SCLK2 )/2–30 140 140 CL = 100 pF –30 –30 30 30 30 30 30 30 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 Notes 1: When bit 4 of the UART control register (address 001B16 or 003316) is “0”. 2: X OUT pin is excluded. Measurement output pin Measurement output pin 100pF 1kΩ 100pF CMOS output N-channel open-drain output Fig. 34 Circuit for measuring output switching characteristics (1) Fig. 35 Circuit for measuring output switching characteristics (2) Note: When bit 4 of the UART contronl register (address 001B16 or 003316 ) is “1” (N-channel open-drain output), and bit 7 of the serial I/O control register (address 001A16 or 003216) is “1”. SWITCHING CHARACTERISTICS 2 (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol t wH(SCLK1) t wH(SCLK2) t wL(SCLK1) t wL(SCLK2) t d(SCLK1 –TX D1) t d(SCLK2 –TX D2) t v(S CLK1–TX D1 ) t v(S CLK2–TX D2 ) t r(SCLK1 ) t f(SCLK1) t r(SCLK2 ) t f(SCLK2) t r(CMOS) t f(CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O2 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O2 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O2 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O2 output valid time (Note 1) Serial I/O1 clock output rise time Serial I/O1 clock output fall time Serial I/O2 clock output rise time Serial I/O2 clock output fall time CMOS output rise time (Note 2) CMOS output fall time (Note 2) Test conditions Min. t c(SCLK1 )/2–50 t c(SCLK2 )/2–50 t c(SCLK1 )/2–50 t c(SCLK2 )/2–50 350 350 CL = 100 pF –30 –30 50 50 50 50 50 50 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 20 Notes 1: When bit 4 of the UART control register (address 001B16 or 003316) is “0”. 2: X OUT pin excluded. 40 MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING DIAGRAM tc(CNTR) twH(CNTR) CNTR0, CNTR 1 0.8VCC 0.2VCC twL(CNTR) twH(INT) INT0, INT 1 0.8VCC 0.2VCC twL(INT) tw(RESET) RESET 0.8VCC 0.2VCC tc(X IN ) twH(X IN) XIN 0.8VCC 0.2VCC twL(X IN) tc(S CLK1 ), tc(S CLK2 ) tf SCLK1 0.2VCC SCLK2 tsu(R XD1 – SCLK1 ) tsu(R XD2 – SCLK2 ) RX D1 RX D2 0.8VCC 0.2VCC twL(S CLK1 ), twL(S CLK2 ) tr 0.8VCC twH(SCLK1 ), twH(S CLK2 ) th(S CLK1 – RX D1), th(SCLK 2 – RX D2) td(S CLK1 – TXD1), td(S CLK2 – TXD2) T X D1 T X D2 tv(S CLK1 – TXD1), tv(S CLK2 – TXD2) 41 REVISION DESCRIPTION LIST Rev. No. 1.0 First Edition 7510 GROUP DATA SHEET Revision Description Rev. date 980110 (1/1) MITSUBISHI MICROCOMPUTERS 7510 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. 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