M37733MHL

P ge. ion. icat o chan t ecif l sp ubject fina re s a ot a is n limits his e: T ametric otic par N e Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DESCRIPTION The M37733MHLXXXHP is a single-chip microcomputer using the 7700 Family core. This single-chip microcomputer has a CPU and a bus interface unit. The CPU is a 16-bit parallel processor that can be an 8-bit parallel processor, and the bus interface unit enhances the memory access efficiency to execute instructions fast. This microcomputer also includes a 32 kHz oscillation circuit, in addition to the ROM, RAM, multiple-function timers, serial I/O, A-D converter, and so on. Its strong points are the low power dissipation, the low supply voltage, and the small package. qInterrupts ............................................................ 19 types, 7 levels qMultiple-function 16-bit timer ................................................. 5 + 3 qSerial I/O (UART or clock synchronous) ..................................... 3 q10-bit A-D converter .............................................. 8-channel inputs q12-bit watchdog timer qProgrammable input/output (ports P0, P1, P2, P3, P4, P5, P6, P7, P8) ............................... 68 qClock generating circuit ........................................ 2 circuits built-in qSmall package ...................... 80-pin plastic molded fine-pitch QFP (80P6D-A;0.5 mm lead pitch) APPLICATION FEATURES qNumber of basic instructions .................................................. 103 qMemory size ROM ................................................. 124 Kbytes RAM ................................................ 3968 bytes qInstruction execution time The fastest instruction at 12 MHz frequency ...................... 333 ns qSingle power supply ...................................................... 2.7–5.5 V qLow power dissipation (At 3 V supply voltage, 12 MHz frequency) ............................................ 9 mW (Typ.) Control devices for general commercial equipment such as office automation, office equipment, personal information equipment, and so on. Control devices for general industrial equipment such as communication equipment, and so on. PIN CONFIGURATION (TOP VIEW) 56 49 55 44 50 58 57 59 54 52 51 53 48 60 47 46 45 43 P85/CLK1 P84/CTS1/RTS1 P83/T XD0 P82/R XD0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AVCC VREF AVSS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG /TXD2 P74/AN4/R XD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 P70/AN0 P67/TB2 IN/ SUB 42 41 P86/RxD1 P87/Tx D1 P00 /A0 P01 /A1 P02 /A2 P03 /A3 P04 /A4 P05 /A5 P06 /A6 P07 /A7 P10 /A8/D8 P11 /A9/D9 P12 /A10/D10 P13 /A11/D11 P14 /A12/D12 P15 /A13/D13 P16 /A14/D14 P17 /A15/D15 P20 /A16/D 0 P21 /A17/D 1 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 M37733MHLXXXHP 31 30 29 28 27 26 25 24 23 22 21 P22/A18 /D2 P23/A19 /D3 P24/A 20/D4 P25/A 21/D5 P26/A 22/D6 P27/A 23/D7 P30/R/W P31/BHE P32/ALE P33/HLDA VSS E XOUT XIN RESET CNVSS BYTE P40/HOLD P41/RDY P42/ 1 11 10 16 17 13 14 12 15 18 P66 /TB1IN P65 /TB0IN P64 /INT2 P63 /INT1 P62 /INT0 P61/TA4IN P60 /TA4OUT P57/TA3 IN /KI 3 P56/TA3OUT/KI 2 P55/TA2IN /KI 1 P54/TA2OUT/KI 0 P53/TA1IN P52 /TA1OUT P51/TA0IN P50/TA0 OUT P47 P46 P45 P44 P43 Outline 80P6D-A, 80P6Q-A 19 20 2 5 4 1 3 6 7 8 9 P . . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Reference External data bus width voltage input selection input VREF BYTE Data Bus(Even) Data Bus(Odd) Data Buffer DBH(8) P0(8) Data Buffer DBL(8) Instruction Register(8) Instruction Queue Buffer Q0(8) Instruction Queue Buffer Q1(8) Address Bus Incrementer(24) (0V) AVSS Input/Output port P2 Input/Output port P8 Input/Output port P7 Input/Output port P6 Input/Output port P5 Input/Output port P4 Input/Output port P3 Program Address Register PA(24) Data Address Register DA(24) P2(8) CNVss Incrementer/Decrementer(24) (0V) VSS Program Bank Register PG(8) Data Bank Register DT(8) UART1(9) UART2(9) UART0(9) VCC Input Butter Register IB(16) Watchdog Timer Timer TB2(16) Timer TB1(16) Timer TB0(16) Processor Status Register PS(11) Reset input RESET Direct Page Register DPR(16) Stack Pointer S(16) Timer TA4(16) M37733MHLXXXHP BLOCK DIAGRAM Timer TA3(16) Timer TA2(16) Timer TA1(16) Timer TA0(16) Index Register Y(16) XCOUT XCIN Index Register X(16) Accumulator B(16) Enable output E Accumulator A(16) Clock Generating Circuit 3968 bytes P7(8) Clock input Clock output XIN XOUT RAM Arithmetic Logic Unit(16) XCOUT XCIN 124 Kbytes 2 ROM P8(8) P6(8) P5(8) P4(8) P3(4) Program Counter PC(16) A-D Converter(10) Input/Output port P1 Instruction Queue Buffer Q2(8) P1(8) AVCC Input/Output port P0 P . . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FUNCTIONS OF M37733MHLXXXHP Parameter Number of basic instructions Instruction execution time Memory size Input/Output ports Multi-function timers Serial I/O A-D converter Watchdog timer Interrupts Clock generating circuit Supply voltage Power dissipation Input/Output characteristic Memory expansion Operating temperature range Device structure Package Input/Output voltage Output current ROM RAM P0 – P2, P4 – P8 P3 TA0, TA1, TA2, TA3, TA4 TB0, TB1, TB2 Functions 103 333 ns (the fastest instruction at external clock 12 MHz frequency) 124 Kbytes 3968 bytes 8-bit ! 8 4-bit ! 1 16-bit ! 5 16-bit ! 3 (UART or clock synchronous serial I/O) ! 3 10-bit ! 1 (8 channels) 12-bit ! 1 3 external types, 16 internal types Each interrupt can be set to the priority level (0 – 7.) 2 circuits built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) 2.7 – 5.5 V 9 mW (at 3 V supply voltage, external clock 12 MHz frequency) 22.5 mW (at 5 V supply voltage, external clock 12 MHz frequency) 5V 5 mA Maximum 16 Mbytes –40 to 85 °C CMOS high-performance silicon gate process 80-pin plastic molded fine-pitch QFP (80P6D-A;0.5 mm lead pitch) 3 P . . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Pin Vcc, Vss CNVss RESET Name Input/Output Power source Apply 2.7 – 5.5 V to Vcc and 0 V to Vss. CNVss input Reset input Clock input Clock output Enable output External data bus width selection input Analog power source input Reference voltage input I/O port P0 Input Input Input Output Output Input Functions XIN XOUT E BYTE AVcc, AVss VREF P00 – P07 This pin controls the processor mode. Connect to Vss for the single-chip mode and the memory expansion mode, and to Vcc for the microprocessor mode. When “L” level is applied to this pin, the microcomputer enters the reset state. These are pins of main-clock generating circuit. Connect a ceramic resonator or a quartzcrystal oscillator between XIN and XOUT. When an external clock is used, the clock source should be connected to the XIN pin, and the XOUT pin should be left open. This pin functions as the enable signal output pin which indicates the access status in the internal bus. When output level of E signal is “L”, data/instruction read or data write is performed. In the memory expansion mode or the microprocessor mode, this pin determines whether the external data bus has an 8-bit width or a 16-bit width. The data bus has a 16-bit width when “L” signal is input and an 8-bit width when “H” signal is input. Power source input pin for the A-D converter. Externally connect AVcc to Vcc and AVss to Vss. This is reference voltage input pin for the A-D converter. In the single-chip mode, port P0 becomes an 8-bit I/O port. An I/O direction register is available so that each pin can be programmed for input or output. These ports are in the input mode when reset. In the memory expansion mode or the microprocessor mode, these pins output address (A0 – A7). In the single-chip mode, these pins have the same functions as port P0. When the BYTE pin is set to “L” in the memory expansion mode or the microprocessor mode and external data bus has a 16-bit width, high-order data (D8 – D15) is input/output or an address (A8 – A15) is output. When the BYTE pin is “H” and an external data bus has an 8-bit width, only address (A8 – A15) is output. In the single-chip mode, these pins have the same functions as port P0. In the memory expansion mode or the microprocessor mode, low-order data (D0 – D7) is input/output or an address (A16 – A23) is output. In the single-chip mode, these pins have the same function as port P0. In the memory expansion mode or the microprocessor mode, R/W, BHE, ALE, and HLDA signals are output. In the single-chip mode, these pins have the same functions as port P0. In the memory expansion mode or the microprocessor mode, P40, P41, and P42 become HOLD and RDY input pins, and a clock φ 1 output pin, respectively. Functions of the other pins are the same as in the single-chip mode. However, in the memory expansion mode, P42 can be selected as an I/O port. In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for timers A0 to A3 and input pins for key input interrupt input (KI0 – KI3). In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for timer A4, input pins for external interrupt input (INT0 – INT2) and input pins for timers B0 to B2. P67 also functions as sub-clock φ SUB output pin. In addition to having the same functions as port P0 in the single-chip mode, these pins function as input pins for A-D converter. P72 to P75 also function as I/O pins for UART2. Additionally, P76 and P77 have the function as the output pin (XCOUT) and the input pin (XCIN) of the sub-clock (32 kHz) oscillation circuit, respectively. When P76 and P77 are used as the XCOUT and XCIN pins, connect a resonator or an oscillator between the both. In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for UART 0 and UART 1. Input I/O P10 – P17 I/O port P1 I/O P20 – P27 I/O port P2 I/O P30 – P33 I/O port P3 P40 – P47 I/O port P4 I/O I/O P50 – P57 I/O port P5 P60 – P67 I/O port P6 I/O I/O P70 – P77 I/O port P7 I/O P80 – P87 I/O port P8 I/O 4 P ion. hange. icat ecif ct to c l sp fina re subje ot a its a is n his tric lim e e: T otic param N e Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER BASIC FUNCTION BLOCKS The M37733MHLXXXHP has the same functions as the M37733MHBXXXFP except for the package and the reset circuit. Refer to the section on the M37733MHBXXXFP. ADDRESSING MODES The M37733MHLXXXHP has 28 powerful addressing modes. Refer to the “7700 Family Software Manual” for the details. MACHINE INSTRUCTION LIST RESET CIRCUIT The microcomputer is released from the reset state when the RESET pin is returned to “H” level after holding it at “L” level with the power source voltage at 2.7 – 5.5 V. Program execution starts at the address formed by setting address A23 – A16 to 0016, A15 – A 8 to the contents of address FFFF16 , and A7 – A0 to the contents of address FFFE16. Figure 3 shows an example of a reset circuit. When the stabilized clock is input from the external to the main-clock oscillation circuit, the reset input voltage must be 0.55 V or less when the power source voltage reaches 2.7 V. When a resonator/oscillator is connected to the main-clock oscillation circuit, change the reset input voltage from “L” to “H” after the main-clock oscillation is fully stabilized. The status of the internal registers during reset is the same as the M37733MHBXXXFP’s. _____ The M37733MHLXXXHP has 103 machine instructions. Refer to the “7700 Family Software Manual” for the details. DATA REQUIRED FOR MASK ROM ORDERING Please send the following data for mask orders. (1) M37733MHLXXXHP mask ROM order confirmation form (2) 80P6D, 80P6Q mark specification form (3) ROM data (EPROM 3 sets) Power on VCC RESET 2.7V 0V VCC RESET 0V 0.55V Note. In this case, stabilized clock is input from the external to the main-clock oscillation circuit. Perform careful evalvation at the system design level before using. Fig. 1 Example of a reset circuit 5 P ion. hange. icat ecif ct to c l sp fina re subje ot a its a is n his tric lim e e: T otic param N e Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ABSOLUTE MAXIMUM RATINGS Symbol Vcc AVcc VI VI Parameter Conditions Power source voltage Analog power source voltage _____ Input voltage RESET, CNVss, BYTE Input voltage P00 – P07, P10 – P17 , P20 – P27, P30 – P33, P4 0 – P47, P50 – P57, P60 – P67, P70 – P77 , P80 – P87, VREF, XIN Output voltage P00 – P07, P10 – P17 , P20 – P27, P30 – P33, P4 0 – P47, P50 – P57, P60 – P67, P70 – P77 , P80 – P87, _ XOUT, E Power dissipation Ta = 25 °C Operating temperature Storage temperature Ratings –0.3 to +7 –0.3 to +7 –0.3 to +12 –0.3 to Vcc + 0.3 Unit V V V V VO Pd T opr T stg –0.3 to Vcc + 0.3 200 –40 to +85 – 65 to +150 V mW °C °C RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V ± 10%, Ta = –40 to +85 °C, unless otherwise noted) Symbol Vcc AVcc Vss AVss VIH VIH VIH VIL VIL VIL IOH(peak) Power source voltage Parameter f(XIN ) : Operating f(XIN ) : Stopped, f(XCIN) = 32.768 kHz Analog power source voltage Power source voltage Analog power source voltage High-level input voltage P00 – P07 , P30 – P33, P40 – P47 , P50 – P57, P60 – P6 7, _____ P7 0 – P77, P80 – P87 , XIN, RESET, CNVss, BYTE, XCIN (Note 3) High-level input voltage P10 – P17 , P20 – P27 (in single-chip mode) High-level input voltage P10 – P17 , P20 – P27 (in memory expansion mode and microprocessor mode) Low-level input voltage P00 – P07, P30 – P33, P40 – P47, P50 – P57, P60 – P67 , _____ P7 0 – P77, P80 – P87 , XIN, RESET, CNVss, BYTE, XCIN (Note 3) Low-level input voltage P10 – P17, P20 – P2 7 (in single-chip mode) Low-level input voltage P10 – P17, P20 – P2 7 (in memory expansion mode and microprocessor mode) High-level peak output current P00 – P07, P10 – P17 , P20 – P27, P30 – P33 , P4 0 – P47, P50 – P5 7, P60 – P67, P70 – P7 7, P8 0 – P87 High-level average output current P00 – P0 7, P10 – P17, P20 – P27 , P30 – P33, P40 – P47, P50 – P57, P60 – P6 7, P70 – P77, P80 – P87 Low-level peak output current P00 – P0 7, P10 – P17, P20 – P27 , P30 – P33, P40 – P4 3, P54 – P57, P60 – P67, P70 – P77 , P80 – P8 7 Low-level peak output current P44 – P47 , P50 – P53 Low-level average output current P00 – P07 , P10 – P17, P20 – P27, P30 – P3 3, P40 – P43, P54 – P57 , P60 – P67, P70 – P77 , P80 – P87 Low-level average output current P44 – P47, P50 – P5 3 Main-clock oscillation frequency (Note 4) Sub-clock oscillation frequency Min. 2.7 2.7 Limits Typ. Max. 5.5 5.5 Unit V V V V Vcc Vcc Vcc 0.2Vcc 0.2Vcc 0.16Vcc –10 V V V V V V mA Vcc 0 0 0.8 Vcc 0.8 Vcc 0.5 Vcc 0 0 0 IOH(avg) –5 mA IOL(peak) IOL(peak) IOL(avg) IOL(avg) f(XIN ) f(XCIN) 10 16 5 12 12 50 mA mA mA mA MHz kHz 32.768 Notes 1. Average output current is the average value of a 100 ms interval. 2. The sum of IOL(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOH(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, and P7 must be 100 mA or less, and the sum of IOH(peak) for ports P4, P5, P6, and P7 must be 80 mA or less. 3. Limits VIH and V IL for XCIN are applied when the sub clock external input selection bit = “1”. 4. The maximum value of f(XIN) = 6 MHz when the main clock division selection bit = “1”. 6 P . . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted) Symbol VOH VOH VOH Parameter High-level output voltage P00 – P07, P10 – P17, P20 – P27, P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87 High-level output voltage P00 – P07, P10 – P17, P20 – P27, P33 High-level output voltage P30 – P32 Test conditions VCC = 5 V, IOH = –10 mA VCC = 3 V, IOH = –1 mA Min. 3 2.5 4.7 3.1 4.8 2.6 3.4 4.8 2.6 Limits Typ. Max. Unit V V V VOH High-level output voltage E Low-level output voltage P00 – P07, P10 – P17, P20 – P27, P33, P40 – P43, P54 – P57, P60 – P67, P70 – P77, P80 – P87 Low-level output voltage P44 – P47, P50 – P53 Low-level output voltage P00 – P07, P10 – P17, P20 – P27, P33 Low-level output voltage P30 – P32 VCC = 5 V, IOH = –400 µA VCC = 5 V, IOH = –10 mA VCC = 5 V, IOH = –400 µA VCC = 3 V, IOH = –1 mA VCC = 5 V, IOH = –10 mA VCC = 5 V, IOH = –400 µA VCC = 3 V, IOH = –1 mA VCC = 5 V, IOL = 10 mA VCC = 3 V, IOL = 1 mA VCC = 5 V, IOL = 16 mA VCC = 3 V, IOL = 10 mA VCC = 5 V, IOL = 2 mA VCC = 5 V, IOL = 10 mA VCC = 5 V, IOL = 2 mA VCC = 3 V, IOL = 1 mA VCC = 5 V, IOL = 10 mA VCC = 5 V, IOL = 2 mA VCC = 3 V, IOL = 1 mA VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V, VI = 5 V VCC = 3 V, VI = 3 V VCC = 5 V, VI = 0 V VCC = 3 V, VI = 0 V VI = 0 V, without a pull-up transistor VI = 0 V, with a pull-up transistor VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V V 2 0.5 1.8 1.5 0.45 1.9 0.43 0.4 1.6 0.4 0.4 V V V V VOL VOL VOL VOL VOL Low-level output voltage E Hysteresis HOLD, RDY, TA0IN – TA4IN, TB0IN – TB2IN, INT0 – INT2, ADTRG, CTS0, CTS1, CTS2, CLK0, CLK1, CLK2, KI0 – KI3 Hysteresis RESET Hysteresis XIN Hysteresis XCIN (When external clock is input) High-level input current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87, XIN, RESET, CNVss, BYTE Low-level input current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P53, P60, P61, P65 – P67, P70 – P77, P80 – P87, XIN, RESET, CNVss, BYTE Low-level input current P54 – P57, P62 – P64 V 0.4 0.1 0.2 0.1 0.1 0.06 0.1 0.06 1 0.7 0.5 0.4 0.4 0.26 0.4 0.26 5 4 –5 –4 –5 –4 µA V V V V µA VT+ – VT– VT+ – VT– VT+ – VT– VT+ – VT– IIH IIL µA IIL –0.25 –0.08 2 –0.5 –0.18 –1.0 –0.35 mA V VRAM RAM hold voltage When clock is stopped. 7 P . . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –40 to +85 °C, unless otherwise noted) Symbol Parameter Test conditions VCC = 5 V, f(XIN) = 12 MHz (square waveform), (f(f2) = 6 MHz), f(XCIN) = 32.768 kHz, in operating (Note 1) VCC = 3 V, f(XIN) = 12 MHz (square waveform), (f(f2) = 6 MHz), f(XCIN) = 32.768 kHz, in operating (Note 1) VCC = 3 V, f(XIN) = 12 MHz (square waveform), (f(f2) = 0.75 MHz), f(XCIN) : Stopped, in operating Min. Limits Typ. Max. Unit 4.5 9 mA 3 6 mA ICC Power source current When single-chip mode, output pins are open, and other pins are VSS. VCC = 3 V, f(XIN) = 12 MHz (square waveform), f(XCIN) = 32.768 kHz, when a WIT instruction is executed (Note 2) VCC = 3 V, f(XIN) : Stopped, f(XCIN) = 32.768 kHz, in operating (Note 3) VCC = 3 V, f(XIN) : Stopped, f(XCIN) = 32.768 kHz, when a WIT instruction is executed (Note 4) Ta = 25 °C, when clock is stopped Ta = 85 °C, when clock is stopped 0.4 0.8 mA 6 12 µA 30 60 µA 3 6 µA 1 20 µA µA Notes 1. This applies when the main clock external input selection bit = “1”, the main clock division selection bit = “0”, and the signal output stop bit = “1”. 2. This applies when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1”. 3. This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4. This applies when the XCOUT drivability selection bit = “0” and the system clock stop bit at wait state = “1”. A–D CONVERTER CHARACTERISTICS (VCC = AVCC = 5 V, VSS = AVSS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted (Note)) Symbol — — RLADDER tCONV VREF VIA Parameter Resolution Absolute accuracy Ladder resistance Conversion time Reference voltage Analog input voltage Test conditions VREF = VCC VREF = VCC VREF = VCC Min. Limits Typ. Max. 10 ±3 25 VCC VREF Unit Bits LSB kΩ µs V V 10 19.6 2.7 0 Note. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHz. 8 P . . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER TIMING REQUIREMENTS (VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted (Note 1)) Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHZ. 2. Input signal’s rise/fall time must be 100 ns or less, unless otherwise noted. External clock input Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time (Note 1) External clock input high-level pulse width (Note 2) External clock input low-level pulse width (Note 2) External clock rise time External clock fall time Limits Min. 83 33 33 Max. Unit ns ns ns ns ns 15 15 Notes 1. When the main clock division selection bit = “1”, the minimum value of tc = 166 ns. 2. When the main clock division selection bit = “1”, values of tw(H) / tc and tw(L) / tc must be set to values from 0.45 through 0.55. Single-chip mode Symbol tsu(P0D–E) tsu(P1D–E) tsu(P2D–E) tsu(P3D–E) tsu(P4D–E) tsu(P5D–E) tsu(P6D–E) tsu(P7D–E) tsu(P8D–E) th(E–P0D) th(E–P1D) th(E–P2D) th(E–P3D) th(E–P4D) th(E–P5D) th(E–P6D) th(E–P7D) th(E–P8D) Port P0 input setup time Port P1 input setup time Port P2 input setup time Port P3 input setup time Port P4 input setup time Port P5 input setup time Port P6 input setup time Port P7 input setup time Port P8 input setup time Port P0 input hold time Port P1 input hold time Port P2 input hold time Port P3 input hold time Port P4 input hold time Port P5 input hold time Port P6 input hold time Port P7 input hold time Port P8 input hold time Parameter Limits Min. 200 200 200 200 200 200 200 200 200 0 0 0 0 0 0 0 0 0 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Memory expansion mode and microprocessor mode Symbol tsu(D–E) tsu(RDY– φ1) tsu(HOLD– φ1) th(E–D) th( φ1–RDY) th( φ1–HOLD) Data input setup time RDY input setup time HOLD input setup time Data input hold time RDY input hold time HOLD input hold time Parameter Limits Min. 50 80 80 0 0 0 Max. Unit ns ns ns ns ns ns 9 P . . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A input Symbol tc(TA) tw(TAH) tw(TAL) (Count input in event counter mode) Parameter Limits Min. 250 125 125 Max. Unit ns ns ns TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Timer A input (Gating input in timer mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time (Note) TAiIN input high-level pulse width (Note) TAiIN input low-level pulse width (Note) Parameter Limits Min. 666 333 333 Max. Unit ns ns ns Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”. Timer A input (External trigger input in one-shot pulse mode) Symbol t c(TA) tw(TAH) tw(TAL) TAiIN input cycle time (Note) TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Limits Min. 666 166 166 Max. Unit ns ns ns Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”. Timer A input (External trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Limits Min. 166 166 Max. Unit ns ns Timer A input (Up-down input in event counter mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP–TIN) th(TIN–UP) TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time Parameter Limits Min. 3333 1666 1666 666 666 Max. Unit ns ns ns ns ns Timer A input (Two-phase pulse input in event counter mode) Symbol tc(TA) tsu(TAjIN–TAjOUT) tsu(TAjOUT–TAjIN) TAjIN input cycle time TAjIN input setup time TAjOUT input setup time Parameter Limits Min. 2000 500 500 Max. Unit ns ns ns 10 P . . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B input (Count input in event counter mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (one edge count) TBiIN input high-level pulse width (one edge count) TBiIN input low-level pulse width (one edge count) TBiIN input cycle time (both edges count) TBiIN input high-level pulse width (both edges count) TBiIN input low-level pulse width (both edges count) Limits Min. 250 125 125 500 250 250 Max. Unit ns ns ns ns ns ns Timer B input (Pulse period measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time (Note) TBiIN input high-level pulse width (Note) TBiIN input low-level pulse width (Note) Parameter Limits Min. 666 333 333 Max. Unit ns ns ns Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”. Timer B input (Pulse width measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time (Note) TBiIN input high-level pulse width (Note) TBiIN input low-level pulse width (Note) Parameter Limits Min. 666 333 333 Max. Unit ns ns ns Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”. A-D trigger input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (minimum allowable trigger) ADTRG input low-level pulse width Limits Min. 1333 166 Max. Unit ns ns Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C–Q) th(C–Q) tsu(D–C) th(C–D) CLKi input cycle time CLKi input high-level pulse width CLKi input low-level pulse width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Parameter Limits Min. 333 166 166 0 65 75 Max. Unit ns ns ns ns ns ns ns 100 External interrupt INTi input, key input interrupt KIi input Symbol tw(INH) tw(INL) tw(KIL) INTi input high-level pulse width INTi input low-level pulse width KIi input low-level pulse width Parameter Limits Min. 250 250 250 Max. Unit ns ns ns 11 P . . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DATA FORMULAS Timer A input (Gating input in timer mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Limits Min. 8 ! 109 2 • f(f2) 4 ! 109 2 • f(f2) 4 ! 109 2 • f(f2) Max. Unit ns ns ns Timer A input (External trigger input in one-shot pulse mode) Symbol tc(TA) TAiIN input cycle time Parameter Limits Min. 8 ! 109 2 • f(f2) Max. Unit ns Timer B input (In pulse period measurement mode or pulse width measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width Parameter Limits Min. 8 ! 109 2 • f(f2) 4 ! 109 2 • f(f2) 4 ! 109 2 • f(f2) Max. Unit ns ns ns Note. f(f2) represents the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 9 in data sheet “M37733MHBXXXFP”. 12 P ion. hange. icat ecif ct to c l sp fina re subje a not sa is is ric limit t : Th tice arame No e p Som M ELI R IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER SWITCHING CHARACTERISTICS (VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to +85°C, f(XIN) = 12 MHz, unless otherwise noted (Note)) Single-chip mode Symbol td(E–P0Q) td(E–P1Q) td(E–P2Q) td(E–P3Q) td(E–P4Q) td(E–P5Q) td(E–P6Q) td(E–P7Q) td(E–P8Q) Parameter Port P0 data output delay time Port P1 data output delay time Port P2 data output delay time Port P3 data output delay time Port P4 data output delay time Port P5 data output delay time Port P6 data output delay time Port P7 data output delay time Port P8 data output delay time Test conditions Limits Min. Max. 300 300 300 300 300 300 300 300 300 Unit ns ns ns ns ns ns ns ns ns Fig. 2 Note. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHz. P0 P1 P2 P3 P4 P5 P6 P7 P8 1 E 50 pF Fig. 2 Measuring circuit for ports P0 – P8 and φ 1 13 P . . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory expansion mode and microprocessor mode (VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to +85°C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) Symbol td(An–E) Address output delay time Parameter Test (Note 2) Wait mode conditions No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 Limits Min. 20 182 20 162 40 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 40 123 10 93 9 40 Fig. 2 4 40 90 No wait Wait 1 Wait 0 40 131 298 10 53 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 20 182 20 182 33 33 0 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns td(A–E) Address output delay time Address hold time ALE pulse width th(E–An) tw(ALE) tsu(A–ALE) Address output set up time th(ALE–A) Address hold time td(ALE–E) td(E–DQ) th(E–DQ) tw(EL) tpxz(E–DZ) tpzx(E–DZ) td(BHE–E) ALE output delay time Data output delay time Data hold time E pulse width Floating start delay time Floating release delay time BHE output delay time td(R/W–E) th(E–BHE) th(E–R/W) td(E– φ 1) td( φ 1–HLDA) R/ W output delay time BHE hold time R/ W hold time φ 1 output delay time HLDA output delay time 30 120 Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHz. 2. No wait : Wait bit = “1”. Wait 1 : The external memory area is accessed with wait bit = “0” and wait selection bit = “1”. Wait 0 : The external memory area is accessed with wait bit = “0” and wait selection bit = “0”. 14 P . . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory expansion mode and microprocessor mode Bus timing data formulas (VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to +85 °C, Symbol Parameter f(XIN) = 12 MHz (Max., Note), unless otherwise noted) Limits Min. 1 ! 109 – 63 2 · f(f2) 9 3 ! 10 – 68 2 · f(f2) 1 ! 109 – 63 2 · f(f2) 3 ! 109 – 88 2 · f(f2) 9 1 ! 10 – 43 2 · f(f2) 9 1 ! 10 – 43 2 · f(f2) 9 2 ! 10 – 43 2 · f(f2) 1 ! 109 – 73 2 · f(f2) 2 ! 109 – 73 2 · f(f2) 9 1 ! 10 2 · f(f2) 9 td(An–E) Address output delay time Wait mode No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 Max. Unit ns ns ns ns ns ns ns ns ns ns td(A–E) Address output delay time th(E–An) Address hold time No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 tw(ALE) ALE pulse width tsu(A–ALE) Address output set up time th(ALE–A) Address hold time – 43 ns ns 4 1 ! 109 2 · f(f2) 1 ! 109 2 · f(f2) 2 ! 109 2 · f(f2) 4 ! 109 2 · f(f2) 1 ! 109 2 · f(f2) 1 ! 109 2 · f(f2) 3 ! 109 2 · f(f2) 1 ! 109 2 · f(f2) 3 ! 109 2 · f(f2) 1 ! 109 2 · f(f2) 1 ! 109 2 · f(f2) 0 – 43 90 – 43 – 35 – 35 10 – 30 – 63 – 68 – 63 – 68 – 50 – 50 30 td(ALE–E) td(E–DQ) th(E–DQ) ALE output delay time ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data output delay time Data hold time No wait tw(EL) tpxz(E–DZ) tpzx(E–DZ) E pulse width Wait 1 Wait 0 Floating start delay time Floating release delay time No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 td(BHE–E) BHE output delay time td(R/W–E) R/W output delay time th(E–BHE) th(E–R/W) td(E– φ 1) BHE hold time R/W hold time φ 1 output delay time Notes 1. This applies when the main-clock division selection bit = “0”. 2. f(f2) represents the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 9 in data sheet “M37733MHBXXXFP”. 15 P . . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER TIMING DIAGRAM XIN tr tf tc tw(H) tw(L) E td(E–P0Q) Port P0 output tsu(P0D–E) Port P0 input th(E–P0D) td(E–P1Q) Port P1 output tsu(P1D–E) Port P1 input th(E–P1D) td(E–P2Q) Port P2 output tsu(P2D–E) Port P2 input th(E–P2D) td(E–P3Q) Port P3 output tsu(P3D–E) Port P3 input th(E–P3D) td(E–P4Q) Port P4 output tsu(P4D–E) Port P4 input th(E–P4D) td(E–P5Q) Port P5 output tsu(P5D–E) Port P5 input th(E–P5D) td(E–P6Q) Port P6 output tsu(P6D–E) Port P6 input th(E–P6D) td(E–P7Q) Port P7 output tsu(P7D–E) Port P7 input th(E–P7D) td(E–P8Q) Port P8 output tsu(P8D–E) Port P8 input th(E–P8D) 16 P . . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) In event count mode TAiOUT input (Up-down input) TAiIN input (when count by falling) TAiIN input (when count by rising) th(TIN–UP) tsu(UP–TIN) In event counter mode (When two-phase pulse input is selected) TAjIN input tsu(TAjIN–TAjOUT) tc(TA) tsu(TAjIN–TAjOUT) tsu(TAjOUT–TAjIN) TAjOUT input tsu(TAjOUT–TAjIN) tc(TB) tw(TBH) TBiIN input tw(TBL) 17 P . . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) th(C–Q) TxDi td(C–Q) RxDi tSU(D–C) th(C–D) tw(INL) INTi input Kli input tw(INH) tw(KNL) 18 P . . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory expansion mode and microprocessor mode (When wait bit = “1”) φ1 E RDY input tsu(RDY– φ1) th( φ1–RDY) ( When wait bit = “0”) φ1 E RDY input tsu(RDY– φ1) th( φ1–RDY) (When wait bit = “1” or “0” in common) φ1 tsu(HOLD– φ1) HOLD input th( φ1–HOLD) td( φ1–HLDA) HLDA output td( φ1–HLDA) Test conditions • VCC = 2.7 – 5.5 V • Input timing voltage : V IL = 0.2 V CC, VIH = 0.8 V CC • Output timing voltage : V OL = 0.8 V, VOH = 2.0 V 19 P . . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory expansion mode and microprocessor mode (No wait : When wait bit = “1”) tw(L) tw(H) tf tr tc XIN 1 td(E- 1) td(Etw(EL) 1) E td(An-E) th(E-An) Address Address Address An tw(ALE) td(ALE-E) ALE th(ALE-A) tsu(A-ALE) th(E-DQ) tpxz(E-DZ) tpzx(E-DZ) Am/Dm Address Data Address th(E-D) tsu(D-E) Data Address td(E-DQ) td(A-E) DmIN th(E-BHE) td(BHE-E) BHE td(R/W-E) th(E-R/W) R/W Test condition • VCC = 2.7 – 5.5 V • Output timing voltage : VOL = 0.8 V, VOH = 2.0 V • Data input DmIN : VIL = 0.16 VCC, VIH = 0.5 VCC 20 P . . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory expansion mode and microprocessor mode (Wait 1 : The external area is accessed when wait bit = “0” and wait selection bit = “1”.) tw(L) XIN tw(H) tf tr tc φ1 td(E– φ1) tw(EL) E td(E– φ1) td(An–E) An th(E–An) Address Address tw(ALE) ALE td(ALE–E) th(ALE–A) tsu(A–ALE) Am/Dm Address Data th(E–DQ) tpxz(E–DZ) Address tpzx(E–DZ) Address td(A–E) td(E–DQ) tsu(D–E) th(E–D) DmIN Data td(BHE–E) th(E–BHE) BHE td(R/W–E) R/W th(E–R/W) Test condition • Vcc = 2.7 – 5.5 V • Output timing voltage : V OL = 0.8 V, V OH = 2.0 V • Data input Dm IN : VIL = 0.16 Vcc, V IH = 0.5 Vcc 21 P . . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory expansion mode and microprocessor mode (Wait 0 : The external memory area is accessed when wait bit = “0” and wait selection bit = “0”.) tw(L) XIN tw(H) tf tr tc φ1 td(E– φ1) E td(E– φ1) tw(EL) td(An–E) An Address th(E–An) Address Address tw(ALE) ALE td(ALE–E) tsu(A–ALE) th(ALE–A) th(E–DQ) tpxz(E–DZ) Address tpzx(E–DZ) Address Am/Dm Address td(A–E) Data td(E–DQ) tsu(D–E) DmIN th(E–BHE) Data th(E–D) td(BHE–E) BHE td(R/W–E) R/W th(E–R/W) Test conditions • Vcc = 2.7 – 5.5 V • Output timing voltage : V OL = 0.8 V, V OH = 2.0 V • Data input Dm IN : VIL = 0.16 Vcc, V IH = 0.5 Vcc 22 P . . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PACKAGE OUTLINE 23 P . . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ–SH00–44B Mask ROM number Note : Please fill in all items marked Issuance signatures Company name Date issued 1. Confirmation Specify the name of the product being ordered. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM areas EPROM Type : 27C201 00000 00010 20000 (1) Set “FF16 ” in the shaded area. (2) Address 016 to 1016 are the area for storing the data on model designation and options.This area must be written with the data shown below. Details for option data are given next in the section describing the STP instruction option. Address and data are written in hexadecimal notation. 128K 4D 33 37 37 33 33 4D 48 Address 0 1 2 3 4 5 6 7 4C FF FF FF FF FF FF FF Address Address Option data 10 8 9 A B C D E F (hexadecimal notation) Date: TEL ( Responsible officer Supervisor Customer ) DATA 3FFFF 2. STP instruction option One of the following sets of data should be written to the option data address (1016) of the EPROM you have ordered. Check @ in the appropriate box. STP instruction enable STP instruction disable 0116 0016 Address 1016 Address 1016 3. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered fill out the appropriate 80P6D Mark Specification Form (for M37733MHLXXXHP) and attach to the Mask ROM Order Confirmation Form. 4. Comments 24 Receipt 7700 FAMILY MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP 16-BIT MICROCOMPUTER M37733MHLXXXHP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature P . . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL IN Y AR MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 25 PR ge. ion. icat o chan t ecif l sp ubject a a fin are s not s limit is is : Th metric ice Not e para Som MI ELI NA RY MITSUBISHI MICROCOMPUTERS M37733MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. • Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. • All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. • Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. • The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. • If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. • Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. © 1996 MITSUBISHI ELECTRIC CORP. H-LF429-A KI-9606 Printed in Japan (ROD) 2 New publication, effective Jun. 1996. Specifications subject to change without notice. REVISION DESCRIPTION LIST Rev. No. 1.00 1.01 First Edition The following are added: • MASK ROM ORDER CONFIRMATION FORM • MARK SPECIFICATION FORM 2.00 The following are revised: Page P1 PIN CONFIGURATION (TOP VIEW) P5 Right column Line 2 Previous Version M37733MHLXXXHP Datasheet Revision Description Rev. date 970414 980421 980731 Revised Version Outline 80P6D-A The M37733MHLXXXHP has 28 powerful addressing modes. Refer to the SINGLE-CHIP 16BIT MICROCOMPUTERS DATA BOOK for the details of each addressing mode. Outline 80P6D-A, 80P6Q-A The M37733MHLXXXHP has 28 powerful addressing modes. R efer to the “7700 Family Software Manual” for the details. MACHINE INSTRUCTION LIST MACHINE INSTRUCTION LIST The M37733MHLXXXHP has 103 machine instructions. Refer to the SINGLE-CHIP 16-BIT MICROCOMPUTERS DATA BOOK for details. Line 10 P6 RECOMMENDED OPERATING CONDITIONS (2) 80P6D mark specification form The M37733MHLXXXHP has 103 machine instructions. Refer to the “7700 Family Software Manual” for the details. (2) 80P6D, 80P6Q mark specification form Previous Version Symbol Vcc Power source voltage Parameter f(XIN) : Operating f(XIN) : Stopped, f(XCIN) = 32.768 kHz Revised Version Limits Min. 4.5 2.7 Typ. 5.0 Max. 5.5 5.5 Unit V Symbol Vcc Power source voltage Parameter f(XIN) : Operating f(XIN) : Stopped, f(XCIN) = 32.768 kHz Previous Version Limits Min. 2.7 2.7 Typ. Max. 5.5 5.5 Unit V P9 Memory expansion mode and microprocessor mode Symbol tsu (D–E) Data input setup time Parameter Limits Min. 80 Max. Unit ns Revised Version Symbol tsu (D–E) Data input setup time Parameter Limits Min. 50 Max. Unit ns (1)